1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_cmp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
142 micro_cos(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src
)
145 dst
->f
[0] = cosf(src
->f
[0]);
146 dst
->f
[1] = cosf(src
->f
[1]);
147 dst
->f
[2] = cosf(src
->f
[2]);
148 dst
->f
[3] = cosf(src
->f
[3]);
152 micro_d2f(union tgsi_exec_channel
*dst
,
153 const union tgsi_double_channel
*src
)
155 dst
->f
[0] = (float)src
->d
[0];
156 dst
->f
[1] = (float)src
->d
[1];
157 dst
->f
[2] = (float)src
->d
[2];
158 dst
->f
[3] = (float)src
->d
[3];
162 micro_d2i(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->i
[0] = (int)src
->d
[0];
166 dst
->i
[1] = (int)src
->d
[1];
167 dst
->i
[2] = (int)src
->d
[2];
168 dst
->i
[3] = (int)src
->d
[3];
172 micro_d2u(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->u
[0] = (unsigned)src
->d
[0];
176 dst
->u
[1] = (unsigned)src
->d
[1];
177 dst
->u
[2] = (unsigned)src
->d
[2];
178 dst
->u
[3] = (unsigned)src
->d
[3];
181 micro_dabs(union tgsi_double_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
185 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
186 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
187 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
191 micro_dadd(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
195 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
196 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
197 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
201 micro_ddiv(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] / src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] / src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] / src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] / src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddx_fine(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
225 dst
->f
[1] = src
->f
[TILE_TOP_RIGHT
] - src
->f
[TILE_TOP_LEFT
];
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
232 micro_ddy(union tgsi_exec_channel
*dst
,
233 const union tgsi_exec_channel
*src
)
238 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
242 micro_ddy_fine(union tgsi_exec_channel
*dst
,
243 const union tgsi_exec_channel
*src
)
246 dst
->f
[2] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
248 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_TOP_RIGHT
];
252 micro_dmul(union tgsi_double_channel
*dst
,
253 const union tgsi_double_channel
*src
)
255 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
256 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
257 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
258 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
262 micro_dmax(union tgsi_double_channel
*dst
,
263 const union tgsi_double_channel
*src
)
265 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
266 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
267 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
268 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
272 micro_dmin(union tgsi_double_channel
*dst
,
273 const union tgsi_double_channel
*src
)
275 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
276 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
277 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
278 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
282 micro_dneg(union tgsi_double_channel
*dst
,
283 const union tgsi_double_channel
*src
)
285 dst
->d
[0] = -src
->d
[0];
286 dst
->d
[1] = -src
->d
[1];
287 dst
->d
[2] = -src
->d
[2];
288 dst
->d
[3] = -src
->d
[3];
292 micro_dslt(union tgsi_double_channel
*dst
,
293 const union tgsi_double_channel
*src
)
295 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
296 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
297 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
298 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
302 micro_dsne(union tgsi_double_channel
*dst
,
303 const union tgsi_double_channel
*src
)
305 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
306 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
307 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
308 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
312 micro_dsge(union tgsi_double_channel
*dst
,
313 const union tgsi_double_channel
*src
)
315 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
316 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
317 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
318 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
322 micro_dseq(union tgsi_double_channel
*dst
,
323 const union tgsi_double_channel
*src
)
325 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
326 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
327 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
328 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
332 micro_drcp(union tgsi_double_channel
*dst
,
333 const union tgsi_double_channel
*src
)
335 dst
->d
[0] = 1.0 / src
->d
[0];
336 dst
->d
[1] = 1.0 / src
->d
[1];
337 dst
->d
[2] = 1.0 / src
->d
[2];
338 dst
->d
[3] = 1.0 / src
->d
[3];
342 micro_dsqrt(union tgsi_double_channel
*dst
,
343 const union tgsi_double_channel
*src
)
345 dst
->d
[0] = sqrt(src
->d
[0]);
346 dst
->d
[1] = sqrt(src
->d
[1]);
347 dst
->d
[2] = sqrt(src
->d
[2]);
348 dst
->d
[3] = sqrt(src
->d
[3]);
352 micro_drsq(union tgsi_double_channel
*dst
,
353 const union tgsi_double_channel
*src
)
355 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
356 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
357 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
358 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
362 micro_dmad(union tgsi_double_channel
*dst
,
363 const union tgsi_double_channel
*src
)
365 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
366 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
367 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
368 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
372 micro_dfrac(union tgsi_double_channel
*dst
,
373 const union tgsi_double_channel
*src
)
375 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
376 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
377 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
378 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
382 micro_dldexp(union tgsi_double_channel
*dst
,
383 const union tgsi_double_channel
*src0
,
384 union tgsi_exec_channel
*src1
)
386 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
387 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
388 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
389 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
393 micro_dfracexp(union tgsi_double_channel
*dst
,
394 union tgsi_exec_channel
*dst_exp
,
395 const union tgsi_double_channel
*src
)
397 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
398 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
399 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
400 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
404 micro_exp2(union tgsi_exec_channel
*dst
,
405 const union tgsi_exec_channel
*src
)
408 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
409 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
410 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
411 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
414 /* Inf is okay for this instruction, so clamp it to silence assertions. */
416 union tgsi_exec_channel clamped
;
418 for (i
= 0; i
< 4; i
++) {
419 if (src
->f
[i
] > 127.99999f
) {
420 clamped
.f
[i
] = 127.99999f
;
421 } else if (src
->f
[i
] < -126.99999f
) {
422 clamped
.f
[i
] = -126.99999f
;
424 clamped
.f
[i
] = src
->f
[i
];
430 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
431 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
432 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
433 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
434 #endif /* FAST_MATH */
438 micro_f2d(union tgsi_double_channel
*dst
,
439 const union tgsi_exec_channel
*src
)
441 dst
->d
[0] = (double)src
->f
[0];
442 dst
->d
[1] = (double)src
->f
[1];
443 dst
->d
[2] = (double)src
->f
[2];
444 dst
->d
[3] = (double)src
->f
[3];
448 micro_flr(union tgsi_exec_channel
*dst
,
449 const union tgsi_exec_channel
*src
)
451 dst
->f
[0] = floorf(src
->f
[0]);
452 dst
->f
[1] = floorf(src
->f
[1]);
453 dst
->f
[2] = floorf(src
->f
[2]);
454 dst
->f
[3] = floorf(src
->f
[3]);
458 micro_frc(union tgsi_exec_channel
*dst
,
459 const union tgsi_exec_channel
*src
)
461 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
462 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
463 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
464 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
468 micro_i2d(union tgsi_double_channel
*dst
,
469 const union tgsi_exec_channel
*src
)
471 dst
->d
[0] = (double)src
->i
[0];
472 dst
->d
[1] = (double)src
->i
[1];
473 dst
->d
[2] = (double)src
->i
[2];
474 dst
->d
[3] = (double)src
->i
[3];
478 micro_iabs(union tgsi_exec_channel
*dst
,
479 const union tgsi_exec_channel
*src
)
481 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
482 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
483 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
484 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
488 micro_ineg(union tgsi_exec_channel
*dst
,
489 const union tgsi_exec_channel
*src
)
491 dst
->i
[0] = -src
->i
[0];
492 dst
->i
[1] = -src
->i
[1];
493 dst
->i
[2] = -src
->i
[2];
494 dst
->i
[3] = -src
->i
[3];
498 micro_lg2(union tgsi_exec_channel
*dst
,
499 const union tgsi_exec_channel
*src
)
502 dst
->f
[0] = util_fast_log2(src
->f
[0]);
503 dst
->f
[1] = util_fast_log2(src
->f
[1]);
504 dst
->f
[2] = util_fast_log2(src
->f
[2]);
505 dst
->f
[3] = util_fast_log2(src
->f
[3]);
507 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
508 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
509 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
510 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
515 micro_lrp(union tgsi_exec_channel
*dst
,
516 const union tgsi_exec_channel
*src0
,
517 const union tgsi_exec_channel
*src1
,
518 const union tgsi_exec_channel
*src2
)
520 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
521 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
522 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
523 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
527 micro_mad(union tgsi_exec_channel
*dst
,
528 const union tgsi_exec_channel
*src0
,
529 const union tgsi_exec_channel
*src1
,
530 const union tgsi_exec_channel
*src2
)
532 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
533 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
534 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
535 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
539 micro_mov(union tgsi_exec_channel
*dst
,
540 const union tgsi_exec_channel
*src
)
542 dst
->u
[0] = src
->u
[0];
543 dst
->u
[1] = src
->u
[1];
544 dst
->u
[2] = src
->u
[2];
545 dst
->u
[3] = src
->u
[3];
549 micro_rcp(union tgsi_exec_channel
*dst
,
550 const union tgsi_exec_channel
*src
)
552 #if 0 /* for debugging */
553 assert(src
->f
[0] != 0.0f
);
554 assert(src
->f
[1] != 0.0f
);
555 assert(src
->f
[2] != 0.0f
);
556 assert(src
->f
[3] != 0.0f
);
558 dst
->f
[0] = 1.0f
/ src
->f
[0];
559 dst
->f
[1] = 1.0f
/ src
->f
[1];
560 dst
->f
[2] = 1.0f
/ src
->f
[2];
561 dst
->f
[3] = 1.0f
/ src
->f
[3];
565 micro_rnd(union tgsi_exec_channel
*dst
,
566 const union tgsi_exec_channel
*src
)
568 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
569 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
570 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
571 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
575 micro_rsq(union tgsi_exec_channel
*dst
,
576 const union tgsi_exec_channel
*src
)
578 #if 0 /* for debugging */
579 assert(src
->f
[0] != 0.0f
);
580 assert(src
->f
[1] != 0.0f
);
581 assert(src
->f
[2] != 0.0f
);
582 assert(src
->f
[3] != 0.0f
);
584 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
585 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
586 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
587 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
591 micro_sqrt(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src
)
594 dst
->f
[0] = sqrtf(src
->f
[0]);
595 dst
->f
[1] = sqrtf(src
->f
[1]);
596 dst
->f
[2] = sqrtf(src
->f
[2]);
597 dst
->f
[3] = sqrtf(src
->f
[3]);
601 micro_seq(union tgsi_exec_channel
*dst
,
602 const union tgsi_exec_channel
*src0
,
603 const union tgsi_exec_channel
*src1
)
605 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
606 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
607 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
608 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
612 micro_sge(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src0
,
614 const union tgsi_exec_channel
*src1
)
616 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
617 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
618 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
619 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
623 micro_sgn(union tgsi_exec_channel
*dst
,
624 const union tgsi_exec_channel
*src
)
626 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
627 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
628 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
629 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
633 micro_isgn(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
637 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
638 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
639 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
643 micro_sgt(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_sin(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src
)
657 dst
->f
[0] = sinf(src
->f
[0]);
658 dst
->f
[1] = sinf(src
->f
[1]);
659 dst
->f
[2] = sinf(src
->f
[2]);
660 dst
->f
[3] = sinf(src
->f
[3]);
664 micro_sle(union tgsi_exec_channel
*dst
,
665 const union tgsi_exec_channel
*src0
,
666 const union tgsi_exec_channel
*src1
)
668 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
669 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
670 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
671 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
675 micro_slt(union tgsi_exec_channel
*dst
,
676 const union tgsi_exec_channel
*src0
,
677 const union tgsi_exec_channel
*src1
)
679 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
680 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
681 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
682 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
686 micro_sne(union tgsi_exec_channel
*dst
,
687 const union tgsi_exec_channel
*src0
,
688 const union tgsi_exec_channel
*src1
)
690 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
691 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
692 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
693 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
697 micro_trunc(union tgsi_exec_channel
*dst
,
698 const union tgsi_exec_channel
*src
)
700 dst
->f
[0] = truncf(src
->f
[0]);
701 dst
->f
[1] = truncf(src
->f
[1]);
702 dst
->f
[2] = truncf(src
->f
[2]);
703 dst
->f
[3] = truncf(src
->f
[3]);
707 micro_u2d(union tgsi_double_channel
*dst
,
708 const union tgsi_exec_channel
*src
)
710 dst
->d
[0] = (double)src
->u
[0];
711 dst
->d
[1] = (double)src
->u
[1];
712 dst
->d
[2] = (double)src
->u
[2];
713 dst
->d
[3] = (double)src
->u
[3];
717 micro_i64abs(union tgsi_double_channel
*dst
,
718 const union tgsi_double_channel
*src
)
720 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
721 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
722 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
723 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
727 micro_i64sgn(union tgsi_double_channel
*dst
,
728 const union tgsi_double_channel
*src
)
730 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
731 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
732 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
733 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
737 micro_i64neg(union tgsi_double_channel
*dst
,
738 const union tgsi_double_channel
*src
)
740 dst
->i64
[0] = -src
->i64
[0];
741 dst
->i64
[1] = -src
->i64
[1];
742 dst
->i64
[2] = -src
->i64
[2];
743 dst
->i64
[3] = -src
->i64
[3];
747 micro_u64seq(union tgsi_double_channel
*dst
,
748 const union tgsi_double_channel
*src
)
750 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
751 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
752 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
753 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
757 micro_u64sne(union tgsi_double_channel
*dst
,
758 const union tgsi_double_channel
*src
)
760 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
761 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
762 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
763 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
767 micro_i64slt(union tgsi_double_channel
*dst
,
768 const union tgsi_double_channel
*src
)
770 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
771 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
772 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
773 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
777 micro_u64slt(union tgsi_double_channel
*dst
,
778 const union tgsi_double_channel
*src
)
780 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
781 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
782 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
783 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
787 micro_i64sge(union tgsi_double_channel
*dst
,
788 const union tgsi_double_channel
*src
)
790 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
791 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
792 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
793 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
797 micro_u64sge(union tgsi_double_channel
*dst
,
798 const union tgsi_double_channel
*src
)
800 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
801 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
802 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
803 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
807 micro_u64max(union tgsi_double_channel
*dst
,
808 const union tgsi_double_channel
*src
)
810 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
811 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
812 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
813 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
817 micro_i64max(union tgsi_double_channel
*dst
,
818 const union tgsi_double_channel
*src
)
820 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
821 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
822 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
823 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
827 micro_u64min(union tgsi_double_channel
*dst
,
828 const union tgsi_double_channel
*src
)
830 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
831 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
832 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
833 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
837 micro_i64min(union tgsi_double_channel
*dst
,
838 const union tgsi_double_channel
*src
)
840 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
841 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
842 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
843 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
847 micro_u64add(union tgsi_double_channel
*dst
,
848 const union tgsi_double_channel
*src
)
850 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
851 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
852 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
853 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
857 micro_u64mul(union tgsi_double_channel
*dst
,
858 const union tgsi_double_channel
*src
)
860 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
861 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
862 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
863 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
867 micro_u64div(union tgsi_double_channel
*dst
,
868 const union tgsi_double_channel
*src
)
870 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] / src
[1].u64
[0] : ~0ull;
871 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] / src
[1].u64
[1] : ~0ull;
872 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] / src
[1].u64
[2] : ~0ull;
873 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] / src
[1].u64
[3] : ~0ull;
877 micro_i64div(union tgsi_double_channel
*dst
,
878 const union tgsi_double_channel
*src
)
880 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] / src
[1].i64
[0] : 0;
881 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] / src
[1].i64
[1] : 0;
882 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] / src
[1].i64
[2] : 0;
883 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] / src
[1].i64
[3] : 0;
887 micro_u64mod(union tgsi_double_channel
*dst
,
888 const union tgsi_double_channel
*src
)
890 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] % src
[1].u64
[0] : ~0ull;
891 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] % src
[1].u64
[1] : ~0ull;
892 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] % src
[1].u64
[2] : ~0ull;
893 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] % src
[1].u64
[3] : ~0ull;
897 micro_i64mod(union tgsi_double_channel
*dst
,
898 const union tgsi_double_channel
*src
)
900 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] % src
[1].i64
[0] : ~0ll;
901 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] % src
[1].i64
[1] : ~0ll;
902 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] % src
[1].i64
[2] : ~0ll;
903 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] % src
[1].i64
[3] : ~0ll;
907 micro_u64shl(union tgsi_double_channel
*dst
,
908 const union tgsi_double_channel
*src0
,
909 union tgsi_exec_channel
*src1
)
911 unsigned masked_count
;
912 masked_count
= src1
->u
[0] & 0x3f;
913 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
914 masked_count
= src1
->u
[1] & 0x3f;
915 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
916 masked_count
= src1
->u
[2] & 0x3f;
917 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
918 masked_count
= src1
->u
[3] & 0x3f;
919 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
923 micro_i64shr(union tgsi_double_channel
*dst
,
924 const union tgsi_double_channel
*src0
,
925 union tgsi_exec_channel
*src1
)
927 unsigned masked_count
;
928 masked_count
= src1
->u
[0] & 0x3f;
929 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
930 masked_count
= src1
->u
[1] & 0x3f;
931 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
932 masked_count
= src1
->u
[2] & 0x3f;
933 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
934 masked_count
= src1
->u
[3] & 0x3f;
935 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
939 micro_u64shr(union tgsi_double_channel
*dst
,
940 const union tgsi_double_channel
*src0
,
941 union tgsi_exec_channel
*src1
)
943 unsigned masked_count
;
944 masked_count
= src1
->u
[0] & 0x3f;
945 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
946 masked_count
= src1
->u
[1] & 0x3f;
947 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
948 masked_count
= src1
->u
[2] & 0x3f;
949 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
950 masked_count
= src1
->u
[3] & 0x3f;
951 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
954 enum tgsi_exec_datatype
{
955 TGSI_EXEC_DATA_FLOAT
,
958 TGSI_EXEC_DATA_DOUBLE
,
959 TGSI_EXEC_DATA_INT64
,
960 TGSI_EXEC_DATA_UINT64
,
964 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
966 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
967 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
968 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
969 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
970 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
971 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
972 #define TEMP_PRIMITIVE_S1_I TGSI_EXEC_TEMP_PRIMITIVE_S1_I
973 #define TEMP_PRIMITIVE_S1_C TGSI_EXEC_TEMP_PRIMITIVE_S1_C
974 #define TEMP_PRIMITIVE_S2_I TGSI_EXEC_TEMP_PRIMITIVE_S2_I
975 #define TEMP_PRIMITIVE_S2_C TGSI_EXEC_TEMP_PRIMITIVE_S2_C
976 #define TEMP_PRIMITIVE_S3_I TGSI_EXEC_TEMP_PRIMITIVE_S3_I
977 #define TEMP_PRIMITIVE_S3_C TGSI_EXEC_TEMP_PRIMITIVE_S3_C
979 static const struct {
982 } temp_prim_idxs
[] = {
983 { TEMP_PRIMITIVE_I
, TEMP_PRIMITIVE_C
},
984 { TEMP_PRIMITIVE_S1_I
, TEMP_PRIMITIVE_S1_C
},
985 { TEMP_PRIMITIVE_S2_I
, TEMP_PRIMITIVE_S2_C
},
986 { TEMP_PRIMITIVE_S3_I
, TEMP_PRIMITIVE_S3_C
},
989 /** The execution mask depends on the conditional mask and the loop mask */
990 #define UPDATE_EXEC_MASK(MACH) \
991 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
994 static const union tgsi_exec_channel ZeroVec
=
995 { { 0.0, 0.0, 0.0, 0.0 } };
997 static const union tgsi_exec_channel OneVec
= {
998 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
1001 static const union tgsi_exec_channel P128Vec
= {
1002 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
1005 static const union tgsi_exec_channel M128Vec
= {
1006 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
1011 * Assert that none of the float values in 'chan' are infinite or NaN.
1012 * NaN and Inf may occur normally during program execution and should
1013 * not lead to crashes, etc. But when debugging, it's helpful to catch
1017 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
1019 assert(!util_is_inf_or_nan((chan
)->f
[0]));
1020 assert(!util_is_inf_or_nan((chan
)->f
[1]));
1021 assert(!util_is_inf_or_nan((chan
)->f
[2]));
1022 assert(!util_is_inf_or_nan((chan
)->f
[3]));
1028 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
1030 debug_printf("%s = {%f, %f, %f, %f}\n",
1031 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1038 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1040 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1042 debug_printf("Temp[%u] =\n", index
);
1043 for (i
= 0; i
< 4; i
++) {
1044 debug_printf(" %c: { %f, %f, %f, %f }\n",
1056 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1059 const unsigned *buf_sizes
)
1063 for (i
= 0; i
< num_bufs
; i
++) {
1064 mach
->Consts
[i
] = bufs
[i
];
1065 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1070 * Initialize machine state by expanding tokens to full instructions,
1071 * allocating temporary storage, setting up constants, etc.
1072 * After this, we can call tgsi_exec_machine_run() many times.
1075 tgsi_exec_machine_bind_shader(
1076 struct tgsi_exec_machine
*mach
,
1077 const struct tgsi_token
*tokens
,
1078 struct tgsi_sampler
*sampler
,
1079 struct tgsi_image
*image
,
1080 struct tgsi_buffer
*buffer
)
1083 struct tgsi_parse_context parse
;
1084 struct tgsi_full_instruction
*instructions
;
1085 struct tgsi_full_declaration
*declarations
;
1086 uint maxInstructions
= 10, numInstructions
= 0;
1087 uint maxDeclarations
= 10, numDeclarations
= 0;
1090 tgsi_dump(tokens
, 0);
1096 mach
->Tokens
= tokens
;
1097 mach
->Sampler
= sampler
;
1098 mach
->Image
= image
;
1099 mach
->Buffer
= buffer
;
1102 /* unbind and free all */
1103 FREE(mach
->Declarations
);
1104 mach
->Declarations
= NULL
;
1105 mach
->NumDeclarations
= 0;
1107 FREE(mach
->Instructions
);
1108 mach
->Instructions
= NULL
;
1109 mach
->NumInstructions
= 0;
1114 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1115 if (k
!= TGSI_PARSE_OK
) {
1116 debug_printf( "Problem parsing!\n" );
1121 mach
->NumOutputs
= 0;
1123 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1124 mach
->SysSemanticToIndex
[k
] = -1;
1126 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1127 !mach
->UsedGeometryShader
) {
1128 struct tgsi_exec_vector
*inputs
;
1129 struct tgsi_exec_vector
*outputs
;
1131 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1132 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1138 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1139 TGSI_MAX_TOTAL_VERTICES
, 16);
1146 align_free(mach
->Inputs
);
1147 align_free(mach
->Outputs
);
1149 mach
->Inputs
= inputs
;
1150 mach
->Outputs
= outputs
;
1151 mach
->UsedGeometryShader
= TRUE
;
1154 declarations
= (struct tgsi_full_declaration
*)
1155 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1157 if (!declarations
) {
1161 instructions
= (struct tgsi_full_instruction
*)
1162 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1164 if (!instructions
) {
1165 FREE( declarations
);
1169 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1172 tgsi_parse_token( &parse
);
1173 switch( parse
.FullToken
.Token
.Type
) {
1174 case TGSI_TOKEN_TYPE_DECLARATION
:
1175 /* save expanded declaration */
1176 if (numDeclarations
== maxDeclarations
) {
1177 declarations
= REALLOC(declarations
,
1179 * sizeof(struct tgsi_full_declaration
),
1180 (maxDeclarations
+ 10)
1181 * sizeof(struct tgsi_full_declaration
));
1182 maxDeclarations
+= 10;
1184 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1186 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1187 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1192 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1193 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1194 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1197 memcpy(declarations
+ numDeclarations
,
1198 &parse
.FullToken
.FullDeclaration
,
1199 sizeof(declarations
[0]));
1203 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1205 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1206 assert( size
<= 4 );
1207 if (mach
->ImmLimit
>= mach
->ImmsReserved
) {
1208 unsigned newReserved
= mach
->ImmsReserved
? 2 * mach
->ImmsReserved
: 128;
1209 float4
*imms
= REALLOC(mach
->Imms
, mach
->ImmsReserved
, newReserved
* sizeof(float4
));
1211 mach
->ImmsReserved
= newReserved
;
1214 debug_printf("Unable to (re)allocate space for immidiate constants\n");
1219 for( i
= 0; i
< size
; i
++ ) {
1220 mach
->Imms
[mach
->ImmLimit
][i
] =
1221 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1223 mach
->ImmLimit
+= 1;
1227 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1229 /* save expanded instruction */
1230 if (numInstructions
== maxInstructions
) {
1231 instructions
= REALLOC(instructions
,
1233 * sizeof(struct tgsi_full_instruction
),
1234 (maxInstructions
+ 10)
1235 * sizeof(struct tgsi_full_instruction
));
1236 maxInstructions
+= 10;
1239 memcpy(instructions
+ numInstructions
,
1240 &parse
.FullToken
.FullInstruction
,
1241 sizeof(instructions
[0]));
1246 case TGSI_TOKEN_TYPE_PROPERTY
:
1247 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1248 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1249 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1258 tgsi_parse_free (&parse
);
1260 FREE(mach
->Declarations
);
1261 mach
->Declarations
= declarations
;
1262 mach
->NumDeclarations
= numDeclarations
;
1264 FREE(mach
->Instructions
);
1265 mach
->Instructions
= instructions
;
1266 mach
->NumInstructions
= numInstructions
;
1270 struct tgsi_exec_machine
*
1271 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1273 struct tgsi_exec_machine
*mach
;
1275 mach
= align_malloc( sizeof *mach
, 16 );
1279 memset(mach
, 0, sizeof(*mach
));
1281 mach
->ShaderType
= shader_type
;
1282 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1283 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1285 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1286 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1287 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1288 if (!mach
->Inputs
|| !mach
->Outputs
)
1292 if (shader_type
== PIPE_SHADER_FRAGMENT
) {
1293 mach
->InputSampleOffsetApply
= align_malloc(sizeof(apply_sample_offset_func
) * PIPE_MAX_SHADER_INPUTS
, 16);
1294 if (!mach
->InputSampleOffsetApply
)
1299 /* silence warnings */
1308 align_free(mach
->InputSampleOffsetApply
);
1309 align_free(mach
->Inputs
);
1310 align_free(mach
->Outputs
);
1318 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1321 FREE(mach
->Instructions
);
1322 FREE(mach
->Declarations
);
1325 align_free(mach
->InputSampleOffsetApply
);
1326 align_free(mach
->Inputs
);
1327 align_free(mach
->Outputs
);
1334 micro_add(union tgsi_exec_channel
*dst
,
1335 const union tgsi_exec_channel
*src0
,
1336 const union tgsi_exec_channel
*src1
)
1338 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1339 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1340 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1341 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1346 union tgsi_exec_channel
*dst
,
1347 const union tgsi_exec_channel
*src0
,
1348 const union tgsi_exec_channel
*src1
)
1350 if (src1
->f
[0] != 0) {
1351 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1353 if (src1
->f
[1] != 0) {
1354 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1356 if (src1
->f
[2] != 0) {
1357 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1359 if (src1
->f
[3] != 0) {
1360 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1366 union tgsi_exec_channel
*dst
,
1367 const union tgsi_exec_channel
*src0
,
1368 const union tgsi_exec_channel
*src1
,
1369 const union tgsi_exec_channel
*src2
,
1370 const union tgsi_exec_channel
*src3
)
1372 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1373 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1374 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1375 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1379 micro_max(union tgsi_exec_channel
*dst
,
1380 const union tgsi_exec_channel
*src0
,
1381 const union tgsi_exec_channel
*src1
)
1383 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1384 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1385 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1386 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1390 micro_min(union tgsi_exec_channel
*dst
,
1391 const union tgsi_exec_channel
*src0
,
1392 const union tgsi_exec_channel
*src1
)
1394 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1395 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1396 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1397 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1401 micro_mul(union tgsi_exec_channel
*dst
,
1402 const union tgsi_exec_channel
*src0
,
1403 const union tgsi_exec_channel
*src1
)
1405 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1406 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1407 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1408 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1413 union tgsi_exec_channel
*dst
,
1414 const union tgsi_exec_channel
*src
)
1416 dst
->f
[0] = -src
->f
[0];
1417 dst
->f
[1] = -src
->f
[1];
1418 dst
->f
[2] = -src
->f
[2];
1419 dst
->f
[3] = -src
->f
[3];
1424 union tgsi_exec_channel
*dst
,
1425 const union tgsi_exec_channel
*src0
,
1426 const union tgsi_exec_channel
*src1
)
1429 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1430 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1431 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1432 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1434 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1435 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1436 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1437 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1442 micro_ldexp(union tgsi_exec_channel
*dst
,
1443 const union tgsi_exec_channel
*src0
,
1444 const union tgsi_exec_channel
*src1
)
1446 dst
->f
[0] = ldexpf(src0
->f
[0], src1
->i
[0]);
1447 dst
->f
[1] = ldexpf(src0
->f
[1], src1
->i
[1]);
1448 dst
->f
[2] = ldexpf(src0
->f
[2], src1
->i
[2]);
1449 dst
->f
[3] = ldexpf(src0
->f
[3], src1
->i
[3]);
1453 micro_sub(union tgsi_exec_channel
*dst
,
1454 const union tgsi_exec_channel
*src0
,
1455 const union tgsi_exec_channel
*src1
)
1457 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1458 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1459 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1460 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1464 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1467 const union tgsi_exec_channel
*index
,
1468 const union tgsi_exec_channel
*index2D
,
1469 union tgsi_exec_channel
*chan
)
1473 assert(swizzle
< 4);
1476 case TGSI_FILE_CONSTANT
:
1477 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1478 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1479 assert(mach
->Consts
[index2D
->i
[i
]]);
1481 if (index
->i
[i
] < 0) {
1484 /* NOTE: copying the const value as a uint instead of float */
1485 const uint constbuf
= index2D
->i
[i
];
1486 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1487 const int pos
= index
->i
[i
] * 4 + swizzle
;
1488 /* const buffer bounds check */
1489 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1491 /* Debug: print warning */
1492 static int count
= 0;
1494 debug_printf("TGSI Exec: const buffer index %d"
1495 " out of bounds\n", pos
);
1500 chan
->u
[i
] = buf
[pos
];
1505 case TGSI_FILE_INPUT
:
1506 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1508 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1509 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1510 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1511 index2D->i[i], index->i[i]);
1513 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1515 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1516 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1520 case TGSI_FILE_SYSTEM_VALUE
:
1521 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1522 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1526 case TGSI_FILE_TEMPORARY
:
1527 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1528 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1529 assert(index2D
->i
[i
] == 0);
1531 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1535 case TGSI_FILE_IMMEDIATE
:
1536 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1537 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1538 assert(index2D
->i
[i
] == 0);
1540 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1544 case TGSI_FILE_ADDRESS
:
1545 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1546 assert(index
->i
[i
] >= 0);
1547 assert(index2D
->i
[i
] == 0);
1549 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1553 case TGSI_FILE_OUTPUT
:
1554 /* vertex/fragment output vars can be read too */
1555 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1556 assert(index
->i
[i
] >= 0);
1557 assert(index2D
->i
[i
] == 0);
1559 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1565 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1572 get_index_registers(const struct tgsi_exec_machine
*mach
,
1573 const struct tgsi_full_src_register
*reg
,
1574 union tgsi_exec_channel
*index
,
1575 union tgsi_exec_channel
*index2D
)
1579 /* We start with a direct index into a register file.
1583 * file = Register.File
1584 * [1] = Register.Index
1589 index
->i
[3] = reg
->Register
.Index
;
1591 /* There is an extra source register that indirectly subscripts
1592 * a register file. The direct index now becomes an offset
1593 * that is being added to the indirect register.
1597 * ind = Indirect.File
1598 * [2] = Indirect.Index
1599 * .x = Indirect.SwizzleX
1601 if (reg
->Register
.Indirect
) {
1602 union tgsi_exec_channel index2
;
1603 union tgsi_exec_channel indir_index
;
1604 const uint execmask
= mach
->ExecMask
;
1607 /* which address register (always zero now) */
1611 index2
.i
[3] = reg
->Indirect
.Index
;
1612 /* get current value of address register[swizzle] */
1613 swizzle
= reg
->Indirect
.Swizzle
;
1614 fetch_src_file_channel(mach
,
1621 /* add value of address register to the offset */
1622 index
->i
[0] += indir_index
.i
[0];
1623 index
->i
[1] += indir_index
.i
[1];
1624 index
->i
[2] += indir_index
.i
[2];
1625 index
->i
[3] += indir_index
.i
[3];
1627 /* for disabled execution channels, zero-out the index to
1628 * avoid using a potential garbage value.
1630 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1631 if ((execmask
& (1 << i
)) == 0)
1636 /* There is an extra source register that is a second
1637 * subscript to a register file. Effectively it means that
1638 * the register file is actually a 2D array of registers.
1642 * [3] = Dimension.Index
1644 if (reg
->Register
.Dimension
) {
1648 index2D
->i
[3] = reg
->Dimension
.Index
;
1650 /* Again, the second subscript index can be addressed indirectly
1651 * identically to the first one.
1652 * Nothing stops us from indirectly addressing the indirect register,
1653 * but there is no need for that, so we won't exercise it.
1655 * file[ind[4].y+3][1],
1657 * ind = DimIndirect.File
1658 * [4] = DimIndirect.Index
1659 * .y = DimIndirect.SwizzleX
1661 if (reg
->Dimension
.Indirect
) {
1662 union tgsi_exec_channel index2
;
1663 union tgsi_exec_channel indir_index
;
1664 const uint execmask
= mach
->ExecMask
;
1670 index2
.i
[3] = reg
->DimIndirect
.Index
;
1672 swizzle
= reg
->DimIndirect
.Swizzle
;
1673 fetch_src_file_channel(mach
,
1674 reg
->DimIndirect
.File
,
1680 index2D
->i
[0] += indir_index
.i
[0];
1681 index2D
->i
[1] += indir_index
.i
[1];
1682 index2D
->i
[2] += indir_index
.i
[2];
1683 index2D
->i
[3] += indir_index
.i
[3];
1685 /* for disabled execution channels, zero-out the index to
1686 * avoid using a potential garbage value.
1688 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1689 if ((execmask
& (1 << i
)) == 0) {
1695 /* If by any chance there was a need for a 3D array of register
1696 * files, we would have to check whether Dimension is followed
1697 * by a dimension register and continue the saga.
1709 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1710 union tgsi_exec_channel
*chan
,
1711 const struct tgsi_full_src_register
*reg
,
1712 const uint chan_index
)
1714 union tgsi_exec_channel index
;
1715 union tgsi_exec_channel index2D
;
1718 get_index_registers(mach
, reg
, &index
, &index2D
);
1721 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1722 fetch_src_file_channel(mach
,
1731 fetch_source(const struct tgsi_exec_machine
*mach
,
1732 union tgsi_exec_channel
*chan
,
1733 const struct tgsi_full_src_register
*reg
,
1734 const uint chan_index
,
1735 enum tgsi_exec_datatype src_datatype
)
1737 fetch_source_d(mach
, chan
, reg
, chan_index
);
1739 if (reg
->Register
.Absolute
) {
1740 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1741 micro_abs(chan
, chan
);
1743 micro_iabs(chan
, chan
);
1747 if (reg
->Register
.Negate
) {
1748 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1749 micro_neg(chan
, chan
);
1751 micro_ineg(chan
, chan
);
1756 static union tgsi_exec_channel
*
1757 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1758 const union tgsi_exec_channel
*chan
,
1759 const struct tgsi_full_dst_register
*reg
,
1761 enum tgsi_exec_datatype dst_datatype
)
1763 static union tgsi_exec_channel null
;
1764 union tgsi_exec_channel
*dst
;
1765 union tgsi_exec_channel index2D
;
1766 int offset
= 0; /* indirection offset */
1770 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1771 check_inf_or_nan(chan
);
1774 /* There is an extra source register that indirectly subscripts
1775 * a register file. The direct index now becomes an offset
1776 * that is being added to the indirect register.
1780 * ind = Indirect.File
1781 * [2] = Indirect.Index
1782 * .x = Indirect.SwizzleX
1784 if (reg
->Register
.Indirect
) {
1785 union tgsi_exec_channel index
;
1786 union tgsi_exec_channel indir_index
;
1789 /* which address register (always zero for now) */
1793 index
.i
[3] = reg
->Indirect
.Index
;
1795 /* get current value of address register[swizzle] */
1796 swizzle
= reg
->Indirect
.Swizzle
;
1798 /* fetch values from the address/indirection register */
1799 fetch_src_file_channel(mach
,
1806 /* save indirection offset */
1807 offset
= indir_index
.i
[0];
1810 /* There is an extra source register that is a second
1811 * subscript to a register file. Effectively it means that
1812 * the register file is actually a 2D array of registers.
1816 * [3] = Dimension.Index
1818 if (reg
->Register
.Dimension
) {
1822 index2D
.i
[3] = reg
->Dimension
.Index
;
1824 /* Again, the second subscript index can be addressed indirectly
1825 * identically to the first one.
1826 * Nothing stops us from indirectly addressing the indirect register,
1827 * but there is no need for that, so we won't exercise it.
1829 * file[ind[4].y+3][1],
1831 * ind = DimIndirect.File
1832 * [4] = DimIndirect.Index
1833 * .y = DimIndirect.SwizzleX
1835 if (reg
->Dimension
.Indirect
) {
1836 union tgsi_exec_channel index2
;
1837 union tgsi_exec_channel indir_index
;
1838 const uint execmask
= mach
->ExecMask
;
1845 index2
.i
[3] = reg
->DimIndirect
.Index
;
1847 swizzle
= reg
->DimIndirect
.Swizzle
;
1848 fetch_src_file_channel(mach
,
1849 reg
->DimIndirect
.File
,
1855 index2D
.i
[0] += indir_index
.i
[0];
1856 index2D
.i
[1] += indir_index
.i
[1];
1857 index2D
.i
[2] += indir_index
.i
[2];
1858 index2D
.i
[3] += indir_index
.i
[3];
1860 /* for disabled execution channels, zero-out the index to
1861 * avoid using a potential garbage value.
1863 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1864 if ((execmask
& (1 << i
)) == 0) {
1870 /* If by any chance there was a need for a 3D array of register
1871 * files, we would have to check whether Dimension is followed
1872 * by a dimension register and continue the saga.
1881 switch (reg
->Register
.File
) {
1882 case TGSI_FILE_NULL
:
1886 case TGSI_FILE_OUTPUT
:
1887 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1888 + reg
->Register
.Index
;
1889 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1891 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1892 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1893 reg
->Register
.Index
);
1894 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1895 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1896 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1897 if (execmask
& (1 << i
))
1898 debug_printf("%f, ", chan
->f
[i
]);
1899 debug_printf(")\n");
1904 case TGSI_FILE_TEMPORARY
:
1905 index
= reg
->Register
.Index
;
1906 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1907 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1910 case TGSI_FILE_ADDRESS
:
1911 index
= reg
->Register
.Index
;
1912 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1924 store_dest_double(struct tgsi_exec_machine
*mach
,
1925 const union tgsi_exec_channel
*chan
,
1926 const struct tgsi_full_dst_register
*reg
,
1928 enum tgsi_exec_datatype dst_datatype
)
1930 union tgsi_exec_channel
*dst
;
1931 const uint execmask
= mach
->ExecMask
;
1934 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1939 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1940 if (execmask
& (1 << i
))
1941 dst
->i
[i
] = chan
->i
[i
];
1945 store_dest(struct tgsi_exec_machine
*mach
,
1946 const union tgsi_exec_channel
*chan
,
1947 const struct tgsi_full_dst_register
*reg
,
1948 const struct tgsi_full_instruction
*inst
,
1950 enum tgsi_exec_datatype dst_datatype
)
1952 union tgsi_exec_channel
*dst
;
1953 const uint execmask
= mach
->ExecMask
;
1956 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1960 if (!inst
->Instruction
.Saturate
) {
1961 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1962 if (execmask
& (1 << i
))
1963 dst
->i
[i
] = chan
->i
[i
];
1966 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1967 if (execmask
& (1 << i
)) {
1968 if (chan
->f
[i
] < 0.0f
)
1970 else if (chan
->f
[i
] > 1.0f
)
1973 dst
->i
[i
] = chan
->i
[i
];
1978 #define FETCH(VAL,INDEX,CHAN)\
1979 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1981 #define IFETCH(VAL,INDEX,CHAN)\
1982 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1986 * Execute ARB-style KIL which is predicated by a src register.
1987 * Kill fragment if any of the four values is less than zero.
1990 exec_kill_if(struct tgsi_exec_machine
*mach
,
1991 const struct tgsi_full_instruction
*inst
)
1995 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1996 union tgsi_exec_channel r
[1];
1998 /* This mask stores component bits that were already tested. */
2001 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2006 /* unswizzle channel */
2007 swizzle
= tgsi_util_get_full_src_register_swizzle (
2011 /* check if the component has not been already tested */
2012 if (uniquemask
& (1 << swizzle
))
2014 uniquemask
|= 1 << swizzle
;
2016 FETCH(&r
[0], 0, chan_index
);
2017 for (i
= 0; i
< 4; i
++)
2018 if (r
[0].f
[i
] < 0.0f
)
2022 /* restrict to fragments currently executing */
2023 kilmask
&= mach
->ExecMask
;
2025 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2029 * Unconditional fragment kill/discard.
2032 exec_kill(struct tgsi_exec_machine
*mach
)
2034 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2036 /* kill fragment for all fragments currently executing */
2037 kilmask
= mach
->ExecMask
;
2038 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2042 emit_vertex(struct tgsi_exec_machine
*mach
,
2043 const struct tgsi_full_instruction
*inst
)
2045 union tgsi_exec_channel r
[1];
2047 unsigned *prim_count
;
2048 /* FIXME: check for exec mask correctly
2050 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2051 if ((mach->ExecMask & (1 << i)))
2053 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2054 stream_id
= r
[0].u
[0];
2055 prim_count
= &mach
->Temps
[temp_prim_idxs
[stream_id
].idx
].xyzw
[temp_prim_idxs
[stream_id
].chan
].u
[0];
2056 if (mach
->ExecMask
) {
2057 if (mach
->Primitives
[stream_id
][*prim_count
] >= mach
->MaxOutputVertices
)
2060 if (mach
->Primitives
[stream_id
][*prim_count
] == 0)
2061 mach
->PrimitiveOffsets
[stream_id
][*prim_count
] = mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0];
2062 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2063 mach
->Primitives
[stream_id
][*prim_count
]++;
2068 emit_primitive(struct tgsi_exec_machine
*mach
,
2069 const struct tgsi_full_instruction
*inst
)
2071 unsigned *prim_count
;
2072 union tgsi_exec_channel r
[1];
2073 unsigned stream_id
= 0;
2074 /* FIXME: check for exec mask correctly
2076 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2077 if ((mach->ExecMask & (1 << i)))
2080 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2081 stream_id
= r
[0].u
[0];
2083 prim_count
= &mach
->Temps
[temp_prim_idxs
[stream_id
].idx
].xyzw
[temp_prim_idxs
[stream_id
].chan
].u
[0];
2084 if (mach
->ExecMask
) {
2086 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2087 mach
->Primitives
[stream_id
][*prim_count
] = 0;
2092 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2094 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2096 mach
->Primitives
[0][mach
->Temps
[temp_prim_idxs
[0].idx
].xyzw
[temp_prim_idxs
[0].chan
].u
[0]];
2097 if (emitted_verts
) {
2098 emit_primitive(mach
, NULL
);
2105 * Fetch four texture samples using STR texture coordinates.
2108 fetch_texel( struct tgsi_sampler
*sampler
,
2109 const unsigned sview_idx
,
2110 const unsigned sampler_idx
,
2111 const union tgsi_exec_channel
*s
,
2112 const union tgsi_exec_channel
*t
,
2113 const union tgsi_exec_channel
*p
,
2114 const union tgsi_exec_channel
*c0
,
2115 const union tgsi_exec_channel
*c1
,
2116 float derivs
[3][2][TGSI_QUAD_SIZE
],
2117 const int8_t offset
[3],
2118 enum tgsi_sampler_control control
,
2119 union tgsi_exec_channel
*r
,
2120 union tgsi_exec_channel
*g
,
2121 union tgsi_exec_channel
*b
,
2122 union tgsi_exec_channel
*a
)
2125 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2127 /* FIXME: handle explicit derivs, offsets */
2128 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2129 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2131 for (j
= 0; j
< 4; j
++) {
2132 r
->f
[j
] = rgba
[0][j
];
2133 g
->f
[j
] = rgba
[1][j
];
2134 b
->f
[j
] = rgba
[2][j
];
2135 a
->f
[j
] = rgba
[3][j
];
2140 #define TEX_MODIFIER_NONE 0
2141 #define TEX_MODIFIER_PROJECTED 1
2142 #define TEX_MODIFIER_LOD_BIAS 2
2143 #define TEX_MODIFIER_EXPLICIT_LOD 3
2144 #define TEX_MODIFIER_LEVEL_ZERO 4
2145 #define TEX_MODIFIER_GATHER 5
2148 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2151 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2152 const struct tgsi_full_instruction
*inst
,
2155 if (inst
->Texture
.NumOffsets
== 1) {
2156 union tgsi_exec_channel index
;
2157 union tgsi_exec_channel offset
[3];
2158 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2159 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2160 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2161 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2162 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2163 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2164 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2165 offsets
[0] = offset
[0].i
[0];
2166 offsets
[1] = offset
[1].i
[0];
2167 offsets
[2] = offset
[2].i
[0];
2169 assert(inst
->Texture
.NumOffsets
== 0);
2170 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2176 * Fetch dx and dy values for one channel (s, t or r).
2177 * Put dx values into one float array, dy values into another.
2180 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2181 const struct tgsi_full_instruction
*inst
,
2184 float derivs
[2][TGSI_QUAD_SIZE
])
2186 union tgsi_exec_channel d
;
2187 FETCH(&d
, regdsrcx
, chan
);
2188 derivs
[0][0] = d
.f
[0];
2189 derivs
[0][1] = d
.f
[1];
2190 derivs
[0][2] = d
.f
[2];
2191 derivs
[0][3] = d
.f
[3];
2192 FETCH(&d
, regdsrcx
+ 1, chan
);
2193 derivs
[1][0] = d
.f
[0];
2194 derivs
[1][1] = d
.f
[1];
2195 derivs
[1][2] = d
.f
[2];
2196 derivs
[1][3] = d
.f
[3];
2200 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2201 const struct tgsi_full_instruction
*inst
,
2206 if (inst
->Src
[sampler
].Register
.Indirect
) {
2207 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2208 union tgsi_exec_channel indir_index
, index2
;
2209 const uint execmask
= mach
->ExecMask
;
2213 index2
.i
[3] = reg
->Indirect
.Index
;
2215 fetch_src_file_channel(mach
,
2217 reg
->Indirect
.Swizzle
,
2221 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2222 if (execmask
& (1 << i
)) {
2223 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2229 unit
= inst
->Src
[sampler
].Register
.Index
;
2235 * execute a texture instruction.
2237 * modifier is used to control the channel routing for the
2238 * instruction variants like proj, lod, and texture with lod bias.
2239 * sampler indicates which src register the sampler is contained in.
2242 exec_tex(struct tgsi_exec_machine
*mach
,
2243 const struct tgsi_full_instruction
*inst
,
2244 uint modifier
, uint sampler
)
2246 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2247 union tgsi_exec_channel r
[5];
2248 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2252 int dim
, shadow_ref
, i
;
2254 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2255 /* always fetch all 3 offsets, overkill but keeps code simple */
2256 fetch_texel_offsets(mach
, inst
, offsets
);
2258 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2259 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2261 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2262 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2265 if (shadow_ref
>= 0)
2266 assert(shadow_ref
>= dim
&& shadow_ref
< (int)ARRAY_SIZE(args
));
2268 /* fetch modifier to the last argument */
2269 if (modifier
!= TEX_MODIFIER_NONE
) {
2270 const int last
= ARRAY_SIZE(args
) - 1;
2272 /* fetch modifier from src0.w or src1.x */
2274 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2275 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2278 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2281 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2282 args
[last
] = &r
[last
];
2286 args
[last
] = &ZeroVec
;
2289 /* point unused arguments to zero vector */
2290 for (i
= dim
; i
< last
; i
++)
2293 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2294 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2295 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2296 control
= TGSI_SAMPLER_LOD_BIAS
;
2297 else if (modifier
== TEX_MODIFIER_GATHER
)
2298 control
= TGSI_SAMPLER_GATHER
;
2301 for (i
= dim
; i
< (int)ARRAY_SIZE(args
); i
++)
2305 /* fetch coordinates */
2306 for (i
= 0; i
< dim
; i
++) {
2307 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2310 micro_div(&r
[i
], &r
[i
], proj
);
2315 /* fetch reference value */
2316 if (shadow_ref
>= 0) {
2317 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2320 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2322 args
[shadow_ref
] = &r
[shadow_ref
];
2325 fetch_texel(mach
->Sampler
, unit
, unit
,
2326 args
[0], args
[1], args
[2], args
[3], args
[4],
2327 NULL
, offsets
, control
,
2328 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2331 debug_printf("fetch r: %g %g %g %g\n",
2332 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2333 debug_printf("fetch g: %g %g %g %g\n",
2334 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2335 debug_printf("fetch b: %g %g %g %g\n",
2336 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2337 debug_printf("fetch a: %g %g %g %g\n",
2338 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2341 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2342 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2343 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2349 exec_lodq(struct tgsi_exec_machine
*mach
,
2350 const struct tgsi_full_instruction
*inst
)
2352 uint resource_unit
, sampler_unit
;
2355 union tgsi_exec_channel coords
[4];
2356 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2357 union tgsi_exec_channel r
[2];
2359 resource_unit
= fetch_sampler_unit(mach
, inst
, 1);
2360 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2361 uint target
= mach
->SamplerViews
[resource_unit
].Resource
;
2362 dim
= tgsi_util_get_texture_coord_dim(target
);
2363 sampler_unit
= fetch_sampler_unit(mach
, inst
, 2);
2365 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2366 sampler_unit
= resource_unit
;
2368 assert(dim
<= ARRAY_SIZE(coords
));
2369 /* fetch coordinates */
2370 for (i
= 0; i
< dim
; i
++) {
2371 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2372 args
[i
] = &coords
[i
];
2374 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2377 mach
->Sampler
->query_lod(mach
->Sampler
, resource_unit
, sampler_unit
,
2382 TGSI_SAMPLER_LOD_NONE
,
2386 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2387 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2388 TGSI_EXEC_DATA_FLOAT
);
2390 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2391 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2392 TGSI_EXEC_DATA_FLOAT
);
2394 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2395 unsigned char swizzles
[4];
2397 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2398 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2399 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2400 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2402 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2403 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2404 if (swizzles
[chan
] >= 2) {
2405 store_dest(mach
, &ZeroVec
,
2406 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2408 store_dest(mach
, &r
[swizzles
[chan
]],
2409 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2414 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2415 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2416 TGSI_EXEC_DATA_FLOAT
);
2418 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2419 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2420 TGSI_EXEC_DATA_FLOAT
);
2426 exec_txd(struct tgsi_exec_machine
*mach
,
2427 const struct tgsi_full_instruction
*inst
)
2429 union tgsi_exec_channel r
[4];
2430 float derivs
[3][2][TGSI_QUAD_SIZE
];
2435 unit
= fetch_sampler_unit(mach
, inst
, 3);
2436 /* always fetch all 3 offsets, overkill but keeps code simple */
2437 fetch_texel_offsets(mach
, inst
, offsets
);
2439 switch (inst
->Texture
.Texture
) {
2440 case TGSI_TEXTURE_1D
:
2441 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2443 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2445 fetch_texel(mach
->Sampler
, unit
, unit
,
2446 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2447 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2448 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2451 case TGSI_TEXTURE_SHADOW1D
:
2452 case TGSI_TEXTURE_1D_ARRAY
:
2453 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2454 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2455 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2456 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2457 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2459 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2461 fetch_texel(mach
->Sampler
, unit
, unit
,
2462 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2463 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2464 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2467 case TGSI_TEXTURE_2D
:
2468 case TGSI_TEXTURE_RECT
:
2469 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2470 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2472 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2473 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2475 fetch_texel(mach
->Sampler
, unit
, unit
,
2476 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2477 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2478 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2482 case TGSI_TEXTURE_SHADOW2D
:
2483 case TGSI_TEXTURE_SHADOWRECT
:
2484 case TGSI_TEXTURE_2D_ARRAY
:
2485 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2486 /* only SHADOW2D_ARRAY actually needs W */
2487 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2488 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2489 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2490 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2492 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2493 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2495 fetch_texel(mach
->Sampler
, unit
, unit
,
2496 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2497 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2498 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2501 case TGSI_TEXTURE_3D
:
2502 case TGSI_TEXTURE_CUBE
:
2503 case TGSI_TEXTURE_CUBE_ARRAY
:
2504 case TGSI_TEXTURE_SHADOWCUBE
:
2505 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2506 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2507 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2508 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2509 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2511 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2512 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2513 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2515 fetch_texel(mach
->Sampler
, unit
, unit
,
2516 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2517 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2518 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2525 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2526 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2527 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2534 exec_txf(struct tgsi_exec_machine
*mach
,
2535 const struct tgsi_full_instruction
*inst
)
2537 union tgsi_exec_channel r
[4];
2540 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2545 unit
= fetch_sampler_unit(mach
, inst
, 1);
2546 /* always fetch all 3 offsets, overkill but keeps code simple */
2547 fetch_texel_offsets(mach
, inst
, offsets
);
2549 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2551 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2552 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2553 target
= mach
->SamplerViews
[unit
].Resource
;
2556 target
= inst
->Texture
.Texture
;
2559 case TGSI_TEXTURE_3D
:
2560 case TGSI_TEXTURE_2D_ARRAY
:
2561 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2562 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2563 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2565 case TGSI_TEXTURE_2D
:
2566 case TGSI_TEXTURE_RECT
:
2567 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2568 case TGSI_TEXTURE_SHADOW2D
:
2569 case TGSI_TEXTURE_SHADOWRECT
:
2570 case TGSI_TEXTURE_1D_ARRAY
:
2571 case TGSI_TEXTURE_2D_MSAA
:
2572 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2574 case TGSI_TEXTURE_BUFFER
:
2575 case TGSI_TEXTURE_1D
:
2576 case TGSI_TEXTURE_SHADOW1D
:
2577 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2584 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2587 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2588 r
[0].f
[j
] = rgba
[0][j
];
2589 r
[1].f
[j
] = rgba
[1][j
];
2590 r
[2].f
[j
] = rgba
[2][j
];
2591 r
[3].f
[j
] = rgba
[3][j
];
2594 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2595 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2596 unsigned char swizzles
[4];
2597 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2598 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2599 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2600 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2602 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2603 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2604 store_dest(mach
, &r
[swizzles
[chan
]],
2605 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2610 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2611 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2612 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2619 exec_txq(struct tgsi_exec_machine
*mach
,
2620 const struct tgsi_full_instruction
*inst
)
2623 union tgsi_exec_channel r
[4], src
;
2628 unit
= fetch_sampler_unit(mach
, inst
, 1);
2630 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2632 /* XXX: This interface can't return per-pixel values */
2633 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2635 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2636 for (j
= 0; j
< 4; j
++) {
2637 r
[j
].i
[i
] = result
[j
];
2641 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2642 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2643 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2644 TGSI_EXEC_DATA_INT
);
2650 exec_sample(struct tgsi_exec_machine
*mach
,
2651 const struct tgsi_full_instruction
*inst
,
2652 uint modifier
, boolean compare
)
2654 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2655 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2656 union tgsi_exec_channel r
[5], c1
;
2657 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2658 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2660 unsigned char swizzles
[4];
2663 /* always fetch all 3 offsets, overkill but keeps code simple */
2664 fetch_texel_offsets(mach
, inst
, offsets
);
2666 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2668 if (modifier
!= TEX_MODIFIER_NONE
) {
2669 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2670 FETCH(&c1
, 3, TGSI_CHAN_X
);
2672 control
= TGSI_SAMPLER_LOD_BIAS
;
2674 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2675 FETCH(&c1
, 3, TGSI_CHAN_X
);
2677 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2679 else if (modifier
== TEX_MODIFIER_GATHER
) {
2680 control
= TGSI_SAMPLER_GATHER
;
2683 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2684 control
= TGSI_SAMPLER_LOD_ZERO
;
2688 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2690 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2691 case TGSI_TEXTURE_1D
:
2693 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2694 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2695 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2696 NULL
, offsets
, control
,
2697 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2700 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2701 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2702 NULL
, offsets
, control
,
2703 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2707 case TGSI_TEXTURE_1D_ARRAY
:
2708 case TGSI_TEXTURE_2D
:
2709 case TGSI_TEXTURE_RECT
:
2710 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2712 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2713 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2714 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2715 NULL
, offsets
, control
,
2716 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2719 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2720 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2721 NULL
, offsets
, control
,
2722 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2726 case TGSI_TEXTURE_2D_ARRAY
:
2727 case TGSI_TEXTURE_3D
:
2728 case TGSI_TEXTURE_CUBE
:
2729 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2730 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2732 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2733 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2734 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2735 NULL
, offsets
, control
,
2736 &r
[0], &r
[1], &r
[2], &r
[3]);
2739 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2740 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2741 NULL
, offsets
, control
,
2742 &r
[0], &r
[1], &r
[2], &r
[3]);
2746 case TGSI_TEXTURE_CUBE_ARRAY
:
2747 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2748 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2749 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2751 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2752 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2753 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2754 NULL
, offsets
, control
,
2755 &r
[0], &r
[1], &r
[2], &r
[3]);
2758 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2759 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2760 NULL
, offsets
, control
,
2761 &r
[0], &r
[1], &r
[2], &r
[3]);
2770 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2771 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2772 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2773 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2775 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2776 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2777 store_dest(mach
, &r
[swizzles
[chan
]],
2778 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2784 exec_sample_d(struct tgsi_exec_machine
*mach
,
2785 const struct tgsi_full_instruction
*inst
)
2787 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2788 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2789 union tgsi_exec_channel r
[4];
2790 float derivs
[3][2][TGSI_QUAD_SIZE
];
2792 unsigned char swizzles
[4];
2795 /* always fetch all 3 offsets, overkill but keeps code simple */
2796 fetch_texel_offsets(mach
, inst
, offsets
);
2798 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2800 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2801 case TGSI_TEXTURE_1D
:
2802 case TGSI_TEXTURE_1D_ARRAY
:
2803 /* only 1D array actually needs Y */
2804 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2806 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2808 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2809 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2810 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2811 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2814 case TGSI_TEXTURE_2D
:
2815 case TGSI_TEXTURE_RECT
:
2816 case TGSI_TEXTURE_2D_ARRAY
:
2817 /* only 2D array actually needs Z */
2818 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2819 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2821 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2822 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2824 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2825 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2826 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2827 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2830 case TGSI_TEXTURE_3D
:
2831 case TGSI_TEXTURE_CUBE
:
2832 case TGSI_TEXTURE_CUBE_ARRAY
:
2833 /* only cube array actually needs W */
2834 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2835 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2836 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2838 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2839 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2840 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2842 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2843 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2844 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2845 &r
[0], &r
[1], &r
[2], &r
[3]);
2852 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2853 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2854 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2855 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2857 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2858 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2859 store_dest(mach
, &r
[swizzles
[chan
]],
2860 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2867 * Evaluate a constant-valued coefficient at the position of the
2872 struct tgsi_exec_machine
*mach
,
2878 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2879 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2884 interp_constant_offset(
2885 UNUSED
const struct tgsi_exec_machine
*mach
,
2886 UNUSED
unsigned attrib
,
2887 UNUSED
unsigned chan
,
2890 UNUSED
union tgsi_exec_channel
*out_chan
)
2895 * Evaluate a linear-valued coefficient at the position of the
2899 interp_linear_offset(
2900 const struct tgsi_exec_machine
*mach
,
2905 union tgsi_exec_channel
*out_chan
)
2907 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2908 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2909 const float delta
= ofs_x
* dadx
+ ofs_y
* dady
;
2910 out_chan
->f
[0] += delta
;
2911 out_chan
->f
[1] += delta
;
2912 out_chan
->f
[2] += delta
;
2913 out_chan
->f
[3] += delta
;
2917 eval_linear_coef(struct tgsi_exec_machine
*mach
,
2921 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2922 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2923 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2924 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2925 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2927 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2928 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2929 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2930 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2934 * Evaluate a perspective-valued coefficient at the position of the
2939 interp_perspective_offset(
2940 const struct tgsi_exec_machine
*mach
,
2945 union tgsi_exec_channel
*out_chan
)
2947 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2948 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2949 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2950 const float delta
= ofs_x
* dadx
+ ofs_y
* dady
;
2951 out_chan
->f
[0] += delta
/ w
[0];
2952 out_chan
->f
[1] += delta
/ w
[1];
2953 out_chan
->f
[2] += delta
/ w
[2];
2954 out_chan
->f
[3] += delta
/ w
[3];
2958 eval_perspective_coef(
2959 struct tgsi_exec_machine
*mach
,
2963 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2964 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2965 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2966 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2967 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2968 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2969 /* divide by W here */
2970 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2971 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2972 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2973 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2977 typedef void (* eval_coef_func
)(
2978 struct tgsi_exec_machine
*mach
,
2983 exec_declaration(struct tgsi_exec_machine
*mach
,
2984 const struct tgsi_full_declaration
*decl
)
2986 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2987 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2991 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2992 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2993 uint first
, last
, mask
;
2995 first
= decl
->Range
.First
;
2996 last
= decl
->Range
.Last
;
2997 mask
= decl
->Declaration
.UsageMask
;
2999 /* XXX we could remove this special-case code since
3000 * mach->InterpCoefs[first].a0 should already have the
3001 * front/back-face value. But we should first update the
3002 * ureg code to emit the right UsageMask value (WRITEMASK_X).
3003 * Then, we could remove the tgsi_exec_machine::Face field.
3005 /* XXX make FACE a system value */
3006 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
3009 assert(decl
->Semantic
.Index
== 0);
3010 assert(first
== last
);
3012 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3013 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
3016 eval_coef_func eval
;
3017 apply_sample_offset_func interp
;
3020 switch (decl
->Interp
.Interpolate
) {
3021 case TGSI_INTERPOLATE_CONSTANT
:
3022 eval
= eval_constant_coef
;
3023 interp
= interp_constant_offset
;
3026 case TGSI_INTERPOLATE_LINEAR
:
3027 eval
= eval_linear_coef
;
3028 interp
= interp_linear_offset
;
3031 case TGSI_INTERPOLATE_PERSPECTIVE
:
3032 eval
= eval_perspective_coef
;
3033 interp
= interp_perspective_offset
;
3036 case TGSI_INTERPOLATE_COLOR
:
3037 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
3038 interp
= mach
->flatshade_color
? interp_constant_offset
: interp_perspective_offset
;
3046 for (i
= first
; i
<= last
; i
++)
3047 mach
->InputSampleOffsetApply
[i
] = interp
;
3049 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3050 if (mask
& (1 << j
)) {
3051 for (i
= first
; i
<= last
; i
++) {
3058 if (DEBUG_EXECUTION
) {
3060 for (i
= first
; i
<= last
; ++i
) {
3061 debug_printf("IN[%2u] = ", i
);
3062 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3066 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3067 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
3068 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
3069 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
3070 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
3079 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
3080 const union tgsi_exec_channel
*src
);
3083 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
3084 const struct tgsi_full_instruction
*inst
,
3086 enum tgsi_exec_datatype dst_datatype
,
3087 enum tgsi_exec_datatype src_datatype
)
3090 union tgsi_exec_channel src
;
3091 union tgsi_exec_channel dst
;
3093 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3095 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3096 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3097 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3103 exec_vector_unary(struct tgsi_exec_machine
*mach
,
3104 const struct tgsi_full_instruction
*inst
,
3106 enum tgsi_exec_datatype dst_datatype
,
3107 enum tgsi_exec_datatype src_datatype
)
3110 struct tgsi_exec_vector dst
;
3112 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3113 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3114 union tgsi_exec_channel src
;
3116 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3117 op(&dst
.xyzw
[chan
], &src
);
3120 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3121 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3122 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3127 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3128 const union tgsi_exec_channel
*src0
,
3129 const union tgsi_exec_channel
*src1
);
3132 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3133 const struct tgsi_full_instruction
*inst
,
3135 enum tgsi_exec_datatype dst_datatype
,
3136 enum tgsi_exec_datatype src_datatype
)
3139 union tgsi_exec_channel src
[2];
3140 union tgsi_exec_channel dst
;
3142 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3143 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3144 op(&dst
, &src
[0], &src
[1]);
3145 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3146 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3147 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3153 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3154 const struct tgsi_full_instruction
*inst
,
3156 enum tgsi_exec_datatype dst_datatype
,
3157 enum tgsi_exec_datatype src_datatype
)
3160 struct tgsi_exec_vector dst
;
3162 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3163 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3164 union tgsi_exec_channel src
[2];
3166 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3167 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3168 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3171 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3172 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3173 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3178 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3179 const union tgsi_exec_channel
*src0
,
3180 const union tgsi_exec_channel
*src1
,
3181 const union tgsi_exec_channel
*src2
);
3184 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3185 const struct tgsi_full_instruction
*inst
,
3186 micro_trinary_op op
,
3187 enum tgsi_exec_datatype dst_datatype
,
3188 enum tgsi_exec_datatype src_datatype
)
3191 struct tgsi_exec_vector dst
;
3193 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3194 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3195 union tgsi_exec_channel src
[3];
3197 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3198 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3199 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3200 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3203 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3204 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3205 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3210 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3211 const union tgsi_exec_channel
*src0
,
3212 const union tgsi_exec_channel
*src1
,
3213 const union tgsi_exec_channel
*src2
,
3214 const union tgsi_exec_channel
*src3
);
3217 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3218 const struct tgsi_full_instruction
*inst
,
3219 micro_quaternary_op op
,
3220 enum tgsi_exec_datatype dst_datatype
,
3221 enum tgsi_exec_datatype src_datatype
)
3224 struct tgsi_exec_vector dst
;
3226 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3227 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3228 union tgsi_exec_channel src
[4];
3230 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3231 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3232 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3233 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3234 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3237 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3238 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3239 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3245 exec_dp3(struct tgsi_exec_machine
*mach
,
3246 const struct tgsi_full_instruction
*inst
)
3249 union tgsi_exec_channel arg
[3];
3251 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3252 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3253 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3255 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3256 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3257 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3258 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3261 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3262 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3263 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3269 exec_dp4(struct tgsi_exec_machine
*mach
,
3270 const struct tgsi_full_instruction
*inst
)
3273 union tgsi_exec_channel arg
[3];
3275 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3276 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3277 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3279 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3280 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3281 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3282 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3285 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3286 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3287 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3293 exec_dp2(struct tgsi_exec_machine
*mach
,
3294 const struct tgsi_full_instruction
*inst
)
3297 union tgsi_exec_channel arg
[3];
3299 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3300 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3301 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3303 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3304 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3305 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3307 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3308 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3309 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3315 exec_pk2h(struct tgsi_exec_machine
*mach
,
3316 const struct tgsi_full_instruction
*inst
)
3319 union tgsi_exec_channel arg
[2], dst
;
3321 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3322 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3323 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3324 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3325 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3327 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3328 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3329 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3335 exec_up2h(struct tgsi_exec_machine
*mach
,
3336 const struct tgsi_full_instruction
*inst
)
3339 union tgsi_exec_channel arg
, dst
[2];
3341 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3342 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3343 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3344 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3346 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3347 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3348 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3354 micro_ucmp(union tgsi_exec_channel
*dst
,
3355 const union tgsi_exec_channel
*src0
,
3356 const union tgsi_exec_channel
*src1
,
3357 const union tgsi_exec_channel
*src2
)
3359 dst
->f
[0] = src0
->u
[0] ? src1
->f
[0] : src2
->f
[0];
3360 dst
->f
[1] = src0
->u
[1] ? src1
->f
[1] : src2
->f
[1];
3361 dst
->f
[2] = src0
->u
[2] ? src1
->f
[2] : src2
->f
[2];
3362 dst
->f
[3] = src0
->u
[3] ? src1
->f
[3] : src2
->f
[3];
3366 exec_ucmp(struct tgsi_exec_machine
*mach
,
3367 const struct tgsi_full_instruction
*inst
)
3370 struct tgsi_exec_vector dst
;
3372 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3373 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3374 union tgsi_exec_channel src
[3];
3376 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
,
3377 TGSI_EXEC_DATA_UINT
);
3378 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
,
3379 TGSI_EXEC_DATA_FLOAT
);
3380 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
,
3381 TGSI_EXEC_DATA_FLOAT
);
3382 micro_ucmp(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3385 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3386 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3387 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
,
3388 TGSI_EXEC_DATA_FLOAT
);
3394 exec_dst(struct tgsi_exec_machine
*mach
,
3395 const struct tgsi_full_instruction
*inst
)
3397 union tgsi_exec_channel r
[2];
3398 union tgsi_exec_channel d
[4];
3400 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3401 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3402 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3403 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3405 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3406 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3408 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3409 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3412 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3413 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3415 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3416 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3418 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3419 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3421 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3422 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3427 exec_log(struct tgsi_exec_machine
*mach
,
3428 const struct tgsi_full_instruction
*inst
)
3430 union tgsi_exec_channel r
[3];
3432 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3433 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3434 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3435 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3436 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3437 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3439 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3440 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3441 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3442 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3444 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3445 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3447 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3448 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3453 exec_exp(struct tgsi_exec_machine
*mach
,
3454 const struct tgsi_full_instruction
*inst
)
3456 union tgsi_exec_channel r
[3];
3458 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3459 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3460 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3461 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3462 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3464 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3465 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3466 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3468 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3469 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3470 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3472 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3473 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3478 exec_lit(struct tgsi_exec_machine
*mach
,
3479 const struct tgsi_full_instruction
*inst
)
3481 union tgsi_exec_channel r
[3];
3482 union tgsi_exec_channel d
[3];
3484 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3485 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3486 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3487 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3488 micro_max(&r
[1], &r
[1], &ZeroVec
);
3490 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3491 micro_min(&r
[2], &r
[2], &P128Vec
);
3492 micro_max(&r
[2], &r
[2], &M128Vec
);
3493 micro_pow(&r
[1], &r
[1], &r
[2]);
3494 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3495 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3497 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3498 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3499 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3502 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3503 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3506 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3507 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3512 exec_break(struct tgsi_exec_machine
*mach
)
3514 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3515 /* turn off loop channels for each enabled exec channel */
3516 mach
->LoopMask
&= ~mach
->ExecMask
;
3517 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3518 UPDATE_EXEC_MASK(mach
);
3520 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3522 mach
->Switch
.mask
= 0x0;
3524 UPDATE_EXEC_MASK(mach
);
3529 exec_switch(struct tgsi_exec_machine
*mach
,
3530 const struct tgsi_full_instruction
*inst
)
3532 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3533 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3535 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3536 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3537 mach
->Switch
.mask
= 0x0;
3538 mach
->Switch
.defaultMask
= 0x0;
3540 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3541 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3543 UPDATE_EXEC_MASK(mach
);
3547 exec_case(struct tgsi_exec_machine
*mach
,
3548 const struct tgsi_full_instruction
*inst
)
3550 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3551 union tgsi_exec_channel src
;
3554 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3556 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3559 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3562 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3565 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3569 mach
->Switch
.defaultMask
|= mask
;
3571 mach
->Switch
.mask
|= mask
& prevMask
;
3573 UPDATE_EXEC_MASK(mach
);
3576 /* FIXME: this will only work if default is last */
3578 exec_default(struct tgsi_exec_machine
*mach
)
3580 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3582 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3584 UPDATE_EXEC_MASK(mach
);
3588 exec_endswitch(struct tgsi_exec_machine
*mach
)
3590 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3591 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3593 UPDATE_EXEC_MASK(mach
);
3596 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3597 const union tgsi_double_channel
*src
);
3599 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3600 const union tgsi_double_channel
*src0
,
3601 union tgsi_exec_channel
*src1
);
3603 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3604 const union tgsi_exec_channel
*src
);
3606 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3607 const union tgsi_double_channel
*src
);
3610 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3611 union tgsi_double_channel
*chan
,
3612 const struct tgsi_full_src_register
*reg
,
3616 union tgsi_exec_channel src
[2];
3619 fetch_source_d(mach
, &src
[0], reg
, chan_0
);
3620 fetch_source_d(mach
, &src
[1], reg
, chan_1
);
3622 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3623 chan
->u
[i
][0] = src
[0].u
[i
];
3624 chan
->u
[i
][1] = src
[1].u
[i
];
3626 if (reg
->Register
.Absolute
) {
3627 micro_dabs(chan
, chan
);
3629 if (reg
->Register
.Negate
) {
3630 micro_dneg(chan
, chan
);
3635 store_double_channel(struct tgsi_exec_machine
*mach
,
3636 const union tgsi_double_channel
*chan
,
3637 const struct tgsi_full_dst_register
*reg
,
3638 const struct tgsi_full_instruction
*inst
,
3642 union tgsi_exec_channel dst
[2];
3644 union tgsi_double_channel temp
;
3645 const uint execmask
= mach
->ExecMask
;
3647 if (!inst
->Instruction
.Saturate
) {
3648 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3649 if (execmask
& (1 << i
)) {
3650 dst
[0].u
[i
] = chan
->u
[i
][0];
3651 dst
[1].u
[i
] = chan
->u
[i
][1];
3655 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3656 if (execmask
& (1 << i
)) {
3657 if (chan
->d
[i
] < 0.0)
3659 else if (chan
->d
[i
] > 1.0)
3662 temp
.d
[i
] = chan
->d
[i
];
3664 dst
[0].u
[i
] = temp
.u
[i
][0];
3665 dst
[1].u
[i
] = temp
.u
[i
][1];
3669 store_dest_double(mach
, &dst
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3670 if (chan_1
!= (unsigned)-1)
3671 store_dest_double(mach
, &dst
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3675 exec_double_unary(struct tgsi_exec_machine
*mach
,
3676 const struct tgsi_full_instruction
*inst
,
3679 union tgsi_double_channel src
;
3680 union tgsi_double_channel dst
;
3682 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3683 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3685 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3687 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3688 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3690 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3695 exec_double_binary(struct tgsi_exec_machine
*mach
,
3696 const struct tgsi_full_instruction
*inst
,
3698 enum tgsi_exec_datatype dst_datatype
)
3700 union tgsi_double_channel src
[2];
3701 union tgsi_double_channel dst
;
3702 int first_dest_chan
, second_dest_chan
;
3705 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3706 /* these are & because of the way DSLT etc store their destinations */
3707 if (wmask
& TGSI_WRITEMASK_XY
) {
3708 first_dest_chan
= TGSI_CHAN_X
;
3709 second_dest_chan
= TGSI_CHAN_Y
;
3710 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3711 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3712 second_dest_chan
= -1;
3715 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3716 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3718 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3721 if (wmask
& TGSI_WRITEMASK_ZW
) {
3722 first_dest_chan
= TGSI_CHAN_Z
;
3723 second_dest_chan
= TGSI_CHAN_W
;
3724 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3725 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3726 second_dest_chan
= -1;
3729 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3730 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3732 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3737 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3738 const struct tgsi_full_instruction
*inst
,
3741 union tgsi_double_channel src
[3];
3742 union tgsi_double_channel dst
;
3744 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3745 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3746 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3747 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3749 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3751 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3752 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3753 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3754 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3756 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3761 exec_dldexp(struct tgsi_exec_machine
*mach
,
3762 const struct tgsi_full_instruction
*inst
)
3764 union tgsi_double_channel src0
;
3765 union tgsi_exec_channel src1
;
3766 union tgsi_double_channel dst
;
3769 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3770 if (wmask
& TGSI_WRITEMASK_XY
) {
3771 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3772 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3773 micro_dldexp(&dst
, &src0
, &src1
);
3774 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3777 if (wmask
& TGSI_WRITEMASK_ZW
) {
3778 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3779 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3780 micro_dldexp(&dst
, &src0
, &src1
);
3781 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3786 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3787 const struct tgsi_full_instruction
*inst
)
3789 union tgsi_double_channel src
;
3790 union tgsi_double_channel dst
;
3791 union tgsi_exec_channel dst_exp
;
3793 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3794 micro_dfracexp(&dst
, &dst_exp
, &src
);
3795 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)
3796 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3797 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)
3798 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3799 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3800 if (inst
->Dst
[1].Register
.WriteMask
& (1 << chan
))
3801 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, chan
, TGSI_EXEC_DATA_INT
);
3806 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3807 const struct tgsi_full_instruction
*inst
,
3810 union tgsi_double_channel src0
;
3811 union tgsi_exec_channel src1
;
3812 union tgsi_double_channel dst
;
3815 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3816 if (wmask
& TGSI_WRITEMASK_XY
) {
3817 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3818 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3819 op(&dst
, &src0
, &src1
);
3820 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3823 if (wmask
& TGSI_WRITEMASK_ZW
) {
3824 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3825 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3826 op(&dst
, &src0
, &src1
);
3827 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3832 get_image_coord_dim(unsigned tgsi_tex
)
3836 case TGSI_TEXTURE_BUFFER
:
3837 case TGSI_TEXTURE_1D
:
3840 case TGSI_TEXTURE_2D
:
3841 case TGSI_TEXTURE_RECT
:
3842 case TGSI_TEXTURE_1D_ARRAY
:
3843 case TGSI_TEXTURE_2D_MSAA
:
3846 case TGSI_TEXTURE_3D
:
3847 case TGSI_TEXTURE_CUBE
:
3848 case TGSI_TEXTURE_2D_ARRAY
:
3849 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3850 case TGSI_TEXTURE_CUBE_ARRAY
:
3854 assert(!"unknown texture target");
3863 get_image_coord_sample(unsigned tgsi_tex
)
3867 case TGSI_TEXTURE_2D_MSAA
:
3870 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3880 exec_load_img(struct tgsi_exec_machine
*mach
,
3881 const struct tgsi_full_instruction
*inst
)
3883 union tgsi_exec_channel r
[4], sample_r
;
3889 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3890 struct tgsi_image_params params
;
3891 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3893 unit
= fetch_sampler_unit(mach
, inst
, 0);
3894 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3895 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3898 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3900 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3901 params
.format
= inst
->Memory
.Format
;
3903 for (i
= 0; i
< dim
; i
++) {
3904 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3908 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3910 mach
->Image
->load(mach
->Image
, ¶ms
,
3911 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3913 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3914 r
[0].f
[j
] = rgba
[0][j
];
3915 r
[1].f
[j
] = rgba
[1][j
];
3916 r
[2].f
[j
] = rgba
[2][j
];
3917 r
[3].f
[j
] = rgba
[3][j
];
3919 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3920 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3921 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3927 exec_load_buf(struct tgsi_exec_machine
*mach
,
3928 const struct tgsi_full_instruction
*inst
)
3930 union tgsi_exec_channel r
[4];
3934 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3935 struct tgsi_buffer_params params
;
3936 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3938 unit
= fetch_sampler_unit(mach
, inst
, 0);
3940 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3942 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3944 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3946 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3947 r
[0].f
[j
] = rgba
[0][j
];
3948 r
[1].f
[j
] = rgba
[1][j
];
3949 r
[2].f
[j
] = rgba
[2][j
];
3950 r
[3].f
[j
] = rgba
[3][j
];
3952 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3953 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3954 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3960 exec_load_mem(struct tgsi_exec_machine
*mach
,
3961 const struct tgsi_full_instruction
*inst
)
3963 union tgsi_exec_channel r
[4];
3965 char *ptr
= mach
->LocalMem
;
3969 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3970 if (r
[0].u
[0] >= mach
->LocalMemSize
)
3976 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3977 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3978 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3979 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
3984 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3985 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3986 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3992 exec_load(struct tgsi_exec_machine
*mach
,
3993 const struct tgsi_full_instruction
*inst
)
3995 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
3996 exec_load_img(mach
, inst
);
3997 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
3998 exec_load_buf(mach
, inst
);
3999 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4000 exec_load_mem(mach
, inst
);
4004 fetch_store_img_unit(struct tgsi_exec_machine
*mach
,
4005 const struct tgsi_full_dst_register
*dst
)
4009 if (dst
->Register
.Indirect
) {
4010 union tgsi_exec_channel indir_index
, index2
;
4011 const uint execmask
= mach
->ExecMask
;
4015 index2
.i
[3] = dst
->Indirect
.Index
;
4017 fetch_src_file_channel(mach
,
4019 dst
->Indirect
.Swizzle
,
4023 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4024 if (execmask
& (1 << i
)) {
4025 unit
= dst
->Register
.Index
+ indir_index
.i
[i
];
4030 unit
= dst
->Register
.Index
;
4036 exec_store_img(struct tgsi_exec_machine
*mach
,
4037 const struct tgsi_full_instruction
*inst
)
4039 union tgsi_exec_channel r
[3], sample_r
;
4040 union tgsi_exec_channel value
[4];
4041 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4042 struct tgsi_image_params params
;
4047 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4048 unit
= fetch_store_img_unit(mach
, &inst
->Dst
[0]);
4049 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4050 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4053 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4055 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4056 params
.format
= inst
->Memory
.Format
;
4058 for (i
= 0; i
< dim
; i
++) {
4059 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
4062 for (i
= 0; i
< 4; i
++) {
4063 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4066 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
4068 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4069 rgba
[0][j
] = value
[0].f
[j
];
4070 rgba
[1][j
] = value
[1].f
[j
];
4071 rgba
[2][j
] = value
[2].f
[j
];
4072 rgba
[3][j
] = value
[3].f
[j
];
4075 mach
->Image
->store(mach
->Image
, ¶ms
,
4076 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4081 exec_store_buf(struct tgsi_exec_machine
*mach
,
4082 const struct tgsi_full_instruction
*inst
)
4084 union tgsi_exec_channel r
[3];
4085 union tgsi_exec_channel value
[4];
4086 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4087 struct tgsi_buffer_params params
;
4090 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4092 unit
= fetch_store_img_unit(mach
, &inst
->Dst
[0]);
4094 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4096 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4098 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4099 for (i
= 0; i
< 4; i
++) {
4100 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4103 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4104 rgba
[0][j
] = value
[0].f
[j
];
4105 rgba
[1][j
] = value
[1].f
[j
];
4106 rgba
[2][j
] = value
[2].f
[j
];
4107 rgba
[3][j
] = value
[3].f
[j
];
4110 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4116 exec_store_mem(struct tgsi_exec_machine
*mach
,
4117 const struct tgsi_full_instruction
*inst
)
4119 union tgsi_exec_channel r
[3];
4120 union tgsi_exec_channel value
[4];
4122 char *ptr
= mach
->LocalMem
;
4123 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4124 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4126 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4128 for (i
= 0; i
< 4; i
++) {
4129 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4132 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4136 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4137 if (execmask
& (1 << i
)) {
4138 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4139 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4140 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4148 exec_store(struct tgsi_exec_machine
*mach
,
4149 const struct tgsi_full_instruction
*inst
)
4151 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4152 exec_store_img(mach
, inst
);
4153 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4154 exec_store_buf(mach
, inst
);
4155 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4156 exec_store_mem(mach
, inst
);
4160 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4161 const struct tgsi_full_instruction
*inst
)
4163 union tgsi_exec_channel r
[4], sample_r
;
4164 union tgsi_exec_channel value
[4], value2
[4];
4165 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4166 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4167 struct tgsi_image_params params
;
4172 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4173 unit
= fetch_sampler_unit(mach
, inst
, 0);
4174 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4175 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4178 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4180 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4181 params
.format
= inst
->Memory
.Format
;
4183 for (i
= 0; i
< dim
; i
++) {
4184 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4187 for (i
= 0; i
< 4; i
++) {
4188 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4189 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4190 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4193 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4195 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4196 rgba
[0][j
] = value
[0].f
[j
];
4197 rgba
[1][j
] = value
[1].f
[j
];
4198 rgba
[2][j
] = value
[2].f
[j
];
4199 rgba
[3][j
] = value
[3].f
[j
];
4201 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4202 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4203 rgba2
[0][j
] = value2
[0].f
[j
];
4204 rgba2
[1][j
] = value2
[1].f
[j
];
4205 rgba2
[2][j
] = value2
[2].f
[j
];
4206 rgba2
[3][j
] = value2
[3].f
[j
];
4210 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4211 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4214 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4215 r
[0].f
[j
] = rgba
[0][j
];
4216 r
[1].f
[j
] = rgba
[1][j
];
4217 r
[2].f
[j
] = rgba
[2][j
];
4218 r
[3].f
[j
] = rgba
[3][j
];
4220 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4221 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4222 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4228 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4229 const struct tgsi_full_instruction
*inst
)
4231 union tgsi_exec_channel r
[4];
4232 union tgsi_exec_channel value
[4], value2
[4];
4233 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4234 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4235 struct tgsi_buffer_params params
;
4238 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4240 unit
= fetch_sampler_unit(mach
, inst
, 0);
4242 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4244 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4246 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4248 for (i
= 0; i
< 4; i
++) {
4249 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4250 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4251 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4254 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4255 rgba
[0][j
] = value
[0].f
[j
];
4256 rgba
[1][j
] = value
[1].f
[j
];
4257 rgba
[2][j
] = value
[2].f
[j
];
4258 rgba
[3][j
] = value
[3].f
[j
];
4260 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4261 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4262 rgba2
[0][j
] = value2
[0].f
[j
];
4263 rgba2
[1][j
] = value2
[1].f
[j
];
4264 rgba2
[2][j
] = value2
[2].f
[j
];
4265 rgba2
[3][j
] = value2
[3].f
[j
];
4269 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4273 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4274 r
[0].f
[j
] = rgba
[0][j
];
4275 r
[1].f
[j
] = rgba
[1][j
];
4276 r
[2].f
[j
] = rgba
[2][j
];
4277 r
[3].f
[j
] = rgba
[3][j
];
4279 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4280 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4281 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4287 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4288 const struct tgsi_full_instruction
*inst
)
4290 union tgsi_exec_channel r
[4];
4291 union tgsi_exec_channel value
[4], value2
[4];
4292 char *ptr
= mach
->LocalMem
;
4296 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4297 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4298 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4300 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4305 for (i
= 0; i
< 4; i
++) {
4306 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4307 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4308 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4311 memcpy(&r
[0].u
[0], ptr
, 4);
4313 switch (inst
->Instruction
.Opcode
) {
4314 case TGSI_OPCODE_ATOMUADD
:
4315 val
+= value
[0].u
[0];
4317 case TGSI_OPCODE_ATOMXOR
:
4318 val
^= value
[0].u
[0];
4320 case TGSI_OPCODE_ATOMOR
:
4321 val
|= value
[0].u
[0];
4323 case TGSI_OPCODE_ATOMAND
:
4324 val
&= value
[0].u
[0];
4326 case TGSI_OPCODE_ATOMUMIN
:
4327 val
= MIN2(val
, value
[0].u
[0]);
4329 case TGSI_OPCODE_ATOMUMAX
:
4330 val
= MAX2(val
, value
[0].u
[0]);
4332 case TGSI_OPCODE_ATOMIMIN
:
4333 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4335 case TGSI_OPCODE_ATOMIMAX
:
4336 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4338 case TGSI_OPCODE_ATOMXCHG
:
4339 val
= value
[0].i
[0];
4341 case TGSI_OPCODE_ATOMCAS
:
4342 if (val
== value
[0].u
[0])
4343 val
= value2
[0].u
[0];
4345 case TGSI_OPCODE_ATOMFADD
:
4346 val
= fui(r
[0].f
[0] + value
[0].f
[0]);
4351 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4352 if (execmask
& (1 << i
))
4353 memcpy(ptr
, &val
, 4);
4355 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4356 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4357 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4363 exec_atomop(struct tgsi_exec_machine
*mach
,
4364 const struct tgsi_full_instruction
*inst
)
4366 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4367 exec_atomop_img(mach
, inst
);
4368 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4369 exec_atomop_buf(mach
, inst
);
4370 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4371 exec_atomop_mem(mach
, inst
);
4375 exec_resq_img(struct tgsi_exec_machine
*mach
,
4376 const struct tgsi_full_instruction
*inst
)
4379 union tgsi_exec_channel r
[4];
4382 struct tgsi_image_params params
;
4383 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4385 unit
= fetch_sampler_unit(mach
, inst
, 0);
4387 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4389 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4390 params
.format
= inst
->Memory
.Format
;
4392 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4394 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4395 for (j
= 0; j
< 4; j
++) {
4396 r
[j
].i
[i
] = result
[j
];
4400 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4401 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4402 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4403 TGSI_EXEC_DATA_INT
);
4409 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4410 const struct tgsi_full_instruction
*inst
)
4413 union tgsi_exec_channel r
[4];
4416 struct tgsi_buffer_params params
;
4417 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4419 unit
= fetch_sampler_unit(mach
, inst
, 0);
4421 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4424 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4426 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4430 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4431 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4432 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4433 TGSI_EXEC_DATA_INT
);
4439 exec_resq(struct tgsi_exec_machine
*mach
,
4440 const struct tgsi_full_instruction
*inst
)
4442 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4443 exec_resq_img(mach
, inst
);
4445 exec_resq_buf(mach
, inst
);
4449 micro_f2u64(union tgsi_double_channel
*dst
,
4450 const union tgsi_exec_channel
*src
)
4452 dst
->u64
[0] = (uint64_t)src
->f
[0];
4453 dst
->u64
[1] = (uint64_t)src
->f
[1];
4454 dst
->u64
[2] = (uint64_t)src
->f
[2];
4455 dst
->u64
[3] = (uint64_t)src
->f
[3];
4459 micro_f2i64(union tgsi_double_channel
*dst
,
4460 const union tgsi_exec_channel
*src
)
4462 dst
->i64
[0] = (int64_t)src
->f
[0];
4463 dst
->i64
[1] = (int64_t)src
->f
[1];
4464 dst
->i64
[2] = (int64_t)src
->f
[2];
4465 dst
->i64
[3] = (int64_t)src
->f
[3];
4469 micro_u2i64(union tgsi_double_channel
*dst
,
4470 const union tgsi_exec_channel
*src
)
4472 dst
->u64
[0] = (uint64_t)src
->u
[0];
4473 dst
->u64
[1] = (uint64_t)src
->u
[1];
4474 dst
->u64
[2] = (uint64_t)src
->u
[2];
4475 dst
->u64
[3] = (uint64_t)src
->u
[3];
4479 micro_i2i64(union tgsi_double_channel
*dst
,
4480 const union tgsi_exec_channel
*src
)
4482 dst
->i64
[0] = (int64_t)src
->i
[0];
4483 dst
->i64
[1] = (int64_t)src
->i
[1];
4484 dst
->i64
[2] = (int64_t)src
->i
[2];
4485 dst
->i64
[3] = (int64_t)src
->i
[3];
4489 micro_d2u64(union tgsi_double_channel
*dst
,
4490 const union tgsi_double_channel
*src
)
4492 dst
->u64
[0] = (uint64_t)src
->d
[0];
4493 dst
->u64
[1] = (uint64_t)src
->d
[1];
4494 dst
->u64
[2] = (uint64_t)src
->d
[2];
4495 dst
->u64
[3] = (uint64_t)src
->d
[3];
4499 micro_d2i64(union tgsi_double_channel
*dst
,
4500 const union tgsi_double_channel
*src
)
4502 dst
->i64
[0] = (int64_t)src
->d
[0];
4503 dst
->i64
[1] = (int64_t)src
->d
[1];
4504 dst
->i64
[2] = (int64_t)src
->d
[2];
4505 dst
->i64
[3] = (int64_t)src
->d
[3];
4509 micro_u642d(union tgsi_double_channel
*dst
,
4510 const union tgsi_double_channel
*src
)
4512 dst
->d
[0] = (double)src
->u64
[0];
4513 dst
->d
[1] = (double)src
->u64
[1];
4514 dst
->d
[2] = (double)src
->u64
[2];
4515 dst
->d
[3] = (double)src
->u64
[3];
4519 micro_i642d(union tgsi_double_channel
*dst
,
4520 const union tgsi_double_channel
*src
)
4522 dst
->d
[0] = (double)src
->i64
[0];
4523 dst
->d
[1] = (double)src
->i64
[1];
4524 dst
->d
[2] = (double)src
->i64
[2];
4525 dst
->d
[3] = (double)src
->i64
[3];
4529 micro_u642f(union tgsi_exec_channel
*dst
,
4530 const union tgsi_double_channel
*src
)
4532 dst
->f
[0] = (float)src
->u64
[0];
4533 dst
->f
[1] = (float)src
->u64
[1];
4534 dst
->f
[2] = (float)src
->u64
[2];
4535 dst
->f
[3] = (float)src
->u64
[3];
4539 micro_i642f(union tgsi_exec_channel
*dst
,
4540 const union tgsi_double_channel
*src
)
4542 dst
->f
[0] = (float)src
->i64
[0];
4543 dst
->f
[1] = (float)src
->i64
[1];
4544 dst
->f
[2] = (float)src
->i64
[2];
4545 dst
->f
[3] = (float)src
->i64
[3];
4549 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4550 const struct tgsi_full_instruction
*inst
,
4552 enum tgsi_exec_datatype src_datatype
)
4554 union tgsi_exec_channel src
;
4555 union tgsi_double_channel dst
;
4557 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4558 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4560 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4562 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4563 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4565 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4570 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4571 const struct tgsi_full_instruction
*inst
,
4573 enum tgsi_exec_datatype dst_datatype
)
4575 union tgsi_double_channel src
;
4576 union tgsi_exec_channel dst
;
4577 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4580 for (i
= 0; i
< 2; i
++) {
4583 wm
&= ~(1 << (bit
- 1));
4585 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4587 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4589 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4595 micro_i2f(union tgsi_exec_channel
*dst
,
4596 const union tgsi_exec_channel
*src
)
4598 dst
->f
[0] = (float)src
->i
[0];
4599 dst
->f
[1] = (float)src
->i
[1];
4600 dst
->f
[2] = (float)src
->i
[2];
4601 dst
->f
[3] = (float)src
->i
[3];
4605 micro_not(union tgsi_exec_channel
*dst
,
4606 const union tgsi_exec_channel
*src
)
4608 dst
->u
[0] = ~src
->u
[0];
4609 dst
->u
[1] = ~src
->u
[1];
4610 dst
->u
[2] = ~src
->u
[2];
4611 dst
->u
[3] = ~src
->u
[3];
4615 micro_shl(union tgsi_exec_channel
*dst
,
4616 const union tgsi_exec_channel
*src0
,
4617 const union tgsi_exec_channel
*src1
)
4619 unsigned masked_count
;
4620 masked_count
= src1
->u
[0] & 0x1f;
4621 dst
->u
[0] = src0
->u
[0] << masked_count
;
4622 masked_count
= src1
->u
[1] & 0x1f;
4623 dst
->u
[1] = src0
->u
[1] << masked_count
;
4624 masked_count
= src1
->u
[2] & 0x1f;
4625 dst
->u
[2] = src0
->u
[2] << masked_count
;
4626 masked_count
= src1
->u
[3] & 0x1f;
4627 dst
->u
[3] = src0
->u
[3] << masked_count
;
4631 micro_and(union tgsi_exec_channel
*dst
,
4632 const union tgsi_exec_channel
*src0
,
4633 const union tgsi_exec_channel
*src1
)
4635 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4636 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4637 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4638 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4642 micro_or(union tgsi_exec_channel
*dst
,
4643 const union tgsi_exec_channel
*src0
,
4644 const union tgsi_exec_channel
*src1
)
4646 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4647 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4648 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4649 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4653 micro_xor(union tgsi_exec_channel
*dst
,
4654 const union tgsi_exec_channel
*src0
,
4655 const union tgsi_exec_channel
*src1
)
4657 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4658 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4659 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4660 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4664 micro_mod(union tgsi_exec_channel
*dst
,
4665 const union tgsi_exec_channel
*src0
,
4666 const union tgsi_exec_channel
*src1
)
4668 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] % src1
->i
[0] : ~0;
4669 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] % src1
->i
[1] : ~0;
4670 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] % src1
->i
[2] : ~0;
4671 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] % src1
->i
[3] : ~0;
4675 micro_f2i(union tgsi_exec_channel
*dst
,
4676 const union tgsi_exec_channel
*src
)
4678 dst
->i
[0] = (int)src
->f
[0];
4679 dst
->i
[1] = (int)src
->f
[1];
4680 dst
->i
[2] = (int)src
->f
[2];
4681 dst
->i
[3] = (int)src
->f
[3];
4685 micro_fseq(union tgsi_exec_channel
*dst
,
4686 const union tgsi_exec_channel
*src0
,
4687 const union tgsi_exec_channel
*src1
)
4689 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4690 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4691 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4692 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4696 micro_fsge(union tgsi_exec_channel
*dst
,
4697 const union tgsi_exec_channel
*src0
,
4698 const union tgsi_exec_channel
*src1
)
4700 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4701 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4702 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4703 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4707 micro_fslt(union tgsi_exec_channel
*dst
,
4708 const union tgsi_exec_channel
*src0
,
4709 const union tgsi_exec_channel
*src1
)
4711 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4712 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4713 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4714 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4718 micro_fsne(union tgsi_exec_channel
*dst
,
4719 const union tgsi_exec_channel
*src0
,
4720 const union tgsi_exec_channel
*src1
)
4722 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4723 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4724 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4725 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4729 micro_idiv(union tgsi_exec_channel
*dst
,
4730 const union tgsi_exec_channel
*src0
,
4731 const union tgsi_exec_channel
*src1
)
4733 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4734 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4735 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4736 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4740 micro_imax(union tgsi_exec_channel
*dst
,
4741 const union tgsi_exec_channel
*src0
,
4742 const union tgsi_exec_channel
*src1
)
4744 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4745 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4746 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4747 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4751 micro_imin(union tgsi_exec_channel
*dst
,
4752 const union tgsi_exec_channel
*src0
,
4753 const union tgsi_exec_channel
*src1
)
4755 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4756 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4757 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4758 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4762 micro_isge(union tgsi_exec_channel
*dst
,
4763 const union tgsi_exec_channel
*src0
,
4764 const union tgsi_exec_channel
*src1
)
4766 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4767 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4768 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4769 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4773 micro_ishr(union tgsi_exec_channel
*dst
,
4774 const union tgsi_exec_channel
*src0
,
4775 const union tgsi_exec_channel
*src1
)
4777 unsigned masked_count
;
4778 masked_count
= src1
->i
[0] & 0x1f;
4779 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4780 masked_count
= src1
->i
[1] & 0x1f;
4781 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4782 masked_count
= src1
->i
[2] & 0x1f;
4783 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4784 masked_count
= src1
->i
[3] & 0x1f;
4785 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4789 micro_islt(union tgsi_exec_channel
*dst
,
4790 const union tgsi_exec_channel
*src0
,
4791 const union tgsi_exec_channel
*src1
)
4793 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4794 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4795 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4796 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4800 micro_f2u(union tgsi_exec_channel
*dst
,
4801 const union tgsi_exec_channel
*src
)
4803 dst
->u
[0] = (uint
)src
->f
[0];
4804 dst
->u
[1] = (uint
)src
->f
[1];
4805 dst
->u
[2] = (uint
)src
->f
[2];
4806 dst
->u
[3] = (uint
)src
->f
[3];
4810 micro_u2f(union tgsi_exec_channel
*dst
,
4811 const union tgsi_exec_channel
*src
)
4813 dst
->f
[0] = (float)src
->u
[0];
4814 dst
->f
[1] = (float)src
->u
[1];
4815 dst
->f
[2] = (float)src
->u
[2];
4816 dst
->f
[3] = (float)src
->u
[3];
4820 micro_uadd(union tgsi_exec_channel
*dst
,
4821 const union tgsi_exec_channel
*src0
,
4822 const union tgsi_exec_channel
*src1
)
4824 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4825 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4826 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4827 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4831 micro_udiv(union tgsi_exec_channel
*dst
,
4832 const union tgsi_exec_channel
*src0
,
4833 const union tgsi_exec_channel
*src1
)
4835 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4836 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4837 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4838 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4842 micro_umad(union tgsi_exec_channel
*dst
,
4843 const union tgsi_exec_channel
*src0
,
4844 const union tgsi_exec_channel
*src1
,
4845 const union tgsi_exec_channel
*src2
)
4847 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4848 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4849 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4850 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4854 micro_umax(union tgsi_exec_channel
*dst
,
4855 const union tgsi_exec_channel
*src0
,
4856 const union tgsi_exec_channel
*src1
)
4858 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4859 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4860 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4861 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4865 micro_umin(union tgsi_exec_channel
*dst
,
4866 const union tgsi_exec_channel
*src0
,
4867 const union tgsi_exec_channel
*src1
)
4869 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4870 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4871 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4872 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4876 micro_umod(union tgsi_exec_channel
*dst
,
4877 const union tgsi_exec_channel
*src0
,
4878 const union tgsi_exec_channel
*src1
)
4880 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4881 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4882 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4883 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4887 micro_umul(union tgsi_exec_channel
*dst
,
4888 const union tgsi_exec_channel
*src0
,
4889 const union tgsi_exec_channel
*src1
)
4891 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4892 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4893 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4894 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4898 micro_imul_hi(union tgsi_exec_channel
*dst
,
4899 const union tgsi_exec_channel
*src0
,
4900 const union tgsi_exec_channel
*src1
)
4902 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4903 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4904 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4905 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4906 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4911 micro_umul_hi(union tgsi_exec_channel
*dst
,
4912 const union tgsi_exec_channel
*src0
,
4913 const union tgsi_exec_channel
*src1
)
4915 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4916 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4917 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4918 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4919 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4924 micro_useq(union tgsi_exec_channel
*dst
,
4925 const union tgsi_exec_channel
*src0
,
4926 const union tgsi_exec_channel
*src1
)
4928 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4929 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4930 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4931 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4935 micro_usge(union tgsi_exec_channel
*dst
,
4936 const union tgsi_exec_channel
*src0
,
4937 const union tgsi_exec_channel
*src1
)
4939 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4940 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4941 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4942 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4946 micro_ushr(union tgsi_exec_channel
*dst
,
4947 const union tgsi_exec_channel
*src0
,
4948 const union tgsi_exec_channel
*src1
)
4950 unsigned masked_count
;
4951 masked_count
= src1
->u
[0] & 0x1f;
4952 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4953 masked_count
= src1
->u
[1] & 0x1f;
4954 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4955 masked_count
= src1
->u
[2] & 0x1f;
4956 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4957 masked_count
= src1
->u
[3] & 0x1f;
4958 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4962 micro_uslt(union tgsi_exec_channel
*dst
,
4963 const union tgsi_exec_channel
*src0
,
4964 const union tgsi_exec_channel
*src1
)
4966 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4967 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4968 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4969 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4973 micro_usne(union tgsi_exec_channel
*dst
,
4974 const union tgsi_exec_channel
*src0
,
4975 const union tgsi_exec_channel
*src1
)
4977 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4978 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4979 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4980 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4984 micro_uarl(union tgsi_exec_channel
*dst
,
4985 const union tgsi_exec_channel
*src
)
4987 dst
->i
[0] = src
->u
[0];
4988 dst
->i
[1] = src
->u
[1];
4989 dst
->i
[2] = src
->u
[2];
4990 dst
->i
[3] = src
->u
[3];
4994 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4997 micro_ibfe(union tgsi_exec_channel
*dst
,
4998 const union tgsi_exec_channel
*src0
,
4999 const union tgsi_exec_channel
*src1
,
5000 const union tgsi_exec_channel
*src2
)
5003 for (i
= 0; i
< 4; i
++) {
5004 int width
= src2
->i
[i
];
5005 int offset
= src1
->i
[i
] & 0x1f;
5006 if (width
== 32 && offset
== 0) {
5007 dst
->i
[i
] = src0
->i
[i
];
5013 else if (width
+ offset
< 32)
5014 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
5016 dst
->i
[i
] = src0
->i
[i
] >> offset
;
5021 * Unsigned bitfield extract
5024 micro_ubfe(union tgsi_exec_channel
*dst
,
5025 const union tgsi_exec_channel
*src0
,
5026 const union tgsi_exec_channel
*src1
,
5027 const union tgsi_exec_channel
*src2
)
5030 for (i
= 0; i
< 4; i
++) {
5031 int width
= src2
->u
[i
];
5032 int offset
= src1
->u
[i
] & 0x1f;
5033 if (width
== 32 && offset
== 0) {
5034 dst
->u
[i
] = src0
->u
[i
];
5040 else if (width
+ offset
< 32)
5041 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
5043 dst
->u
[i
] = src0
->u
[i
] >> offset
;
5048 * Bitfield insert: copy low bits from src1 into a region of src0.
5051 micro_bfi(union tgsi_exec_channel
*dst
,
5052 const union tgsi_exec_channel
*src0
,
5053 const union tgsi_exec_channel
*src1
,
5054 const union tgsi_exec_channel
*src2
,
5055 const union tgsi_exec_channel
*src3
)
5058 for (i
= 0; i
< 4; i
++) {
5059 int width
= src3
->u
[i
];
5060 int offset
= src2
->u
[i
] & 0x1f;
5062 dst
->u
[i
] = src1
->u
[i
];
5064 int bitmask
= ((1 << width
) - 1) << offset
;
5065 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
5071 micro_brev(union tgsi_exec_channel
*dst
,
5072 const union tgsi_exec_channel
*src
)
5074 dst
->u
[0] = util_bitreverse(src
->u
[0]);
5075 dst
->u
[1] = util_bitreverse(src
->u
[1]);
5076 dst
->u
[2] = util_bitreverse(src
->u
[2]);
5077 dst
->u
[3] = util_bitreverse(src
->u
[3]);
5081 micro_popc(union tgsi_exec_channel
*dst
,
5082 const union tgsi_exec_channel
*src
)
5084 dst
->u
[0] = util_bitcount(src
->u
[0]);
5085 dst
->u
[1] = util_bitcount(src
->u
[1]);
5086 dst
->u
[2] = util_bitcount(src
->u
[2]);
5087 dst
->u
[3] = util_bitcount(src
->u
[3]);
5091 micro_lsb(union tgsi_exec_channel
*dst
,
5092 const union tgsi_exec_channel
*src
)
5094 dst
->i
[0] = ffs(src
->u
[0]) - 1;
5095 dst
->i
[1] = ffs(src
->u
[1]) - 1;
5096 dst
->i
[2] = ffs(src
->u
[2]) - 1;
5097 dst
->i
[3] = ffs(src
->u
[3]) - 1;
5101 micro_imsb(union tgsi_exec_channel
*dst
,
5102 const union tgsi_exec_channel
*src
)
5104 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
5105 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
5106 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
5107 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
5111 micro_umsb(union tgsi_exec_channel
*dst
,
5112 const union tgsi_exec_channel
*src
)
5114 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
5115 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
5116 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5117 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5122 exec_interp_at_sample(struct tgsi_exec_machine
*mach
,
5123 const struct tgsi_full_instruction
*inst
)
5125 union tgsi_exec_channel index
;
5126 union tgsi_exec_channel index2D
;
5127 union tgsi_exec_channel result
[TGSI_NUM_CHANNELS
];
5128 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5130 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5131 assert(inst
->Src
[1].Register
.File
== TGSI_FILE_IMMEDIATE
);
5133 get_index_registers(mach
, reg
, &index
, &index2D
);
5134 float sample
= mach
->Imms
[inst
->Src
[1].Register
.Index
][inst
->Src
[1].Register
.SwizzleX
];
5136 /* Short cut: sample 0 is like a normal fetch */
5137 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5138 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5141 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
,
5143 if (sample
!= 0.0f
) {
5145 /* TODO: define the samples > 0, but so far we only do fake MSAA */
5149 unsigned pos
= index2D
.i
[chan
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
.i
[chan
];
5151 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
5152 mach
->InputSampleOffsetApply
[pos
](mach
, pos
, chan
, x
, y
, &result
[chan
]);
5154 store_dest(mach
, &result
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5160 exec_interp_at_offset(struct tgsi_exec_machine
*mach
,
5161 const struct tgsi_full_instruction
*inst
)
5163 union tgsi_exec_channel index
;
5164 union tgsi_exec_channel index2D
;
5165 union tgsi_exec_channel ofsx
;
5166 union tgsi_exec_channel ofsy
;
5167 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5169 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5171 get_index_registers(mach
, reg
, &index
, &index2D
);
5172 unsigned pos
= index2D
.i
[0] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
.i
[0];
5174 fetch_source(mach
, &ofsx
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
5175 fetch_source(mach
, &ofsy
, &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
5177 for (int chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5178 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5180 union tgsi_exec_channel result
;
5181 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
, &result
);
5182 mach
->InputSampleOffsetApply
[pos
](mach
, pos
, chan
, ofsx
.f
[chan
], ofsy
.f
[chan
], &result
);
5183 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5189 exec_interp_at_centroid(struct tgsi_exec_machine
*mach
,
5190 const struct tgsi_full_instruction
*inst
)
5192 union tgsi_exec_channel index
;
5193 union tgsi_exec_channel index2D
;
5194 union tgsi_exec_channel result
[TGSI_NUM_CHANNELS
];
5195 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5197 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5198 get_index_registers(mach
, reg
, &index
, &index2D
);
5200 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5201 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5204 /* Here we should add the change to use a sample that lies within the
5205 * primitive (Section 15.2):
5207 * "When interpolating variables declared using centroid in ,
5208 * the variable is sampled at a location within the pixel covered
5209 * by the primitive generating the fragment.
5211 * The built-in functions interpolateAtCentroid ... will sample
5212 * variables as though they were declared with the centroid ...
5215 * Since we only support 1 sample currently, this is just a pass-through.
5217 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
,
5219 store_dest(mach
, &result
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5226 * Execute a TGSI instruction.
5227 * Returns TRUE if a barrier instruction is hit,
5232 struct tgsi_exec_machine
*mach
,
5233 const struct tgsi_full_instruction
*inst
,
5236 union tgsi_exec_channel r
[10];
5240 switch (inst
->Instruction
.Opcode
) {
5241 case TGSI_OPCODE_ARL
:
5242 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5245 case TGSI_OPCODE_MOV
:
5246 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5249 case TGSI_OPCODE_LIT
:
5250 exec_lit(mach
, inst
);
5253 case TGSI_OPCODE_RCP
:
5254 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5257 case TGSI_OPCODE_RSQ
:
5258 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5261 case TGSI_OPCODE_EXP
:
5262 exec_exp(mach
, inst
);
5265 case TGSI_OPCODE_LOG
:
5266 exec_log(mach
, inst
);
5269 case TGSI_OPCODE_MUL
:
5270 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5273 case TGSI_OPCODE_ADD
:
5274 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5277 case TGSI_OPCODE_DP3
:
5278 exec_dp3(mach
, inst
);
5281 case TGSI_OPCODE_DP4
:
5282 exec_dp4(mach
, inst
);
5285 case TGSI_OPCODE_DST
:
5286 exec_dst(mach
, inst
);
5289 case TGSI_OPCODE_MIN
:
5290 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5293 case TGSI_OPCODE_MAX
:
5294 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5297 case TGSI_OPCODE_SLT
:
5298 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5301 case TGSI_OPCODE_SGE
:
5302 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5305 case TGSI_OPCODE_MAD
:
5306 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5309 case TGSI_OPCODE_LRP
:
5310 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5313 case TGSI_OPCODE_SQRT
:
5314 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5317 case TGSI_OPCODE_FRC
:
5318 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5321 case TGSI_OPCODE_FLR
:
5322 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5325 case TGSI_OPCODE_ROUND
:
5326 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5329 case TGSI_OPCODE_EX2
:
5330 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5333 case TGSI_OPCODE_LG2
:
5334 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5337 case TGSI_OPCODE_POW
:
5338 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5341 case TGSI_OPCODE_LDEXP
:
5342 exec_vector_binary(mach
, inst
, micro_ldexp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5345 case TGSI_OPCODE_COS
:
5346 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5349 case TGSI_OPCODE_DDX_FINE
:
5350 exec_vector_unary(mach
, inst
, micro_ddx_fine
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5353 case TGSI_OPCODE_DDX
:
5354 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5357 case TGSI_OPCODE_DDY_FINE
:
5358 exec_vector_unary(mach
, inst
, micro_ddy_fine
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5361 case TGSI_OPCODE_DDY
:
5362 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5365 case TGSI_OPCODE_KILL
:
5369 case TGSI_OPCODE_KILL_IF
:
5370 exec_kill_if (mach
, inst
);
5373 case TGSI_OPCODE_PK2H
:
5374 exec_pk2h(mach
, inst
);
5377 case TGSI_OPCODE_PK2US
:
5381 case TGSI_OPCODE_PK4B
:
5385 case TGSI_OPCODE_PK4UB
:
5389 case TGSI_OPCODE_SEQ
:
5390 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5393 case TGSI_OPCODE_SGT
:
5394 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5397 case TGSI_OPCODE_SIN
:
5398 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5401 case TGSI_OPCODE_SLE
:
5402 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5405 case TGSI_OPCODE_SNE
:
5406 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5409 case TGSI_OPCODE_TEX
:
5410 /* simple texture lookup */
5411 /* src[0] = texcoord */
5412 /* src[1] = sampler unit */
5413 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5416 case TGSI_OPCODE_TXB
:
5417 /* Texture lookup with lod bias */
5418 /* src[0] = texcoord (src[0].w = LOD bias) */
5419 /* src[1] = sampler unit */
5420 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5423 case TGSI_OPCODE_TXD
:
5424 /* Texture lookup with explict partial derivatives */
5425 /* src[0] = texcoord */
5426 /* src[1] = d[strq]/dx */
5427 /* src[2] = d[strq]/dy */
5428 /* src[3] = sampler unit */
5429 exec_txd(mach
, inst
);
5432 case TGSI_OPCODE_TXL
:
5433 /* Texture lookup with explit LOD */
5434 /* src[0] = texcoord (src[0].w = LOD) */
5435 /* src[1] = sampler unit */
5436 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5439 case TGSI_OPCODE_TXP
:
5440 /* Texture lookup with projection */
5441 /* src[0] = texcoord (src[0].w = projection) */
5442 /* src[1] = sampler unit */
5443 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5446 case TGSI_OPCODE_TG4
:
5447 /* src[0] = texcoord */
5448 /* src[1] = component */
5449 /* src[2] = sampler unit */
5450 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5453 case TGSI_OPCODE_LODQ
:
5454 /* src[0] = texcoord */
5455 /* src[1] = sampler unit */
5456 exec_lodq(mach
, inst
);
5459 case TGSI_OPCODE_UP2H
:
5460 exec_up2h(mach
, inst
);
5463 case TGSI_OPCODE_UP2US
:
5467 case TGSI_OPCODE_UP4B
:
5471 case TGSI_OPCODE_UP4UB
:
5475 case TGSI_OPCODE_ARR
:
5476 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5479 case TGSI_OPCODE_CAL
:
5480 /* skip the call if no execution channels are enabled */
5481 if (mach
->ExecMask
) {
5484 /* First, record the depths of the execution stacks.
5485 * This is important for deeply nested/looped return statements.
5486 * We have to unwind the stacks by the correct amount. For a
5487 * real code generator, we could determine the number of entries
5488 * to pop off each stack with simple static analysis and avoid
5489 * implementing this data structure at run time.
5491 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5492 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5493 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5494 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5495 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5496 /* note that PC was already incremented above */
5497 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5499 mach
->CallStackTop
++;
5501 /* Second, push the Cond, Loop, Cont, Func stacks */
5502 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5503 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5504 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5505 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5506 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5507 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5509 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5510 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5511 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5512 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5513 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5514 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5516 /* Finally, jump to the subroutine. The label is a pointer
5517 * (an instruction number) to the BGNSUB instruction.
5519 *pc
= inst
->Label
.Label
;
5520 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5521 == TGSI_OPCODE_BGNSUB
);
5525 case TGSI_OPCODE_RET
:
5526 mach
->FuncMask
&= ~mach
->ExecMask
;
5527 UPDATE_EXEC_MASK(mach
);
5529 if (mach
->FuncMask
== 0x0) {
5530 /* really return now (otherwise, keep executing */
5532 if (mach
->CallStackTop
== 0) {
5533 /* returning from main() */
5534 mach
->CondStackTop
= 0;
5535 mach
->LoopStackTop
= 0;
5536 mach
->ContStackTop
= 0;
5537 mach
->LoopLabelStackTop
= 0;
5538 mach
->SwitchStackTop
= 0;
5539 mach
->BreakStackTop
= 0;
5544 assert(mach
->CallStackTop
> 0);
5545 mach
->CallStackTop
--;
5547 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5548 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5550 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5551 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5553 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5554 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5556 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5557 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5559 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5560 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5562 assert(mach
->FuncStackTop
> 0);
5563 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5565 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5567 UPDATE_EXEC_MASK(mach
);
5571 case TGSI_OPCODE_SSG
:
5572 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5575 case TGSI_OPCODE_CMP
:
5576 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5579 case TGSI_OPCODE_DIV
:
5580 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5583 case TGSI_OPCODE_DP2
:
5584 exec_dp2(mach
, inst
);
5587 case TGSI_OPCODE_IF
:
5589 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5590 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5591 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5592 /* update CondMask */
5594 mach
->CondMask
&= ~0x1;
5597 mach
->CondMask
&= ~0x2;
5600 mach
->CondMask
&= ~0x4;
5603 mach
->CondMask
&= ~0x8;
5605 UPDATE_EXEC_MASK(mach
);
5606 /* Todo: If CondMask==0, jump to ELSE */
5609 case TGSI_OPCODE_UIF
:
5611 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5612 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5613 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5614 /* update CondMask */
5616 mach
->CondMask
&= ~0x1;
5619 mach
->CondMask
&= ~0x2;
5622 mach
->CondMask
&= ~0x4;
5625 mach
->CondMask
&= ~0x8;
5627 UPDATE_EXEC_MASK(mach
);
5628 /* Todo: If CondMask==0, jump to ELSE */
5631 case TGSI_OPCODE_ELSE
:
5632 /* invert CondMask wrt previous mask */
5635 assert(mach
->CondStackTop
> 0);
5636 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5637 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5638 UPDATE_EXEC_MASK(mach
);
5639 /* Todo: If CondMask==0, jump to ENDIF */
5643 case TGSI_OPCODE_ENDIF
:
5645 assert(mach
->CondStackTop
> 0);
5646 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5647 UPDATE_EXEC_MASK(mach
);
5650 case TGSI_OPCODE_END
:
5651 /* make sure we end primitives which haven't
5652 * been explicitly emitted */
5653 conditional_emit_primitive(mach
);
5654 /* halt execution */
5658 case TGSI_OPCODE_CEIL
:
5659 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5662 case TGSI_OPCODE_I2F
:
5663 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5666 case TGSI_OPCODE_NOT
:
5667 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5670 case TGSI_OPCODE_TRUNC
:
5671 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5674 case TGSI_OPCODE_SHL
:
5675 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5678 case TGSI_OPCODE_AND
:
5679 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5682 case TGSI_OPCODE_OR
:
5683 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5686 case TGSI_OPCODE_MOD
:
5687 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5690 case TGSI_OPCODE_XOR
:
5691 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5694 case TGSI_OPCODE_TXF
:
5695 exec_txf(mach
, inst
);
5698 case TGSI_OPCODE_TXQ
:
5699 exec_txq(mach
, inst
);
5702 case TGSI_OPCODE_EMIT
:
5703 emit_vertex(mach
, inst
);
5706 case TGSI_OPCODE_ENDPRIM
:
5707 emit_primitive(mach
, inst
);
5710 case TGSI_OPCODE_BGNLOOP
:
5711 /* push LoopMask and ContMasks */
5712 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5713 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5714 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5715 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5717 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5718 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5719 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5720 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5721 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5724 case TGSI_OPCODE_ENDLOOP
:
5725 /* Restore ContMask, but don't pop */
5726 assert(mach
->ContStackTop
> 0);
5727 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5728 UPDATE_EXEC_MASK(mach
);
5729 if (mach
->ExecMask
) {
5730 /* repeat loop: jump to instruction just past BGNLOOP */
5731 assert(mach
->LoopLabelStackTop
> 0);
5732 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5735 /* exit loop: pop LoopMask */
5736 assert(mach
->LoopStackTop
> 0);
5737 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5739 assert(mach
->ContStackTop
> 0);
5740 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5741 assert(mach
->LoopLabelStackTop
> 0);
5742 --mach
->LoopLabelStackTop
;
5744 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5746 UPDATE_EXEC_MASK(mach
);
5749 case TGSI_OPCODE_BRK
:
5753 case TGSI_OPCODE_CONT
:
5754 /* turn off cont channels for each enabled exec channel */
5755 mach
->ContMask
&= ~mach
->ExecMask
;
5756 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5757 UPDATE_EXEC_MASK(mach
);
5760 case TGSI_OPCODE_BGNSUB
:
5764 case TGSI_OPCODE_ENDSUB
:
5766 * XXX: This really should be a no-op. We should never reach this opcode.
5769 assert(mach
->CallStackTop
> 0);
5770 mach
->CallStackTop
--;
5772 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5773 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5775 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5776 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5778 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5779 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5781 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5782 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5784 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5785 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5787 assert(mach
->FuncStackTop
> 0);
5788 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5790 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5792 UPDATE_EXEC_MASK(mach
);
5795 case TGSI_OPCODE_NOP
:
5798 case TGSI_OPCODE_F2I
:
5799 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5802 case TGSI_OPCODE_FSEQ
:
5803 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5806 case TGSI_OPCODE_FSGE
:
5807 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5810 case TGSI_OPCODE_FSLT
:
5811 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5814 case TGSI_OPCODE_FSNE
:
5815 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5818 case TGSI_OPCODE_IDIV
:
5819 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5822 case TGSI_OPCODE_IMAX
:
5823 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5826 case TGSI_OPCODE_IMIN
:
5827 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5830 case TGSI_OPCODE_INEG
:
5831 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5834 case TGSI_OPCODE_ISGE
:
5835 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5838 case TGSI_OPCODE_ISHR
:
5839 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5842 case TGSI_OPCODE_ISLT
:
5843 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5846 case TGSI_OPCODE_F2U
:
5847 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5850 case TGSI_OPCODE_U2F
:
5851 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5854 case TGSI_OPCODE_UADD
:
5855 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5858 case TGSI_OPCODE_UDIV
:
5859 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5862 case TGSI_OPCODE_UMAD
:
5863 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5866 case TGSI_OPCODE_UMAX
:
5867 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5870 case TGSI_OPCODE_UMIN
:
5871 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5874 case TGSI_OPCODE_UMOD
:
5875 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5878 case TGSI_OPCODE_UMUL
:
5879 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5882 case TGSI_OPCODE_IMUL_HI
:
5883 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5886 case TGSI_OPCODE_UMUL_HI
:
5887 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5890 case TGSI_OPCODE_USEQ
:
5891 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5894 case TGSI_OPCODE_USGE
:
5895 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5898 case TGSI_OPCODE_USHR
:
5899 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5902 case TGSI_OPCODE_USLT
:
5903 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5906 case TGSI_OPCODE_USNE
:
5907 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5910 case TGSI_OPCODE_SWITCH
:
5911 exec_switch(mach
, inst
);
5914 case TGSI_OPCODE_CASE
:
5915 exec_case(mach
, inst
);
5918 case TGSI_OPCODE_DEFAULT
:
5922 case TGSI_OPCODE_ENDSWITCH
:
5923 exec_endswitch(mach
);
5926 case TGSI_OPCODE_SAMPLE_I
:
5927 exec_txf(mach
, inst
);
5930 case TGSI_OPCODE_SAMPLE_I_MS
:
5931 exec_txf(mach
, inst
);
5934 case TGSI_OPCODE_SAMPLE
:
5935 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5938 case TGSI_OPCODE_SAMPLE_B
:
5939 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5942 case TGSI_OPCODE_SAMPLE_C
:
5943 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5946 case TGSI_OPCODE_SAMPLE_C_LZ
:
5947 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5950 case TGSI_OPCODE_SAMPLE_D
:
5951 exec_sample_d(mach
, inst
);
5954 case TGSI_OPCODE_SAMPLE_L
:
5955 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5958 case TGSI_OPCODE_GATHER4
:
5959 exec_sample(mach
, inst
, TEX_MODIFIER_GATHER
, FALSE
);
5962 case TGSI_OPCODE_SVIEWINFO
:
5963 exec_txq(mach
, inst
);
5966 case TGSI_OPCODE_SAMPLE_POS
:
5970 case TGSI_OPCODE_SAMPLE_INFO
:
5974 case TGSI_OPCODE_LOD
:
5975 exec_lodq(mach
, inst
);
5978 case TGSI_OPCODE_UARL
:
5979 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5982 case TGSI_OPCODE_UCMP
:
5983 exec_ucmp(mach
, inst
);
5986 case TGSI_OPCODE_IABS
:
5987 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5990 case TGSI_OPCODE_ISSG
:
5991 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5994 case TGSI_OPCODE_TEX2
:
5995 /* simple texture lookup */
5996 /* src[0] = texcoord */
5997 /* src[1] = compare */
5998 /* src[2] = sampler unit */
5999 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
6001 case TGSI_OPCODE_TXB2
:
6002 /* simple texture lookup */
6003 /* src[0] = texcoord */
6005 /* src[2] = sampler unit */
6006 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
6008 case TGSI_OPCODE_TXL2
:
6009 /* simple texture lookup */
6010 /* src[0] = texcoord */
6012 /* src[2] = sampler unit */
6013 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
6016 case TGSI_OPCODE_IBFE
:
6017 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
6019 case TGSI_OPCODE_UBFE
:
6020 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6022 case TGSI_OPCODE_BFI
:
6023 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6025 case TGSI_OPCODE_BREV
:
6026 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6028 case TGSI_OPCODE_POPC
:
6029 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6031 case TGSI_OPCODE_LSB
:
6032 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
6034 case TGSI_OPCODE_IMSB
:
6035 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
6037 case TGSI_OPCODE_UMSB
:
6038 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
6041 case TGSI_OPCODE_F2D
:
6042 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
6045 case TGSI_OPCODE_D2F
:
6046 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
6049 case TGSI_OPCODE_DABS
:
6050 exec_double_unary(mach
, inst
, micro_dabs
);
6053 case TGSI_OPCODE_DNEG
:
6054 exec_double_unary(mach
, inst
, micro_dneg
);
6057 case TGSI_OPCODE_DADD
:
6058 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
6061 case TGSI_OPCODE_DDIV
:
6062 exec_double_binary(mach
, inst
, micro_ddiv
, TGSI_EXEC_DATA_DOUBLE
);
6065 case TGSI_OPCODE_DMUL
:
6066 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
6069 case TGSI_OPCODE_DMAX
:
6070 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
6073 case TGSI_OPCODE_DMIN
:
6074 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
6077 case TGSI_OPCODE_DSLT
:
6078 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
6081 case TGSI_OPCODE_DSGE
:
6082 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
6085 case TGSI_OPCODE_DSEQ
:
6086 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
6089 case TGSI_OPCODE_DSNE
:
6090 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
6093 case TGSI_OPCODE_DRCP
:
6094 exec_double_unary(mach
, inst
, micro_drcp
);
6097 case TGSI_OPCODE_DSQRT
:
6098 exec_double_unary(mach
, inst
, micro_dsqrt
);
6101 case TGSI_OPCODE_DRSQ
:
6102 exec_double_unary(mach
, inst
, micro_drsq
);
6105 case TGSI_OPCODE_DMAD
:
6106 exec_double_trinary(mach
, inst
, micro_dmad
);
6109 case TGSI_OPCODE_DFRAC
:
6110 exec_double_unary(mach
, inst
, micro_dfrac
);
6113 case TGSI_OPCODE_DLDEXP
:
6114 exec_dldexp(mach
, inst
);
6117 case TGSI_OPCODE_DFRACEXP
:
6118 exec_dfracexp(mach
, inst
);
6121 case TGSI_OPCODE_I2D
:
6122 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
6125 case TGSI_OPCODE_D2I
:
6126 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
6129 case TGSI_OPCODE_U2D
:
6130 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
6133 case TGSI_OPCODE_D2U
:
6134 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
6137 case TGSI_OPCODE_LOAD
:
6138 exec_load(mach
, inst
);
6141 case TGSI_OPCODE_STORE
:
6142 exec_store(mach
, inst
);
6145 case TGSI_OPCODE_ATOMUADD
:
6146 case TGSI_OPCODE_ATOMXCHG
:
6147 case TGSI_OPCODE_ATOMCAS
:
6148 case TGSI_OPCODE_ATOMAND
:
6149 case TGSI_OPCODE_ATOMOR
:
6150 case TGSI_OPCODE_ATOMXOR
:
6151 case TGSI_OPCODE_ATOMUMIN
:
6152 case TGSI_OPCODE_ATOMUMAX
:
6153 case TGSI_OPCODE_ATOMIMIN
:
6154 case TGSI_OPCODE_ATOMIMAX
:
6155 case TGSI_OPCODE_ATOMFADD
:
6156 exec_atomop(mach
, inst
);
6159 case TGSI_OPCODE_RESQ
:
6160 exec_resq(mach
, inst
);
6162 case TGSI_OPCODE_BARRIER
:
6163 case TGSI_OPCODE_MEMBAR
:
6167 case TGSI_OPCODE_I64ABS
:
6168 exec_double_unary(mach
, inst
, micro_i64abs
);
6171 case TGSI_OPCODE_I64SSG
:
6172 exec_double_unary(mach
, inst
, micro_i64sgn
);
6175 case TGSI_OPCODE_I64NEG
:
6176 exec_double_unary(mach
, inst
, micro_i64neg
);
6179 case TGSI_OPCODE_U64SEQ
:
6180 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
6183 case TGSI_OPCODE_U64SNE
:
6184 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
6187 case TGSI_OPCODE_I64SLT
:
6188 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
6190 case TGSI_OPCODE_U64SLT
:
6191 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
6194 case TGSI_OPCODE_I64SGE
:
6195 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
6197 case TGSI_OPCODE_U64SGE
:
6198 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
6201 case TGSI_OPCODE_I64MIN
:
6202 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
6204 case TGSI_OPCODE_U64MIN
:
6205 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
6207 case TGSI_OPCODE_I64MAX
:
6208 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
6210 case TGSI_OPCODE_U64MAX
:
6211 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
6213 case TGSI_OPCODE_U64ADD
:
6214 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
6216 case TGSI_OPCODE_U64MUL
:
6217 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
6219 case TGSI_OPCODE_U64SHL
:
6220 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
6222 case TGSI_OPCODE_I64SHR
:
6223 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
6225 case TGSI_OPCODE_U64SHR
:
6226 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
6228 case TGSI_OPCODE_U64DIV
:
6229 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6231 case TGSI_OPCODE_I64DIV
:
6232 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6234 case TGSI_OPCODE_U64MOD
:
6235 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6237 case TGSI_OPCODE_I64MOD
:
6238 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6241 case TGSI_OPCODE_F2U64
:
6242 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6245 case TGSI_OPCODE_F2I64
:
6246 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6249 case TGSI_OPCODE_U2I64
:
6250 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6252 case TGSI_OPCODE_I2I64
:
6253 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6256 case TGSI_OPCODE_D2U64
:
6257 exec_double_unary(mach
, inst
, micro_d2u64
);
6260 case TGSI_OPCODE_D2I64
:
6261 exec_double_unary(mach
, inst
, micro_d2i64
);
6264 case TGSI_OPCODE_U642F
:
6265 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6267 case TGSI_OPCODE_I642F
:
6268 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6271 case TGSI_OPCODE_U642D
:
6272 exec_double_unary(mach
, inst
, micro_u642d
);
6274 case TGSI_OPCODE_I642D
:
6275 exec_double_unary(mach
, inst
, micro_i642d
);
6277 case TGSI_OPCODE_INTERP_SAMPLE
:
6278 exec_interp_at_sample(mach
, inst
);
6280 case TGSI_OPCODE_INTERP_OFFSET
:
6281 exec_interp_at_offset(mach
, inst
);
6283 case TGSI_OPCODE_INTERP_CENTROID
:
6284 exec_interp_at_centroid(mach
, inst
);
6293 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6295 uint default_mask
= 0xf;
6297 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6298 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6300 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6301 for (unsigned i
= 0; i
< TGSI_MAX_VERTEX_STREAMS
; i
++) {
6302 mach
->Temps
[temp_prim_idxs
[i
].idx
].xyzw
[temp_prim_idxs
[i
].chan
].u
[0] = 0;
6303 mach
->Primitives
[i
][0] = 0;
6305 /* GS runs on a single primitive for now */
6309 if (mach
->NonHelperMask
== 0)
6310 mach
->NonHelperMask
= default_mask
;
6311 mach
->CondMask
= default_mask
;
6312 mach
->LoopMask
= default_mask
;
6313 mach
->ContMask
= default_mask
;
6314 mach
->FuncMask
= default_mask
;
6315 mach
->ExecMask
= default_mask
;
6317 mach
->Switch
.mask
= default_mask
;
6319 assert(mach
->CondStackTop
== 0);
6320 assert(mach
->LoopStackTop
== 0);
6321 assert(mach
->ContStackTop
== 0);
6322 assert(mach
->SwitchStackTop
== 0);
6323 assert(mach
->BreakStackTop
== 0);
6324 assert(mach
->CallStackTop
== 0);
6328 * Run TGSI interpreter.
6329 * \return bitmask of "alive" quad components
6332 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6336 mach
->pc
= start_pc
;
6339 tgsi_exec_machine_setup_masks(mach
);
6341 /* execute declarations (interpolants) */
6342 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6343 exec_declaration( mach
, mach
->Declarations
+i
);
6349 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6350 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6354 memset(mach
->Temps
, 0, sizeof(temps
));
6356 memset(mach
->Outputs
, 0, sizeof(outputs
));
6357 memset(temps
, 0, sizeof(temps
));
6358 memset(outputs
, 0, sizeof(outputs
));
6362 /* execute instructions, until pc is set to -1 */
6363 while (mach
->pc
!= -1) {
6364 boolean barrier_hit
;
6368 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6371 assert(mach
->pc
< (int) mach
->NumInstructions
);
6372 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6374 /* for compute shaders if we hit a barrier return now for later rescheduling */
6375 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6379 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6380 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6383 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6384 debug_printf("TEMP[%2u] = ", i
);
6385 for (j
= 0; j
< 4; j
++) {
6389 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6390 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6391 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6392 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6393 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6397 if (mach
->Outputs
) {
6398 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6399 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6402 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6403 debug_printf("OUT[%2u] = ", i
);
6404 for (j
= 0; j
< 4; j
++) {
6408 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6409 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6410 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6411 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6412 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6422 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6423 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6425 * Scale back depth component.
6427 for (i
= 0; i
< 4; i
++)
6428 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6432 /* Strictly speaking, these assertions aren't really needed but they
6433 * can potentially catch some bugs in the control flow code.
6435 assert(mach
->CondStackTop
== 0);
6436 assert(mach
->LoopStackTop
== 0);
6437 assert(mach
->ContStackTop
== 0);
6438 assert(mach
->SwitchStackTop
== 0);
6439 assert(mach
->BreakStackTop
== 0);
6440 assert(mach
->CallStackTop
== 0);
6442 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];