1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
66 #define DEBUG_EXECUTION 0
71 #define TILE_TOP_LEFT 0
72 #define TILE_TOP_RIGHT 1
73 #define TILE_BOTTOM_LEFT 2
74 #define TILE_BOTTOM_RIGHT 3
76 union tgsi_double_channel
{
77 double d
[TGSI_QUAD_SIZE
];
78 unsigned u
[TGSI_QUAD_SIZE
][2];
81 struct tgsi_double_vector
{
82 union tgsi_double_channel xy
;
83 union tgsi_double_channel zw
;
87 micro_abs(union tgsi_exec_channel
*dst
,
88 const union tgsi_exec_channel
*src
)
90 dst
->f
[0] = fabsf(src
->f
[0]);
91 dst
->f
[1] = fabsf(src
->f
[1]);
92 dst
->f
[2] = fabsf(src
->f
[2]);
93 dst
->f
[3] = fabsf(src
->f
[3]);
97 micro_arl(union tgsi_exec_channel
*dst
,
98 const union tgsi_exec_channel
*src
)
100 dst
->i
[0] = (int)floorf(src
->f
[0]);
101 dst
->i
[1] = (int)floorf(src
->f
[1]);
102 dst
->i
[2] = (int)floorf(src
->f
[2]);
103 dst
->i
[3] = (int)floorf(src
->f
[3]);
107 micro_arr(union tgsi_exec_channel
*dst
,
108 const union tgsi_exec_channel
*src
)
110 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
111 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
112 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
113 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
117 micro_ceil(union tgsi_exec_channel
*dst
,
118 const union tgsi_exec_channel
*src
)
120 dst
->f
[0] = ceilf(src
->f
[0]);
121 dst
->f
[1] = ceilf(src
->f
[1]);
122 dst
->f
[2] = ceilf(src
->f
[2]);
123 dst
->f
[3] = ceilf(src
->f
[3]);
127 micro_clamp(union tgsi_exec_channel
*dst
,
128 const union tgsi_exec_channel
*src0
,
129 const union tgsi_exec_channel
*src1
,
130 const union tgsi_exec_channel
*src2
)
132 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
133 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
134 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
135 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
139 micro_cmp(union tgsi_exec_channel
*dst
,
140 const union tgsi_exec_channel
*src0
,
141 const union tgsi_exec_channel
*src1
,
142 const union tgsi_exec_channel
*src2
)
144 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
145 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
146 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
147 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
151 micro_cos(union tgsi_exec_channel
*dst
,
152 const union tgsi_exec_channel
*src
)
154 dst
->f
[0] = cosf(src
->f
[0]);
155 dst
->f
[1] = cosf(src
->f
[1]);
156 dst
->f
[2] = cosf(src
->f
[2]);
157 dst
->f
[3] = cosf(src
->f
[3]);
161 micro_d2f(union tgsi_exec_channel
*dst
,
162 const union tgsi_double_channel
*src
)
164 dst
->f
[0] = (float)src
->d
[0];
165 dst
->f
[1] = (float)src
->d
[1];
166 dst
->f
[2] = (float)src
->d
[2];
167 dst
->f
[3] = (float)src
->d
[3];
171 micro_d2i(union tgsi_exec_channel
*dst
,
172 const union tgsi_double_channel
*src
)
174 dst
->i
[0] = (int)src
->d
[0];
175 dst
->i
[1] = (int)src
->d
[1];
176 dst
->i
[2] = (int)src
->d
[2];
177 dst
->i
[3] = (int)src
->d
[3];
181 micro_d2u(union tgsi_exec_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->u
[0] = (unsigned)src
->d
[0];
185 dst
->u
[1] = (unsigned)src
->d
[1];
186 dst
->u
[2] = (unsigned)src
->d
[2];
187 dst
->u
[3] = (unsigned)src
->d
[3];
190 micro_dabs(union tgsi_double_channel
*dst
,
191 const union tgsi_double_channel
*src
)
193 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
194 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
195 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
196 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
200 micro_dadd(union tgsi_double_channel
*dst
,
201 const union tgsi_double_channel
*src
)
203 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
204 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
205 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
206 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
210 micro_ddx(union tgsi_exec_channel
*dst
,
211 const union tgsi_exec_channel
*src
)
216 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
220 micro_ddy(union tgsi_exec_channel
*dst
,
221 const union tgsi_exec_channel
*src
)
226 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
230 micro_dmul(union tgsi_double_channel
*dst
,
231 const union tgsi_double_channel
*src
)
233 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
234 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
235 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
236 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
240 micro_dmax(union tgsi_double_channel
*dst
,
241 const union tgsi_double_channel
*src
)
243 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
244 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
245 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
246 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
250 micro_dmin(union tgsi_double_channel
*dst
,
251 const union tgsi_double_channel
*src
)
253 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
254 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
255 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
256 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
260 micro_dneg(union tgsi_double_channel
*dst
,
261 const union tgsi_double_channel
*src
)
263 dst
->d
[0] = -src
->d
[0];
264 dst
->d
[1] = -src
->d
[1];
265 dst
->d
[2] = -src
->d
[2];
266 dst
->d
[3] = -src
->d
[3];
270 micro_dslt(union tgsi_double_channel
*dst
,
271 const union tgsi_double_channel
*src
)
273 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
274 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
275 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
276 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
280 micro_dsne(union tgsi_double_channel
*dst
,
281 const union tgsi_double_channel
*src
)
283 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
284 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
285 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
286 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
290 micro_dsge(union tgsi_double_channel
*dst
,
291 const union tgsi_double_channel
*src
)
293 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
294 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
295 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
296 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
300 micro_dseq(union tgsi_double_channel
*dst
,
301 const union tgsi_double_channel
*src
)
303 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
304 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
305 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
306 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
310 micro_drcp(union tgsi_double_channel
*dst
,
311 const union tgsi_double_channel
*src
)
313 dst
->d
[0] = 1.0 / src
->d
[0];
314 dst
->d
[1] = 1.0 / src
->d
[1];
315 dst
->d
[2] = 1.0 / src
->d
[2];
316 dst
->d
[3] = 1.0 / src
->d
[3];
320 micro_dsqrt(union tgsi_double_channel
*dst
,
321 const union tgsi_double_channel
*src
)
323 dst
->d
[0] = sqrt(src
->d
[0]);
324 dst
->d
[1] = sqrt(src
->d
[1]);
325 dst
->d
[2] = sqrt(src
->d
[2]);
326 dst
->d
[3] = sqrt(src
->d
[3]);
330 micro_drsq(union tgsi_double_channel
*dst
,
331 const union tgsi_double_channel
*src
)
333 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
334 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
335 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
336 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
340 micro_dmad(union tgsi_double_channel
*dst
,
341 const union tgsi_double_channel
*src
)
343 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
344 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
345 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
346 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
350 micro_dfrac(union tgsi_double_channel
*dst
,
351 const union tgsi_double_channel
*src
)
353 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
354 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
355 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
356 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
360 micro_dldexp(union tgsi_double_channel
*dst
,
361 const union tgsi_double_channel
*src0
,
362 union tgsi_exec_channel
*src1
)
364 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
365 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
366 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
367 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
371 micro_dfracexp(union tgsi_double_channel
*dst
,
372 union tgsi_exec_channel
*dst_exp
,
373 const union tgsi_double_channel
*src
)
375 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
376 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
377 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
378 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
382 micro_exp2(union tgsi_exec_channel
*dst
,
383 const union tgsi_exec_channel
*src
)
386 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
387 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
388 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
389 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
392 /* Inf is okay for this instruction, so clamp it to silence assertions. */
394 union tgsi_exec_channel clamped
;
396 for (i
= 0; i
< 4; i
++) {
397 if (src
->f
[i
] > 127.99999f
) {
398 clamped
.f
[i
] = 127.99999f
;
399 } else if (src
->f
[i
] < -126.99999f
) {
400 clamped
.f
[i
] = -126.99999f
;
402 clamped
.f
[i
] = src
->f
[i
];
408 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
409 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
410 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
411 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
412 #endif /* FAST_MATH */
416 micro_f2d(union tgsi_double_channel
*dst
,
417 const union tgsi_exec_channel
*src
)
419 dst
->d
[0] = (double)src
->f
[0];
420 dst
->d
[1] = (double)src
->f
[1];
421 dst
->d
[2] = (double)src
->f
[2];
422 dst
->d
[3] = (double)src
->f
[3];
426 micro_flr(union tgsi_exec_channel
*dst
,
427 const union tgsi_exec_channel
*src
)
429 dst
->f
[0] = floorf(src
->f
[0]);
430 dst
->f
[1] = floorf(src
->f
[1]);
431 dst
->f
[2] = floorf(src
->f
[2]);
432 dst
->f
[3] = floorf(src
->f
[3]);
436 micro_frc(union tgsi_exec_channel
*dst
,
437 const union tgsi_exec_channel
*src
)
439 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
440 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
441 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
442 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
446 micro_i2d(union tgsi_double_channel
*dst
,
447 const union tgsi_exec_channel
*src
)
449 dst
->d
[0] = (double)src
->i
[0];
450 dst
->d
[1] = (double)src
->i
[1];
451 dst
->d
[2] = (double)src
->i
[2];
452 dst
->d
[3] = (double)src
->i
[3];
456 micro_iabs(union tgsi_exec_channel
*dst
,
457 const union tgsi_exec_channel
*src
)
459 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
460 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
461 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
462 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
466 micro_ineg(union tgsi_exec_channel
*dst
,
467 const union tgsi_exec_channel
*src
)
469 dst
->i
[0] = -src
->i
[0];
470 dst
->i
[1] = -src
->i
[1];
471 dst
->i
[2] = -src
->i
[2];
472 dst
->i
[3] = -src
->i
[3];
476 micro_lg2(union tgsi_exec_channel
*dst
,
477 const union tgsi_exec_channel
*src
)
480 dst
->f
[0] = util_fast_log2(src
->f
[0]);
481 dst
->f
[1] = util_fast_log2(src
->f
[1]);
482 dst
->f
[2] = util_fast_log2(src
->f
[2]);
483 dst
->f
[3] = util_fast_log2(src
->f
[3]);
485 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
486 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
487 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
488 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
493 micro_lrp(union tgsi_exec_channel
*dst
,
494 const union tgsi_exec_channel
*src0
,
495 const union tgsi_exec_channel
*src1
,
496 const union tgsi_exec_channel
*src2
)
498 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
499 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
500 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
501 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
505 micro_mad(union tgsi_exec_channel
*dst
,
506 const union tgsi_exec_channel
*src0
,
507 const union tgsi_exec_channel
*src1
,
508 const union tgsi_exec_channel
*src2
)
510 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
511 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
512 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
513 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
517 micro_mov(union tgsi_exec_channel
*dst
,
518 const union tgsi_exec_channel
*src
)
520 dst
->u
[0] = src
->u
[0];
521 dst
->u
[1] = src
->u
[1];
522 dst
->u
[2] = src
->u
[2];
523 dst
->u
[3] = src
->u
[3];
527 micro_rcp(union tgsi_exec_channel
*dst
,
528 const union tgsi_exec_channel
*src
)
530 #if 0 /* for debugging */
531 assert(src
->f
[0] != 0.0f
);
532 assert(src
->f
[1] != 0.0f
);
533 assert(src
->f
[2] != 0.0f
);
534 assert(src
->f
[3] != 0.0f
);
536 dst
->f
[0] = 1.0f
/ src
->f
[0];
537 dst
->f
[1] = 1.0f
/ src
->f
[1];
538 dst
->f
[2] = 1.0f
/ src
->f
[2];
539 dst
->f
[3] = 1.0f
/ src
->f
[3];
543 micro_rnd(union tgsi_exec_channel
*dst
,
544 const union tgsi_exec_channel
*src
)
546 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
547 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
548 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
549 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
553 micro_rsq(union tgsi_exec_channel
*dst
,
554 const union tgsi_exec_channel
*src
)
556 #if 0 /* for debugging */
557 assert(src
->f
[0] != 0.0f
);
558 assert(src
->f
[1] != 0.0f
);
559 assert(src
->f
[2] != 0.0f
);
560 assert(src
->f
[3] != 0.0f
);
562 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
563 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
564 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
565 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
569 micro_sqrt(union tgsi_exec_channel
*dst
,
570 const union tgsi_exec_channel
*src
)
572 dst
->f
[0] = sqrtf(src
->f
[0]);
573 dst
->f
[1] = sqrtf(src
->f
[1]);
574 dst
->f
[2] = sqrtf(src
->f
[2]);
575 dst
->f
[3] = sqrtf(src
->f
[3]);
579 micro_seq(union tgsi_exec_channel
*dst
,
580 const union tgsi_exec_channel
*src0
,
581 const union tgsi_exec_channel
*src1
)
583 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
584 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
585 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
586 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
590 micro_sge(union tgsi_exec_channel
*dst
,
591 const union tgsi_exec_channel
*src0
,
592 const union tgsi_exec_channel
*src1
)
594 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
595 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
596 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
597 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
601 micro_sgn(union tgsi_exec_channel
*dst
,
602 const union tgsi_exec_channel
*src
)
604 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
605 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
611 micro_isgn(union tgsi_exec_channel
*dst
,
612 const union tgsi_exec_channel
*src
)
614 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
615 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
616 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
617 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
621 micro_sgt(union tgsi_exec_channel
*dst
,
622 const union tgsi_exec_channel
*src0
,
623 const union tgsi_exec_channel
*src1
)
625 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
626 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
627 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
628 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
632 micro_sin(union tgsi_exec_channel
*dst
,
633 const union tgsi_exec_channel
*src
)
635 dst
->f
[0] = sinf(src
->f
[0]);
636 dst
->f
[1] = sinf(src
->f
[1]);
637 dst
->f
[2] = sinf(src
->f
[2]);
638 dst
->f
[3] = sinf(src
->f
[3]);
642 micro_sle(union tgsi_exec_channel
*dst
,
643 const union tgsi_exec_channel
*src0
,
644 const union tgsi_exec_channel
*src1
)
646 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
647 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
648 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
649 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
653 micro_slt(union tgsi_exec_channel
*dst
,
654 const union tgsi_exec_channel
*src0
,
655 const union tgsi_exec_channel
*src1
)
657 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
658 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
659 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
660 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
664 micro_sne(union tgsi_exec_channel
*dst
,
665 const union tgsi_exec_channel
*src0
,
666 const union tgsi_exec_channel
*src1
)
668 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
669 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
670 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
671 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
675 micro_trunc(union tgsi_exec_channel
*dst
,
676 const union tgsi_exec_channel
*src
)
678 dst
->f
[0] = (float)(int)src
->f
[0];
679 dst
->f
[1] = (float)(int)src
->f
[1];
680 dst
->f
[2] = (float)(int)src
->f
[2];
681 dst
->f
[3] = (float)(int)src
->f
[3];
685 micro_u2d(union tgsi_double_channel
*dst
,
686 const union tgsi_exec_channel
*src
)
688 dst
->d
[0] = (double)src
->u
[0];
689 dst
->d
[1] = (double)src
->u
[1];
690 dst
->d
[2] = (double)src
->u
[2];
691 dst
->d
[3] = (double)src
->u
[3];
694 enum tgsi_exec_datatype
{
695 TGSI_EXEC_DATA_FLOAT
,
698 TGSI_EXEC_DATA_DOUBLE
702 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
704 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
705 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
706 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
707 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
708 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
709 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
712 /** The execution mask depends on the conditional mask and the loop mask */
713 #define UPDATE_EXEC_MASK(MACH) \
714 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
717 static const union tgsi_exec_channel ZeroVec
=
718 { { 0.0, 0.0, 0.0, 0.0 } };
720 static const union tgsi_exec_channel OneVec
= {
721 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
724 static const union tgsi_exec_channel P128Vec
= {
725 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
728 static const union tgsi_exec_channel M128Vec
= {
729 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
734 * Assert that none of the float values in 'chan' are infinite or NaN.
735 * NaN and Inf may occur normally during program execution and should
736 * not lead to crashes, etc. But when debugging, it's helpful to catch
740 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
742 assert(!util_is_inf_or_nan((chan
)->f
[0]));
743 assert(!util_is_inf_or_nan((chan
)->f
[1]));
744 assert(!util_is_inf_or_nan((chan
)->f
[2]));
745 assert(!util_is_inf_or_nan((chan
)->f
[3]));
751 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
753 debug_printf("%s = {%f, %f, %f, %f}\n",
754 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
761 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
763 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
765 debug_printf("Temp[%u] =\n", index
);
766 for (i
= 0; i
< 4; i
++) {
767 debug_printf(" %c: { %f, %f, %f, %f }\n",
779 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
782 const unsigned *buf_sizes
)
786 for (i
= 0; i
< num_bufs
; i
++) {
787 mach
->Consts
[i
] = bufs
[i
];
788 mach
->ConstsSize
[i
] = buf_sizes
[i
];
794 * Check if there's a potential src/dst register data dependency when
795 * using SOA execution.
798 * This would expand into:
803 * The second instruction will have the wrong value for t0 if executed as-is.
806 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
810 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
811 if (writemask
== TGSI_WRITEMASK_X
||
812 writemask
== TGSI_WRITEMASK_Y
||
813 writemask
== TGSI_WRITEMASK_Z
||
814 writemask
== TGSI_WRITEMASK_W
||
815 writemask
== TGSI_WRITEMASK_NONE
) {
816 /* no chance of data dependency */
820 /* loop over src regs */
821 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
822 if ((inst
->Src
[i
].Register
.File
==
823 inst
->Dst
[0].Register
.File
) &&
824 ((inst
->Src
[i
].Register
.Index
==
825 inst
->Dst
[0].Register
.Index
) ||
826 inst
->Src
[i
].Register
.Indirect
||
827 inst
->Dst
[0].Register
.Indirect
)) {
828 /* loop over dest channels */
829 uint channelsWritten
= 0x0;
830 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
831 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
832 /* check if we're reading a channel that's been written */
833 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
834 if (channelsWritten
& (1 << swizzle
)) {
838 channelsWritten
|= (1 << chan
);
848 * Initialize machine state by expanding tokens to full instructions,
849 * allocating temporary storage, setting up constants, etc.
850 * After this, we can call tgsi_exec_machine_run() many times.
853 tgsi_exec_machine_bind_shader(
854 struct tgsi_exec_machine
*mach
,
855 const struct tgsi_token
*tokens
,
856 struct tgsi_sampler
*sampler
,
857 struct tgsi_image
*image
,
858 struct tgsi_buffer
*buffer
)
861 struct tgsi_parse_context parse
;
862 struct tgsi_full_instruction
*instructions
;
863 struct tgsi_full_declaration
*declarations
;
864 uint maxInstructions
= 10, numInstructions
= 0;
865 uint maxDeclarations
= 10, numDeclarations
= 0;
868 tgsi_dump(tokens
, 0);
874 mach
->Tokens
= tokens
;
875 mach
->Sampler
= sampler
;
877 mach
->Buffer
= buffer
;
880 /* unbind and free all */
881 FREE(mach
->Declarations
);
882 mach
->Declarations
= NULL
;
883 mach
->NumDeclarations
= 0;
885 FREE(mach
->Instructions
);
886 mach
->Instructions
= NULL
;
887 mach
->NumInstructions
= 0;
892 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
893 if (k
!= TGSI_PARSE_OK
) {
894 debug_printf( "Problem parsing!\n" );
899 mach
->NumOutputs
= 0;
901 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
902 !mach
->UsedGeometryShader
) {
903 struct tgsi_exec_vector
*inputs
;
904 struct tgsi_exec_vector
*outputs
;
906 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
907 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
913 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
914 TGSI_MAX_TOTAL_VERTICES
, 16);
921 align_free(mach
->Inputs
);
922 align_free(mach
->Outputs
);
924 mach
->Inputs
= inputs
;
925 mach
->Outputs
= outputs
;
926 mach
->UsedGeometryShader
= TRUE
;
929 declarations
= (struct tgsi_full_declaration
*)
930 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
936 instructions
= (struct tgsi_full_instruction
*)
937 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
940 FREE( declarations
);
944 while( !tgsi_parse_end_of_tokens( &parse
) ) {
947 tgsi_parse_token( &parse
);
948 switch( parse
.FullToken
.Token
.Type
) {
949 case TGSI_TOKEN_TYPE_DECLARATION
:
950 /* save expanded declaration */
951 if (numDeclarations
== maxDeclarations
) {
952 declarations
= REALLOC(declarations
,
954 * sizeof(struct tgsi_full_declaration
),
955 (maxDeclarations
+ 10)
956 * sizeof(struct tgsi_full_declaration
));
957 maxDeclarations
+= 10;
959 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
961 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
962 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
967 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
968 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
969 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
972 memcpy(declarations
+ numDeclarations
,
973 &parse
.FullToken
.FullDeclaration
,
974 sizeof(declarations
[0]));
978 case TGSI_TOKEN_TYPE_IMMEDIATE
:
980 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
982 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
984 for( i
= 0; i
< size
; i
++ ) {
985 mach
->Imms
[mach
->ImmLimit
][i
] =
986 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
992 case TGSI_TOKEN_TYPE_INSTRUCTION
:
994 /* save expanded instruction */
995 if (numInstructions
== maxInstructions
) {
996 instructions
= REALLOC(instructions
,
998 * sizeof(struct tgsi_full_instruction
),
999 (maxInstructions
+ 10)
1000 * sizeof(struct tgsi_full_instruction
));
1001 maxInstructions
+= 10;
1004 memcpy(instructions
+ numInstructions
,
1005 &parse
.FullToken
.FullInstruction
,
1006 sizeof(instructions
[0]));
1011 case TGSI_TOKEN_TYPE_PROPERTY
:
1012 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1013 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1014 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1023 tgsi_parse_free (&parse
);
1025 FREE(mach
->Declarations
);
1026 mach
->Declarations
= declarations
;
1027 mach
->NumDeclarations
= numDeclarations
;
1029 FREE(mach
->Instructions
);
1030 mach
->Instructions
= instructions
;
1031 mach
->NumInstructions
= numInstructions
;
1035 struct tgsi_exec_machine
*
1036 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1038 struct tgsi_exec_machine
*mach
;
1041 mach
= align_malloc( sizeof *mach
, 16 );
1045 memset(mach
, 0, sizeof(*mach
));
1047 mach
->ShaderType
= shader_type
;
1048 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1049 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1050 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
1052 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1053 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1054 if (!mach
->Inputs
|| !mach
->Outputs
)
1057 /* Setup constants needed by the SSE2 executor. */
1058 for( i
= 0; i
< 4; i
++ ) {
1059 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1060 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1061 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1062 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1063 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1064 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1065 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1066 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1067 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1068 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1072 /* silence warnings */
1081 align_free(mach
->Inputs
);
1082 align_free(mach
->Outputs
);
1090 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1093 FREE(mach
->Instructions
);
1094 FREE(mach
->Declarations
);
1096 align_free(mach
->Inputs
);
1097 align_free(mach
->Outputs
);
1104 micro_add(union tgsi_exec_channel
*dst
,
1105 const union tgsi_exec_channel
*src0
,
1106 const union tgsi_exec_channel
*src1
)
1108 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1109 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1110 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1111 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1116 union tgsi_exec_channel
*dst
,
1117 const union tgsi_exec_channel
*src0
,
1118 const union tgsi_exec_channel
*src1
)
1120 if (src1
->f
[0] != 0) {
1121 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1123 if (src1
->f
[1] != 0) {
1124 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1126 if (src1
->f
[2] != 0) {
1127 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1129 if (src1
->f
[3] != 0) {
1130 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1136 union tgsi_exec_channel
*dst
,
1137 const union tgsi_exec_channel
*src0
,
1138 const union tgsi_exec_channel
*src1
,
1139 const union tgsi_exec_channel
*src2
,
1140 const union tgsi_exec_channel
*src3
)
1142 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1143 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1144 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1145 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1149 micro_max(union tgsi_exec_channel
*dst
,
1150 const union tgsi_exec_channel
*src0
,
1151 const union tgsi_exec_channel
*src1
)
1153 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1154 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1155 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1156 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1160 micro_min(union tgsi_exec_channel
*dst
,
1161 const union tgsi_exec_channel
*src0
,
1162 const union tgsi_exec_channel
*src1
)
1164 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1165 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1166 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1167 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1171 micro_mul(union tgsi_exec_channel
*dst
,
1172 const union tgsi_exec_channel
*src0
,
1173 const union tgsi_exec_channel
*src1
)
1175 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1176 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1177 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1178 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1183 union tgsi_exec_channel
*dst
,
1184 const union tgsi_exec_channel
*src
)
1186 dst
->f
[0] = -src
->f
[0];
1187 dst
->f
[1] = -src
->f
[1];
1188 dst
->f
[2] = -src
->f
[2];
1189 dst
->f
[3] = -src
->f
[3];
1194 union tgsi_exec_channel
*dst
,
1195 const union tgsi_exec_channel
*src0
,
1196 const union tgsi_exec_channel
*src1
)
1199 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1200 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1201 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1202 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1204 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1205 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1206 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1207 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1212 micro_sub(union tgsi_exec_channel
*dst
,
1213 const union tgsi_exec_channel
*src0
,
1214 const union tgsi_exec_channel
*src1
)
1216 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1217 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1218 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1219 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1223 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1224 const uint chan_index
,
1227 const union tgsi_exec_channel
*index
,
1228 const union tgsi_exec_channel
*index2D
,
1229 union tgsi_exec_channel
*chan
)
1233 assert(swizzle
< 4);
1236 case TGSI_FILE_CONSTANT
:
1237 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1238 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1239 assert(mach
->Consts
[index2D
->i
[i
]]);
1241 if (index
->i
[i
] < 0) {
1244 /* NOTE: copying the const value as a uint instead of float */
1245 const uint constbuf
= index2D
->i
[i
];
1246 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1247 const int pos
= index
->i
[i
] * 4 + swizzle
;
1248 /* const buffer bounds check */
1249 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1251 /* Debug: print warning */
1252 static int count
= 0;
1254 debug_printf("TGSI Exec: const buffer index %d"
1255 " out of bounds\n", pos
);
1260 chan
->u
[i
] = buf
[pos
];
1265 case TGSI_FILE_INPUT
:
1266 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1268 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1269 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1270 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1271 index2D->i[i], index->i[i]);
1273 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1275 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1276 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1280 case TGSI_FILE_SYSTEM_VALUE
:
1281 /* XXX no swizzling at this point. Will be needed if we put
1282 * gl_FragCoord, for example, in a sys value register.
1284 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1285 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1289 case TGSI_FILE_TEMPORARY
:
1290 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1291 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1292 assert(index2D
->i
[i
] == 0);
1294 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1298 case TGSI_FILE_IMMEDIATE
:
1299 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1300 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1301 assert(index2D
->i
[i
] == 0);
1303 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1307 case TGSI_FILE_ADDRESS
:
1308 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1309 assert(index
->i
[i
] >= 0);
1310 assert(index2D
->i
[i
] == 0);
1312 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1316 case TGSI_FILE_PREDICATE
:
1317 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1318 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1319 assert(index2D
->i
[i
] == 0);
1321 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1325 case TGSI_FILE_OUTPUT
:
1326 /* vertex/fragment output vars can be read too */
1327 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1328 assert(index
->i
[i
] >= 0);
1329 assert(index2D
->i
[i
] == 0);
1331 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1337 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1344 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1345 union tgsi_exec_channel
*chan
,
1346 const struct tgsi_full_src_register
*reg
,
1347 const uint chan_index
,
1348 enum tgsi_exec_datatype src_datatype
)
1350 union tgsi_exec_channel index
;
1351 union tgsi_exec_channel index2D
;
1354 /* We start with a direct index into a register file.
1358 * file = Register.File
1359 * [1] = Register.Index
1364 index
.i
[3] = reg
->Register
.Index
;
1366 /* There is an extra source register that indirectly subscripts
1367 * a register file. The direct index now becomes an offset
1368 * that is being added to the indirect register.
1372 * ind = Indirect.File
1373 * [2] = Indirect.Index
1374 * .x = Indirect.SwizzleX
1376 if (reg
->Register
.Indirect
) {
1377 union tgsi_exec_channel index2
;
1378 union tgsi_exec_channel indir_index
;
1379 const uint execmask
= mach
->ExecMask
;
1382 /* which address register (always zero now) */
1386 index2
.i
[3] = reg
->Indirect
.Index
;
1387 /* get current value of address register[swizzle] */
1388 swizzle
= reg
->Indirect
.Swizzle
;
1389 fetch_src_file_channel(mach
,
1397 /* add value of address register to the offset */
1398 index
.i
[0] += indir_index
.i
[0];
1399 index
.i
[1] += indir_index
.i
[1];
1400 index
.i
[2] += indir_index
.i
[2];
1401 index
.i
[3] += indir_index
.i
[3];
1403 /* for disabled execution channels, zero-out the index to
1404 * avoid using a potential garbage value.
1406 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1407 if ((execmask
& (1 << i
)) == 0)
1412 /* There is an extra source register that is a second
1413 * subscript to a register file. Effectively it means that
1414 * the register file is actually a 2D array of registers.
1418 * [3] = Dimension.Index
1420 if (reg
->Register
.Dimension
) {
1424 index2D
.i
[3] = reg
->Dimension
.Index
;
1426 /* Again, the second subscript index can be addressed indirectly
1427 * identically to the first one.
1428 * Nothing stops us from indirectly addressing the indirect register,
1429 * but there is no need for that, so we won't exercise it.
1431 * file[ind[4].y+3][1],
1433 * ind = DimIndirect.File
1434 * [4] = DimIndirect.Index
1435 * .y = DimIndirect.SwizzleX
1437 if (reg
->Dimension
.Indirect
) {
1438 union tgsi_exec_channel index2
;
1439 union tgsi_exec_channel indir_index
;
1440 const uint execmask
= mach
->ExecMask
;
1446 index2
.i
[3] = reg
->DimIndirect
.Index
;
1448 swizzle
= reg
->DimIndirect
.Swizzle
;
1449 fetch_src_file_channel(mach
,
1451 reg
->DimIndirect
.File
,
1457 index2D
.i
[0] += indir_index
.i
[0];
1458 index2D
.i
[1] += indir_index
.i
[1];
1459 index2D
.i
[2] += indir_index
.i
[2];
1460 index2D
.i
[3] += indir_index
.i
[3];
1462 /* for disabled execution channels, zero-out the index to
1463 * avoid using a potential garbage value.
1465 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1466 if ((execmask
& (1 << i
)) == 0) {
1472 /* If by any chance there was a need for a 3D array of register
1473 * files, we would have to check whether Dimension is followed
1474 * by a dimension register and continue the saga.
1483 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1484 fetch_src_file_channel(mach
,
1494 fetch_source(const struct tgsi_exec_machine
*mach
,
1495 union tgsi_exec_channel
*chan
,
1496 const struct tgsi_full_src_register
*reg
,
1497 const uint chan_index
,
1498 enum tgsi_exec_datatype src_datatype
)
1500 fetch_source_d(mach
, chan
, reg
, chan_index
, src_datatype
);
1502 if (reg
->Register
.Absolute
) {
1503 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1504 micro_abs(chan
, chan
);
1506 micro_iabs(chan
, chan
);
1510 if (reg
->Register
.Negate
) {
1511 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1512 micro_neg(chan
, chan
);
1514 micro_ineg(chan
, chan
);
1519 static union tgsi_exec_channel
*
1520 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1521 const union tgsi_exec_channel
*chan
,
1522 const struct tgsi_full_dst_register
*reg
,
1523 const struct tgsi_full_instruction
*inst
,
1525 enum tgsi_exec_datatype dst_datatype
)
1528 static union tgsi_exec_channel null
;
1529 union tgsi_exec_channel
*dst
;
1530 union tgsi_exec_channel index2D
;
1531 uint execmask
= mach
->ExecMask
;
1532 int offset
= 0; /* indirection offset */
1536 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1537 check_inf_or_nan(chan
);
1540 /* There is an extra source register that indirectly subscripts
1541 * a register file. The direct index now becomes an offset
1542 * that is being added to the indirect register.
1546 * ind = Indirect.File
1547 * [2] = Indirect.Index
1548 * .x = Indirect.SwizzleX
1550 if (reg
->Register
.Indirect
) {
1551 union tgsi_exec_channel index
;
1552 union tgsi_exec_channel indir_index
;
1555 /* which address register (always zero for now) */
1559 index
.i
[3] = reg
->Indirect
.Index
;
1561 /* get current value of address register[swizzle] */
1562 swizzle
= reg
->Indirect
.Swizzle
;
1564 /* fetch values from the address/indirection register */
1565 fetch_src_file_channel(mach
,
1573 /* save indirection offset */
1574 offset
= indir_index
.i
[0];
1577 /* There is an extra source register that is a second
1578 * subscript to a register file. Effectively it means that
1579 * the register file is actually a 2D array of registers.
1583 * [3] = Dimension.Index
1585 if (reg
->Register
.Dimension
) {
1589 index2D
.i
[3] = reg
->Dimension
.Index
;
1591 /* Again, the second subscript index can be addressed indirectly
1592 * identically to the first one.
1593 * Nothing stops us from indirectly addressing the indirect register,
1594 * but there is no need for that, so we won't exercise it.
1596 * file[ind[4].y+3][1],
1598 * ind = DimIndirect.File
1599 * [4] = DimIndirect.Index
1600 * .y = DimIndirect.SwizzleX
1602 if (reg
->Dimension
.Indirect
) {
1603 union tgsi_exec_channel index2
;
1604 union tgsi_exec_channel indir_index
;
1605 const uint execmask
= mach
->ExecMask
;
1612 index2
.i
[3] = reg
->DimIndirect
.Index
;
1614 swizzle
= reg
->DimIndirect
.Swizzle
;
1615 fetch_src_file_channel(mach
,
1617 reg
->DimIndirect
.File
,
1623 index2D
.i
[0] += indir_index
.i
[0];
1624 index2D
.i
[1] += indir_index
.i
[1];
1625 index2D
.i
[2] += indir_index
.i
[2];
1626 index2D
.i
[3] += indir_index
.i
[3];
1628 /* for disabled execution channels, zero-out the index to
1629 * avoid using a potential garbage value.
1631 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1632 if ((execmask
& (1 << i
)) == 0) {
1638 /* If by any chance there was a need for a 3D array of register
1639 * files, we would have to check whether Dimension is followed
1640 * by a dimension register and continue the saga.
1649 switch (reg
->Register
.File
) {
1650 case TGSI_FILE_NULL
:
1654 case TGSI_FILE_OUTPUT
:
1655 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1656 + reg
->Register
.Index
;
1657 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1659 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1660 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1661 reg
->Register
.Index
);
1662 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1663 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1664 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1665 if (execmask
& (1 << i
))
1666 debug_printf("%f, ", chan
->f
[i
]);
1667 debug_printf(")\n");
1672 case TGSI_FILE_TEMPORARY
:
1673 index
= reg
->Register
.Index
;
1674 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1675 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1678 case TGSI_FILE_ADDRESS
:
1679 index
= reg
->Register
.Index
;
1680 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1683 case TGSI_FILE_PREDICATE
:
1684 index
= reg
->Register
.Index
;
1685 assert(index
< TGSI_EXEC_NUM_PREDS
);
1686 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1694 if (inst
->Instruction
.Predicate
) {
1696 union tgsi_exec_channel
*pred
;
1698 switch (chan_index
) {
1700 swizzle
= inst
->Predicate
.SwizzleX
;
1703 swizzle
= inst
->Predicate
.SwizzleY
;
1706 swizzle
= inst
->Predicate
.SwizzleZ
;
1709 swizzle
= inst
->Predicate
.SwizzleW
;
1716 assert(inst
->Predicate
.Index
== 0);
1718 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1720 if (inst
->Predicate
.Negate
) {
1721 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1723 execmask
&= ~(1 << i
);
1727 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1729 execmask
&= ~(1 << i
);
1739 store_dest_double(struct tgsi_exec_machine
*mach
,
1740 const union tgsi_exec_channel
*chan
,
1741 const struct tgsi_full_dst_register
*reg
,
1742 const struct tgsi_full_instruction
*inst
,
1744 enum tgsi_exec_datatype dst_datatype
)
1746 union tgsi_exec_channel
*dst
;
1747 const uint execmask
= mach
->ExecMask
;
1750 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1756 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1757 if (execmask
& (1 << i
))
1758 dst
->i
[i
] = chan
->i
[i
];
1762 store_dest(struct tgsi_exec_machine
*mach
,
1763 const union tgsi_exec_channel
*chan
,
1764 const struct tgsi_full_dst_register
*reg
,
1765 const struct tgsi_full_instruction
*inst
,
1767 enum tgsi_exec_datatype dst_datatype
)
1769 union tgsi_exec_channel
*dst
;
1770 const uint execmask
= mach
->ExecMask
;
1773 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1778 if (!inst
->Instruction
.Saturate
) {
1779 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1780 if (execmask
& (1 << i
))
1781 dst
->i
[i
] = chan
->i
[i
];
1784 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1785 if (execmask
& (1 << i
)) {
1786 if (chan
->f
[i
] < 0.0f
)
1788 else if (chan
->f
[i
] > 1.0f
)
1791 dst
->i
[i
] = chan
->i
[i
];
1796 #define FETCH(VAL,INDEX,CHAN)\
1797 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1799 #define IFETCH(VAL,INDEX,CHAN)\
1800 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1804 * Execute ARB-style KIL which is predicated by a src register.
1805 * Kill fragment if any of the four values is less than zero.
1808 exec_kill_if(struct tgsi_exec_machine
*mach
,
1809 const struct tgsi_full_instruction
*inst
)
1813 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1814 union tgsi_exec_channel r
[1];
1816 /* This mask stores component bits that were already tested. */
1819 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1824 /* unswizzle channel */
1825 swizzle
= tgsi_util_get_full_src_register_swizzle (
1829 /* check if the component has not been already tested */
1830 if (uniquemask
& (1 << swizzle
))
1832 uniquemask
|= 1 << swizzle
;
1834 FETCH(&r
[0], 0, chan_index
);
1835 for (i
= 0; i
< 4; i
++)
1836 if (r
[0].f
[i
] < 0.0f
)
1840 /* restrict to fragments currently executing */
1841 kilmask
&= mach
->ExecMask
;
1843 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1847 * Unconditional fragment kill/discard.
1850 exec_kill(struct tgsi_exec_machine
*mach
,
1851 const struct tgsi_full_instruction
*inst
)
1853 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1855 /* kill fragment for all fragments currently executing */
1856 kilmask
= mach
->ExecMask
;
1857 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1861 emit_vertex(struct tgsi_exec_machine
*mach
)
1863 /* FIXME: check for exec mask correctly
1865 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1866 if ((mach->ExecMask & (1 << i)))
1868 if (mach
->ExecMask
) {
1869 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
1872 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1873 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1878 emit_primitive(struct tgsi_exec_machine
*mach
)
1880 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1881 /* FIXME: check for exec mask correctly
1883 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1884 if ((mach->ExecMask & (1 << i)))
1886 if (mach
->ExecMask
) {
1888 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1889 mach
->Primitives
[*prim_count
] = 0;
1894 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1896 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1898 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1899 if (emitted_verts
) {
1900 emit_primitive(mach
);
1907 * Fetch four texture samples using STR texture coordinates.
1910 fetch_texel( struct tgsi_sampler
*sampler
,
1911 const unsigned sview_idx
,
1912 const unsigned sampler_idx
,
1913 const union tgsi_exec_channel
*s
,
1914 const union tgsi_exec_channel
*t
,
1915 const union tgsi_exec_channel
*p
,
1916 const union tgsi_exec_channel
*c0
,
1917 const union tgsi_exec_channel
*c1
,
1918 float derivs
[3][2][TGSI_QUAD_SIZE
],
1919 const int8_t offset
[3],
1920 enum tgsi_sampler_control control
,
1921 union tgsi_exec_channel
*r
,
1922 union tgsi_exec_channel
*g
,
1923 union tgsi_exec_channel
*b
,
1924 union tgsi_exec_channel
*a
)
1927 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1929 /* FIXME: handle explicit derivs, offsets */
1930 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
1931 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
1933 for (j
= 0; j
< 4; j
++) {
1934 r
->f
[j
] = rgba
[0][j
];
1935 g
->f
[j
] = rgba
[1][j
];
1936 b
->f
[j
] = rgba
[2][j
];
1937 a
->f
[j
] = rgba
[3][j
];
1942 #define TEX_MODIFIER_NONE 0
1943 #define TEX_MODIFIER_PROJECTED 1
1944 #define TEX_MODIFIER_LOD_BIAS 2
1945 #define TEX_MODIFIER_EXPLICIT_LOD 3
1946 #define TEX_MODIFIER_LEVEL_ZERO 4
1947 #define TEX_MODIFIER_GATHER 5
1950 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1953 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
1954 const struct tgsi_full_instruction
*inst
,
1957 if (inst
->Texture
.NumOffsets
== 1) {
1958 union tgsi_exec_channel index
;
1959 union tgsi_exec_channel offset
[3];
1960 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
1961 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1962 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
1963 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1964 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
1965 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1966 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
1967 offsets
[0] = offset
[0].i
[0];
1968 offsets
[1] = offset
[1].i
[0];
1969 offsets
[2] = offset
[2].i
[0];
1971 assert(inst
->Texture
.NumOffsets
== 0);
1972 offsets
[0] = offsets
[1] = offsets
[2] = 0;
1978 * Fetch dx and dy values for one channel (s, t or r).
1979 * Put dx values into one float array, dy values into another.
1982 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
1983 const struct tgsi_full_instruction
*inst
,
1986 float derivs
[2][TGSI_QUAD_SIZE
])
1988 union tgsi_exec_channel d
;
1989 FETCH(&d
, regdsrcx
, chan
);
1990 derivs
[0][0] = d
.f
[0];
1991 derivs
[0][1] = d
.f
[1];
1992 derivs
[0][2] = d
.f
[2];
1993 derivs
[0][3] = d
.f
[3];
1994 FETCH(&d
, regdsrcx
+ 1, chan
);
1995 derivs
[1][0] = d
.f
[0];
1996 derivs
[1][1] = d
.f
[1];
1997 derivs
[1][2] = d
.f
[2];
1998 derivs
[1][3] = d
.f
[3];
2002 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2003 const struct tgsi_full_instruction
*inst
,
2008 if (inst
->Src
[sampler
].Register
.Indirect
) {
2009 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2010 union tgsi_exec_channel indir_index
, index2
;
2011 const uint execmask
= mach
->ExecMask
;
2015 index2
.i
[3] = reg
->Indirect
.Index
;
2017 fetch_src_file_channel(mach
,
2020 reg
->Indirect
.Swizzle
,
2024 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2025 if (execmask
& (1 << i
)) {
2026 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2032 unit
= inst
->Src
[sampler
].Register
.Index
;
2038 * execute a texture instruction.
2040 * modifier is used to control the channel routing for the
2041 * instruction variants like proj, lod, and texture with lod bias.
2042 * sampler indicates which src register the sampler is contained in.
2045 exec_tex(struct tgsi_exec_machine
*mach
,
2046 const struct tgsi_full_instruction
*inst
,
2047 uint modifier
, uint sampler
)
2049 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2050 union tgsi_exec_channel r
[5];
2051 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2055 int dim
, shadow_ref
, i
;
2057 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2058 /* always fetch all 3 offsets, overkill but keeps code simple */
2059 fetch_texel_offsets(mach
, inst
, offsets
);
2061 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2062 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2064 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2065 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2068 if (shadow_ref
>= 0)
2069 assert(shadow_ref
>= dim
&& shadow_ref
< Elements(args
));
2071 /* fetch modifier to the last argument */
2072 if (modifier
!= TEX_MODIFIER_NONE
) {
2073 const int last
= Elements(args
) - 1;
2075 /* fetch modifier from src0.w or src1.x */
2077 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2078 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2081 assert(shadow_ref
!= 4);
2082 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2085 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2086 args
[last
] = &r
[last
];
2090 args
[last
] = &ZeroVec
;
2093 /* point unused arguments to zero vector */
2094 for (i
= dim
; i
< last
; i
++)
2097 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2098 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2099 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2100 control
= TGSI_SAMPLER_LOD_BIAS
;
2101 else if (modifier
== TEX_MODIFIER_GATHER
)
2102 control
= TGSI_SAMPLER_GATHER
;
2105 for (i
= dim
; i
< Elements(args
); i
++)
2109 /* fetch coordinates */
2110 for (i
= 0; i
< dim
; i
++) {
2111 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2114 micro_div(&r
[i
], &r
[i
], proj
);
2119 /* fetch reference value */
2120 if (shadow_ref
>= 0) {
2121 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2124 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2126 args
[shadow_ref
] = &r
[shadow_ref
];
2129 fetch_texel(mach
->Sampler
, unit
, unit
,
2130 args
[0], args
[1], args
[2], args
[3], args
[4],
2131 NULL
, offsets
, control
,
2132 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2135 debug_printf("fetch r: %g %g %g %g\n",
2136 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2137 debug_printf("fetch g: %g %g %g %g\n",
2138 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2139 debug_printf("fetch b: %g %g %g %g\n",
2140 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2141 debug_printf("fetch a: %g %g %g %g\n",
2142 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2145 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2146 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2147 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2153 exec_lodq(struct tgsi_exec_machine
*mach
,
2154 const struct tgsi_full_instruction
*inst
)
2159 union tgsi_exec_channel coords
[4];
2160 const union tgsi_exec_channel
*args
[Elements(coords
)];
2161 union tgsi_exec_channel r
[2];
2163 unit
= fetch_sampler_unit(mach
, inst
, 1);
2164 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2165 assert(dim
<= Elements(coords
));
2166 /* fetch coordinates */
2167 for (i
= 0; i
< dim
; i
++) {
2168 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2169 args
[i
] = &coords
[i
];
2171 for (i
= dim
; i
< Elements(coords
); i
++) {
2174 mach
->Sampler
->query_lod(mach
->Sampler
, unit
, unit
,
2179 TGSI_SAMPLER_LOD_NONE
,
2183 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2184 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2185 TGSI_EXEC_DATA_FLOAT
);
2187 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2188 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2189 TGSI_EXEC_DATA_FLOAT
);
2194 exec_txd(struct tgsi_exec_machine
*mach
,
2195 const struct tgsi_full_instruction
*inst
)
2197 union tgsi_exec_channel r
[4];
2198 float derivs
[3][2][TGSI_QUAD_SIZE
];
2203 unit
= fetch_sampler_unit(mach
, inst
, 3);
2204 /* always fetch all 3 offsets, overkill but keeps code simple */
2205 fetch_texel_offsets(mach
, inst
, offsets
);
2207 switch (inst
->Texture
.Texture
) {
2208 case TGSI_TEXTURE_1D
:
2209 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2211 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2213 fetch_texel(mach
->Sampler
, unit
, unit
,
2214 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2215 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2216 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2219 case TGSI_TEXTURE_SHADOW1D
:
2220 case TGSI_TEXTURE_1D_ARRAY
:
2221 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2222 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2223 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2224 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2225 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2227 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2229 fetch_texel(mach
->Sampler
, unit
, unit
,
2230 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2231 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2232 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2235 case TGSI_TEXTURE_2D
:
2236 case TGSI_TEXTURE_RECT
:
2237 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2238 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2240 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2241 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2243 fetch_texel(mach
->Sampler
, unit
, unit
,
2244 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2245 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2246 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2250 case TGSI_TEXTURE_SHADOW2D
:
2251 case TGSI_TEXTURE_SHADOWRECT
:
2252 case TGSI_TEXTURE_2D_ARRAY
:
2253 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2254 /* only SHADOW2D_ARRAY actually needs W */
2255 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2256 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2257 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2258 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2260 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2261 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2263 fetch_texel(mach
->Sampler
, unit
, unit
,
2264 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2265 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2266 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2269 case TGSI_TEXTURE_3D
:
2270 case TGSI_TEXTURE_CUBE
:
2271 case TGSI_TEXTURE_CUBE_ARRAY
:
2272 case TGSI_TEXTURE_SHADOWCUBE
:
2273 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2274 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2275 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2276 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2277 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2279 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2280 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2281 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2283 fetch_texel(mach
->Sampler
, unit
, unit
,
2284 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2285 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2286 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2293 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2294 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2295 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2302 exec_txf(struct tgsi_exec_machine
*mach
,
2303 const struct tgsi_full_instruction
*inst
)
2305 union tgsi_exec_channel r
[4];
2308 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2313 unit
= fetch_sampler_unit(mach
, inst
, 1);
2314 /* always fetch all 3 offsets, overkill but keeps code simple */
2315 fetch_texel_offsets(mach
, inst
, offsets
);
2317 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2319 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2320 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2321 target
= mach
->SamplerViews
[unit
].Resource
;
2324 target
= inst
->Texture
.Texture
;
2327 case TGSI_TEXTURE_3D
:
2328 case TGSI_TEXTURE_2D_ARRAY
:
2329 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2330 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2331 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2333 case TGSI_TEXTURE_2D
:
2334 case TGSI_TEXTURE_RECT
:
2335 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2336 case TGSI_TEXTURE_SHADOW2D
:
2337 case TGSI_TEXTURE_SHADOWRECT
:
2338 case TGSI_TEXTURE_1D_ARRAY
:
2339 case TGSI_TEXTURE_2D_MSAA
:
2340 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2342 case TGSI_TEXTURE_BUFFER
:
2343 case TGSI_TEXTURE_1D
:
2344 case TGSI_TEXTURE_SHADOW1D
:
2345 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2352 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2355 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2356 r
[0].f
[j
] = rgba
[0][j
];
2357 r
[1].f
[j
] = rgba
[1][j
];
2358 r
[2].f
[j
] = rgba
[2][j
];
2359 r
[3].f
[j
] = rgba
[3][j
];
2362 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2363 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2364 unsigned char swizzles
[4];
2365 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2366 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2367 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2368 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2370 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2371 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2372 store_dest(mach
, &r
[swizzles
[chan
]],
2373 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2378 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2379 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2380 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2387 exec_txq(struct tgsi_exec_machine
*mach
,
2388 const struct tgsi_full_instruction
*inst
)
2391 union tgsi_exec_channel r
[4], src
;
2396 unit
= fetch_sampler_unit(mach
, inst
, 1);
2398 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2400 /* XXX: This interface can't return per-pixel values */
2401 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2403 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2404 for (j
= 0; j
< 4; j
++) {
2405 r
[j
].i
[i
] = result
[j
];
2409 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2410 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2411 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2412 TGSI_EXEC_DATA_INT
);
2418 exec_sample(struct tgsi_exec_machine
*mach
,
2419 const struct tgsi_full_instruction
*inst
,
2420 uint modifier
, boolean compare
)
2422 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2423 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2424 union tgsi_exec_channel r
[5], c1
;
2425 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2426 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2428 unsigned char swizzles
[4];
2431 /* always fetch all 3 offsets, overkill but keeps code simple */
2432 fetch_texel_offsets(mach
, inst
, offsets
);
2434 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2436 if (modifier
!= TEX_MODIFIER_NONE
) {
2437 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2438 FETCH(&c1
, 3, TGSI_CHAN_X
);
2440 control
= TGSI_SAMPLER_LOD_BIAS
;
2442 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2443 FETCH(&c1
, 3, TGSI_CHAN_X
);
2445 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2448 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2449 control
= TGSI_SAMPLER_LOD_ZERO
;
2453 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2455 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2456 case TGSI_TEXTURE_1D
:
2458 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2459 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2460 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2461 NULL
, offsets
, control
,
2462 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2465 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2466 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2467 NULL
, offsets
, control
,
2468 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2472 case TGSI_TEXTURE_1D_ARRAY
:
2473 case TGSI_TEXTURE_2D
:
2474 case TGSI_TEXTURE_RECT
:
2475 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2477 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2478 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2479 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2480 NULL
, offsets
, control
,
2481 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2484 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2485 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2486 NULL
, offsets
, control
,
2487 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2491 case TGSI_TEXTURE_2D_ARRAY
:
2492 case TGSI_TEXTURE_3D
:
2493 case TGSI_TEXTURE_CUBE
:
2494 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2495 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2497 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2498 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2499 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2500 NULL
, offsets
, control
,
2501 &r
[0], &r
[1], &r
[2], &r
[3]);
2504 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2505 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2506 NULL
, offsets
, control
,
2507 &r
[0], &r
[1], &r
[2], &r
[3]);
2511 case TGSI_TEXTURE_CUBE_ARRAY
:
2512 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2513 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2514 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2516 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2517 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2518 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2519 NULL
, offsets
, control
,
2520 &r
[0], &r
[1], &r
[2], &r
[3]);
2523 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2524 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2525 NULL
, offsets
, control
,
2526 &r
[0], &r
[1], &r
[2], &r
[3]);
2535 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2536 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2537 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2538 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2540 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2541 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2542 store_dest(mach
, &r
[swizzles
[chan
]],
2543 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2549 exec_sample_d(struct tgsi_exec_machine
*mach
,
2550 const struct tgsi_full_instruction
*inst
)
2552 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2553 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2554 union tgsi_exec_channel r
[4];
2555 float derivs
[3][2][TGSI_QUAD_SIZE
];
2557 unsigned char swizzles
[4];
2560 /* always fetch all 3 offsets, overkill but keeps code simple */
2561 fetch_texel_offsets(mach
, inst
, offsets
);
2563 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2565 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2566 case TGSI_TEXTURE_1D
:
2567 case TGSI_TEXTURE_1D_ARRAY
:
2568 /* only 1D array actually needs Y */
2569 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2571 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2573 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2574 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2575 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2576 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2579 case TGSI_TEXTURE_2D
:
2580 case TGSI_TEXTURE_RECT
:
2581 case TGSI_TEXTURE_2D_ARRAY
:
2582 /* only 2D array actually needs Z */
2583 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2584 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2586 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2587 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2589 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2590 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2591 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2592 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2595 case TGSI_TEXTURE_3D
:
2596 case TGSI_TEXTURE_CUBE
:
2597 case TGSI_TEXTURE_CUBE_ARRAY
:
2598 /* only cube array actually needs W */
2599 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2600 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2601 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2603 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2604 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2605 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2607 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2608 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2609 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2610 &r
[0], &r
[1], &r
[2], &r
[3]);
2617 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2618 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2619 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2620 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2622 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2623 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2624 store_dest(mach
, &r
[swizzles
[chan
]],
2625 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2632 * Evaluate a constant-valued coefficient at the position of the
2637 struct tgsi_exec_machine
*mach
,
2643 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2644 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2649 * Evaluate a linear-valued coefficient at the position of the
2654 struct tgsi_exec_machine
*mach
,
2658 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2659 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2660 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2661 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2662 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2663 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2664 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2665 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2666 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2670 * Evaluate a perspective-valued coefficient at the position of the
2674 eval_perspective_coef(
2675 struct tgsi_exec_machine
*mach
,
2679 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2680 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2681 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2682 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2683 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2684 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2685 /* divide by W here */
2686 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2687 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2688 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2689 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2693 typedef void (* eval_coef_func
)(
2694 struct tgsi_exec_machine
*mach
,
2699 exec_declaration(struct tgsi_exec_machine
*mach
,
2700 const struct tgsi_full_declaration
*decl
)
2702 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2703 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2707 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2708 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2709 uint first
, last
, mask
;
2711 first
= decl
->Range
.First
;
2712 last
= decl
->Range
.Last
;
2713 mask
= decl
->Declaration
.UsageMask
;
2715 /* XXX we could remove this special-case code since
2716 * mach->InterpCoefs[first].a0 should already have the
2717 * front/back-face value. But we should first update the
2718 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2719 * Then, we could remove the tgsi_exec_machine::Face field.
2721 /* XXX make FACE a system value */
2722 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2725 assert(decl
->Semantic
.Index
== 0);
2726 assert(first
== last
);
2728 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2729 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2732 eval_coef_func eval
;
2735 switch (decl
->Interp
.Interpolate
) {
2736 case TGSI_INTERPOLATE_CONSTANT
:
2737 eval
= eval_constant_coef
;
2740 case TGSI_INTERPOLATE_LINEAR
:
2741 eval
= eval_linear_coef
;
2744 case TGSI_INTERPOLATE_PERSPECTIVE
:
2745 eval
= eval_perspective_coef
;
2748 case TGSI_INTERPOLATE_COLOR
:
2749 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2757 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2758 if (mask
& (1 << j
)) {
2759 for (i
= first
; i
<= last
; i
++) {
2766 if (DEBUG_EXECUTION
) {
2768 for (i
= first
; i
<= last
; ++i
) {
2769 debug_printf("IN[%2u] = ", i
);
2770 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2774 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2775 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2776 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2777 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2778 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2787 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2788 const union tgsi_exec_channel
*src
);
2791 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2792 const struct tgsi_full_instruction
*inst
,
2794 enum tgsi_exec_datatype dst_datatype
,
2795 enum tgsi_exec_datatype src_datatype
)
2798 union tgsi_exec_channel src
;
2799 union tgsi_exec_channel dst
;
2801 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2803 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2804 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2805 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2811 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2812 const struct tgsi_full_instruction
*inst
,
2814 enum tgsi_exec_datatype dst_datatype
,
2815 enum tgsi_exec_datatype src_datatype
)
2818 struct tgsi_exec_vector dst
;
2820 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2821 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2822 union tgsi_exec_channel src
;
2824 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2825 op(&dst
.xyzw
[chan
], &src
);
2828 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2829 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2830 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2835 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2836 const union tgsi_exec_channel
*src0
,
2837 const union tgsi_exec_channel
*src1
);
2840 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2841 const struct tgsi_full_instruction
*inst
,
2843 enum tgsi_exec_datatype dst_datatype
,
2844 enum tgsi_exec_datatype src_datatype
)
2847 union tgsi_exec_channel src
[2];
2848 union tgsi_exec_channel dst
;
2850 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2851 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
2852 op(&dst
, &src
[0], &src
[1]);
2853 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2854 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2855 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2861 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2862 const struct tgsi_full_instruction
*inst
,
2864 enum tgsi_exec_datatype dst_datatype
,
2865 enum tgsi_exec_datatype src_datatype
)
2868 struct tgsi_exec_vector dst
;
2870 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2871 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2872 union tgsi_exec_channel src
[2];
2874 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2875 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2876 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2879 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2880 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2881 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2886 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2887 const union tgsi_exec_channel
*src0
,
2888 const union tgsi_exec_channel
*src1
,
2889 const union tgsi_exec_channel
*src2
);
2892 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2893 const struct tgsi_full_instruction
*inst
,
2894 micro_trinary_op op
,
2895 enum tgsi_exec_datatype dst_datatype
,
2896 enum tgsi_exec_datatype src_datatype
)
2899 struct tgsi_exec_vector dst
;
2901 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2902 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2903 union tgsi_exec_channel src
[3];
2905 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2906 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2907 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2908 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2911 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2912 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2913 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2918 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
2919 const union tgsi_exec_channel
*src0
,
2920 const union tgsi_exec_channel
*src1
,
2921 const union tgsi_exec_channel
*src2
,
2922 const union tgsi_exec_channel
*src3
);
2925 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
2926 const struct tgsi_full_instruction
*inst
,
2927 micro_quaternary_op op
,
2928 enum tgsi_exec_datatype dst_datatype
,
2929 enum tgsi_exec_datatype src_datatype
)
2932 struct tgsi_exec_vector dst
;
2934 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2935 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2936 union tgsi_exec_channel src
[4];
2938 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2939 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2940 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2941 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
2942 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
2945 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2946 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2947 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2953 exec_dp3(struct tgsi_exec_machine
*mach
,
2954 const struct tgsi_full_instruction
*inst
)
2957 union tgsi_exec_channel arg
[3];
2959 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2960 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2961 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2963 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2964 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2965 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2966 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2969 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2970 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2971 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2977 exec_dp4(struct tgsi_exec_machine
*mach
,
2978 const struct tgsi_full_instruction
*inst
)
2981 union tgsi_exec_channel arg
[3];
2983 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2984 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2985 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2987 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2988 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2989 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2990 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2993 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2994 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2995 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3001 exec_dp2a(struct tgsi_exec_machine
*mach
,
3002 const struct tgsi_full_instruction
*inst
)
3005 union tgsi_exec_channel arg
[3];
3007 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3008 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3009 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3011 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3012 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3013 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3015 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3016 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3018 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3019 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3020 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3026 exec_dph(struct tgsi_exec_machine
*mach
,
3027 const struct tgsi_full_instruction
*inst
)
3030 union tgsi_exec_channel arg
[3];
3032 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3033 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3034 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3036 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3037 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3038 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3040 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3041 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3042 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3044 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3045 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3047 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3048 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3049 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3055 exec_dp2(struct tgsi_exec_machine
*mach
,
3056 const struct tgsi_full_instruction
*inst
)
3059 union tgsi_exec_channel arg
[3];
3061 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3062 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3063 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3065 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3066 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3067 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3069 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3070 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3071 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3077 exec_pk2h(struct tgsi_exec_machine
*mach
,
3078 const struct tgsi_full_instruction
*inst
)
3081 union tgsi_exec_channel arg
[2], dst
;
3083 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3084 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3085 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3086 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3087 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3089 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3090 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3091 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3097 exec_up2h(struct tgsi_exec_machine
*mach
,
3098 const struct tgsi_full_instruction
*inst
)
3101 union tgsi_exec_channel arg
, dst
[2];
3103 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3104 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3105 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3106 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3108 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3109 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3110 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3116 exec_scs(struct tgsi_exec_machine
*mach
,
3117 const struct tgsi_full_instruction
*inst
)
3119 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
3120 union tgsi_exec_channel arg
;
3121 union tgsi_exec_channel result
;
3123 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3125 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3126 micro_cos(&result
, &arg
);
3127 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3129 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3130 micro_sin(&result
, &arg
);
3131 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3134 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3135 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3137 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3138 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3143 exec_xpd(struct tgsi_exec_machine
*mach
,
3144 const struct tgsi_full_instruction
*inst
)
3146 union tgsi_exec_channel r
[6];
3147 union tgsi_exec_channel d
[3];
3149 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3150 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3152 micro_mul(&r
[2], &r
[0], &r
[1]);
3154 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3155 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3157 micro_mul(&r
[5], &r
[3], &r
[4] );
3158 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
3160 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3162 micro_mul(&r
[3], &r
[3], &r
[2]);
3164 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3166 micro_mul(&r
[1], &r
[1], &r
[5]);
3167 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
3169 micro_mul(&r
[5], &r
[5], &r
[4]);
3170 micro_mul(&r
[0], &r
[0], &r
[2]);
3171 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
3173 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3174 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3176 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3177 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3179 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3180 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3182 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3183 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3188 exec_dst(struct tgsi_exec_machine
*mach
,
3189 const struct tgsi_full_instruction
*inst
)
3191 union tgsi_exec_channel r
[2];
3192 union tgsi_exec_channel d
[4];
3194 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3195 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3196 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3197 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3199 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3200 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3202 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3203 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3206 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3207 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3209 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3210 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3212 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3213 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3215 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3216 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3221 exec_log(struct tgsi_exec_machine
*mach
,
3222 const struct tgsi_full_instruction
*inst
)
3224 union tgsi_exec_channel r
[3];
3226 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3227 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3228 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3229 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3230 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3231 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3233 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3234 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3235 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3236 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3238 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3239 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3241 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3242 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3247 exec_exp(struct tgsi_exec_machine
*mach
,
3248 const struct tgsi_full_instruction
*inst
)
3250 union tgsi_exec_channel r
[3];
3252 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3253 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3254 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3255 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3256 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3258 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3259 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3260 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3262 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3263 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3264 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3266 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3267 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3272 exec_lit(struct tgsi_exec_machine
*mach
,
3273 const struct tgsi_full_instruction
*inst
)
3275 union tgsi_exec_channel r
[3];
3276 union tgsi_exec_channel d
[3];
3278 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3279 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3280 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3281 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3282 micro_max(&r
[1], &r
[1], &ZeroVec
);
3284 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3285 micro_min(&r
[2], &r
[2], &P128Vec
);
3286 micro_max(&r
[2], &r
[2], &M128Vec
);
3287 micro_pow(&r
[1], &r
[1], &r
[2]);
3288 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3289 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3291 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3292 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3293 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3296 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3297 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3300 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3301 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3306 exec_break(struct tgsi_exec_machine
*mach
)
3308 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3309 /* turn off loop channels for each enabled exec channel */
3310 mach
->LoopMask
&= ~mach
->ExecMask
;
3311 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3312 UPDATE_EXEC_MASK(mach
);
3314 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3316 mach
->Switch
.mask
= 0x0;
3318 UPDATE_EXEC_MASK(mach
);
3323 exec_switch(struct tgsi_exec_machine
*mach
,
3324 const struct tgsi_full_instruction
*inst
)
3326 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3327 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3329 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3330 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3331 mach
->Switch
.mask
= 0x0;
3332 mach
->Switch
.defaultMask
= 0x0;
3334 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3335 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3337 UPDATE_EXEC_MASK(mach
);
3341 exec_case(struct tgsi_exec_machine
*mach
,
3342 const struct tgsi_full_instruction
*inst
)
3344 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3345 union tgsi_exec_channel src
;
3348 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3350 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3353 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3356 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3359 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3363 mach
->Switch
.defaultMask
|= mask
;
3365 mach
->Switch
.mask
|= mask
& prevMask
;
3367 UPDATE_EXEC_MASK(mach
);
3370 /* FIXME: this will only work if default is last */
3372 exec_default(struct tgsi_exec_machine
*mach
)
3374 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3376 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3378 UPDATE_EXEC_MASK(mach
);
3382 exec_endswitch(struct tgsi_exec_machine
*mach
)
3384 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3385 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3387 UPDATE_EXEC_MASK(mach
);
3390 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3391 const union tgsi_double_channel
*src
);
3394 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3395 union tgsi_double_channel
*chan
,
3396 const struct tgsi_full_src_register
*reg
,
3400 union tgsi_exec_channel src
[2];
3403 fetch_source_d(mach
, &src
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3404 fetch_source_d(mach
, &src
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3406 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3407 chan
->u
[i
][0] = src
[0].u
[i
];
3408 chan
->u
[i
][1] = src
[1].u
[i
];
3410 if (reg
->Register
.Absolute
) {
3411 micro_dabs(chan
, chan
);
3413 if (reg
->Register
.Negate
) {
3414 micro_dneg(chan
, chan
);
3419 store_double_channel(struct tgsi_exec_machine
*mach
,
3420 const union tgsi_double_channel
*chan
,
3421 const struct tgsi_full_dst_register
*reg
,
3422 const struct tgsi_full_instruction
*inst
,
3426 union tgsi_exec_channel dst
[2];
3428 union tgsi_double_channel temp
;
3429 const uint execmask
= mach
->ExecMask
;
3431 if (!inst
->Instruction
.Saturate
) {
3432 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3433 if (execmask
& (1 << i
)) {
3434 dst
[0].u
[i
] = chan
->u
[i
][0];
3435 dst
[1].u
[i
] = chan
->u
[i
][1];
3439 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3440 if (execmask
& (1 << i
)) {
3441 if (chan
->d
[i
] < 0.0)
3443 else if (chan
->d
[i
] > 1.0)
3446 temp
.d
[i
] = chan
->d
[i
];
3448 dst
[0].u
[i
] = temp
.u
[i
][0];
3449 dst
[1].u
[i
] = temp
.u
[i
][1];
3453 store_dest_double(mach
, &dst
[0], reg
, inst
, chan_0
, TGSI_EXEC_DATA_UINT
);
3455 store_dest_double(mach
, &dst
[1], reg
, inst
, chan_1
, TGSI_EXEC_DATA_UINT
);
3459 exec_double_unary(struct tgsi_exec_machine
*mach
,
3460 const struct tgsi_full_instruction
*inst
,
3463 union tgsi_double_channel src
;
3464 union tgsi_double_channel dst
;
3466 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3467 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3469 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3471 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3472 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3474 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3479 exec_double_binary(struct tgsi_exec_machine
*mach
,
3480 const struct tgsi_full_instruction
*inst
,
3482 enum tgsi_exec_datatype dst_datatype
)
3484 union tgsi_double_channel src
[2];
3485 union tgsi_double_channel dst
;
3486 int first_dest_chan
, second_dest_chan
;
3489 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3490 /* these are & because of the way DSLT etc store their destinations */
3491 if (wmask
& TGSI_WRITEMASK_XY
) {
3492 first_dest_chan
= TGSI_CHAN_X
;
3493 second_dest_chan
= TGSI_CHAN_Y
;
3494 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3495 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3496 second_dest_chan
= -1;
3499 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3500 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3502 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3505 if (wmask
& TGSI_WRITEMASK_ZW
) {
3506 first_dest_chan
= TGSI_CHAN_Z
;
3507 second_dest_chan
= TGSI_CHAN_W
;
3508 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3509 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3510 second_dest_chan
= -1;
3513 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3514 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3516 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3521 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3522 const struct tgsi_full_instruction
*inst
,
3525 union tgsi_double_channel src
[3];
3526 union tgsi_double_channel dst
;
3528 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3529 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3530 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3531 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3533 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3535 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3536 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3537 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3538 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3540 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3545 exec_f2d(struct tgsi_exec_machine
*mach
,
3546 const struct tgsi_full_instruction
*inst
)
3548 union tgsi_exec_channel src
;
3549 union tgsi_double_channel dst
;
3551 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3552 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3553 micro_f2d(&dst
, &src
);
3554 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3556 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3557 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3558 micro_f2d(&dst
, &src
);
3559 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3564 exec_d2f(struct tgsi_exec_machine
*mach
,
3565 const struct tgsi_full_instruction
*inst
)
3567 union tgsi_double_channel src
;
3568 union tgsi_exec_channel dst
;
3569 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3572 for (i
= 0; i
< 2; i
++) {
3575 wm
&= ~(1 << (bit
- 1));
3577 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3579 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3580 micro_d2f(&dst
, &src
);
3581 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_FLOAT
);
3587 exec_i2d(struct tgsi_exec_machine
*mach
,
3588 const struct tgsi_full_instruction
*inst
)
3590 union tgsi_exec_channel src
;
3591 union tgsi_double_channel dst
;
3593 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3594 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3595 micro_i2d(&dst
, &src
);
3596 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3598 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3599 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_INT
);
3600 micro_i2d(&dst
, &src
);
3601 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3606 exec_d2i(struct tgsi_exec_machine
*mach
,
3607 const struct tgsi_full_instruction
*inst
)
3609 union tgsi_double_channel src
;
3610 union tgsi_exec_channel dst
;
3611 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3614 for (i
= 0; i
< 2; i
++) {
3617 wm
&= ~(1 << (bit
- 1));
3619 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3621 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3622 micro_d2i(&dst
, &src
);
3623 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_INT
);
3628 exec_u2d(struct tgsi_exec_machine
*mach
,
3629 const struct tgsi_full_instruction
*inst
)
3631 union tgsi_exec_channel src
;
3632 union tgsi_double_channel dst
;
3634 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3635 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3636 micro_u2d(&dst
, &src
);
3637 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3639 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3640 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_UINT
);
3641 micro_u2d(&dst
, &src
);
3642 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3647 exec_d2u(struct tgsi_exec_machine
*mach
,
3648 const struct tgsi_full_instruction
*inst
)
3650 union tgsi_double_channel src
;
3651 union tgsi_exec_channel dst
;
3652 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3655 for (i
= 0; i
< 2; i
++) {
3658 wm
&= ~(1 << (bit
- 1));
3660 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3662 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3663 micro_d2u(&dst
, &src
);
3664 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_UINT
);
3670 exec_dldexp(struct tgsi_exec_machine
*mach
,
3671 const struct tgsi_full_instruction
*inst
)
3673 union tgsi_double_channel src0
;
3674 union tgsi_exec_channel src1
;
3675 union tgsi_double_channel dst
;
3678 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3679 if (wmask
& TGSI_WRITEMASK_XY
) {
3680 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3681 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3682 micro_dldexp(&dst
, &src0
, &src1
);
3683 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3686 if (wmask
& TGSI_WRITEMASK_ZW
) {
3687 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3688 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3689 micro_dldexp(&dst
, &src0
, &src1
);
3690 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3695 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3696 const struct tgsi_full_instruction
*inst
)
3698 union tgsi_double_channel src
;
3699 union tgsi_double_channel dst
;
3700 union tgsi_exec_channel dst_exp
;
3702 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)) {
3703 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3704 micro_dfracexp(&dst
, &dst_exp
, &src
);
3705 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3706 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3708 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)) {
3709 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3710 micro_dfracexp(&dst
, &dst_exp
, &src
);
3711 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3712 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3717 get_image_coord_dim(unsigned tgsi_tex
)
3721 case TGSI_TEXTURE_BUFFER
:
3722 case TGSI_TEXTURE_1D
:
3725 case TGSI_TEXTURE_2D
:
3726 case TGSI_TEXTURE_RECT
:
3727 case TGSI_TEXTURE_1D_ARRAY
:
3728 case TGSI_TEXTURE_2D_MSAA
:
3731 case TGSI_TEXTURE_3D
:
3732 case TGSI_TEXTURE_CUBE
:
3733 case TGSI_TEXTURE_2D_ARRAY
:
3734 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3735 case TGSI_TEXTURE_CUBE_ARRAY
:
3739 assert(!"unknown texture target");
3748 get_image_coord_sample(unsigned tgsi_tex
)
3752 case TGSI_TEXTURE_2D_MSAA
:
3755 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3765 exec_load_img(struct tgsi_exec_machine
*mach
,
3766 const struct tgsi_full_instruction
*inst
)
3768 union tgsi_exec_channel r
[4], sample_r
;
3774 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3775 struct tgsi_image_params params
;
3776 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3778 unit
= fetch_sampler_unit(mach
, inst
, 0);
3779 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3780 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3783 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3785 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3786 params
.format
= inst
->Memory
.Format
;
3788 for (i
= 0; i
< dim
; i
++) {
3789 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3793 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3795 mach
->Image
->load(mach
->Image
, ¶ms
,
3796 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3798 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3799 r
[0].f
[j
] = rgba
[0][j
];
3800 r
[1].f
[j
] = rgba
[1][j
];
3801 r
[2].f
[j
] = rgba
[2][j
];
3802 r
[3].f
[j
] = rgba
[3][j
];
3804 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3805 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3806 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3812 exec_load_buf(struct tgsi_exec_machine
*mach
,
3813 const struct tgsi_full_instruction
*inst
)
3815 union tgsi_exec_channel r
[4];
3819 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3820 struct tgsi_buffer_params params
;
3821 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3823 unit
= fetch_sampler_unit(mach
, inst
, 0);
3825 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3827 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3829 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3831 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3832 r
[0].f
[j
] = rgba
[0][j
];
3833 r
[1].f
[j
] = rgba
[1][j
];
3834 r
[2].f
[j
] = rgba
[2][j
];
3835 r
[3].f
[j
] = rgba
[3][j
];
3837 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3838 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3839 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3845 exec_load(struct tgsi_exec_machine
*mach
,
3846 const struct tgsi_full_instruction
*inst
)
3848 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
3849 exec_load_img(mach
, inst
);
3851 exec_load_buf(mach
, inst
);
3855 exec_store_img(struct tgsi_exec_machine
*mach
,
3856 const struct tgsi_full_instruction
*inst
)
3858 union tgsi_exec_channel r
[3], sample_r
;
3859 union tgsi_exec_channel value
[4];
3860 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3861 struct tgsi_image_params params
;
3866 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3867 unit
= inst
->Dst
[0].Register
.Index
;
3868 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3869 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3872 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3874 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3875 params
.format
= inst
->Memory
.Format
;
3877 for (i
= 0; i
< dim
; i
++) {
3878 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
3881 for (i
= 0; i
< 4; i
++) {
3882 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3885 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
3887 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3888 rgba
[0][j
] = value
[0].f
[j
];
3889 rgba
[1][j
] = value
[1].f
[j
];
3890 rgba
[2][j
] = value
[2].f
[j
];
3891 rgba
[3][j
] = value
[3].f
[j
];
3894 mach
->Image
->store(mach
->Image
, ¶ms
,
3895 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3900 exec_store_buf(struct tgsi_exec_machine
*mach
,
3901 const struct tgsi_full_instruction
*inst
)
3903 union tgsi_exec_channel r
[3];
3904 union tgsi_exec_channel value
[4];
3905 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3906 struct tgsi_buffer_params params
;
3909 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3911 unit
= inst
->Dst
[0].Register
.Index
;
3913 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3915 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
3917 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
3918 for (i
= 0; i
< 4; i
++) {
3919 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3922 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3923 rgba
[0][j
] = value
[0].f
[j
];
3924 rgba
[1][j
] = value
[1].f
[j
];
3925 rgba
[2][j
] = value
[2].f
[j
];
3926 rgba
[3][j
] = value
[3].f
[j
];
3929 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
3935 exec_store(struct tgsi_exec_machine
*mach
,
3936 const struct tgsi_full_instruction
*inst
)
3938 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
3939 exec_store_img(mach
, inst
);
3941 exec_store_buf(mach
, inst
);
3945 exec_atomop_img(struct tgsi_exec_machine
*mach
,
3946 const struct tgsi_full_instruction
*inst
)
3948 union tgsi_exec_channel r
[4], sample_r
;
3949 union tgsi_exec_channel value
[4], value2
[4];
3950 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3951 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3952 struct tgsi_image_params params
;
3957 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3958 unit
= fetch_sampler_unit(mach
, inst
, 0);
3959 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3960 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3963 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3965 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3966 params
.format
= inst
->Memory
.Format
;
3968 for (i
= 0; i
< dim
; i
++) {
3969 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3972 for (i
= 0; i
< 4; i
++) {
3973 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
3974 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
3975 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
3978 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3980 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3981 rgba
[0][j
] = value
[0].f
[j
];
3982 rgba
[1][j
] = value
[1].f
[j
];
3983 rgba
[2][j
] = value
[2].f
[j
];
3984 rgba
[3][j
] = value
[3].f
[j
];
3986 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
3987 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3988 rgba2
[0][j
] = value2
[0].f
[j
];
3989 rgba2
[1][j
] = value2
[1].f
[j
];
3990 rgba2
[2][j
] = value2
[2].f
[j
];
3991 rgba2
[3][j
] = value2
[3].f
[j
];
3995 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
3996 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3999 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4000 r
[0].f
[j
] = rgba
[0][j
];
4001 r
[1].f
[j
] = rgba
[1][j
];
4002 r
[2].f
[j
] = rgba
[2][j
];
4003 r
[3].f
[j
] = rgba
[3][j
];
4005 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4006 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4007 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4013 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4014 const struct tgsi_full_instruction
*inst
)
4016 union tgsi_exec_channel r
[4];
4017 union tgsi_exec_channel value
[4], value2
[4];
4018 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4019 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4020 struct tgsi_buffer_params params
;
4023 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4025 unit
= fetch_sampler_unit(mach
, inst
, 0);
4027 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4029 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4031 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4033 for (i
= 0; i
< 4; i
++) {
4034 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4035 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4036 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4039 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4040 rgba
[0][j
] = value
[0].f
[j
];
4041 rgba
[1][j
] = value
[1].f
[j
];
4042 rgba
[2][j
] = value
[2].f
[j
];
4043 rgba
[3][j
] = value
[3].f
[j
];
4045 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4046 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4047 rgba2
[0][j
] = value2
[0].f
[j
];
4048 rgba2
[1][j
] = value2
[1].f
[j
];
4049 rgba2
[2][j
] = value2
[2].f
[j
];
4050 rgba2
[3][j
] = value2
[3].f
[j
];
4054 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4058 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4059 r
[0].f
[j
] = rgba
[0][j
];
4060 r
[1].f
[j
] = rgba
[1][j
];
4061 r
[2].f
[j
] = rgba
[2][j
];
4062 r
[3].f
[j
] = rgba
[3][j
];
4064 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4065 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4066 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4072 exec_atomop(struct tgsi_exec_machine
*mach
,
4073 const struct tgsi_full_instruction
*inst
)
4075 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4076 exec_atomop_img(mach
, inst
);
4078 exec_atomop_buf(mach
, inst
);
4082 exec_resq_img(struct tgsi_exec_machine
*mach
,
4083 const struct tgsi_full_instruction
*inst
)
4086 union tgsi_exec_channel r
[4];
4089 struct tgsi_image_params params
;
4090 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4092 unit
= fetch_sampler_unit(mach
, inst
, 0);
4094 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4096 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4097 params
.format
= inst
->Memory
.Format
;
4099 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4101 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4102 for (j
= 0; j
< 4; j
++) {
4103 r
[j
].i
[i
] = result
[j
];
4107 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4108 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4109 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4110 TGSI_EXEC_DATA_INT
);
4116 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4117 const struct tgsi_full_instruction
*inst
)
4120 union tgsi_exec_channel r
[4];
4123 struct tgsi_buffer_params params
;
4124 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4126 unit
= fetch_sampler_unit(mach
, inst
, 0);
4128 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4131 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4133 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4137 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4138 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4139 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4140 TGSI_EXEC_DATA_INT
);
4146 exec_resq(struct tgsi_exec_machine
*mach
,
4147 const struct tgsi_full_instruction
*inst
)
4149 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4150 exec_resq_img(mach
, inst
);
4152 exec_resq_buf(mach
, inst
);
4156 micro_i2f(union tgsi_exec_channel
*dst
,
4157 const union tgsi_exec_channel
*src
)
4159 dst
->f
[0] = (float)src
->i
[0];
4160 dst
->f
[1] = (float)src
->i
[1];
4161 dst
->f
[2] = (float)src
->i
[2];
4162 dst
->f
[3] = (float)src
->i
[3];
4166 micro_not(union tgsi_exec_channel
*dst
,
4167 const union tgsi_exec_channel
*src
)
4169 dst
->u
[0] = ~src
->u
[0];
4170 dst
->u
[1] = ~src
->u
[1];
4171 dst
->u
[2] = ~src
->u
[2];
4172 dst
->u
[3] = ~src
->u
[3];
4176 micro_shl(union tgsi_exec_channel
*dst
,
4177 const union tgsi_exec_channel
*src0
,
4178 const union tgsi_exec_channel
*src1
)
4180 unsigned masked_count
;
4181 masked_count
= src1
->u
[0] & 0x1f;
4182 dst
->u
[0] = src0
->u
[0] << masked_count
;
4183 masked_count
= src1
->u
[1] & 0x1f;
4184 dst
->u
[1] = src0
->u
[1] << masked_count
;
4185 masked_count
= src1
->u
[2] & 0x1f;
4186 dst
->u
[2] = src0
->u
[2] << masked_count
;
4187 masked_count
= src1
->u
[3] & 0x1f;
4188 dst
->u
[3] = src0
->u
[3] << masked_count
;
4192 micro_and(union tgsi_exec_channel
*dst
,
4193 const union tgsi_exec_channel
*src0
,
4194 const union tgsi_exec_channel
*src1
)
4196 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4197 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4198 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4199 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4203 micro_or(union tgsi_exec_channel
*dst
,
4204 const union tgsi_exec_channel
*src0
,
4205 const union tgsi_exec_channel
*src1
)
4207 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4208 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4209 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4210 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4214 micro_xor(union tgsi_exec_channel
*dst
,
4215 const union tgsi_exec_channel
*src0
,
4216 const union tgsi_exec_channel
*src1
)
4218 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4219 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4220 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4221 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4225 micro_mod(union tgsi_exec_channel
*dst
,
4226 const union tgsi_exec_channel
*src0
,
4227 const union tgsi_exec_channel
*src1
)
4229 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
4230 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
4231 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
4232 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
4236 micro_f2i(union tgsi_exec_channel
*dst
,
4237 const union tgsi_exec_channel
*src
)
4239 dst
->i
[0] = (int)src
->f
[0];
4240 dst
->i
[1] = (int)src
->f
[1];
4241 dst
->i
[2] = (int)src
->f
[2];
4242 dst
->i
[3] = (int)src
->f
[3];
4246 micro_fseq(union tgsi_exec_channel
*dst
,
4247 const union tgsi_exec_channel
*src0
,
4248 const union tgsi_exec_channel
*src1
)
4250 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4251 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4252 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4253 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4257 micro_fsge(union tgsi_exec_channel
*dst
,
4258 const union tgsi_exec_channel
*src0
,
4259 const union tgsi_exec_channel
*src1
)
4261 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4262 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4263 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4264 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4268 micro_fslt(union tgsi_exec_channel
*dst
,
4269 const union tgsi_exec_channel
*src0
,
4270 const union tgsi_exec_channel
*src1
)
4272 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4273 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4274 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4275 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4279 micro_fsne(union tgsi_exec_channel
*dst
,
4280 const union tgsi_exec_channel
*src0
,
4281 const union tgsi_exec_channel
*src1
)
4283 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4284 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4285 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4286 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4290 micro_idiv(union tgsi_exec_channel
*dst
,
4291 const union tgsi_exec_channel
*src0
,
4292 const union tgsi_exec_channel
*src1
)
4294 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4295 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4296 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4297 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4301 micro_imax(union tgsi_exec_channel
*dst
,
4302 const union tgsi_exec_channel
*src0
,
4303 const union tgsi_exec_channel
*src1
)
4305 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4306 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4307 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4308 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4312 micro_imin(union tgsi_exec_channel
*dst
,
4313 const union tgsi_exec_channel
*src0
,
4314 const union tgsi_exec_channel
*src1
)
4316 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4317 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4318 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4319 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4323 micro_isge(union tgsi_exec_channel
*dst
,
4324 const union tgsi_exec_channel
*src0
,
4325 const union tgsi_exec_channel
*src1
)
4327 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4328 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4329 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4330 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4334 micro_ishr(union tgsi_exec_channel
*dst
,
4335 const union tgsi_exec_channel
*src0
,
4336 const union tgsi_exec_channel
*src1
)
4338 unsigned masked_count
;
4339 masked_count
= src1
->i
[0] & 0x1f;
4340 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4341 masked_count
= src1
->i
[1] & 0x1f;
4342 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4343 masked_count
= src1
->i
[2] & 0x1f;
4344 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4345 masked_count
= src1
->i
[3] & 0x1f;
4346 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4350 micro_islt(union tgsi_exec_channel
*dst
,
4351 const union tgsi_exec_channel
*src0
,
4352 const union tgsi_exec_channel
*src1
)
4354 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4355 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4356 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4357 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4361 micro_f2u(union tgsi_exec_channel
*dst
,
4362 const union tgsi_exec_channel
*src
)
4364 dst
->u
[0] = (uint
)src
->f
[0];
4365 dst
->u
[1] = (uint
)src
->f
[1];
4366 dst
->u
[2] = (uint
)src
->f
[2];
4367 dst
->u
[3] = (uint
)src
->f
[3];
4371 micro_u2f(union tgsi_exec_channel
*dst
,
4372 const union tgsi_exec_channel
*src
)
4374 dst
->f
[0] = (float)src
->u
[0];
4375 dst
->f
[1] = (float)src
->u
[1];
4376 dst
->f
[2] = (float)src
->u
[2];
4377 dst
->f
[3] = (float)src
->u
[3];
4381 micro_uadd(union tgsi_exec_channel
*dst
,
4382 const union tgsi_exec_channel
*src0
,
4383 const union tgsi_exec_channel
*src1
)
4385 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4386 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4387 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4388 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4392 micro_udiv(union tgsi_exec_channel
*dst
,
4393 const union tgsi_exec_channel
*src0
,
4394 const union tgsi_exec_channel
*src1
)
4396 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4397 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4398 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4399 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4403 micro_umad(union tgsi_exec_channel
*dst
,
4404 const union tgsi_exec_channel
*src0
,
4405 const union tgsi_exec_channel
*src1
,
4406 const union tgsi_exec_channel
*src2
)
4408 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4409 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4410 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4411 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4415 micro_umax(union tgsi_exec_channel
*dst
,
4416 const union tgsi_exec_channel
*src0
,
4417 const union tgsi_exec_channel
*src1
)
4419 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4420 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4421 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4422 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4426 micro_umin(union tgsi_exec_channel
*dst
,
4427 const union tgsi_exec_channel
*src0
,
4428 const union tgsi_exec_channel
*src1
)
4430 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4431 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4432 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4433 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4437 micro_umod(union tgsi_exec_channel
*dst
,
4438 const union tgsi_exec_channel
*src0
,
4439 const union tgsi_exec_channel
*src1
)
4441 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4442 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4443 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4444 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4448 micro_umul(union tgsi_exec_channel
*dst
,
4449 const union tgsi_exec_channel
*src0
,
4450 const union tgsi_exec_channel
*src1
)
4452 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4453 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4454 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4455 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4459 micro_imul_hi(union tgsi_exec_channel
*dst
,
4460 const union tgsi_exec_channel
*src0
,
4461 const union tgsi_exec_channel
*src1
)
4463 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4464 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4465 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4466 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4467 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4472 micro_umul_hi(union tgsi_exec_channel
*dst
,
4473 const union tgsi_exec_channel
*src0
,
4474 const union tgsi_exec_channel
*src1
)
4476 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4477 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4478 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4479 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4480 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4485 micro_useq(union tgsi_exec_channel
*dst
,
4486 const union tgsi_exec_channel
*src0
,
4487 const union tgsi_exec_channel
*src1
)
4489 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4490 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4491 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4492 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4496 micro_usge(union tgsi_exec_channel
*dst
,
4497 const union tgsi_exec_channel
*src0
,
4498 const union tgsi_exec_channel
*src1
)
4500 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4501 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4502 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4503 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4507 micro_ushr(union tgsi_exec_channel
*dst
,
4508 const union tgsi_exec_channel
*src0
,
4509 const union tgsi_exec_channel
*src1
)
4511 unsigned masked_count
;
4512 masked_count
= src1
->u
[0] & 0x1f;
4513 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4514 masked_count
= src1
->u
[1] & 0x1f;
4515 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4516 masked_count
= src1
->u
[2] & 0x1f;
4517 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4518 masked_count
= src1
->u
[3] & 0x1f;
4519 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4523 micro_uslt(union tgsi_exec_channel
*dst
,
4524 const union tgsi_exec_channel
*src0
,
4525 const union tgsi_exec_channel
*src1
)
4527 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4528 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4529 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4530 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4534 micro_usne(union tgsi_exec_channel
*dst
,
4535 const union tgsi_exec_channel
*src0
,
4536 const union tgsi_exec_channel
*src1
)
4538 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4539 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4540 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4541 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4545 micro_uarl(union tgsi_exec_channel
*dst
,
4546 const union tgsi_exec_channel
*src
)
4548 dst
->i
[0] = src
->u
[0];
4549 dst
->i
[1] = src
->u
[1];
4550 dst
->i
[2] = src
->u
[2];
4551 dst
->i
[3] = src
->u
[3];
4555 micro_ucmp(union tgsi_exec_channel
*dst
,
4556 const union tgsi_exec_channel
*src0
,
4557 const union tgsi_exec_channel
*src1
,
4558 const union tgsi_exec_channel
*src2
)
4560 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
4561 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
4562 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
4563 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
4567 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4570 micro_ibfe(union tgsi_exec_channel
*dst
,
4571 const union tgsi_exec_channel
*src0
,
4572 const union tgsi_exec_channel
*src1
,
4573 const union tgsi_exec_channel
*src2
)
4576 for (i
= 0; i
< 4; i
++) {
4577 int width
= src2
->i
[i
] & 0x1f;
4578 int offset
= src1
->i
[i
] & 0x1f;
4581 else if (width
+ offset
< 32)
4582 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
4584 dst
->i
[i
] = src0
->i
[i
] >> offset
;
4589 * Unsigned bitfield extract
4592 micro_ubfe(union tgsi_exec_channel
*dst
,
4593 const union tgsi_exec_channel
*src0
,
4594 const union tgsi_exec_channel
*src1
,
4595 const union tgsi_exec_channel
*src2
)
4598 for (i
= 0; i
< 4; i
++) {
4599 int width
= src2
->u
[i
] & 0x1f;
4600 int offset
= src1
->u
[i
] & 0x1f;
4603 else if (width
+ offset
< 32)
4604 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
4606 dst
->u
[i
] = src0
->u
[i
] >> offset
;
4611 * Bitfield insert: copy low bits from src1 into a region of src0.
4614 micro_bfi(union tgsi_exec_channel
*dst
,
4615 const union tgsi_exec_channel
*src0
,
4616 const union tgsi_exec_channel
*src1
,
4617 const union tgsi_exec_channel
*src2
,
4618 const union tgsi_exec_channel
*src3
)
4621 for (i
= 0; i
< 4; i
++) {
4622 int width
= src3
->u
[i
] & 0x1f;
4623 int offset
= src2
->u
[i
] & 0x1f;
4624 int bitmask
= ((1 << width
) - 1) << offset
;
4625 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
4630 micro_brev(union tgsi_exec_channel
*dst
,
4631 const union tgsi_exec_channel
*src
)
4633 dst
->u
[0] = util_bitreverse(src
->u
[0]);
4634 dst
->u
[1] = util_bitreverse(src
->u
[1]);
4635 dst
->u
[2] = util_bitreverse(src
->u
[2]);
4636 dst
->u
[3] = util_bitreverse(src
->u
[3]);
4640 micro_popc(union tgsi_exec_channel
*dst
,
4641 const union tgsi_exec_channel
*src
)
4643 dst
->u
[0] = util_bitcount(src
->u
[0]);
4644 dst
->u
[1] = util_bitcount(src
->u
[1]);
4645 dst
->u
[2] = util_bitcount(src
->u
[2]);
4646 dst
->u
[3] = util_bitcount(src
->u
[3]);
4650 micro_lsb(union tgsi_exec_channel
*dst
,
4651 const union tgsi_exec_channel
*src
)
4653 dst
->i
[0] = ffs(src
->u
[0]) - 1;
4654 dst
->i
[1] = ffs(src
->u
[1]) - 1;
4655 dst
->i
[2] = ffs(src
->u
[2]) - 1;
4656 dst
->i
[3] = ffs(src
->u
[3]) - 1;
4660 micro_imsb(union tgsi_exec_channel
*dst
,
4661 const union tgsi_exec_channel
*src
)
4663 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
4664 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
4665 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
4666 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
4670 micro_umsb(union tgsi_exec_channel
*dst
,
4671 const union tgsi_exec_channel
*src
)
4673 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
4674 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
4675 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
4676 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
4681 struct tgsi_exec_machine
*mach
,
4682 const struct tgsi_full_instruction
*inst
,
4685 union tgsi_exec_channel r
[10];
4689 switch (inst
->Instruction
.Opcode
) {
4690 case TGSI_OPCODE_ARL
:
4691 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4694 case TGSI_OPCODE_MOV
:
4695 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4698 case TGSI_OPCODE_LIT
:
4699 exec_lit(mach
, inst
);
4702 case TGSI_OPCODE_RCP
:
4703 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4706 case TGSI_OPCODE_RSQ
:
4707 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4710 case TGSI_OPCODE_EXP
:
4711 exec_exp(mach
, inst
);
4714 case TGSI_OPCODE_LOG
:
4715 exec_log(mach
, inst
);
4718 case TGSI_OPCODE_MUL
:
4719 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4722 case TGSI_OPCODE_ADD
:
4723 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4726 case TGSI_OPCODE_DP3
:
4727 exec_dp3(mach
, inst
);
4730 case TGSI_OPCODE_DP4
:
4731 exec_dp4(mach
, inst
);
4734 case TGSI_OPCODE_DST
:
4735 exec_dst(mach
, inst
);
4738 case TGSI_OPCODE_MIN
:
4739 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4742 case TGSI_OPCODE_MAX
:
4743 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4746 case TGSI_OPCODE_SLT
:
4747 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4750 case TGSI_OPCODE_SGE
:
4751 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4754 case TGSI_OPCODE_MAD
:
4755 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4758 case TGSI_OPCODE_SUB
:
4759 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4762 case TGSI_OPCODE_LRP
:
4763 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4766 case TGSI_OPCODE_SQRT
:
4767 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4770 case TGSI_OPCODE_DP2A
:
4771 exec_dp2a(mach
, inst
);
4774 case TGSI_OPCODE_FRC
:
4775 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4778 case TGSI_OPCODE_CLAMP
:
4779 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4782 case TGSI_OPCODE_FLR
:
4783 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4786 case TGSI_OPCODE_ROUND
:
4787 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4790 case TGSI_OPCODE_EX2
:
4791 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4794 case TGSI_OPCODE_LG2
:
4795 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4798 case TGSI_OPCODE_POW
:
4799 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4802 case TGSI_OPCODE_XPD
:
4803 exec_xpd(mach
, inst
);
4806 case TGSI_OPCODE_ABS
:
4807 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4810 case TGSI_OPCODE_DPH
:
4811 exec_dph(mach
, inst
);
4814 case TGSI_OPCODE_COS
:
4815 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4818 case TGSI_OPCODE_DDX
:
4819 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4822 case TGSI_OPCODE_DDY
:
4823 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4826 case TGSI_OPCODE_KILL
:
4827 exec_kill (mach
, inst
);
4830 case TGSI_OPCODE_KILL_IF
:
4831 exec_kill_if (mach
, inst
);
4834 case TGSI_OPCODE_PK2H
:
4835 exec_pk2h(mach
, inst
);
4838 case TGSI_OPCODE_PK2US
:
4842 case TGSI_OPCODE_PK4B
:
4846 case TGSI_OPCODE_PK4UB
:
4850 case TGSI_OPCODE_SEQ
:
4851 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4854 case TGSI_OPCODE_SGT
:
4855 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4858 case TGSI_OPCODE_SIN
:
4859 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4862 case TGSI_OPCODE_SLE
:
4863 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4866 case TGSI_OPCODE_SNE
:
4867 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4870 case TGSI_OPCODE_TEX
:
4871 /* simple texture lookup */
4872 /* src[0] = texcoord */
4873 /* src[1] = sampler unit */
4874 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
4877 case TGSI_OPCODE_TXB
:
4878 /* Texture lookup with lod bias */
4879 /* src[0] = texcoord (src[0].w = LOD bias) */
4880 /* src[1] = sampler unit */
4881 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
4884 case TGSI_OPCODE_TXD
:
4885 /* Texture lookup with explict partial derivatives */
4886 /* src[0] = texcoord */
4887 /* src[1] = d[strq]/dx */
4888 /* src[2] = d[strq]/dy */
4889 /* src[3] = sampler unit */
4890 exec_txd(mach
, inst
);
4893 case TGSI_OPCODE_TXL
:
4894 /* Texture lookup with explit LOD */
4895 /* src[0] = texcoord (src[0].w = LOD) */
4896 /* src[1] = sampler unit */
4897 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
4900 case TGSI_OPCODE_TXP
:
4901 /* Texture lookup with projection */
4902 /* src[0] = texcoord (src[0].w = projection) */
4903 /* src[1] = sampler unit */
4904 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
4907 case TGSI_OPCODE_TG4
:
4908 /* src[0] = texcoord */
4909 /* src[1] = component */
4910 /* src[2] = sampler unit */
4911 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
4914 case TGSI_OPCODE_LODQ
:
4915 /* src[0] = texcoord */
4916 /* src[1] = sampler unit */
4917 exec_lodq(mach
, inst
);
4920 case TGSI_OPCODE_UP2H
:
4921 exec_up2h(mach
, inst
);
4924 case TGSI_OPCODE_UP2US
:
4928 case TGSI_OPCODE_UP4B
:
4932 case TGSI_OPCODE_UP4UB
:
4936 case TGSI_OPCODE_ARR
:
4937 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4940 case TGSI_OPCODE_CAL
:
4941 /* skip the call if no execution channels are enabled */
4942 if (mach
->ExecMask
) {
4945 /* First, record the depths of the execution stacks.
4946 * This is important for deeply nested/looped return statements.
4947 * We have to unwind the stacks by the correct amount. For a
4948 * real code generator, we could determine the number of entries
4949 * to pop off each stack with simple static analysis and avoid
4950 * implementing this data structure at run time.
4952 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
4953 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
4954 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
4955 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
4956 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
4957 /* note that PC was already incremented above */
4958 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
4960 mach
->CallStackTop
++;
4962 /* Second, push the Cond, Loop, Cont, Func stacks */
4963 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4964 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4965 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4966 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
4967 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4968 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
4970 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4971 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4972 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4973 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
4974 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4975 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
4977 /* Finally, jump to the subroutine. The label is a pointer
4978 * (an instruction number) to the BGNSUB instruction.
4980 *pc
= inst
->Label
.Label
;
4981 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
4982 == TGSI_OPCODE_BGNSUB
);
4986 case TGSI_OPCODE_RET
:
4987 mach
->FuncMask
&= ~mach
->ExecMask
;
4988 UPDATE_EXEC_MASK(mach
);
4990 if (mach
->FuncMask
== 0x0) {
4991 /* really return now (otherwise, keep executing */
4993 if (mach
->CallStackTop
== 0) {
4994 /* returning from main() */
4995 mach
->CondStackTop
= 0;
4996 mach
->LoopStackTop
= 0;
5001 assert(mach
->CallStackTop
> 0);
5002 mach
->CallStackTop
--;
5004 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5005 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5007 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5008 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5010 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5011 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5013 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5014 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5016 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5017 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5019 assert(mach
->FuncStackTop
> 0);
5020 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5022 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5024 UPDATE_EXEC_MASK(mach
);
5028 case TGSI_OPCODE_SSG
:
5029 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5032 case TGSI_OPCODE_CMP
:
5033 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5036 case TGSI_OPCODE_SCS
:
5037 exec_scs(mach
, inst
);
5040 case TGSI_OPCODE_DIV
:
5041 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5044 case TGSI_OPCODE_DP2
:
5045 exec_dp2(mach
, inst
);
5048 case TGSI_OPCODE_IF
:
5050 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5051 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5052 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5053 /* update CondMask */
5055 mach
->CondMask
&= ~0x1;
5058 mach
->CondMask
&= ~0x2;
5061 mach
->CondMask
&= ~0x4;
5064 mach
->CondMask
&= ~0x8;
5066 UPDATE_EXEC_MASK(mach
);
5067 /* Todo: If CondMask==0, jump to ELSE */
5070 case TGSI_OPCODE_UIF
:
5072 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5073 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5074 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5075 /* update CondMask */
5077 mach
->CondMask
&= ~0x1;
5080 mach
->CondMask
&= ~0x2;
5083 mach
->CondMask
&= ~0x4;
5086 mach
->CondMask
&= ~0x8;
5088 UPDATE_EXEC_MASK(mach
);
5089 /* Todo: If CondMask==0, jump to ELSE */
5092 case TGSI_OPCODE_ELSE
:
5093 /* invert CondMask wrt previous mask */
5096 assert(mach
->CondStackTop
> 0);
5097 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5098 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5099 UPDATE_EXEC_MASK(mach
);
5100 /* Todo: If CondMask==0, jump to ENDIF */
5104 case TGSI_OPCODE_ENDIF
:
5106 assert(mach
->CondStackTop
> 0);
5107 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5108 UPDATE_EXEC_MASK(mach
);
5111 case TGSI_OPCODE_END
:
5112 /* make sure we end primitives which haven't
5113 * been explicitly emitted */
5114 conditional_emit_primitive(mach
);
5115 /* halt execution */
5119 case TGSI_OPCODE_PUSHA
:
5123 case TGSI_OPCODE_POPA
:
5127 case TGSI_OPCODE_CEIL
:
5128 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5131 case TGSI_OPCODE_I2F
:
5132 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5135 case TGSI_OPCODE_NOT
:
5136 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5139 case TGSI_OPCODE_TRUNC
:
5140 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5143 case TGSI_OPCODE_SHL
:
5144 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5147 case TGSI_OPCODE_AND
:
5148 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5151 case TGSI_OPCODE_OR
:
5152 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5155 case TGSI_OPCODE_MOD
:
5156 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5159 case TGSI_OPCODE_XOR
:
5160 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5163 case TGSI_OPCODE_SAD
:
5167 case TGSI_OPCODE_TXF
:
5168 exec_txf(mach
, inst
);
5171 case TGSI_OPCODE_TXQ
:
5172 exec_txq(mach
, inst
);
5175 case TGSI_OPCODE_EMIT
:
5179 case TGSI_OPCODE_ENDPRIM
:
5180 emit_primitive(mach
);
5183 case TGSI_OPCODE_BGNLOOP
:
5184 /* push LoopMask and ContMasks */
5185 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5186 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5187 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5188 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5190 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5191 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5192 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5193 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5194 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5197 case TGSI_OPCODE_ENDLOOP
:
5198 /* Restore ContMask, but don't pop */
5199 assert(mach
->ContStackTop
> 0);
5200 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5201 UPDATE_EXEC_MASK(mach
);
5202 if (mach
->ExecMask
) {
5203 /* repeat loop: jump to instruction just past BGNLOOP */
5204 assert(mach
->LoopLabelStackTop
> 0);
5205 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5208 /* exit loop: pop LoopMask */
5209 assert(mach
->LoopStackTop
> 0);
5210 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5212 assert(mach
->ContStackTop
> 0);
5213 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5214 assert(mach
->LoopLabelStackTop
> 0);
5215 --mach
->LoopLabelStackTop
;
5217 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5219 UPDATE_EXEC_MASK(mach
);
5222 case TGSI_OPCODE_BRK
:
5226 case TGSI_OPCODE_CONT
:
5227 /* turn off cont channels for each enabled exec channel */
5228 mach
->ContMask
&= ~mach
->ExecMask
;
5229 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5230 UPDATE_EXEC_MASK(mach
);
5233 case TGSI_OPCODE_BGNSUB
:
5237 case TGSI_OPCODE_ENDSUB
:
5239 * XXX: This really should be a no-op. We should never reach this opcode.
5242 assert(mach
->CallStackTop
> 0);
5243 mach
->CallStackTop
--;
5245 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5246 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5248 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5249 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5251 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5252 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5254 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5255 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5257 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5258 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5260 assert(mach
->FuncStackTop
> 0);
5261 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5263 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5265 UPDATE_EXEC_MASK(mach
);
5268 case TGSI_OPCODE_NOP
:
5271 case TGSI_OPCODE_BREAKC
:
5272 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
5273 /* update CondMask */
5274 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
5275 mach
->LoopMask
&= ~0x1;
5277 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
5278 mach
->LoopMask
&= ~0x2;
5280 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
5281 mach
->LoopMask
&= ~0x4;
5283 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
5284 mach
->LoopMask
&= ~0x8;
5286 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5287 UPDATE_EXEC_MASK(mach
);
5290 case TGSI_OPCODE_F2I
:
5291 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5294 case TGSI_OPCODE_FSEQ
:
5295 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5298 case TGSI_OPCODE_FSGE
:
5299 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5302 case TGSI_OPCODE_FSLT
:
5303 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5306 case TGSI_OPCODE_FSNE
:
5307 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5310 case TGSI_OPCODE_IDIV
:
5311 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5314 case TGSI_OPCODE_IMAX
:
5315 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5318 case TGSI_OPCODE_IMIN
:
5319 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5322 case TGSI_OPCODE_INEG
:
5323 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5326 case TGSI_OPCODE_ISGE
:
5327 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5330 case TGSI_OPCODE_ISHR
:
5331 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5334 case TGSI_OPCODE_ISLT
:
5335 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5338 case TGSI_OPCODE_F2U
:
5339 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5342 case TGSI_OPCODE_U2F
:
5343 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5346 case TGSI_OPCODE_UADD
:
5347 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5350 case TGSI_OPCODE_UDIV
:
5351 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5354 case TGSI_OPCODE_UMAD
:
5355 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5358 case TGSI_OPCODE_UMAX
:
5359 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5362 case TGSI_OPCODE_UMIN
:
5363 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5366 case TGSI_OPCODE_UMOD
:
5367 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5370 case TGSI_OPCODE_UMUL
:
5371 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5374 case TGSI_OPCODE_IMUL_HI
:
5375 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5378 case TGSI_OPCODE_UMUL_HI
:
5379 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5382 case TGSI_OPCODE_USEQ
:
5383 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5386 case TGSI_OPCODE_USGE
:
5387 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5390 case TGSI_OPCODE_USHR
:
5391 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5394 case TGSI_OPCODE_USLT
:
5395 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5398 case TGSI_OPCODE_USNE
:
5399 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5402 case TGSI_OPCODE_SWITCH
:
5403 exec_switch(mach
, inst
);
5406 case TGSI_OPCODE_CASE
:
5407 exec_case(mach
, inst
);
5410 case TGSI_OPCODE_DEFAULT
:
5414 case TGSI_OPCODE_ENDSWITCH
:
5415 exec_endswitch(mach
);
5418 case TGSI_OPCODE_SAMPLE_I
:
5419 exec_txf(mach
, inst
);
5422 case TGSI_OPCODE_SAMPLE_I_MS
:
5423 exec_txf(mach
, inst
);
5426 case TGSI_OPCODE_SAMPLE
:
5427 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5430 case TGSI_OPCODE_SAMPLE_B
:
5431 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5434 case TGSI_OPCODE_SAMPLE_C
:
5435 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5438 case TGSI_OPCODE_SAMPLE_C_LZ
:
5439 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5442 case TGSI_OPCODE_SAMPLE_D
:
5443 exec_sample_d(mach
, inst
);
5446 case TGSI_OPCODE_SAMPLE_L
:
5447 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5450 case TGSI_OPCODE_GATHER4
:
5454 case TGSI_OPCODE_SVIEWINFO
:
5455 exec_txq(mach
, inst
);
5458 case TGSI_OPCODE_SAMPLE_POS
:
5462 case TGSI_OPCODE_SAMPLE_INFO
:
5466 case TGSI_OPCODE_UARL
:
5467 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5470 case TGSI_OPCODE_UCMP
:
5471 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5474 case TGSI_OPCODE_IABS
:
5475 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5478 case TGSI_OPCODE_ISSG
:
5479 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5482 case TGSI_OPCODE_TEX2
:
5483 /* simple texture lookup */
5484 /* src[0] = texcoord */
5485 /* src[1] = compare */
5486 /* src[2] = sampler unit */
5487 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5489 case TGSI_OPCODE_TXB2
:
5490 /* simple texture lookup */
5491 /* src[0] = texcoord */
5493 /* src[2] = sampler unit */
5494 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5496 case TGSI_OPCODE_TXL2
:
5497 /* simple texture lookup */
5498 /* src[0] = texcoord */
5500 /* src[2] = sampler unit */
5501 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5504 case TGSI_OPCODE_IBFE
:
5505 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5507 case TGSI_OPCODE_UBFE
:
5508 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5510 case TGSI_OPCODE_BFI
:
5511 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5513 case TGSI_OPCODE_BREV
:
5514 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5516 case TGSI_OPCODE_POPC
:
5517 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5519 case TGSI_OPCODE_LSB
:
5520 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5522 case TGSI_OPCODE_IMSB
:
5523 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5525 case TGSI_OPCODE_UMSB
:
5526 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5529 case TGSI_OPCODE_F2D
:
5530 exec_f2d(mach
, inst
);
5533 case TGSI_OPCODE_D2F
:
5534 exec_d2f(mach
, inst
);
5537 case TGSI_OPCODE_DABS
:
5538 exec_double_unary(mach
, inst
, micro_dabs
);
5541 case TGSI_OPCODE_DNEG
:
5542 exec_double_unary(mach
, inst
, micro_dneg
);
5545 case TGSI_OPCODE_DADD
:
5546 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5549 case TGSI_OPCODE_DMUL
:
5550 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
5553 case TGSI_OPCODE_DMAX
:
5554 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
5557 case TGSI_OPCODE_DMIN
:
5558 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
5561 case TGSI_OPCODE_DSLT
:
5562 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
5565 case TGSI_OPCODE_DSGE
:
5566 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
5569 case TGSI_OPCODE_DSEQ
:
5570 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
5573 case TGSI_OPCODE_DSNE
:
5574 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
5577 case TGSI_OPCODE_DRCP
:
5578 exec_double_unary(mach
, inst
, micro_drcp
);
5581 case TGSI_OPCODE_DSQRT
:
5582 exec_double_unary(mach
, inst
, micro_dsqrt
);
5585 case TGSI_OPCODE_DRSQ
:
5586 exec_double_unary(mach
, inst
, micro_drsq
);
5589 case TGSI_OPCODE_DMAD
:
5590 exec_double_trinary(mach
, inst
, micro_dmad
);
5593 case TGSI_OPCODE_DFRAC
:
5594 exec_double_unary(mach
, inst
, micro_dfrac
);
5597 case TGSI_OPCODE_DLDEXP
:
5598 exec_dldexp(mach
, inst
);
5601 case TGSI_OPCODE_DFRACEXP
:
5602 exec_dfracexp(mach
, inst
);
5605 case TGSI_OPCODE_I2D
:
5606 exec_i2d(mach
, inst
);
5609 case TGSI_OPCODE_D2I
:
5610 exec_d2i(mach
, inst
);
5613 case TGSI_OPCODE_U2D
:
5614 exec_u2d(mach
, inst
);
5617 case TGSI_OPCODE_D2U
:
5618 exec_d2u(mach
, inst
);
5621 case TGSI_OPCODE_LOAD
:
5622 exec_load(mach
, inst
);
5625 case TGSI_OPCODE_STORE
:
5626 exec_store(mach
, inst
);
5629 case TGSI_OPCODE_ATOMUADD
:
5630 case TGSI_OPCODE_ATOMXCHG
:
5631 case TGSI_OPCODE_ATOMCAS
:
5632 case TGSI_OPCODE_ATOMAND
:
5633 case TGSI_OPCODE_ATOMOR
:
5634 case TGSI_OPCODE_ATOMXOR
:
5635 case TGSI_OPCODE_ATOMUMIN
:
5636 case TGSI_OPCODE_ATOMUMAX
:
5637 case TGSI_OPCODE_ATOMIMIN
:
5638 case TGSI_OPCODE_ATOMIMAX
:
5639 exec_atomop(mach
, inst
);
5642 case TGSI_OPCODE_RESQ
:
5643 exec_resq(mach
, inst
);
5645 case TGSI_OPCODE_BARRIER
:
5646 case TGSI_OPCODE_MEMBAR
:
5654 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
5656 uint default_mask
= 0xf;
5658 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
5659 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
5661 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
5662 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
5663 mach
->Primitives
[0] = 0;
5664 /* GS runs on a single primitive for now */
5668 if (mach
->NonHelperMask
== 0)
5669 mach
->NonHelperMask
= default_mask
;
5670 mach
->CondMask
= default_mask
;
5671 mach
->LoopMask
= default_mask
;
5672 mach
->ContMask
= default_mask
;
5673 mach
->FuncMask
= default_mask
;
5674 mach
->ExecMask
= default_mask
;
5676 mach
->Switch
.mask
= default_mask
;
5678 assert(mach
->CondStackTop
== 0);
5679 assert(mach
->LoopStackTop
== 0);
5680 assert(mach
->ContStackTop
== 0);
5681 assert(mach
->SwitchStackTop
== 0);
5682 assert(mach
->BreakStackTop
== 0);
5683 assert(mach
->CallStackTop
== 0);
5687 * Run TGSI interpreter.
5688 * \return bitmask of "alive" quad components
5691 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
5696 tgsi_exec_machine_setup_masks(mach
);
5698 /* execute declarations (interpolants) */
5699 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
5700 exec_declaration( mach
, mach
->Declarations
+i
);
5705 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
5706 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
5709 memset(mach
->Temps
, 0, sizeof(temps
));
5710 memset(mach
->Outputs
, 0, sizeof(outputs
));
5711 memset(temps
, 0, sizeof(temps
));
5712 memset(outputs
, 0, sizeof(outputs
));
5715 /* execute instructions, until pc is set to -1 */
5721 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
5724 assert(pc
< (int) mach
->NumInstructions
);
5725 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
5728 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
5729 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
5732 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
5733 debug_printf("TEMP[%2u] = ", i
);
5734 for (j
= 0; j
< 4; j
++) {
5738 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5739 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
5740 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
5741 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
5742 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
5746 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
5747 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
5750 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
5751 debug_printf("OUT[%2u] = ", i
);
5752 for (j
= 0; j
< 4; j
++) {
5756 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5757 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
5758 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
5759 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
5760 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
5769 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5770 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
5772 * Scale back depth component.
5774 for (i
= 0; i
< 4; i
++)
5775 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
5779 /* Strictly speaking, these assertions aren't really needed but they
5780 * can potentially catch some bugs in the control flow code.
5782 assert(mach
->CondStackTop
== 0);
5783 assert(mach
->LoopStackTop
== 0);
5784 assert(mach
->ContStackTop
== 0);
5785 assert(mach
->SwitchStackTop
== 0);
5786 assert(mach
->BreakStackTop
== 0);
5787 assert(mach
->CallStackTop
== 0);
5789 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];