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Merge branch 'master' into pipe-video
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
381 {
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
386 }
387
388 static void
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
391 {
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
396 }
397
398 static void
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
402 {
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
407 }
408
409 static void
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_trunc(union tgsi_exec_channel *dst,
433 const union tgsi_exec_channel *src)
434 {
435 dst->f[0] = (float)(int)src->f[0];
436 dst->f[1] = (float)(int)src->f[1];
437 dst->f[2] = (float)(int)src->f[2];
438 dst->f[3] = (float)(int)src->f[3];
439 }
440
441
442 #define CHAN_X 0
443 #define CHAN_Y 1
444 #define CHAN_Z 2
445 #define CHAN_W 3
446
447 enum tgsi_exec_datatype {
448 TGSI_EXEC_DATA_FLOAT,
449 TGSI_EXEC_DATA_INT,
450 TGSI_EXEC_DATA_UINT
451 };
452
453 /*
454 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
455 */
456 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
457 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
458 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
459 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
460 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
461 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
462 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
463 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
464 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
465 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
466 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
467 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
468 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
469 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
470 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
471 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
472 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
473 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
474 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
475 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
476 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
477 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
478 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
479 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
480 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
481 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
482 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
483 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
484 #define TEMP_R0 TGSI_EXEC_TEMP_R0
485 #define TEMP_P0 TGSI_EXEC_TEMP_P0
486
487 #define IS_CHANNEL_ENABLED(INST, CHAN)\
488 ((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
489
490 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
491 ((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
492
493 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
494 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
495 if (IS_CHANNEL_ENABLED( INST, CHAN ))
496
497 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
498 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
499 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
500
501
502 /** The execution mask depends on the conditional mask and the loop mask */
503 #define UPDATE_EXEC_MASK(MACH) \
504 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
505
506
507 static const union tgsi_exec_channel ZeroVec =
508 { { 0.0, 0.0, 0.0, 0.0 } };
509
510 static const union tgsi_exec_channel OneVec = {
511 {1.0f, 1.0f, 1.0f, 1.0f}
512 };
513
514
515 /**
516 * Assert that none of the float values in 'chan' are infinite or NaN.
517 * NaN and Inf may occur normally during program execution and should
518 * not lead to crashes, etc. But when debugging, it's helpful to catch
519 * them.
520 */
521 static INLINE void
522 check_inf_or_nan(const union tgsi_exec_channel *chan)
523 {
524 assert(!util_is_inf_or_nan((chan)->f[0]));
525 assert(!util_is_inf_or_nan((chan)->f[1]));
526 assert(!util_is_inf_or_nan((chan)->f[2]));
527 assert(!util_is_inf_or_nan((chan)->f[3]));
528 }
529
530
531 #ifdef DEBUG
532 static void
533 print_chan(const char *msg, const union tgsi_exec_channel *chan)
534 {
535 debug_printf("%s = {%f, %f, %f, %f}\n",
536 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
537 }
538 #endif
539
540
541 #ifdef DEBUG
542 static void
543 print_temp(const struct tgsi_exec_machine *mach, uint index)
544 {
545 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
546 int i;
547 debug_printf("Temp[%u] =\n", index);
548 for (i = 0; i < 4; i++) {
549 debug_printf(" %c: { %f, %f, %f, %f }\n",
550 "XYZW"[i],
551 tmp->xyzw[i].f[0],
552 tmp->xyzw[i].f[1],
553 tmp->xyzw[i].f[2],
554 tmp->xyzw[i].f[3]);
555 }
556 }
557 #endif
558
559
560 void
561 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
562 unsigned num_bufs,
563 const void **bufs,
564 const unsigned *buf_sizes)
565 {
566 unsigned i;
567
568 for (i = 0; i < num_bufs; i++) {
569 mach->Consts[i] = bufs[i];
570 mach->ConstsSize[i] = buf_sizes[i];
571 }
572 }
573
574
575
576
577 /**
578 * Check if there's a potential src/dst register data dependency when
579 * using SOA execution.
580 * Example:
581 * MOV T, T.yxwz;
582 * This would expand into:
583 * MOV t0, t1;
584 * MOV t1, t0;
585 * MOV t2, t3;
586 * MOV t3, t2;
587 * The second instruction will have the wrong value for t0 if executed as-is.
588 */
589 boolean
590 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
591 {
592 uint i, chan;
593
594 uint writemask = inst->Dst[0].Register.WriteMask;
595 if (writemask == TGSI_WRITEMASK_X ||
596 writemask == TGSI_WRITEMASK_Y ||
597 writemask == TGSI_WRITEMASK_Z ||
598 writemask == TGSI_WRITEMASK_W ||
599 writemask == TGSI_WRITEMASK_NONE) {
600 /* no chance of data dependency */
601 return FALSE;
602 }
603
604 /* loop over src regs */
605 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
606 if ((inst->Src[i].Register.File ==
607 inst->Dst[0].Register.File) &&
608 ((inst->Src[i].Register.Index ==
609 inst->Dst[0].Register.Index) ||
610 inst->Src[i].Register.Indirect ||
611 inst->Dst[0].Register.Indirect)) {
612 /* loop over dest channels */
613 uint channelsWritten = 0x0;
614 FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
615 /* check if we're reading a channel that's been written */
616 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
617 if (channelsWritten & (1 << swizzle)) {
618 return TRUE;
619 }
620
621 channelsWritten |= (1 << chan);
622 }
623 }
624 }
625 return FALSE;
626 }
627
628
629 /**
630 * Initialize machine state by expanding tokens to full instructions,
631 * allocating temporary storage, setting up constants, etc.
632 * After this, we can call tgsi_exec_machine_run() many times.
633 */
634 void
635 tgsi_exec_machine_bind_shader(
636 struct tgsi_exec_machine *mach,
637 const struct tgsi_token *tokens,
638 uint numSamplers,
639 struct tgsi_sampler **samplers)
640 {
641 uint k;
642 struct tgsi_parse_context parse;
643 struct tgsi_full_instruction *instructions;
644 struct tgsi_full_declaration *declarations;
645 uint maxInstructions = 10, numInstructions = 0;
646 uint maxDeclarations = 10, numDeclarations = 0;
647
648 #if 0
649 tgsi_dump(tokens, 0);
650 #endif
651
652 util_init_math();
653
654 if (numSamplers) {
655 assert(samplers);
656 }
657
658 mach->Tokens = tokens;
659 mach->Samplers = samplers;
660
661 if (!tokens) {
662 /* unbind and free all */
663 if (mach->Declarations) {
664 FREE( mach->Declarations );
665 }
666 mach->Declarations = NULL;
667 mach->NumDeclarations = 0;
668
669 if (mach->Instructions) {
670 FREE( mach->Instructions );
671 }
672 mach->Instructions = NULL;
673 mach->NumInstructions = 0;
674
675 return;
676 }
677
678 k = tgsi_parse_init (&parse, mach->Tokens);
679 if (k != TGSI_PARSE_OK) {
680 debug_printf( "Problem parsing!\n" );
681 return;
682 }
683
684 mach->Processor = parse.FullHeader.Processor.Processor;
685 mach->ImmLimit = 0;
686
687 declarations = (struct tgsi_full_declaration *)
688 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
689
690 if (!declarations) {
691 return;
692 }
693
694 instructions = (struct tgsi_full_instruction *)
695 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
696
697 if (!instructions) {
698 FREE( declarations );
699 return;
700 }
701
702 while( !tgsi_parse_end_of_tokens( &parse ) ) {
703 uint i;
704
705 tgsi_parse_token( &parse );
706 switch( parse.FullToken.Token.Type ) {
707 case TGSI_TOKEN_TYPE_DECLARATION:
708 /* save expanded declaration */
709 if (numDeclarations == maxDeclarations) {
710 declarations = REALLOC(declarations,
711 maxDeclarations
712 * sizeof(struct tgsi_full_declaration),
713 (maxDeclarations + 10)
714 * sizeof(struct tgsi_full_declaration));
715 maxDeclarations += 10;
716 }
717 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
718 unsigned reg;
719 for (reg = parse.FullToken.FullDeclaration.Range.First;
720 reg <= parse.FullToken.FullDeclaration.Range.Last;
721 ++reg) {
722 ++mach->NumOutputs;
723 }
724 }
725 if (parse.FullToken.FullDeclaration.Declaration.File ==
726 TGSI_FILE_IMMEDIATE_ARRAY) {
727 unsigned reg;
728 struct tgsi_full_declaration *decl =
729 &parse.FullToken.FullDeclaration;
730 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
731 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
732 for( i = 0; i < 4; i++ ) {
733 int idx = reg * 4 + i;
734 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
735 }
736 }
737 }
738 memcpy(declarations + numDeclarations,
739 &parse.FullToken.FullDeclaration,
740 sizeof(declarations[0]));
741 numDeclarations++;
742 break;
743
744 case TGSI_TOKEN_TYPE_IMMEDIATE:
745 {
746 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
747 assert( size <= 4 );
748 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
749
750 for( i = 0; i < size; i++ ) {
751 mach->Imms[mach->ImmLimit][i] =
752 parse.FullToken.FullImmediate.u[i].Float;
753 }
754 mach->ImmLimit += 1;
755 }
756 break;
757
758 case TGSI_TOKEN_TYPE_INSTRUCTION:
759
760 /* save expanded instruction */
761 if (numInstructions == maxInstructions) {
762 instructions = REALLOC(instructions,
763 maxInstructions
764 * sizeof(struct tgsi_full_instruction),
765 (maxInstructions + 10)
766 * sizeof(struct tgsi_full_instruction));
767 maxInstructions += 10;
768 }
769
770 memcpy(instructions + numInstructions,
771 &parse.FullToken.FullInstruction,
772 sizeof(instructions[0]));
773
774 numInstructions++;
775 break;
776
777 case TGSI_TOKEN_TYPE_PROPERTY:
778 break;
779
780 default:
781 assert( 0 );
782 }
783 }
784 tgsi_parse_free (&parse);
785
786 if (mach->Declarations) {
787 FREE( mach->Declarations );
788 }
789 mach->Declarations = declarations;
790 mach->NumDeclarations = numDeclarations;
791
792 if (mach->Instructions) {
793 FREE( mach->Instructions );
794 }
795 mach->Instructions = instructions;
796 mach->NumInstructions = numInstructions;
797 }
798
799
800 struct tgsi_exec_machine *
801 tgsi_exec_machine_create( void )
802 {
803 struct tgsi_exec_machine *mach;
804 uint i;
805
806 mach = align_malloc( sizeof *mach, 16 );
807 if (!mach)
808 goto fail;
809
810 memset(mach, 0, sizeof(*mach));
811
812 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
813 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
814 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
815
816 /* Setup constants. */
817 for( i = 0; i < 4; i++ ) {
818 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
819 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
820 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
821 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
822 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
823 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
824 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
825 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
826 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
827 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
828 }
829
830 #ifdef DEBUG
831 /* silence warnings */
832 (void) print_chan;
833 (void) print_temp;
834 #endif
835
836 return mach;
837
838 fail:
839 align_free(mach);
840 return NULL;
841 }
842
843
844 void
845 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
846 {
847 if (mach) {
848 if (mach->Instructions)
849 FREE(mach->Instructions);
850 if (mach->Declarations)
851 FREE(mach->Declarations);
852 }
853
854 align_free(mach);
855 }
856
857 static void
858 micro_add(union tgsi_exec_channel *dst,
859 const union tgsi_exec_channel *src0,
860 const union tgsi_exec_channel *src1)
861 {
862 dst->f[0] = src0->f[0] + src1->f[0];
863 dst->f[1] = src0->f[1] + src1->f[1];
864 dst->f[2] = src0->f[2] + src1->f[2];
865 dst->f[3] = src0->f[3] + src1->f[3];
866 }
867
868 static void
869 micro_div(
870 union tgsi_exec_channel *dst,
871 const union tgsi_exec_channel *src0,
872 const union tgsi_exec_channel *src1 )
873 {
874 if (src1->f[0] != 0) {
875 dst->f[0] = src0->f[0] / src1->f[0];
876 }
877 if (src1->f[1] != 0) {
878 dst->f[1] = src0->f[1] / src1->f[1];
879 }
880 if (src1->f[2] != 0) {
881 dst->f[2] = src0->f[2] / src1->f[2];
882 }
883 if (src1->f[3] != 0) {
884 dst->f[3] = src0->f[3] / src1->f[3];
885 }
886 }
887
888 static void
889 micro_float_clamp(union tgsi_exec_channel *dst,
890 const union tgsi_exec_channel *src)
891 {
892 uint i;
893
894 for (i = 0; i < 4; i++) {
895 if (src->f[i] > 0.0f) {
896 if (src->f[i] > 1.884467e+019f)
897 dst->f[i] = 1.884467e+019f;
898 else if (src->f[i] < 5.42101e-020f)
899 dst->f[i] = 5.42101e-020f;
900 else
901 dst->f[i] = src->f[i];
902 }
903 else {
904 if (src->f[i] < -1.884467e+019f)
905 dst->f[i] = -1.884467e+019f;
906 else if (src->f[i] > -5.42101e-020f)
907 dst->f[i] = -5.42101e-020f;
908 else
909 dst->f[i] = src->f[i];
910 }
911 }
912 }
913
914 static void
915 micro_lt(
916 union tgsi_exec_channel *dst,
917 const union tgsi_exec_channel *src0,
918 const union tgsi_exec_channel *src1,
919 const union tgsi_exec_channel *src2,
920 const union tgsi_exec_channel *src3 )
921 {
922 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
923 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
924 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
925 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
926 }
927
928 static void
929 micro_max(union tgsi_exec_channel *dst,
930 const union tgsi_exec_channel *src0,
931 const union tgsi_exec_channel *src1)
932 {
933 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
934 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
935 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
936 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
937 }
938
939 static void
940 micro_min(union tgsi_exec_channel *dst,
941 const union tgsi_exec_channel *src0,
942 const union tgsi_exec_channel *src1)
943 {
944 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
945 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
946 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
947 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
948 }
949
950 static void
951 micro_mul(union tgsi_exec_channel *dst,
952 const union tgsi_exec_channel *src0,
953 const union tgsi_exec_channel *src1)
954 {
955 dst->f[0] = src0->f[0] * src1->f[0];
956 dst->f[1] = src0->f[1] * src1->f[1];
957 dst->f[2] = src0->f[2] * src1->f[2];
958 dst->f[3] = src0->f[3] * src1->f[3];
959 }
960
961 #if 0
962 static void
963 micro_imul64(
964 union tgsi_exec_channel *dst0,
965 union tgsi_exec_channel *dst1,
966 const union tgsi_exec_channel *src0,
967 const union tgsi_exec_channel *src1 )
968 {
969 dst1->i[0] = src0->i[0] * src1->i[0];
970 dst1->i[1] = src0->i[1] * src1->i[1];
971 dst1->i[2] = src0->i[2] * src1->i[2];
972 dst1->i[3] = src0->i[3] * src1->i[3];
973 dst0->i[0] = 0;
974 dst0->i[1] = 0;
975 dst0->i[2] = 0;
976 dst0->i[3] = 0;
977 }
978 #endif
979
980 #if 0
981 static void
982 micro_umul64(
983 union tgsi_exec_channel *dst0,
984 union tgsi_exec_channel *dst1,
985 const union tgsi_exec_channel *src0,
986 const union tgsi_exec_channel *src1 )
987 {
988 dst1->u[0] = src0->u[0] * src1->u[0];
989 dst1->u[1] = src0->u[1] * src1->u[1];
990 dst1->u[2] = src0->u[2] * src1->u[2];
991 dst1->u[3] = src0->u[3] * src1->u[3];
992 dst0->u[0] = 0;
993 dst0->u[1] = 0;
994 dst0->u[2] = 0;
995 dst0->u[3] = 0;
996 }
997 #endif
998
999
1000 #if 0
1001 static void
1002 micro_movc(
1003 union tgsi_exec_channel *dst,
1004 const union tgsi_exec_channel *src0,
1005 const union tgsi_exec_channel *src1,
1006 const union tgsi_exec_channel *src2 )
1007 {
1008 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
1009 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
1010 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
1011 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
1012 }
1013 #endif
1014
1015 static void
1016 micro_neg(
1017 union tgsi_exec_channel *dst,
1018 const union tgsi_exec_channel *src )
1019 {
1020 dst->f[0] = -src->f[0];
1021 dst->f[1] = -src->f[1];
1022 dst->f[2] = -src->f[2];
1023 dst->f[3] = -src->f[3];
1024 }
1025
1026 static void
1027 micro_pow(
1028 union tgsi_exec_channel *dst,
1029 const union tgsi_exec_channel *src0,
1030 const union tgsi_exec_channel *src1 )
1031 {
1032 #if FAST_MATH
1033 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1034 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1035 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1036 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1037 #else
1038 dst->f[0] = powf( src0->f[0], src1->f[0] );
1039 dst->f[1] = powf( src0->f[1], src1->f[1] );
1040 dst->f[2] = powf( src0->f[2], src1->f[2] );
1041 dst->f[3] = powf( src0->f[3], src1->f[3] );
1042 #endif
1043 }
1044
1045 static void
1046 micro_sub(union tgsi_exec_channel *dst,
1047 const union tgsi_exec_channel *src0,
1048 const union tgsi_exec_channel *src1)
1049 {
1050 dst->f[0] = src0->f[0] - src1->f[0];
1051 dst->f[1] = src0->f[1] - src1->f[1];
1052 dst->f[2] = src0->f[2] - src1->f[2];
1053 dst->f[3] = src0->f[3] - src1->f[3];
1054 }
1055
1056 static void
1057 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1058 const uint file,
1059 const uint swizzle,
1060 const union tgsi_exec_channel *index,
1061 const union tgsi_exec_channel *index2D,
1062 union tgsi_exec_channel *chan)
1063 {
1064 uint i;
1065
1066 assert(swizzle < 4);
1067
1068 switch (file) {
1069 case TGSI_FILE_CONSTANT:
1070 for (i = 0; i < QUAD_SIZE; i++) {
1071 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1072 assert(mach->Consts[index2D->i[i]]);
1073
1074 if (index->i[i] < 0) {
1075 chan->u[i] = 0;
1076 } else {
1077 /* NOTE: copying the const value as a uint instead of float */
1078 const uint constbuf = index2D->i[i];
1079 const uint *buf = (const uint *)mach->Consts[constbuf];
1080 const int pos = index->i[i] * 4 + swizzle;
1081 /* const buffer bounds check */
1082 if (pos < 0 || pos >= mach->ConstsSize[constbuf]) {
1083 if (0) {
1084 /* Debug: print warning */
1085 static int count = 0;
1086 if (count++ < 100)
1087 debug_printf("TGSI Exec: const buffer index %d"
1088 " out of bounds\n", pos);
1089 }
1090 chan->u[i] = 0;
1091 }
1092 else
1093 chan->u[i] = buf[pos];
1094 }
1095 }
1096 break;
1097
1098 case TGSI_FILE_INPUT:
1099 case TGSI_FILE_SYSTEM_VALUE:
1100 for (i = 0; i < QUAD_SIZE; i++) {
1101 /*
1102 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1103 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1104 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1105 index2D->i[i], index->i[i]);
1106 }*/
1107 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1108 assert(pos >= 0);
1109 assert(pos < Elements(mach->Inputs));
1110 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1111 }
1112 break;
1113
1114 case TGSI_FILE_TEMPORARY:
1115 for (i = 0; i < QUAD_SIZE; i++) {
1116 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1117 assert(index2D->i[i] == 0);
1118
1119 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1120 }
1121 break;
1122
1123 case TGSI_FILE_TEMPORARY_ARRAY:
1124 for (i = 0; i < QUAD_SIZE; i++) {
1125 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1126 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1127
1128 chan->u[i] =
1129 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1130 }
1131 break;
1132
1133 case TGSI_FILE_IMMEDIATE:
1134 for (i = 0; i < QUAD_SIZE; i++) {
1135 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1136 assert(index2D->i[i] == 0);
1137
1138 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1139 }
1140 break;
1141
1142 case TGSI_FILE_IMMEDIATE_ARRAY:
1143 for (i = 0; i < QUAD_SIZE; i++) {
1144 assert(index2D->i[i] == 0);
1145
1146 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1147 }
1148 break;
1149
1150 case TGSI_FILE_ADDRESS:
1151 for (i = 0; i < QUAD_SIZE; i++) {
1152 assert(index->i[i] >= 0);
1153 assert(index2D->i[i] == 0);
1154
1155 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1156 }
1157 break;
1158
1159 case TGSI_FILE_PREDICATE:
1160 for (i = 0; i < QUAD_SIZE; i++) {
1161 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1162 assert(index2D->i[i] == 0);
1163
1164 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1165 }
1166 break;
1167
1168 case TGSI_FILE_OUTPUT:
1169 /* vertex/fragment output vars can be read too */
1170 for (i = 0; i < QUAD_SIZE; i++) {
1171 assert(index->i[i] >= 0);
1172 assert(index2D->i[i] == 0);
1173
1174 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1175 }
1176 break;
1177
1178 default:
1179 assert(0);
1180 for (i = 0; i < QUAD_SIZE; i++) {
1181 chan->u[i] = 0;
1182 }
1183 }
1184 }
1185
1186 static void
1187 fetch_source(const struct tgsi_exec_machine *mach,
1188 union tgsi_exec_channel *chan,
1189 const struct tgsi_full_src_register *reg,
1190 const uint chan_index,
1191 enum tgsi_exec_datatype src_datatype)
1192 {
1193 union tgsi_exec_channel index;
1194 union tgsi_exec_channel index2D;
1195 uint swizzle;
1196
1197 /* We start with a direct index into a register file.
1198 *
1199 * file[1],
1200 * where:
1201 * file = Register.File
1202 * [1] = Register.Index
1203 */
1204 index.i[0] =
1205 index.i[1] =
1206 index.i[2] =
1207 index.i[3] = reg->Register.Index;
1208
1209 /* There is an extra source register that indirectly subscripts
1210 * a register file. The direct index now becomes an offset
1211 * that is being added to the indirect register.
1212 *
1213 * file[ind[2].x+1],
1214 * where:
1215 * ind = Indirect.File
1216 * [2] = Indirect.Index
1217 * .x = Indirect.SwizzleX
1218 */
1219 if (reg->Register.Indirect) {
1220 union tgsi_exec_channel index2;
1221 union tgsi_exec_channel indir_index;
1222 const uint execmask = mach->ExecMask;
1223 uint i;
1224
1225 /* which address register (always zero now) */
1226 index2.i[0] =
1227 index2.i[1] =
1228 index2.i[2] =
1229 index2.i[3] = reg->Indirect.Index;
1230 assert(reg->Indirect.File == TGSI_FILE_ADDRESS);
1231 /* get current value of address register[swizzle] */
1232 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1233 fetch_src_file_channel(mach,
1234 reg->Indirect.File,
1235 swizzle,
1236 &index2,
1237 &ZeroVec,
1238 &indir_index);
1239
1240 /* add value of address register to the offset */
1241 index.i[0] += indir_index.i[0];
1242 index.i[1] += indir_index.i[1];
1243 index.i[2] += indir_index.i[2];
1244 index.i[3] += indir_index.i[3];
1245
1246 /* for disabled execution channels, zero-out the index to
1247 * avoid using a potential garbage value.
1248 */
1249 for (i = 0; i < QUAD_SIZE; i++) {
1250 if ((execmask & (1 << i)) == 0)
1251 index.i[i] = 0;
1252 }
1253 }
1254
1255 /* There is an extra source register that is a second
1256 * subscript to a register file. Effectively it means that
1257 * the register file is actually a 2D array of registers.
1258 *
1259 * file[3][1],
1260 * where:
1261 * [3] = Dimension.Index
1262 */
1263 if (reg->Register.Dimension) {
1264 index2D.i[0] =
1265 index2D.i[1] =
1266 index2D.i[2] =
1267 index2D.i[3] = reg->Dimension.Index;
1268
1269 /* Again, the second subscript index can be addressed indirectly
1270 * identically to the first one.
1271 * Nothing stops us from indirectly addressing the indirect register,
1272 * but there is no need for that, so we won't exercise it.
1273 *
1274 * file[ind[4].y+3][1],
1275 * where:
1276 * ind = DimIndirect.File
1277 * [4] = DimIndirect.Index
1278 * .y = DimIndirect.SwizzleX
1279 */
1280 if (reg->Dimension.Indirect) {
1281 union tgsi_exec_channel index2;
1282 union tgsi_exec_channel indir_index;
1283 const uint execmask = mach->ExecMask;
1284 uint i;
1285
1286 index2.i[0] =
1287 index2.i[1] =
1288 index2.i[2] =
1289 index2.i[3] = reg->DimIndirect.Index;
1290
1291 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1292 fetch_src_file_channel(mach,
1293 reg->DimIndirect.File,
1294 swizzle,
1295 &index2,
1296 &ZeroVec,
1297 &indir_index);
1298
1299 index2D.i[0] += indir_index.i[0];
1300 index2D.i[1] += indir_index.i[1];
1301 index2D.i[2] += indir_index.i[2];
1302 index2D.i[3] += indir_index.i[3];
1303
1304 /* for disabled execution channels, zero-out the index to
1305 * avoid using a potential garbage value.
1306 */
1307 for (i = 0; i < QUAD_SIZE; i++) {
1308 if ((execmask & (1 << i)) == 0) {
1309 index2D.i[i] = 0;
1310 }
1311 }
1312 }
1313
1314 /* If by any chance there was a need for a 3D array of register
1315 * files, we would have to check whether Dimension is followed
1316 * by a dimension register and continue the saga.
1317 */
1318 } else {
1319 index2D.i[0] =
1320 index2D.i[1] =
1321 index2D.i[2] =
1322 index2D.i[3] = 0;
1323 }
1324
1325 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1326 fetch_src_file_channel(mach,
1327 reg->Register.File,
1328 swizzle,
1329 &index,
1330 &index2D,
1331 chan);
1332
1333 if (reg->Register.Absolute) {
1334 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1335 micro_abs(chan, chan);
1336 } else {
1337 micro_iabs(chan, chan);
1338 }
1339 }
1340
1341 if (reg->Register.Negate) {
1342 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1343 micro_neg(chan, chan);
1344 } else {
1345 micro_ineg(chan, chan);
1346 }
1347 }
1348 }
1349
1350 static void
1351 store_dest(struct tgsi_exec_machine *mach,
1352 const union tgsi_exec_channel *chan,
1353 const struct tgsi_full_dst_register *reg,
1354 const struct tgsi_full_instruction *inst,
1355 uint chan_index,
1356 enum tgsi_exec_datatype dst_datatype)
1357 {
1358 uint i;
1359 union tgsi_exec_channel null;
1360 union tgsi_exec_channel *dst;
1361 union tgsi_exec_channel index2D;
1362 uint execmask = mach->ExecMask;
1363 int offset = 0; /* indirection offset */
1364 int index;
1365
1366 /* for debugging */
1367 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1368 check_inf_or_nan(chan);
1369 }
1370
1371 /* There is an extra source register that indirectly subscripts
1372 * a register file. The direct index now becomes an offset
1373 * that is being added to the indirect register.
1374 *
1375 * file[ind[2].x+1],
1376 * where:
1377 * ind = Indirect.File
1378 * [2] = Indirect.Index
1379 * .x = Indirect.SwizzleX
1380 */
1381 if (reg->Register.Indirect) {
1382 union tgsi_exec_channel index;
1383 union tgsi_exec_channel indir_index;
1384 uint swizzle;
1385
1386 /* which address register (always zero for now) */
1387 index.i[0] =
1388 index.i[1] =
1389 index.i[2] =
1390 index.i[3] = reg->Indirect.Index;
1391
1392 /* get current value of address register[swizzle] */
1393 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1394
1395 /* fetch values from the address/indirection register */
1396 fetch_src_file_channel(mach,
1397 reg->Indirect.File,
1398 swizzle,
1399 &index,
1400 &ZeroVec,
1401 &indir_index);
1402
1403 /* save indirection offset */
1404 offset = indir_index.i[0];
1405 }
1406
1407 /* There is an extra source register that is a second
1408 * subscript to a register file. Effectively it means that
1409 * the register file is actually a 2D array of registers.
1410 *
1411 * file[3][1],
1412 * where:
1413 * [3] = Dimension.Index
1414 */
1415 if (reg->Register.Dimension) {
1416 index2D.i[0] =
1417 index2D.i[1] =
1418 index2D.i[2] =
1419 index2D.i[3] = reg->Dimension.Index;
1420
1421 /* Again, the second subscript index can be addressed indirectly
1422 * identically to the first one.
1423 * Nothing stops us from indirectly addressing the indirect register,
1424 * but there is no need for that, so we won't exercise it.
1425 *
1426 * file[ind[4].y+3][1],
1427 * where:
1428 * ind = DimIndirect.File
1429 * [4] = DimIndirect.Index
1430 * .y = DimIndirect.SwizzleX
1431 */
1432 if (reg->Dimension.Indirect) {
1433 union tgsi_exec_channel index2;
1434 union tgsi_exec_channel indir_index;
1435 const uint execmask = mach->ExecMask;
1436 unsigned swizzle;
1437 uint i;
1438
1439 index2.i[0] =
1440 index2.i[1] =
1441 index2.i[2] =
1442 index2.i[3] = reg->DimIndirect.Index;
1443
1444 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1445 fetch_src_file_channel(mach,
1446 reg->DimIndirect.File,
1447 swizzle,
1448 &index2,
1449 &ZeroVec,
1450 &indir_index);
1451
1452 index2D.i[0] += indir_index.i[0];
1453 index2D.i[1] += indir_index.i[1];
1454 index2D.i[2] += indir_index.i[2];
1455 index2D.i[3] += indir_index.i[3];
1456
1457 /* for disabled execution channels, zero-out the index to
1458 * avoid using a potential garbage value.
1459 */
1460 for (i = 0; i < QUAD_SIZE; i++) {
1461 if ((execmask & (1 << i)) == 0) {
1462 index2D.i[i] = 0;
1463 }
1464 }
1465 }
1466
1467 /* If by any chance there was a need for a 3D array of register
1468 * files, we would have to check whether Dimension is followed
1469 * by a dimension register and continue the saga.
1470 */
1471 } else {
1472 index2D.i[0] =
1473 index2D.i[1] =
1474 index2D.i[2] =
1475 index2D.i[3] = 0;
1476 }
1477
1478 switch (reg->Register.File) {
1479 case TGSI_FILE_NULL:
1480 dst = &null;
1481 break;
1482
1483 case TGSI_FILE_OUTPUT:
1484 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1485 + reg->Register.Index;
1486 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1487 #if 0
1488 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1489 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1490 for (i = 0; i < QUAD_SIZE; i++)
1491 if (execmask & (1 << i))
1492 fprintf(stderr, "%f, ", chan->f[i]);
1493 fprintf(stderr, ")\n");
1494 }
1495 #endif
1496 break;
1497
1498 case TGSI_FILE_TEMPORARY:
1499 index = reg->Register.Index;
1500 assert( index < TGSI_EXEC_NUM_TEMPS );
1501 dst = &mach->Temps[offset + index].xyzw[chan_index];
1502 break;
1503
1504 case TGSI_FILE_TEMPORARY_ARRAY:
1505 index = reg->Register.Index;
1506 assert( index < TGSI_EXEC_NUM_TEMPS );
1507 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1508 /* XXX we use index2D.i[0] here but somehow we might
1509 * end up with someone trying to store indirectly in
1510 * different buffers */
1511 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1512 break;
1513
1514 case TGSI_FILE_ADDRESS:
1515 index = reg->Register.Index;
1516 dst = &mach->Addrs[index].xyzw[chan_index];
1517 break;
1518
1519 case TGSI_FILE_PREDICATE:
1520 index = reg->Register.Index;
1521 assert(index < TGSI_EXEC_NUM_PREDS);
1522 dst = &mach->Predicates[index].xyzw[chan_index];
1523 break;
1524
1525 default:
1526 assert( 0 );
1527 return;
1528 }
1529
1530 if (inst->Instruction.Predicate) {
1531 uint swizzle;
1532 union tgsi_exec_channel *pred;
1533
1534 switch (chan_index) {
1535 case CHAN_X:
1536 swizzle = inst->Predicate.SwizzleX;
1537 break;
1538 case CHAN_Y:
1539 swizzle = inst->Predicate.SwizzleY;
1540 break;
1541 case CHAN_Z:
1542 swizzle = inst->Predicate.SwizzleZ;
1543 break;
1544 case CHAN_W:
1545 swizzle = inst->Predicate.SwizzleW;
1546 break;
1547 default:
1548 assert(0);
1549 return;
1550 }
1551
1552 assert(inst->Predicate.Index == 0);
1553
1554 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1555
1556 if (inst->Predicate.Negate) {
1557 for (i = 0; i < QUAD_SIZE; i++) {
1558 if (pred->u[i]) {
1559 execmask &= ~(1 << i);
1560 }
1561 }
1562 } else {
1563 for (i = 0; i < QUAD_SIZE; i++) {
1564 if (!pred->u[i]) {
1565 execmask &= ~(1 << i);
1566 }
1567 }
1568 }
1569 }
1570
1571 switch (inst->Instruction.Saturate) {
1572 case TGSI_SAT_NONE:
1573 for (i = 0; i < QUAD_SIZE; i++)
1574 if (execmask & (1 << i))
1575 dst->i[i] = chan->i[i];
1576 break;
1577
1578 case TGSI_SAT_ZERO_ONE:
1579 for (i = 0; i < QUAD_SIZE; i++)
1580 if (execmask & (1 << i)) {
1581 if (chan->f[i] < 0.0f)
1582 dst->f[i] = 0.0f;
1583 else if (chan->f[i] > 1.0f)
1584 dst->f[i] = 1.0f;
1585 else
1586 dst->i[i] = chan->i[i];
1587 }
1588 break;
1589
1590 case TGSI_SAT_MINUS_PLUS_ONE:
1591 for (i = 0; i < QUAD_SIZE; i++)
1592 if (execmask & (1 << i)) {
1593 if (chan->f[i] < -1.0f)
1594 dst->f[i] = -1.0f;
1595 else if (chan->f[i] > 1.0f)
1596 dst->f[i] = 1.0f;
1597 else
1598 dst->i[i] = chan->i[i];
1599 }
1600 break;
1601
1602 default:
1603 assert( 0 );
1604 }
1605 }
1606
1607 #define FETCH(VAL,INDEX,CHAN)\
1608 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1609
1610 #define STORE(VAL,INDEX,CHAN)\
1611 store_dest(mach, VAL, &inst->Dst[INDEX], inst, CHAN, TGSI_EXEC_DATA_FLOAT)
1612
1613
1614 /**
1615 * Execute ARB-style KIL which is predicated by a src register.
1616 * Kill fragment if any of the four values is less than zero.
1617 */
1618 static void
1619 exec_kil(struct tgsi_exec_machine *mach,
1620 const struct tgsi_full_instruction *inst)
1621 {
1622 uint uniquemask;
1623 uint chan_index;
1624 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1625 union tgsi_exec_channel r[1];
1626
1627 /* This mask stores component bits that were already tested. */
1628 uniquemask = 0;
1629
1630 for (chan_index = 0; chan_index < 4; chan_index++)
1631 {
1632 uint swizzle;
1633 uint i;
1634
1635 /* unswizzle channel */
1636 swizzle = tgsi_util_get_full_src_register_swizzle (
1637 &inst->Src[0],
1638 chan_index);
1639
1640 /* check if the component has not been already tested */
1641 if (uniquemask & (1 << swizzle))
1642 continue;
1643 uniquemask |= 1 << swizzle;
1644
1645 FETCH(&r[0], 0, chan_index);
1646 for (i = 0; i < 4; i++)
1647 if (r[0].f[i] < 0.0f)
1648 kilmask |= 1 << i;
1649 }
1650
1651 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1652 }
1653
1654 /**
1655 * Execute NVIDIA-style KIL which is predicated by a condition code.
1656 * Kill fragment if the condition code is TRUE.
1657 */
1658 static void
1659 exec_kilp(struct tgsi_exec_machine *mach,
1660 const struct tgsi_full_instruction *inst)
1661 {
1662 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1663
1664 /* "unconditional" kil */
1665 kilmask = mach->ExecMask;
1666 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1667 }
1668
1669 static void
1670 emit_vertex(struct tgsi_exec_machine *mach)
1671 {
1672 /* FIXME: check for exec mask correctly
1673 unsigned i;
1674 for (i = 0; i < QUAD_SIZE; ++i) {
1675 if ((mach->ExecMask & (1 << i)))
1676 */
1677 if (mach->ExecMask) {
1678 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1679 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1680 }
1681 }
1682
1683 static void
1684 emit_primitive(struct tgsi_exec_machine *mach)
1685 {
1686 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1687 /* FIXME: check for exec mask correctly
1688 unsigned i;
1689 for (i = 0; i < QUAD_SIZE; ++i) {
1690 if ((mach->ExecMask & (1 << i)))
1691 */
1692 if (mach->ExecMask) {
1693 ++(*prim_count);
1694 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1695 mach->Primitives[*prim_count] = 0;
1696 }
1697 }
1698
1699 static void
1700 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1701 {
1702 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1703 int emitted_verts =
1704 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1705 if (emitted_verts) {
1706 emit_primitive(mach);
1707 }
1708 }
1709 }
1710
1711
1712 /*
1713 * Fetch four texture samples using STR texture coordinates.
1714 */
1715 static void
1716 fetch_texel( struct tgsi_sampler *sampler,
1717 const union tgsi_exec_channel *s,
1718 const union tgsi_exec_channel *t,
1719 const union tgsi_exec_channel *p,
1720 const union tgsi_exec_channel *c0,
1721 enum tgsi_sampler_control control,
1722 union tgsi_exec_channel *r,
1723 union tgsi_exec_channel *g,
1724 union tgsi_exec_channel *b,
1725 union tgsi_exec_channel *a )
1726 {
1727 uint j;
1728 float rgba[NUM_CHANNELS][QUAD_SIZE];
1729
1730 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1731
1732 for (j = 0; j < 4; j++) {
1733 r->f[j] = rgba[0][j];
1734 g->f[j] = rgba[1][j];
1735 b->f[j] = rgba[2][j];
1736 a->f[j] = rgba[3][j];
1737 }
1738 }
1739
1740
1741 #define TEX_MODIFIER_NONE 0
1742 #define TEX_MODIFIER_PROJECTED 1
1743 #define TEX_MODIFIER_LOD_BIAS 2
1744 #define TEX_MODIFIER_EXPLICIT_LOD 3
1745
1746
1747 static void
1748 exec_tex(struct tgsi_exec_machine *mach,
1749 const struct tgsi_full_instruction *inst,
1750 uint modifier)
1751 {
1752 const uint unit = inst->Src[1].Register.Index;
1753 union tgsi_exec_channel r[4];
1754 const union tgsi_exec_channel *lod = &ZeroVec;
1755 enum tgsi_sampler_control control;
1756 uint chan_index;
1757
1758 if (modifier != TEX_MODIFIER_NONE) {
1759 FETCH(&r[3], 0, CHAN_W);
1760 if (modifier != TEX_MODIFIER_PROJECTED) {
1761 lod = &r[3];
1762 }
1763 }
1764
1765 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1766 control = tgsi_sampler_lod_explicit;
1767 } else {
1768 control = tgsi_sampler_lod_bias;
1769 }
1770
1771 switch (inst->Texture.Texture) {
1772 case TGSI_TEXTURE_1D:
1773 case TGSI_TEXTURE_SHADOW1D:
1774 FETCH(&r[0], 0, CHAN_X);
1775
1776 if (modifier == TEX_MODIFIER_PROJECTED) {
1777 micro_div(&r[0], &r[0], &r[3]);
1778 }
1779
1780 fetch_texel(mach->Samplers[unit],
1781 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1782 control,
1783 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1784 break;
1785
1786 case TGSI_TEXTURE_2D:
1787 case TGSI_TEXTURE_RECT:
1788 case TGSI_TEXTURE_SHADOW2D:
1789 case TGSI_TEXTURE_SHADOWRECT:
1790 FETCH(&r[0], 0, CHAN_X);
1791 FETCH(&r[1], 0, CHAN_Y);
1792 FETCH(&r[2], 0, CHAN_Z);
1793
1794 if (modifier == TEX_MODIFIER_PROJECTED) {
1795 micro_div(&r[0], &r[0], &r[3]);
1796 micro_div(&r[1], &r[1], &r[3]);
1797 micro_div(&r[2], &r[2], &r[3]);
1798 }
1799
1800 fetch_texel(mach->Samplers[unit],
1801 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1802 control,
1803 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1804 break;
1805
1806 case TGSI_TEXTURE_3D:
1807 case TGSI_TEXTURE_CUBE:
1808 FETCH(&r[0], 0, CHAN_X);
1809 FETCH(&r[1], 0, CHAN_Y);
1810 FETCH(&r[2], 0, CHAN_Z);
1811
1812 if (modifier == TEX_MODIFIER_PROJECTED) {
1813 micro_div(&r[0], &r[0], &r[3]);
1814 micro_div(&r[1], &r[1], &r[3]);
1815 micro_div(&r[2], &r[2], &r[3]);
1816 }
1817
1818 fetch_texel(mach->Samplers[unit],
1819 &r[0], &r[1], &r[2], lod,
1820 control,
1821 &r[0], &r[1], &r[2], &r[3]);
1822 break;
1823
1824 default:
1825 assert(0);
1826 }
1827
1828 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1829 STORE(&r[chan_index], 0, chan_index);
1830 }
1831 }
1832
1833 static void
1834 exec_txd(struct tgsi_exec_machine *mach,
1835 const struct tgsi_full_instruction *inst)
1836 {
1837 const uint unit = inst->Src[3].Register.Index;
1838 union tgsi_exec_channel r[4];
1839 uint chan_index;
1840
1841 /*
1842 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1843 */
1844
1845 switch (inst->Texture.Texture) {
1846 case TGSI_TEXTURE_1D:
1847 case TGSI_TEXTURE_SHADOW1D:
1848
1849 FETCH(&r[0], 0, CHAN_X);
1850
1851 fetch_texel(mach->Samplers[unit],
1852 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1853 tgsi_sampler_lod_bias,
1854 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1855 break;
1856
1857 case TGSI_TEXTURE_2D:
1858 case TGSI_TEXTURE_RECT:
1859 case TGSI_TEXTURE_SHADOW2D:
1860 case TGSI_TEXTURE_SHADOWRECT:
1861
1862 FETCH(&r[0], 0, CHAN_X);
1863 FETCH(&r[1], 0, CHAN_Y);
1864 FETCH(&r[2], 0, CHAN_Z);
1865
1866 fetch_texel(mach->Samplers[unit],
1867 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1868 tgsi_sampler_lod_bias,
1869 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1870 break;
1871
1872 case TGSI_TEXTURE_3D:
1873 case TGSI_TEXTURE_CUBE:
1874
1875 FETCH(&r[0], 0, CHAN_X);
1876 FETCH(&r[1], 0, CHAN_Y);
1877 FETCH(&r[2], 0, CHAN_Z);
1878
1879 fetch_texel(mach->Samplers[unit],
1880 &r[0], &r[1], &r[2], &ZeroVec,
1881 tgsi_sampler_lod_bias,
1882 &r[0], &r[1], &r[2], &r[3]);
1883 break;
1884
1885 default:
1886 assert(0);
1887 }
1888
1889 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1890 STORE(&r[chan_index], 0, chan_index);
1891 }
1892 }
1893
1894
1895 /**
1896 * Evaluate a constant-valued coefficient at the position of the
1897 * current quad.
1898 */
1899 static void
1900 eval_constant_coef(
1901 struct tgsi_exec_machine *mach,
1902 unsigned attrib,
1903 unsigned chan )
1904 {
1905 unsigned i;
1906
1907 for( i = 0; i < QUAD_SIZE; i++ ) {
1908 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1909 }
1910 }
1911
1912 /**
1913 * Evaluate a linear-valued coefficient at the position of the
1914 * current quad.
1915 */
1916 static void
1917 eval_linear_coef(
1918 struct tgsi_exec_machine *mach,
1919 unsigned attrib,
1920 unsigned chan )
1921 {
1922 const float x = mach->QuadPos.xyzw[0].f[0];
1923 const float y = mach->QuadPos.xyzw[1].f[0];
1924 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1925 const float dady = mach->InterpCoefs[attrib].dady[chan];
1926 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1927 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1928 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1929 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1930 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1931 }
1932
1933 /**
1934 * Evaluate a perspective-valued coefficient at the position of the
1935 * current quad.
1936 */
1937 static void
1938 eval_perspective_coef(
1939 struct tgsi_exec_machine *mach,
1940 unsigned attrib,
1941 unsigned chan )
1942 {
1943 const float x = mach->QuadPos.xyzw[0].f[0];
1944 const float y = mach->QuadPos.xyzw[1].f[0];
1945 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1946 const float dady = mach->InterpCoefs[attrib].dady[chan];
1947 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1948 const float *w = mach->QuadPos.xyzw[3].f;
1949 /* divide by W here */
1950 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1951 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1952 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1953 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1954 }
1955
1956
1957 typedef void (* eval_coef_func)(
1958 struct tgsi_exec_machine *mach,
1959 unsigned attrib,
1960 unsigned chan );
1961
1962 static void
1963 exec_declaration(struct tgsi_exec_machine *mach,
1964 const struct tgsi_full_declaration *decl)
1965 {
1966 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
1967 if (decl->Declaration.File == TGSI_FILE_INPUT ||
1968 decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1969 uint first, last, mask;
1970
1971 first = decl->Range.First;
1972 last = decl->Range.Last;
1973 mask = decl->Declaration.UsageMask;
1974
1975 /* XXX we could remove this special-case code since
1976 * mach->InterpCoefs[first].a0 should already have the
1977 * front/back-face value. But we should first update the
1978 * ureg code to emit the right UsageMask value (WRITEMASK_X).
1979 * Then, we could remove the tgsi_exec_machine::Face field.
1980 */
1981 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1982 uint i;
1983
1984 assert(decl->Semantic.Index == 0);
1985 assert(first == last);
1986
1987 for (i = 0; i < QUAD_SIZE; i++) {
1988 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
1989 }
1990 } else {
1991 eval_coef_func eval;
1992 uint i, j;
1993
1994 switch (decl->Declaration.Interpolate) {
1995 case TGSI_INTERPOLATE_CONSTANT:
1996 eval = eval_constant_coef;
1997 break;
1998
1999 case TGSI_INTERPOLATE_LINEAR:
2000 eval = eval_linear_coef;
2001 break;
2002
2003 case TGSI_INTERPOLATE_PERSPECTIVE:
2004 eval = eval_perspective_coef;
2005 break;
2006
2007 default:
2008 assert(0);
2009 return;
2010 }
2011
2012 for (j = 0; j < NUM_CHANNELS; j++) {
2013 if (mask & (1 << j)) {
2014 for (i = first; i <= last; i++) {
2015 eval(mach, i, j);
2016 }
2017 }
2018 }
2019 }
2020 }
2021 }
2022 }
2023
2024 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2025 const union tgsi_exec_channel *src);
2026
2027 static void
2028 exec_scalar_unary(struct tgsi_exec_machine *mach,
2029 const struct tgsi_full_instruction *inst,
2030 micro_unary_op op,
2031 enum tgsi_exec_datatype dst_datatype,
2032 enum tgsi_exec_datatype src_datatype)
2033 {
2034 unsigned int chan;
2035 union tgsi_exec_channel src;
2036 union tgsi_exec_channel dst;
2037
2038 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
2039 op(&dst, &src);
2040 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2041 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2042 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2043 }
2044 }
2045 }
2046
2047 static void
2048 exec_vector_unary(struct tgsi_exec_machine *mach,
2049 const struct tgsi_full_instruction *inst,
2050 micro_unary_op op,
2051 enum tgsi_exec_datatype dst_datatype,
2052 enum tgsi_exec_datatype src_datatype)
2053 {
2054 unsigned int chan;
2055 struct tgsi_exec_vector dst;
2056
2057 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2058 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2059 union tgsi_exec_channel src;
2060
2061 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2062 op(&dst.xyzw[chan], &src);
2063 }
2064 }
2065 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2066 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2067 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2068 }
2069 }
2070 }
2071
2072 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2073 const union tgsi_exec_channel *src0,
2074 const union tgsi_exec_channel *src1);
2075
2076 static void
2077 exec_vector_binary(struct tgsi_exec_machine *mach,
2078 const struct tgsi_full_instruction *inst,
2079 micro_binary_op op,
2080 enum tgsi_exec_datatype dst_datatype,
2081 enum tgsi_exec_datatype src_datatype)
2082 {
2083 unsigned int chan;
2084 struct tgsi_exec_vector dst;
2085
2086 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2087 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2088 union tgsi_exec_channel src[2];
2089
2090 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2091 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2092 op(&dst.xyzw[chan], &src[0], &src[1]);
2093 }
2094 }
2095 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2096 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2097 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2098 }
2099 }
2100 }
2101
2102 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2103 const union tgsi_exec_channel *src0,
2104 const union tgsi_exec_channel *src1,
2105 const union tgsi_exec_channel *src2);
2106
2107 static void
2108 exec_vector_trinary(struct tgsi_exec_machine *mach,
2109 const struct tgsi_full_instruction *inst,
2110 micro_trinary_op op,
2111 enum tgsi_exec_datatype dst_datatype,
2112 enum tgsi_exec_datatype src_datatype)
2113 {
2114 unsigned int chan;
2115 struct tgsi_exec_vector dst;
2116
2117 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2118 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2119 union tgsi_exec_channel src[3];
2120
2121 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2122 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2123 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2124 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2125 }
2126 }
2127 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2128 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2129 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2130 }
2131 }
2132 }
2133
2134 static void
2135 exec_dp3(struct tgsi_exec_machine *mach,
2136 const struct tgsi_full_instruction *inst)
2137 {
2138 unsigned int chan;
2139 union tgsi_exec_channel arg[3];
2140
2141 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2142 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2143 micro_mul(&arg[2], &arg[0], &arg[1]);
2144
2145 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2146 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2147 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2148 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2149 }
2150
2151 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2152 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2153 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2154 }
2155 }
2156 }
2157
2158 static void
2159 exec_dp4(struct tgsi_exec_machine *mach,
2160 const struct tgsi_full_instruction *inst)
2161 {
2162 unsigned int chan;
2163 union tgsi_exec_channel arg[3];
2164
2165 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2166 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2167 micro_mul(&arg[2], &arg[0], &arg[1]);
2168
2169 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2170 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2171 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2172 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2173 }
2174
2175 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2176 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2177 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2178 }
2179 }
2180 }
2181
2182 static void
2183 exec_dp2a(struct tgsi_exec_machine *mach,
2184 const struct tgsi_full_instruction *inst)
2185 {
2186 unsigned int chan;
2187 union tgsi_exec_channel arg[3];
2188
2189 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2190 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2191 micro_mul(&arg[2], &arg[0], &arg[1]);
2192
2193 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2194 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2195 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2196
2197 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2198 micro_add(&arg[0], &arg[0], &arg[1]);
2199
2200 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2201 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2202 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2203 }
2204 }
2205 }
2206
2207 static void
2208 exec_dph(struct tgsi_exec_machine *mach,
2209 const struct tgsi_full_instruction *inst)
2210 {
2211 unsigned int chan;
2212 union tgsi_exec_channel arg[3];
2213
2214 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2215 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2216 micro_mul(&arg[2], &arg[0], &arg[1]);
2217
2218 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2219 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2220 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2221
2222 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2223 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2224 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2225
2226 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2227 micro_add(&arg[0], &arg[0], &arg[1]);
2228
2229 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2230 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2231 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2232 }
2233 }
2234 }
2235
2236 static void
2237 exec_dp2(struct tgsi_exec_machine *mach,
2238 const struct tgsi_full_instruction *inst)
2239 {
2240 unsigned int chan;
2241 union tgsi_exec_channel arg[3];
2242
2243 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2244 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2245 micro_mul(&arg[2], &arg[0], &arg[1]);
2246
2247 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2248 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2249 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2250
2251 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2252 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2253 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2254 }
2255 }
2256 }
2257
2258 static void
2259 exec_nrm4(struct tgsi_exec_machine *mach,
2260 const struct tgsi_full_instruction *inst)
2261 {
2262 unsigned int chan;
2263 union tgsi_exec_channel arg[4];
2264 union tgsi_exec_channel scale;
2265
2266 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2267 micro_mul(&scale, &arg[0], &arg[0]);
2268
2269 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2270 union tgsi_exec_channel product;
2271
2272 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2273 micro_mul(&product, &arg[chan], &arg[chan]);
2274 micro_add(&scale, &scale, &product);
2275 }
2276
2277 micro_rsq(&scale, &scale);
2278
2279 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2280 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2281 micro_mul(&arg[chan], &arg[chan], &scale);
2282 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2283 }
2284 }
2285 }
2286
2287 static void
2288 exec_nrm3(struct tgsi_exec_machine *mach,
2289 const struct tgsi_full_instruction *inst)
2290 {
2291 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2292 unsigned int chan;
2293 union tgsi_exec_channel arg[3];
2294 union tgsi_exec_channel scale;
2295
2296 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2297 micro_mul(&scale, &arg[0], &arg[0]);
2298
2299 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2300 union tgsi_exec_channel product;
2301
2302 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2303 micro_mul(&product, &arg[chan], &arg[chan]);
2304 micro_add(&scale, &scale, &product);
2305 }
2306
2307 micro_rsq(&scale, &scale);
2308
2309 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2310 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2311 micro_mul(&arg[chan], &arg[chan], &scale);
2312 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2313 }
2314 }
2315 }
2316
2317 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2318 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2319 }
2320 }
2321
2322 static void
2323 exec_break(struct tgsi_exec_machine *mach)
2324 {
2325 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2326 /* turn off loop channels for each enabled exec channel */
2327 mach->LoopMask &= ~mach->ExecMask;
2328 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2329 UPDATE_EXEC_MASK(mach);
2330 } else {
2331 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2332
2333 mach->Switch.mask = 0x0;
2334
2335 UPDATE_EXEC_MASK(mach);
2336 }
2337 }
2338
2339 static void
2340 exec_switch(struct tgsi_exec_machine *mach,
2341 const struct tgsi_full_instruction *inst)
2342 {
2343 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2344 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2345
2346 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2347 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2348 mach->Switch.mask = 0x0;
2349 mach->Switch.defaultMask = 0x0;
2350
2351 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2352 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2353
2354 UPDATE_EXEC_MASK(mach);
2355 }
2356
2357 static void
2358 exec_case(struct tgsi_exec_machine *mach,
2359 const struct tgsi_full_instruction *inst)
2360 {
2361 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2362 union tgsi_exec_channel src;
2363 uint mask = 0;
2364
2365 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2366
2367 if (mach->Switch.selector.u[0] == src.u[0]) {
2368 mask |= 0x1;
2369 }
2370 if (mach->Switch.selector.u[1] == src.u[1]) {
2371 mask |= 0x2;
2372 }
2373 if (mach->Switch.selector.u[2] == src.u[2]) {
2374 mask |= 0x4;
2375 }
2376 if (mach->Switch.selector.u[3] == src.u[3]) {
2377 mask |= 0x8;
2378 }
2379
2380 mach->Switch.defaultMask |= mask;
2381
2382 mach->Switch.mask |= mask & prevMask;
2383
2384 UPDATE_EXEC_MASK(mach);
2385 }
2386
2387 static void
2388 exec_default(struct tgsi_exec_machine *mach)
2389 {
2390 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2391
2392 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2393
2394 UPDATE_EXEC_MASK(mach);
2395 }
2396
2397 static void
2398 exec_endswitch(struct tgsi_exec_machine *mach)
2399 {
2400 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2401 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2402
2403 UPDATE_EXEC_MASK(mach);
2404 }
2405
2406 static void
2407 micro_i2f(union tgsi_exec_channel *dst,
2408 const union tgsi_exec_channel *src)
2409 {
2410 dst->f[0] = (float)src->i[0];
2411 dst->f[1] = (float)src->i[1];
2412 dst->f[2] = (float)src->i[2];
2413 dst->f[3] = (float)src->i[3];
2414 }
2415
2416 static void
2417 micro_not(union tgsi_exec_channel *dst,
2418 const union tgsi_exec_channel *src)
2419 {
2420 dst->u[0] = ~src->u[0];
2421 dst->u[1] = ~src->u[1];
2422 dst->u[2] = ~src->u[2];
2423 dst->u[3] = ~src->u[3];
2424 }
2425
2426 static void
2427 micro_shl(union tgsi_exec_channel *dst,
2428 const union tgsi_exec_channel *src0,
2429 const union tgsi_exec_channel *src1)
2430 {
2431 dst->u[0] = src0->u[0] << src1->u[0];
2432 dst->u[1] = src0->u[1] << src1->u[1];
2433 dst->u[2] = src0->u[2] << src1->u[2];
2434 dst->u[3] = src0->u[3] << src1->u[3];
2435 }
2436
2437 static void
2438 micro_and(union tgsi_exec_channel *dst,
2439 const union tgsi_exec_channel *src0,
2440 const union tgsi_exec_channel *src1)
2441 {
2442 dst->u[0] = src0->u[0] & src1->u[0];
2443 dst->u[1] = src0->u[1] & src1->u[1];
2444 dst->u[2] = src0->u[2] & src1->u[2];
2445 dst->u[3] = src0->u[3] & src1->u[3];
2446 }
2447
2448 static void
2449 micro_or(union tgsi_exec_channel *dst,
2450 const union tgsi_exec_channel *src0,
2451 const union tgsi_exec_channel *src1)
2452 {
2453 dst->u[0] = src0->u[0] | src1->u[0];
2454 dst->u[1] = src0->u[1] | src1->u[1];
2455 dst->u[2] = src0->u[2] | src1->u[2];
2456 dst->u[3] = src0->u[3] | src1->u[3];
2457 }
2458
2459 static void
2460 micro_xor(union tgsi_exec_channel *dst,
2461 const union tgsi_exec_channel *src0,
2462 const union tgsi_exec_channel *src1)
2463 {
2464 dst->u[0] = src0->u[0] ^ src1->u[0];
2465 dst->u[1] = src0->u[1] ^ src1->u[1];
2466 dst->u[2] = src0->u[2] ^ src1->u[2];
2467 dst->u[3] = src0->u[3] ^ src1->u[3];
2468 }
2469
2470 static void
2471 micro_f2i(union tgsi_exec_channel *dst,
2472 const union tgsi_exec_channel *src)
2473 {
2474 dst->i[0] = (int)src->f[0];
2475 dst->i[1] = (int)src->f[1];
2476 dst->i[2] = (int)src->f[2];
2477 dst->i[3] = (int)src->f[3];
2478 }
2479
2480 static void
2481 micro_idiv(union tgsi_exec_channel *dst,
2482 const union tgsi_exec_channel *src0,
2483 const union tgsi_exec_channel *src1)
2484 {
2485 dst->i[0] = src0->i[0] / src1->i[0];
2486 dst->i[1] = src0->i[1] / src1->i[1];
2487 dst->i[2] = src0->i[2] / src1->i[2];
2488 dst->i[3] = src0->i[3] / src1->i[3];
2489 }
2490
2491 static void
2492 micro_imax(union tgsi_exec_channel *dst,
2493 const union tgsi_exec_channel *src0,
2494 const union tgsi_exec_channel *src1)
2495 {
2496 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
2497 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
2498 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
2499 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
2500 }
2501
2502 static void
2503 micro_imin(union tgsi_exec_channel *dst,
2504 const union tgsi_exec_channel *src0,
2505 const union tgsi_exec_channel *src1)
2506 {
2507 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
2508 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
2509 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
2510 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
2511 }
2512
2513 static void
2514 micro_isge(union tgsi_exec_channel *dst,
2515 const union tgsi_exec_channel *src0,
2516 const union tgsi_exec_channel *src1)
2517 {
2518 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
2519 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
2520 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
2521 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
2522 }
2523
2524 static void
2525 micro_ishr(union tgsi_exec_channel *dst,
2526 const union tgsi_exec_channel *src0,
2527 const union tgsi_exec_channel *src1)
2528 {
2529 dst->i[0] = src0->i[0] >> src1->i[0];
2530 dst->i[1] = src0->i[1] >> src1->i[1];
2531 dst->i[2] = src0->i[2] >> src1->i[2];
2532 dst->i[3] = src0->i[3] >> src1->i[3];
2533 }
2534
2535 static void
2536 micro_islt(union tgsi_exec_channel *dst,
2537 const union tgsi_exec_channel *src0,
2538 const union tgsi_exec_channel *src1)
2539 {
2540 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
2541 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
2542 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
2543 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
2544 }
2545
2546 static void
2547 micro_f2u(union tgsi_exec_channel *dst,
2548 const union tgsi_exec_channel *src)
2549 {
2550 dst->u[0] = (uint)src->f[0];
2551 dst->u[1] = (uint)src->f[1];
2552 dst->u[2] = (uint)src->f[2];
2553 dst->u[3] = (uint)src->f[3];
2554 }
2555
2556 static void
2557 micro_u2f(union tgsi_exec_channel *dst,
2558 const union tgsi_exec_channel *src)
2559 {
2560 dst->f[0] = (float)src->u[0];
2561 dst->f[1] = (float)src->u[1];
2562 dst->f[2] = (float)src->u[2];
2563 dst->f[3] = (float)src->u[3];
2564 }
2565
2566 static void
2567 micro_uadd(union tgsi_exec_channel *dst,
2568 const union tgsi_exec_channel *src0,
2569 const union tgsi_exec_channel *src1)
2570 {
2571 dst->u[0] = src0->u[0] + src1->u[0];
2572 dst->u[1] = src0->u[1] + src1->u[1];
2573 dst->u[2] = src0->u[2] + src1->u[2];
2574 dst->u[3] = src0->u[3] + src1->u[3];
2575 }
2576
2577 static void
2578 micro_udiv(union tgsi_exec_channel *dst,
2579 const union tgsi_exec_channel *src0,
2580 const union tgsi_exec_channel *src1)
2581 {
2582 dst->u[0] = src0->u[0] / src1->u[0];
2583 dst->u[1] = src0->u[1] / src1->u[1];
2584 dst->u[2] = src0->u[2] / src1->u[2];
2585 dst->u[3] = src0->u[3] / src1->u[3];
2586 }
2587
2588 static void
2589 micro_umad(union tgsi_exec_channel *dst,
2590 const union tgsi_exec_channel *src0,
2591 const union tgsi_exec_channel *src1,
2592 const union tgsi_exec_channel *src2)
2593 {
2594 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
2595 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
2596 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
2597 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
2598 }
2599
2600 static void
2601 micro_umax(union tgsi_exec_channel *dst,
2602 const union tgsi_exec_channel *src0,
2603 const union tgsi_exec_channel *src1)
2604 {
2605 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
2606 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
2607 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
2608 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
2609 }
2610
2611 static void
2612 micro_umin(union tgsi_exec_channel *dst,
2613 const union tgsi_exec_channel *src0,
2614 const union tgsi_exec_channel *src1)
2615 {
2616 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
2617 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
2618 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
2619 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
2620 }
2621
2622 static void
2623 micro_umod(union tgsi_exec_channel *dst,
2624 const union tgsi_exec_channel *src0,
2625 const union tgsi_exec_channel *src1)
2626 {
2627 dst->u[0] = src0->u[0] % src1->u[0];
2628 dst->u[1] = src0->u[1] % src1->u[1];
2629 dst->u[2] = src0->u[2] % src1->u[2];
2630 dst->u[3] = src0->u[3] % src1->u[3];
2631 }
2632
2633 static void
2634 micro_umul(union tgsi_exec_channel *dst,
2635 const union tgsi_exec_channel *src0,
2636 const union tgsi_exec_channel *src1)
2637 {
2638 dst->u[0] = src0->u[0] * src1->u[0];
2639 dst->u[1] = src0->u[1] * src1->u[1];
2640 dst->u[2] = src0->u[2] * src1->u[2];
2641 dst->u[3] = src0->u[3] * src1->u[3];
2642 }
2643
2644 static void
2645 micro_useq(union tgsi_exec_channel *dst,
2646 const union tgsi_exec_channel *src0,
2647 const union tgsi_exec_channel *src1)
2648 {
2649 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
2650 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
2651 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
2652 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
2653 }
2654
2655 static void
2656 micro_usge(union tgsi_exec_channel *dst,
2657 const union tgsi_exec_channel *src0,
2658 const union tgsi_exec_channel *src1)
2659 {
2660 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
2661 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
2662 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
2663 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
2664 }
2665
2666 static void
2667 micro_ushr(union tgsi_exec_channel *dst,
2668 const union tgsi_exec_channel *src0,
2669 const union tgsi_exec_channel *src1)
2670 {
2671 dst->u[0] = src0->u[0] >> src1->u[0];
2672 dst->u[1] = src0->u[1] >> src1->u[1];
2673 dst->u[2] = src0->u[2] >> src1->u[2];
2674 dst->u[3] = src0->u[3] >> src1->u[3];
2675 }
2676
2677 static void
2678 micro_uslt(union tgsi_exec_channel *dst,
2679 const union tgsi_exec_channel *src0,
2680 const union tgsi_exec_channel *src1)
2681 {
2682 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
2683 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
2684 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
2685 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
2686 }
2687
2688 static void
2689 micro_usne(union tgsi_exec_channel *dst,
2690 const union tgsi_exec_channel *src0,
2691 const union tgsi_exec_channel *src1)
2692 {
2693 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
2694 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
2695 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
2696 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
2697 }
2698
2699 static void
2700 exec_instruction(
2701 struct tgsi_exec_machine *mach,
2702 const struct tgsi_full_instruction *inst,
2703 int *pc )
2704 {
2705 uint chan_index;
2706 union tgsi_exec_channel r[10];
2707 union tgsi_exec_channel d[8];
2708
2709 (*pc)++;
2710
2711 switch (inst->Instruction.Opcode) {
2712 case TGSI_OPCODE_ARL:
2713 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2714 break;
2715
2716 case TGSI_OPCODE_MOV:
2717 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
2718 break;
2719
2720 case TGSI_OPCODE_LIT:
2721 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2722 FETCH( &r[0], 0, CHAN_X );
2723 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2724 micro_max(&d[CHAN_Y], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2725 }
2726
2727 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2728 FETCH( &r[1], 0, CHAN_Y );
2729 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2730
2731 FETCH( &r[2], 0, CHAN_W );
2732 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
2733 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
2734 micro_pow( &r[1], &r[1], &r[2] );
2735 micro_lt(&d[CHAN_Z], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2736 }
2737
2738 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2739 STORE(&d[CHAN_Y], 0, CHAN_Y);
2740 }
2741 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2742 STORE(&d[CHAN_Z], 0, CHAN_Z);
2743 }
2744 }
2745 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2746 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
2747 }
2748 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2749 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2750 }
2751 break;
2752
2753 case TGSI_OPCODE_RCP:
2754 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2755 break;
2756
2757 case TGSI_OPCODE_RSQ:
2758 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2759 break;
2760
2761 case TGSI_OPCODE_EXP:
2762 FETCH( &r[0], 0, CHAN_X );
2763 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
2764 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2765 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
2766 STORE( &r[2], 0, CHAN_X ); /* store r2 */
2767 }
2768 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2769 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
2770 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
2771 }
2772 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2773 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
2774 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
2775 }
2776 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2777 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2778 }
2779 break;
2780
2781 case TGSI_OPCODE_LOG:
2782 FETCH( &r[0], 0, CHAN_X );
2783 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
2784 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
2785 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
2786 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2787 STORE( &r[0], 0, CHAN_X );
2788 }
2789 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2790 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
2791 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
2792 STORE( &r[0], 0, CHAN_Y );
2793 }
2794 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2795 STORE( &r[1], 0, CHAN_Z );
2796 }
2797 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2798 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2799 }
2800 break;
2801
2802 case TGSI_OPCODE_MUL:
2803 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2804 break;
2805
2806 case TGSI_OPCODE_ADD:
2807 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2808 break;
2809
2810 case TGSI_OPCODE_DP3:
2811 exec_dp3(mach, inst);
2812 break;
2813
2814 case TGSI_OPCODE_DP4:
2815 exec_dp4(mach, inst);
2816 break;
2817
2818 case TGSI_OPCODE_DST:
2819 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2820 FETCH( &r[0], 0, CHAN_Y );
2821 FETCH( &r[1], 1, CHAN_Y);
2822 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2823 }
2824 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2825 FETCH(&d[CHAN_Z], 0, CHAN_Z);
2826 }
2827 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2828 FETCH(&d[CHAN_W], 1, CHAN_W);
2829 }
2830
2831 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2832 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X);
2833 }
2834 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2835 STORE(&d[CHAN_Y], 0, CHAN_Y);
2836 }
2837 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2838 STORE(&d[CHAN_Z], 0, CHAN_Z);
2839 }
2840 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2841 STORE(&d[CHAN_W], 0, CHAN_W);
2842 }
2843 break;
2844
2845 case TGSI_OPCODE_MIN:
2846 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2847 break;
2848
2849 case TGSI_OPCODE_MAX:
2850 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2851 break;
2852
2853 case TGSI_OPCODE_SLT:
2854 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2855 break;
2856
2857 case TGSI_OPCODE_SGE:
2858 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2859 break;
2860
2861 case TGSI_OPCODE_MAD:
2862 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2863 break;
2864
2865 case TGSI_OPCODE_SUB:
2866 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2867 break;
2868
2869 case TGSI_OPCODE_LRP:
2870 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2871 break;
2872
2873 case TGSI_OPCODE_CND:
2874 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2875 break;
2876
2877 case TGSI_OPCODE_DP2A:
2878 exec_dp2a(mach, inst);
2879 break;
2880
2881 case TGSI_OPCODE_FRC:
2882 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2883 break;
2884
2885 case TGSI_OPCODE_CLAMP:
2886 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2887 break;
2888
2889 case TGSI_OPCODE_FLR:
2890 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2891 break;
2892
2893 case TGSI_OPCODE_ROUND:
2894 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2895 break;
2896
2897 case TGSI_OPCODE_EX2:
2898 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2899 break;
2900
2901 case TGSI_OPCODE_LG2:
2902 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2903 break;
2904
2905 case TGSI_OPCODE_POW:
2906 FETCH(&r[0], 0, CHAN_X);
2907 FETCH(&r[1], 1, CHAN_X);
2908
2909 micro_pow( &r[0], &r[0], &r[1] );
2910
2911 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2912 STORE( &r[0], 0, chan_index );
2913 }
2914 break;
2915
2916 case TGSI_OPCODE_XPD:
2917 FETCH(&r[0], 0, CHAN_Y);
2918 FETCH(&r[1], 1, CHAN_Z);
2919
2920 micro_mul( &r[2], &r[0], &r[1] );
2921
2922 FETCH(&r[3], 0, CHAN_Z);
2923 FETCH(&r[4], 1, CHAN_Y);
2924
2925 micro_mul( &r[5], &r[3], &r[4] );
2926 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2927
2928 FETCH(&r[2], 1, CHAN_X);
2929
2930 micro_mul( &r[3], &r[3], &r[2] );
2931
2932 FETCH(&r[5], 0, CHAN_X);
2933
2934 micro_mul( &r[1], &r[1], &r[5] );
2935 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2936
2937 micro_mul( &r[5], &r[5], &r[4] );
2938 micro_mul( &r[0], &r[0], &r[2] );
2939 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2940
2941 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2942 STORE(&d[CHAN_X], 0, CHAN_X);
2943 }
2944 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2945 STORE(&d[CHAN_Y], 0, CHAN_Y);
2946 }
2947 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2948 STORE(&d[CHAN_Z], 0, CHAN_Z);
2949 }
2950 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2951 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2952 }
2953 break;
2954
2955 case TGSI_OPCODE_ABS:
2956 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2957 break;
2958
2959 case TGSI_OPCODE_RCC:
2960 FETCH(&r[0], 0, CHAN_X);
2961 micro_div(&r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0]);
2962 micro_float_clamp(&r[0], &r[0]);
2963 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2964 STORE(&r[0], 0, chan_index);
2965 }
2966 break;
2967
2968 case TGSI_OPCODE_DPH:
2969 exec_dph(mach, inst);
2970 break;
2971
2972 case TGSI_OPCODE_COS:
2973 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2974 break;
2975
2976 case TGSI_OPCODE_DDX:
2977 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2978 break;
2979
2980 case TGSI_OPCODE_DDY:
2981 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2982 break;
2983
2984 case TGSI_OPCODE_KILP:
2985 exec_kilp (mach, inst);
2986 break;
2987
2988 case TGSI_OPCODE_KIL:
2989 exec_kil (mach, inst);
2990 break;
2991
2992 case TGSI_OPCODE_PK2H:
2993 assert (0);
2994 break;
2995
2996 case TGSI_OPCODE_PK2US:
2997 assert (0);
2998 break;
2999
3000 case TGSI_OPCODE_PK4B:
3001 assert (0);
3002 break;
3003
3004 case TGSI_OPCODE_PK4UB:
3005 assert (0);
3006 break;
3007
3008 case TGSI_OPCODE_RFL:
3009 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
3010 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
3011 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3012 /* r0 = dp3(src0, src0) */
3013 FETCH(&r[2], 0, CHAN_X);
3014 micro_mul(&r[0], &r[2], &r[2]);
3015 FETCH(&r[4], 0, CHAN_Y);
3016 micro_mul(&r[8], &r[4], &r[4]);
3017 micro_add(&r[0], &r[0], &r[8]);
3018 FETCH(&r[6], 0, CHAN_Z);
3019 micro_mul(&r[8], &r[6], &r[6]);
3020 micro_add(&r[0], &r[0], &r[8]);
3021
3022 /* r1 = dp3(src0, src1) */
3023 FETCH(&r[3], 1, CHAN_X);
3024 micro_mul(&r[1], &r[2], &r[3]);
3025 FETCH(&r[5], 1, CHAN_Y);
3026 micro_mul(&r[8], &r[4], &r[5]);
3027 micro_add(&r[1], &r[1], &r[8]);
3028 FETCH(&r[7], 1, CHAN_Z);
3029 micro_mul(&r[8], &r[6], &r[7]);
3030 micro_add(&r[1], &r[1], &r[8]);
3031
3032 /* r1 = 2 * r1 / r0 */
3033 micro_add(&r[1], &r[1], &r[1]);
3034 micro_div(&r[1], &r[1], &r[0]);
3035
3036 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3037 micro_mul(&r[2], &r[2], &r[1]);
3038 micro_sub(&r[2], &r[2], &r[3]);
3039 STORE(&r[2], 0, CHAN_X);
3040 }
3041 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3042 micro_mul(&r[4], &r[4], &r[1]);
3043 micro_sub(&r[4], &r[4], &r[5]);
3044 STORE(&r[4], 0, CHAN_Y);
3045 }
3046 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3047 micro_mul(&r[6], &r[6], &r[1]);
3048 micro_sub(&r[6], &r[6], &r[7]);
3049 STORE(&r[6], 0, CHAN_Z);
3050 }
3051 }
3052 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
3053 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
3054 }
3055 break;
3056
3057 case TGSI_OPCODE_SEQ:
3058 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3059 break;
3060
3061 case TGSI_OPCODE_SFL:
3062 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3063 STORE(&mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, chan_index);
3064 }
3065 break;
3066
3067 case TGSI_OPCODE_SGT:
3068 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3069 break;
3070
3071 case TGSI_OPCODE_SIN:
3072 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3073 break;
3074
3075 case TGSI_OPCODE_SLE:
3076 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3077 break;
3078
3079 case TGSI_OPCODE_SNE:
3080 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3081 break;
3082
3083 case TGSI_OPCODE_STR:
3084 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3085 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, chan_index);
3086 }
3087 break;
3088
3089 case TGSI_OPCODE_TEX:
3090 /* simple texture lookup */
3091 /* src[0] = texcoord */
3092 /* src[1] = sampler unit */
3093 exec_tex(mach, inst, TEX_MODIFIER_NONE);
3094 break;
3095
3096 case TGSI_OPCODE_TXB:
3097 /* Texture lookup with lod bias */
3098 /* src[0] = texcoord (src[0].w = LOD bias) */
3099 /* src[1] = sampler unit */
3100 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
3101 break;
3102
3103 case TGSI_OPCODE_TXD:
3104 /* Texture lookup with explict partial derivatives */
3105 /* src[0] = texcoord */
3106 /* src[1] = d[strq]/dx */
3107 /* src[2] = d[strq]/dy */
3108 /* src[3] = sampler unit */
3109 exec_txd(mach, inst);
3110 break;
3111
3112 case TGSI_OPCODE_TXL:
3113 /* Texture lookup with explit LOD */
3114 /* src[0] = texcoord (src[0].w = LOD) */
3115 /* src[1] = sampler unit */
3116 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3117 break;
3118
3119 case TGSI_OPCODE_TXP:
3120 /* Texture lookup with projection */
3121 /* src[0] = texcoord (src[0].w = projection) */
3122 /* src[1] = sampler unit */
3123 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
3124 break;
3125
3126 case TGSI_OPCODE_UP2H:
3127 assert (0);
3128 break;
3129
3130 case TGSI_OPCODE_UP2US:
3131 assert (0);
3132 break;
3133
3134 case TGSI_OPCODE_UP4B:
3135 assert (0);
3136 break;
3137
3138 case TGSI_OPCODE_UP4UB:
3139 assert (0);
3140 break;
3141
3142 case TGSI_OPCODE_X2D:
3143 FETCH(&r[0], 1, CHAN_X);
3144 FETCH(&r[1], 1, CHAN_Y);
3145 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
3146 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3147 FETCH(&r[2], 2, CHAN_X);
3148 micro_mul(&r[2], &r[2], &r[0]);
3149 FETCH(&r[3], 2, CHAN_Y);
3150 micro_mul(&r[3], &r[3], &r[1]);
3151 micro_add(&r[2], &r[2], &r[3]);
3152 FETCH(&r[3], 0, CHAN_X);
3153 micro_add(&d[CHAN_X], &r[2], &r[3]);
3154
3155 }
3156 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
3157 IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
3158 FETCH(&r[2], 2, CHAN_Z);
3159 micro_mul(&r[2], &r[2], &r[0]);
3160 FETCH(&r[3], 2, CHAN_W);
3161 micro_mul(&r[3], &r[3], &r[1]);
3162 micro_add(&r[2], &r[2], &r[3]);
3163 FETCH(&r[3], 0, CHAN_Y);
3164 micro_add(&d[CHAN_Y], &r[2], &r[3]);
3165
3166 }
3167 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3168 STORE(&d[CHAN_X], 0, CHAN_X);
3169 }
3170 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3171 STORE(&d[CHAN_Y], 0, CHAN_Y);
3172 }
3173 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3174 STORE(&d[CHAN_X], 0, CHAN_Z);
3175 }
3176 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
3177 STORE(&d[CHAN_Y], 0, CHAN_W);
3178 }
3179 break;
3180
3181 case TGSI_OPCODE_ARA:
3182 assert (0);
3183 break;
3184
3185 case TGSI_OPCODE_ARR:
3186 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3187 break;
3188
3189 case TGSI_OPCODE_BRA:
3190 assert (0);
3191 break;
3192
3193 case TGSI_OPCODE_CAL:
3194 /* skip the call if no execution channels are enabled */
3195 if (mach->ExecMask) {
3196 /* do the call */
3197
3198 /* First, record the depths of the execution stacks.
3199 * This is important for deeply nested/looped return statements.
3200 * We have to unwind the stacks by the correct amount. For a
3201 * real code generator, we could determine the number of entries
3202 * to pop off each stack with simple static analysis and avoid
3203 * implementing this data structure at run time.
3204 */
3205 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3206 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3207 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3208 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3209 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3210 /* note that PC was already incremented above */
3211 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3212
3213 mach->CallStackTop++;
3214
3215 /* Second, push the Cond, Loop, Cont, Func stacks */
3216 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3217 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3218 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3219 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3220 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3221 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3222
3223 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3224 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3225 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3226 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3227 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3228 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3229
3230 /* Finally, jump to the subroutine */
3231 *pc = inst->Label.Label;
3232 }
3233 break;
3234
3235 case TGSI_OPCODE_RET:
3236 mach->FuncMask &= ~mach->ExecMask;
3237 UPDATE_EXEC_MASK(mach);
3238
3239 if (mach->FuncMask == 0x0) {
3240 /* really return now (otherwise, keep executing */
3241
3242 if (mach->CallStackTop == 0) {
3243 /* returning from main() */
3244 mach->CondStackTop = 0;
3245 mach->LoopStackTop = 0;
3246 *pc = -1;
3247 return;
3248 }
3249
3250 assert(mach->CallStackTop > 0);
3251 mach->CallStackTop--;
3252
3253 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3254 mach->CondMask = mach->CondStack[mach->CondStackTop];
3255
3256 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3257 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3258
3259 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3260 mach->ContMask = mach->ContStack[mach->ContStackTop];
3261
3262 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3263 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3264
3265 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3266 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3267
3268 assert(mach->FuncStackTop > 0);
3269 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3270
3271 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3272
3273 UPDATE_EXEC_MASK(mach);
3274 }
3275 break;
3276
3277 case TGSI_OPCODE_SSG:
3278 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3279 break;
3280
3281 case TGSI_OPCODE_CMP:
3282 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3283 break;
3284
3285 case TGSI_OPCODE_SCS:
3286 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
3287 FETCH( &r[0], 0, CHAN_X );
3288 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3289 micro_cos(&r[1], &r[0]);
3290 STORE(&r[1], 0, CHAN_X);
3291 }
3292 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3293 micro_sin(&r[1], &r[0]);
3294 STORE(&r[1], 0, CHAN_Y);
3295 }
3296 }
3297 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
3298 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
3299 }
3300 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
3301 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
3302 }
3303 break;
3304
3305 case TGSI_OPCODE_NRM:
3306 exec_nrm3(mach, inst);
3307 break;
3308
3309 case TGSI_OPCODE_NRM4:
3310 exec_nrm4(mach, inst);
3311 break;
3312
3313 case TGSI_OPCODE_DIV:
3314 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3315 break;
3316
3317 case TGSI_OPCODE_DP2:
3318 exec_dp2(mach, inst);
3319 break;
3320
3321 case TGSI_OPCODE_IF:
3322 /* push CondMask */
3323 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3324 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3325 FETCH( &r[0], 0, CHAN_X );
3326 /* update CondMask */
3327 if( ! r[0].u[0] ) {
3328 mach->CondMask &= ~0x1;
3329 }
3330 if( ! r[0].u[1] ) {
3331 mach->CondMask &= ~0x2;
3332 }
3333 if( ! r[0].u[2] ) {
3334 mach->CondMask &= ~0x4;
3335 }
3336 if( ! r[0].u[3] ) {
3337 mach->CondMask &= ~0x8;
3338 }
3339 UPDATE_EXEC_MASK(mach);
3340 /* Todo: If CondMask==0, jump to ELSE */
3341 break;
3342
3343 case TGSI_OPCODE_ELSE:
3344 /* invert CondMask wrt previous mask */
3345 {
3346 uint prevMask;
3347 assert(mach->CondStackTop > 0);
3348 prevMask = mach->CondStack[mach->CondStackTop - 1];
3349 mach->CondMask = ~mach->CondMask & prevMask;
3350 UPDATE_EXEC_MASK(mach);
3351 /* Todo: If CondMask==0, jump to ENDIF */
3352 }
3353 break;
3354
3355 case TGSI_OPCODE_ENDIF:
3356 /* pop CondMask */
3357 assert(mach->CondStackTop > 0);
3358 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3359 UPDATE_EXEC_MASK(mach);
3360 break;
3361
3362 case TGSI_OPCODE_END:
3363 /* make sure we end primitives which haven't
3364 * been explicitly emitted */
3365 conditional_emit_primitive(mach);
3366 /* halt execution */
3367 *pc = -1;
3368 break;
3369
3370 case TGSI_OPCODE_PUSHA:
3371 assert (0);
3372 break;
3373
3374 case TGSI_OPCODE_POPA:
3375 assert (0);
3376 break;
3377
3378 case TGSI_OPCODE_CEIL:
3379 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3380 break;
3381
3382 case TGSI_OPCODE_I2F:
3383 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3384 break;
3385
3386 case TGSI_OPCODE_NOT:
3387 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3388 break;
3389
3390 case TGSI_OPCODE_TRUNC:
3391 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3392 break;
3393
3394 case TGSI_OPCODE_SHL:
3395 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3396 break;
3397
3398 case TGSI_OPCODE_AND:
3399 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3400 break;
3401
3402 case TGSI_OPCODE_OR:
3403 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3404 break;
3405
3406 case TGSI_OPCODE_MOD:
3407 assert (0);
3408 break;
3409
3410 case TGSI_OPCODE_XOR:
3411 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3412 break;
3413
3414 case TGSI_OPCODE_SAD:
3415 assert (0);
3416 break;
3417
3418 case TGSI_OPCODE_TXF:
3419 assert (0);
3420 break;
3421
3422 case TGSI_OPCODE_TXQ:
3423 assert (0);
3424 break;
3425
3426 case TGSI_OPCODE_EMIT:
3427 emit_vertex(mach);
3428 break;
3429
3430 case TGSI_OPCODE_ENDPRIM:
3431 emit_primitive(mach);
3432 break;
3433
3434 case TGSI_OPCODE_BGNLOOP:
3435 /* push LoopMask and ContMasks */
3436 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3437 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3438 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3439 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3440
3441 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3442 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3443 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3444 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3445 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3446 break;
3447
3448 case TGSI_OPCODE_ENDLOOP:
3449 /* Restore ContMask, but don't pop */
3450 assert(mach->ContStackTop > 0);
3451 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3452 UPDATE_EXEC_MASK(mach);
3453 if (mach->ExecMask) {
3454 /* repeat loop: jump to instruction just past BGNLOOP */
3455 assert(mach->LoopLabelStackTop > 0);
3456 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3457 }
3458 else {
3459 /* exit loop: pop LoopMask */
3460 assert(mach->LoopStackTop > 0);
3461 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3462 /* pop ContMask */
3463 assert(mach->ContStackTop > 0);
3464 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3465 assert(mach->LoopLabelStackTop > 0);
3466 --mach->LoopLabelStackTop;
3467
3468 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3469 }
3470 UPDATE_EXEC_MASK(mach);
3471 break;
3472
3473 case TGSI_OPCODE_BRK:
3474 exec_break(mach);
3475 break;
3476
3477 case TGSI_OPCODE_CONT:
3478 /* turn off cont channels for each enabled exec channel */
3479 mach->ContMask &= ~mach->ExecMask;
3480 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3481 UPDATE_EXEC_MASK(mach);
3482 break;
3483
3484 case TGSI_OPCODE_BGNSUB:
3485 /* no-op */
3486 break;
3487
3488 case TGSI_OPCODE_ENDSUB:
3489 /*
3490 * XXX: This really should be a no-op. We should never reach this opcode.
3491 */
3492
3493 assert(mach->CallStackTop > 0);
3494 mach->CallStackTop--;
3495
3496 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3497 mach->CondMask = mach->CondStack[mach->CondStackTop];
3498
3499 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3500 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3501
3502 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3503 mach->ContMask = mach->ContStack[mach->ContStackTop];
3504
3505 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3506 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3507
3508 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3509 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3510
3511 assert(mach->FuncStackTop > 0);
3512 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3513
3514 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3515
3516 UPDATE_EXEC_MASK(mach);
3517 break;
3518
3519 case TGSI_OPCODE_NOP:
3520 break;
3521
3522 case TGSI_OPCODE_BREAKC:
3523 FETCH(&r[0], 0, CHAN_X);
3524 /* update CondMask */
3525 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3526 mach->LoopMask &= ~0x1;
3527 }
3528 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3529 mach->LoopMask &= ~0x2;
3530 }
3531 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3532 mach->LoopMask &= ~0x4;
3533 }
3534 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3535 mach->LoopMask &= ~0x8;
3536 }
3537 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3538 UPDATE_EXEC_MASK(mach);
3539 break;
3540
3541 case TGSI_OPCODE_F2I:
3542 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3543 break;
3544
3545 case TGSI_OPCODE_IDIV:
3546 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3547 break;
3548
3549 case TGSI_OPCODE_IMAX:
3550 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3551 break;
3552
3553 case TGSI_OPCODE_IMIN:
3554 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3555 break;
3556
3557 case TGSI_OPCODE_INEG:
3558 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3559 break;
3560
3561 case TGSI_OPCODE_ISGE:
3562 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3563 break;
3564
3565 case TGSI_OPCODE_ISHR:
3566 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3567 break;
3568
3569 case TGSI_OPCODE_ISLT:
3570 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3571 break;
3572
3573 case TGSI_OPCODE_F2U:
3574 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3575 break;
3576
3577 case TGSI_OPCODE_U2F:
3578 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
3579 break;
3580
3581 case TGSI_OPCODE_UADD:
3582 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3583 break;
3584
3585 case TGSI_OPCODE_UDIV:
3586 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3587 break;
3588
3589 case TGSI_OPCODE_UMAD:
3590 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3591 break;
3592
3593 case TGSI_OPCODE_UMAX:
3594 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3595 break;
3596
3597 case TGSI_OPCODE_UMIN:
3598 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3599 break;
3600
3601 case TGSI_OPCODE_UMOD:
3602 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3603 break;
3604
3605 case TGSI_OPCODE_UMUL:
3606 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3607 break;
3608
3609 case TGSI_OPCODE_USEQ:
3610 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3611 break;
3612
3613 case TGSI_OPCODE_USGE:
3614 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3615 break;
3616
3617 case TGSI_OPCODE_USHR:
3618 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3619 break;
3620
3621 case TGSI_OPCODE_USLT:
3622 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3623 break;
3624
3625 case TGSI_OPCODE_USNE:
3626 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3627 break;
3628
3629 case TGSI_OPCODE_SWITCH:
3630 exec_switch(mach, inst);
3631 break;
3632
3633 case TGSI_OPCODE_CASE:
3634 exec_case(mach, inst);
3635 break;
3636
3637 case TGSI_OPCODE_DEFAULT:
3638 exec_default(mach);
3639 break;
3640
3641 case TGSI_OPCODE_ENDSWITCH:
3642 exec_endswitch(mach);
3643 break;
3644
3645 default:
3646 assert( 0 );
3647 }
3648 }
3649
3650
3651 #define DEBUG_EXECUTION 0
3652
3653
3654 /**
3655 * Run TGSI interpreter.
3656 * \return bitmask of "alive" quad components
3657 */
3658 uint
3659 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3660 {
3661 uint i;
3662 int pc = 0;
3663
3664 mach->CondMask = 0xf;
3665 mach->LoopMask = 0xf;
3666 mach->ContMask = 0xf;
3667 mach->FuncMask = 0xf;
3668 mach->ExecMask = 0xf;
3669
3670 mach->Switch.mask = 0xf;
3671
3672 assert(mach->CondStackTop == 0);
3673 assert(mach->LoopStackTop == 0);
3674 assert(mach->ContStackTop == 0);
3675 assert(mach->SwitchStackTop == 0);
3676 assert(mach->BreakStackTop == 0);
3677 assert(mach->CallStackTop == 0);
3678
3679 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3680 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3681
3682 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3683 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3684 mach->Primitives[0] = 0;
3685 }
3686
3687 for (i = 0; i < QUAD_SIZE; i++) {
3688 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
3689 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
3690 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
3691 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
3692 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
3693 }
3694
3695 /* execute declarations (interpolants) */
3696 for (i = 0; i < mach->NumDeclarations; i++) {
3697 exec_declaration( mach, mach->Declarations+i );
3698 }
3699
3700 {
3701 #if DEBUG_EXECUTION
3702 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
3703 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
3704 uint inst = 1;
3705
3706 memcpy(temps, mach->Temps, sizeof(temps));
3707 memcpy(outputs, mach->Outputs, sizeof(outputs));
3708 #endif
3709
3710 /* execute instructions, until pc is set to -1 */
3711 while (pc != -1) {
3712
3713 #if DEBUG_EXECUTION
3714 uint i;
3715
3716 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
3717 #endif
3718
3719 assert(pc < (int) mach->NumInstructions);
3720 exec_instruction(mach, mach->Instructions + pc, &pc);
3721
3722 #if DEBUG_EXECUTION
3723 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
3724 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
3725 uint j;
3726
3727 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
3728 debug_printf("TEMP[%2u] = ", i);
3729 for (j = 0; j < 4; j++) {
3730 if (j > 0) {
3731 debug_printf(" ");
3732 }
3733 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3734 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
3735 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
3736 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
3737 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
3738 }
3739 }
3740 }
3741 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
3742 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
3743 uint j;
3744
3745 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
3746 debug_printf("OUT[%2u] = ", i);
3747 for (j = 0; j < 4; j++) {
3748 if (j > 0) {
3749 debug_printf(" ");
3750 }
3751 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3752 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
3753 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
3754 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
3755 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
3756 }
3757 }
3758 }
3759 #endif
3760 }
3761 }
3762
3763 #if 0
3764 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3765 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3766 /*
3767 * Scale back depth component.
3768 */
3769 for (i = 0; i < 4; i++)
3770 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3771 }
3772 #endif
3773
3774 /* Strictly speaking, these assertions aren't really needed but they
3775 * can potentially catch some bugs in the control flow code.
3776 */
3777 assert(mach->CondStackTop == 0);
3778 assert(mach->LoopStackTop == 0);
3779 assert(mach->ContStackTop == 0);
3780 assert(mach->SwitchStackTop == 0);
3781 assert(mach->BreakStackTop == 0);
3782 assert(mach->CallStackTop == 0);
3783
3784 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3785 }