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tgsi/exec: implement load/store/atomic on MEMORY.
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64
65
66 #define DEBUG_EXECUTION 0
67
68
69 #define FAST_MATH 0
70
71 #define TILE_TOP_LEFT 0
72 #define TILE_TOP_RIGHT 1
73 #define TILE_BOTTOM_LEFT 2
74 #define TILE_BOTTOM_RIGHT 3
75
76 union tgsi_double_channel {
77 double d[TGSI_QUAD_SIZE];
78 unsigned u[TGSI_QUAD_SIZE][2];
79 };
80
81 struct tgsi_double_vector {
82 union tgsi_double_channel xy;
83 union tgsi_double_channel zw;
84 };
85
86 static void
87 micro_abs(union tgsi_exec_channel *dst,
88 const union tgsi_exec_channel *src)
89 {
90 dst->f[0] = fabsf(src->f[0]);
91 dst->f[1] = fabsf(src->f[1]);
92 dst->f[2] = fabsf(src->f[2]);
93 dst->f[3] = fabsf(src->f[3]);
94 }
95
96 static void
97 micro_arl(union tgsi_exec_channel *dst,
98 const union tgsi_exec_channel *src)
99 {
100 dst->i[0] = (int)floorf(src->f[0]);
101 dst->i[1] = (int)floorf(src->f[1]);
102 dst->i[2] = (int)floorf(src->f[2]);
103 dst->i[3] = (int)floorf(src->f[3]);
104 }
105
106 static void
107 micro_arr(union tgsi_exec_channel *dst,
108 const union tgsi_exec_channel *src)
109 {
110 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
111 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
112 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
113 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
114 }
115
116 static void
117 micro_ceil(union tgsi_exec_channel *dst,
118 const union tgsi_exec_channel *src)
119 {
120 dst->f[0] = ceilf(src->f[0]);
121 dst->f[1] = ceilf(src->f[1]);
122 dst->f[2] = ceilf(src->f[2]);
123 dst->f[3] = ceilf(src->f[3]);
124 }
125
126 static void
127 micro_clamp(union tgsi_exec_channel *dst,
128 const union tgsi_exec_channel *src0,
129 const union tgsi_exec_channel *src1,
130 const union tgsi_exec_channel *src2)
131 {
132 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
133 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
134 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
135 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
136 }
137
138 static void
139 micro_cmp(union tgsi_exec_channel *dst,
140 const union tgsi_exec_channel *src0,
141 const union tgsi_exec_channel *src1,
142 const union tgsi_exec_channel *src2)
143 {
144 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
145 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
146 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
147 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
148 }
149
150 static void
151 micro_cos(union tgsi_exec_channel *dst,
152 const union tgsi_exec_channel *src)
153 {
154 dst->f[0] = cosf(src->f[0]);
155 dst->f[1] = cosf(src->f[1]);
156 dst->f[2] = cosf(src->f[2]);
157 dst->f[3] = cosf(src->f[3]);
158 }
159
160 static void
161 micro_d2f(union tgsi_exec_channel *dst,
162 const union tgsi_double_channel *src)
163 {
164 dst->f[0] = (float)src->d[0];
165 dst->f[1] = (float)src->d[1];
166 dst->f[2] = (float)src->d[2];
167 dst->f[3] = (float)src->d[3];
168 }
169
170 static void
171 micro_d2i(union tgsi_exec_channel *dst,
172 const union tgsi_double_channel *src)
173 {
174 dst->i[0] = (int)src->d[0];
175 dst->i[1] = (int)src->d[1];
176 dst->i[2] = (int)src->d[2];
177 dst->i[3] = (int)src->d[3];
178 }
179
180 static void
181 micro_d2u(union tgsi_exec_channel *dst,
182 const union tgsi_double_channel *src)
183 {
184 dst->u[0] = (unsigned)src->d[0];
185 dst->u[1] = (unsigned)src->d[1];
186 dst->u[2] = (unsigned)src->d[2];
187 dst->u[3] = (unsigned)src->d[3];
188 }
189 static void
190 micro_dabs(union tgsi_double_channel *dst,
191 const union tgsi_double_channel *src)
192 {
193 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
194 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
195 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
196 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
197 }
198
199 static void
200 micro_dadd(union tgsi_double_channel *dst,
201 const union tgsi_double_channel *src)
202 {
203 dst->d[0] = src[0].d[0] + src[1].d[0];
204 dst->d[1] = src[0].d[1] + src[1].d[1];
205 dst->d[2] = src[0].d[2] + src[1].d[2];
206 dst->d[3] = src[0].d[3] + src[1].d[3];
207 }
208
209 static void
210 micro_ddx(union tgsi_exec_channel *dst,
211 const union tgsi_exec_channel *src)
212 {
213 dst->f[0] =
214 dst->f[1] =
215 dst->f[2] =
216 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
217 }
218
219 static void
220 micro_ddy(union tgsi_exec_channel *dst,
221 const union tgsi_exec_channel *src)
222 {
223 dst->f[0] =
224 dst->f[1] =
225 dst->f[2] =
226 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
227 }
228
229 static void
230 micro_dmul(union tgsi_double_channel *dst,
231 const union tgsi_double_channel *src)
232 {
233 dst->d[0] = src[0].d[0] * src[1].d[0];
234 dst->d[1] = src[0].d[1] * src[1].d[1];
235 dst->d[2] = src[0].d[2] * src[1].d[2];
236 dst->d[3] = src[0].d[3] * src[1].d[3];
237 }
238
239 static void
240 micro_dmax(union tgsi_double_channel *dst,
241 const union tgsi_double_channel *src)
242 {
243 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
244 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
245 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
246 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
247 }
248
249 static void
250 micro_dmin(union tgsi_double_channel *dst,
251 const union tgsi_double_channel *src)
252 {
253 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
254 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
255 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
256 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
257 }
258
259 static void
260 micro_dneg(union tgsi_double_channel *dst,
261 const union tgsi_double_channel *src)
262 {
263 dst->d[0] = -src->d[0];
264 dst->d[1] = -src->d[1];
265 dst->d[2] = -src->d[2];
266 dst->d[3] = -src->d[3];
267 }
268
269 static void
270 micro_dslt(union tgsi_double_channel *dst,
271 const union tgsi_double_channel *src)
272 {
273 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
274 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
275 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
276 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
277 }
278
279 static void
280 micro_dsne(union tgsi_double_channel *dst,
281 const union tgsi_double_channel *src)
282 {
283 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
284 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
285 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
286 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
287 }
288
289 static void
290 micro_dsge(union tgsi_double_channel *dst,
291 const union tgsi_double_channel *src)
292 {
293 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
294 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
295 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
296 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
297 }
298
299 static void
300 micro_dseq(union tgsi_double_channel *dst,
301 const union tgsi_double_channel *src)
302 {
303 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
304 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
305 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
306 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
307 }
308
309 static void
310 micro_drcp(union tgsi_double_channel *dst,
311 const union tgsi_double_channel *src)
312 {
313 dst->d[0] = 1.0 / src->d[0];
314 dst->d[1] = 1.0 / src->d[1];
315 dst->d[2] = 1.0 / src->d[2];
316 dst->d[3] = 1.0 / src->d[3];
317 }
318
319 static void
320 micro_dsqrt(union tgsi_double_channel *dst,
321 const union tgsi_double_channel *src)
322 {
323 dst->d[0] = sqrt(src->d[0]);
324 dst->d[1] = sqrt(src->d[1]);
325 dst->d[2] = sqrt(src->d[2]);
326 dst->d[3] = sqrt(src->d[3]);
327 }
328
329 static void
330 micro_drsq(union tgsi_double_channel *dst,
331 const union tgsi_double_channel *src)
332 {
333 dst->d[0] = 1.0 / sqrt(src->d[0]);
334 dst->d[1] = 1.0 / sqrt(src->d[1]);
335 dst->d[2] = 1.0 / sqrt(src->d[2]);
336 dst->d[3] = 1.0 / sqrt(src->d[3]);
337 }
338
339 static void
340 micro_dmad(union tgsi_double_channel *dst,
341 const union tgsi_double_channel *src)
342 {
343 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
344 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
345 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
346 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
347 }
348
349 static void
350 micro_dfrac(union tgsi_double_channel *dst,
351 const union tgsi_double_channel *src)
352 {
353 dst->d[0] = src->d[0] - floor(src->d[0]);
354 dst->d[1] = src->d[1] - floor(src->d[1]);
355 dst->d[2] = src->d[2] - floor(src->d[2]);
356 dst->d[3] = src->d[3] - floor(src->d[3]);
357 }
358
359 static void
360 micro_dldexp(union tgsi_double_channel *dst,
361 const union tgsi_double_channel *src0,
362 union tgsi_exec_channel *src1)
363 {
364 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
365 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
366 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
367 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
368 }
369
370 static void
371 micro_dfracexp(union tgsi_double_channel *dst,
372 union tgsi_exec_channel *dst_exp,
373 const union tgsi_double_channel *src)
374 {
375 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
376 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
377 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
378 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
379 }
380
381 static void
382 micro_exp2(union tgsi_exec_channel *dst,
383 const union tgsi_exec_channel *src)
384 {
385 #if FAST_MATH
386 dst->f[0] = util_fast_exp2(src->f[0]);
387 dst->f[1] = util_fast_exp2(src->f[1]);
388 dst->f[2] = util_fast_exp2(src->f[2]);
389 dst->f[3] = util_fast_exp2(src->f[3]);
390 #else
391 #if DEBUG
392 /* Inf is okay for this instruction, so clamp it to silence assertions. */
393 uint i;
394 union tgsi_exec_channel clamped;
395
396 for (i = 0; i < 4; i++) {
397 if (src->f[i] > 127.99999f) {
398 clamped.f[i] = 127.99999f;
399 } else if (src->f[i] < -126.99999f) {
400 clamped.f[i] = -126.99999f;
401 } else {
402 clamped.f[i] = src->f[i];
403 }
404 }
405 src = &clamped;
406 #endif /* DEBUG */
407
408 dst->f[0] = powf(2.0f, src->f[0]);
409 dst->f[1] = powf(2.0f, src->f[1]);
410 dst->f[2] = powf(2.0f, src->f[2]);
411 dst->f[3] = powf(2.0f, src->f[3]);
412 #endif /* FAST_MATH */
413 }
414
415 static void
416 micro_f2d(union tgsi_double_channel *dst,
417 const union tgsi_exec_channel *src)
418 {
419 dst->d[0] = (double)src->f[0];
420 dst->d[1] = (double)src->f[1];
421 dst->d[2] = (double)src->f[2];
422 dst->d[3] = (double)src->f[3];
423 }
424
425 static void
426 micro_flr(union tgsi_exec_channel *dst,
427 const union tgsi_exec_channel *src)
428 {
429 dst->f[0] = floorf(src->f[0]);
430 dst->f[1] = floorf(src->f[1]);
431 dst->f[2] = floorf(src->f[2]);
432 dst->f[3] = floorf(src->f[3]);
433 }
434
435 static void
436 micro_frc(union tgsi_exec_channel *dst,
437 const union tgsi_exec_channel *src)
438 {
439 dst->f[0] = src->f[0] - floorf(src->f[0]);
440 dst->f[1] = src->f[1] - floorf(src->f[1]);
441 dst->f[2] = src->f[2] - floorf(src->f[2]);
442 dst->f[3] = src->f[3] - floorf(src->f[3]);
443 }
444
445 static void
446 micro_i2d(union tgsi_double_channel *dst,
447 const union tgsi_exec_channel *src)
448 {
449 dst->d[0] = (double)src->i[0];
450 dst->d[1] = (double)src->i[1];
451 dst->d[2] = (double)src->i[2];
452 dst->d[3] = (double)src->i[3];
453 }
454
455 static void
456 micro_iabs(union tgsi_exec_channel *dst,
457 const union tgsi_exec_channel *src)
458 {
459 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
460 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
461 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
462 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
463 }
464
465 static void
466 micro_ineg(union tgsi_exec_channel *dst,
467 const union tgsi_exec_channel *src)
468 {
469 dst->i[0] = -src->i[0];
470 dst->i[1] = -src->i[1];
471 dst->i[2] = -src->i[2];
472 dst->i[3] = -src->i[3];
473 }
474
475 static void
476 micro_lg2(union tgsi_exec_channel *dst,
477 const union tgsi_exec_channel *src)
478 {
479 #if FAST_MATH
480 dst->f[0] = util_fast_log2(src->f[0]);
481 dst->f[1] = util_fast_log2(src->f[1]);
482 dst->f[2] = util_fast_log2(src->f[2]);
483 dst->f[3] = util_fast_log2(src->f[3]);
484 #else
485 dst->f[0] = logf(src->f[0]) * 1.442695f;
486 dst->f[1] = logf(src->f[1]) * 1.442695f;
487 dst->f[2] = logf(src->f[2]) * 1.442695f;
488 dst->f[3] = logf(src->f[3]) * 1.442695f;
489 #endif
490 }
491
492 static void
493 micro_lrp(union tgsi_exec_channel *dst,
494 const union tgsi_exec_channel *src0,
495 const union tgsi_exec_channel *src1,
496 const union tgsi_exec_channel *src2)
497 {
498 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
499 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
500 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
501 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
502 }
503
504 static void
505 micro_mad(union tgsi_exec_channel *dst,
506 const union tgsi_exec_channel *src0,
507 const union tgsi_exec_channel *src1,
508 const union tgsi_exec_channel *src2)
509 {
510 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
511 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
512 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
513 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
514 }
515
516 static void
517 micro_mov(union tgsi_exec_channel *dst,
518 const union tgsi_exec_channel *src)
519 {
520 dst->u[0] = src->u[0];
521 dst->u[1] = src->u[1];
522 dst->u[2] = src->u[2];
523 dst->u[3] = src->u[3];
524 }
525
526 static void
527 micro_rcp(union tgsi_exec_channel *dst,
528 const union tgsi_exec_channel *src)
529 {
530 #if 0 /* for debugging */
531 assert(src->f[0] != 0.0f);
532 assert(src->f[1] != 0.0f);
533 assert(src->f[2] != 0.0f);
534 assert(src->f[3] != 0.0f);
535 #endif
536 dst->f[0] = 1.0f / src->f[0];
537 dst->f[1] = 1.0f / src->f[1];
538 dst->f[2] = 1.0f / src->f[2];
539 dst->f[3] = 1.0f / src->f[3];
540 }
541
542 static void
543 micro_rnd(union tgsi_exec_channel *dst,
544 const union tgsi_exec_channel *src)
545 {
546 dst->f[0] = floorf(src->f[0] + 0.5f);
547 dst->f[1] = floorf(src->f[1] + 0.5f);
548 dst->f[2] = floorf(src->f[2] + 0.5f);
549 dst->f[3] = floorf(src->f[3] + 0.5f);
550 }
551
552 static void
553 micro_rsq(union tgsi_exec_channel *dst,
554 const union tgsi_exec_channel *src)
555 {
556 #if 0 /* for debugging */
557 assert(src->f[0] != 0.0f);
558 assert(src->f[1] != 0.0f);
559 assert(src->f[2] != 0.0f);
560 assert(src->f[3] != 0.0f);
561 #endif
562 dst->f[0] = 1.0f / sqrtf(src->f[0]);
563 dst->f[1] = 1.0f / sqrtf(src->f[1]);
564 dst->f[2] = 1.0f / sqrtf(src->f[2]);
565 dst->f[3] = 1.0f / sqrtf(src->f[3]);
566 }
567
568 static void
569 micro_sqrt(union tgsi_exec_channel *dst,
570 const union tgsi_exec_channel *src)
571 {
572 dst->f[0] = sqrtf(src->f[0]);
573 dst->f[1] = sqrtf(src->f[1]);
574 dst->f[2] = sqrtf(src->f[2]);
575 dst->f[3] = sqrtf(src->f[3]);
576 }
577
578 static void
579 micro_seq(union tgsi_exec_channel *dst,
580 const union tgsi_exec_channel *src0,
581 const union tgsi_exec_channel *src1)
582 {
583 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
584 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
585 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
586 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
587 }
588
589 static void
590 micro_sge(union tgsi_exec_channel *dst,
591 const union tgsi_exec_channel *src0,
592 const union tgsi_exec_channel *src1)
593 {
594 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
595 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
596 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
597 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
598 }
599
600 static void
601 micro_sgn(union tgsi_exec_channel *dst,
602 const union tgsi_exec_channel *src)
603 {
604 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
605 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
606 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
607 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
608 }
609
610 static void
611 micro_isgn(union tgsi_exec_channel *dst,
612 const union tgsi_exec_channel *src)
613 {
614 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
615 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
616 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
617 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
618 }
619
620 static void
621 micro_sgt(union tgsi_exec_channel *dst,
622 const union tgsi_exec_channel *src0,
623 const union tgsi_exec_channel *src1)
624 {
625 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
626 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
627 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
628 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
629 }
630
631 static void
632 micro_sin(union tgsi_exec_channel *dst,
633 const union tgsi_exec_channel *src)
634 {
635 dst->f[0] = sinf(src->f[0]);
636 dst->f[1] = sinf(src->f[1]);
637 dst->f[2] = sinf(src->f[2]);
638 dst->f[3] = sinf(src->f[3]);
639 }
640
641 static void
642 micro_sle(union tgsi_exec_channel *dst,
643 const union tgsi_exec_channel *src0,
644 const union tgsi_exec_channel *src1)
645 {
646 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
647 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
648 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
649 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
650 }
651
652 static void
653 micro_slt(union tgsi_exec_channel *dst,
654 const union tgsi_exec_channel *src0,
655 const union tgsi_exec_channel *src1)
656 {
657 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
658 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
659 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
660 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
661 }
662
663 static void
664 micro_sne(union tgsi_exec_channel *dst,
665 const union tgsi_exec_channel *src0,
666 const union tgsi_exec_channel *src1)
667 {
668 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
669 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
670 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
671 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
672 }
673
674 static void
675 micro_trunc(union tgsi_exec_channel *dst,
676 const union tgsi_exec_channel *src)
677 {
678 dst->f[0] = (float)(int)src->f[0];
679 dst->f[1] = (float)(int)src->f[1];
680 dst->f[2] = (float)(int)src->f[2];
681 dst->f[3] = (float)(int)src->f[3];
682 }
683
684 static void
685 micro_u2d(union tgsi_double_channel *dst,
686 const union tgsi_exec_channel *src)
687 {
688 dst->d[0] = (double)src->u[0];
689 dst->d[1] = (double)src->u[1];
690 dst->d[2] = (double)src->u[2];
691 dst->d[3] = (double)src->u[3];
692 }
693
694 enum tgsi_exec_datatype {
695 TGSI_EXEC_DATA_FLOAT,
696 TGSI_EXEC_DATA_INT,
697 TGSI_EXEC_DATA_UINT,
698 TGSI_EXEC_DATA_DOUBLE
699 };
700
701 /*
702 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
703 */
704 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
705 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
706 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
707 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
708 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
709 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
710
711
712 /** The execution mask depends on the conditional mask and the loop mask */
713 #define UPDATE_EXEC_MASK(MACH) \
714 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
715
716
717 static const union tgsi_exec_channel ZeroVec =
718 { { 0.0, 0.0, 0.0, 0.0 } };
719
720 static const union tgsi_exec_channel OneVec = {
721 {1.0f, 1.0f, 1.0f, 1.0f}
722 };
723
724 static const union tgsi_exec_channel P128Vec = {
725 {128.0f, 128.0f, 128.0f, 128.0f}
726 };
727
728 static const union tgsi_exec_channel M128Vec = {
729 {-128.0f, -128.0f, -128.0f, -128.0f}
730 };
731
732
733 /**
734 * Assert that none of the float values in 'chan' are infinite or NaN.
735 * NaN and Inf may occur normally during program execution and should
736 * not lead to crashes, etc. But when debugging, it's helpful to catch
737 * them.
738 */
739 static inline void
740 check_inf_or_nan(const union tgsi_exec_channel *chan)
741 {
742 assert(!util_is_inf_or_nan((chan)->f[0]));
743 assert(!util_is_inf_or_nan((chan)->f[1]));
744 assert(!util_is_inf_or_nan((chan)->f[2]));
745 assert(!util_is_inf_or_nan((chan)->f[3]));
746 }
747
748
749 #ifdef DEBUG
750 static void
751 print_chan(const char *msg, const union tgsi_exec_channel *chan)
752 {
753 debug_printf("%s = {%f, %f, %f, %f}\n",
754 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
755 }
756 #endif
757
758
759 #ifdef DEBUG
760 static void
761 print_temp(const struct tgsi_exec_machine *mach, uint index)
762 {
763 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
764 int i;
765 debug_printf("Temp[%u] =\n", index);
766 for (i = 0; i < 4; i++) {
767 debug_printf(" %c: { %f, %f, %f, %f }\n",
768 "XYZW"[i],
769 tmp->xyzw[i].f[0],
770 tmp->xyzw[i].f[1],
771 tmp->xyzw[i].f[2],
772 tmp->xyzw[i].f[3]);
773 }
774 }
775 #endif
776
777
778 void
779 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
780 unsigned num_bufs,
781 const void **bufs,
782 const unsigned *buf_sizes)
783 {
784 unsigned i;
785
786 for (i = 0; i < num_bufs; i++) {
787 mach->Consts[i] = bufs[i];
788 mach->ConstsSize[i] = buf_sizes[i];
789 }
790 }
791
792
793 /**
794 * Check if there's a potential src/dst register data dependency when
795 * using SOA execution.
796 * Example:
797 * MOV T, T.yxwz;
798 * This would expand into:
799 * MOV t0, t1;
800 * MOV t1, t0;
801 * MOV t2, t3;
802 * MOV t3, t2;
803 * The second instruction will have the wrong value for t0 if executed as-is.
804 */
805 boolean
806 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
807 {
808 uint i, chan;
809
810 uint writemask = inst->Dst[0].Register.WriteMask;
811 if (writemask == TGSI_WRITEMASK_X ||
812 writemask == TGSI_WRITEMASK_Y ||
813 writemask == TGSI_WRITEMASK_Z ||
814 writemask == TGSI_WRITEMASK_W ||
815 writemask == TGSI_WRITEMASK_NONE) {
816 /* no chance of data dependency */
817 return FALSE;
818 }
819
820 /* loop over src regs */
821 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
822 if ((inst->Src[i].Register.File ==
823 inst->Dst[0].Register.File) &&
824 ((inst->Src[i].Register.Index ==
825 inst->Dst[0].Register.Index) ||
826 inst->Src[i].Register.Indirect ||
827 inst->Dst[0].Register.Indirect)) {
828 /* loop over dest channels */
829 uint channelsWritten = 0x0;
830 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
831 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
832 /* check if we're reading a channel that's been written */
833 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
834 if (channelsWritten & (1 << swizzle)) {
835 return TRUE;
836 }
837
838 channelsWritten |= (1 << chan);
839 }
840 }
841 }
842 }
843 return FALSE;
844 }
845
846
847 /**
848 * Initialize machine state by expanding tokens to full instructions,
849 * allocating temporary storage, setting up constants, etc.
850 * After this, we can call tgsi_exec_machine_run() many times.
851 */
852 void
853 tgsi_exec_machine_bind_shader(
854 struct tgsi_exec_machine *mach,
855 const struct tgsi_token *tokens,
856 struct tgsi_sampler *sampler,
857 struct tgsi_image *image,
858 struct tgsi_buffer *buffer)
859 {
860 uint k;
861 struct tgsi_parse_context parse;
862 struct tgsi_full_instruction *instructions;
863 struct tgsi_full_declaration *declarations;
864 uint maxInstructions = 10, numInstructions = 0;
865 uint maxDeclarations = 10, numDeclarations = 0;
866
867 #if 0
868 tgsi_dump(tokens, 0);
869 #endif
870
871 util_init_math();
872
873
874 mach->Tokens = tokens;
875 mach->Sampler = sampler;
876 mach->Image = image;
877 mach->Buffer = buffer;
878
879 if (!tokens) {
880 /* unbind and free all */
881 FREE(mach->Declarations);
882 mach->Declarations = NULL;
883 mach->NumDeclarations = 0;
884
885 FREE(mach->Instructions);
886 mach->Instructions = NULL;
887 mach->NumInstructions = 0;
888
889 return;
890 }
891
892 k = tgsi_parse_init (&parse, mach->Tokens);
893 if (k != TGSI_PARSE_OK) {
894 debug_printf( "Problem parsing!\n" );
895 return;
896 }
897
898 mach->ImmLimit = 0;
899 mach->NumOutputs = 0;
900
901 if (mach->ShaderType == PIPE_SHADER_GEOMETRY &&
902 !mach->UsedGeometryShader) {
903 struct tgsi_exec_vector *inputs;
904 struct tgsi_exec_vector *outputs;
905
906 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
907 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
908 16);
909
910 if (!inputs)
911 return;
912
913 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
914 TGSI_MAX_TOTAL_VERTICES, 16);
915
916 if (!outputs) {
917 align_free(inputs);
918 return;
919 }
920
921 align_free(mach->Inputs);
922 align_free(mach->Outputs);
923
924 mach->Inputs = inputs;
925 mach->Outputs = outputs;
926 mach->UsedGeometryShader = TRUE;
927 }
928
929 declarations = (struct tgsi_full_declaration *)
930 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
931
932 if (!declarations) {
933 return;
934 }
935
936 instructions = (struct tgsi_full_instruction *)
937 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
938
939 if (!instructions) {
940 FREE( declarations );
941 return;
942 }
943
944 while( !tgsi_parse_end_of_tokens( &parse ) ) {
945 uint i;
946
947 tgsi_parse_token( &parse );
948 switch( parse.FullToken.Token.Type ) {
949 case TGSI_TOKEN_TYPE_DECLARATION:
950 /* save expanded declaration */
951 if (numDeclarations == maxDeclarations) {
952 declarations = REALLOC(declarations,
953 maxDeclarations
954 * sizeof(struct tgsi_full_declaration),
955 (maxDeclarations + 10)
956 * sizeof(struct tgsi_full_declaration));
957 maxDeclarations += 10;
958 }
959 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
960 unsigned reg;
961 for (reg = parse.FullToken.FullDeclaration.Range.First;
962 reg <= parse.FullToken.FullDeclaration.Range.Last;
963 ++reg) {
964 ++mach->NumOutputs;
965 }
966 }
967 else if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
968 const struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
969 mach->SysSemanticToIndex[decl->Semantic.Name] = decl->Range.First;
970 }
971
972 memcpy(declarations + numDeclarations,
973 &parse.FullToken.FullDeclaration,
974 sizeof(declarations[0]));
975 numDeclarations++;
976 break;
977
978 case TGSI_TOKEN_TYPE_IMMEDIATE:
979 {
980 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
981 assert( size <= 4 );
982 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
983
984 for( i = 0; i < size; i++ ) {
985 mach->Imms[mach->ImmLimit][i] =
986 parse.FullToken.FullImmediate.u[i].Float;
987 }
988 mach->ImmLimit += 1;
989 }
990 break;
991
992 case TGSI_TOKEN_TYPE_INSTRUCTION:
993
994 /* save expanded instruction */
995 if (numInstructions == maxInstructions) {
996 instructions = REALLOC(instructions,
997 maxInstructions
998 * sizeof(struct tgsi_full_instruction),
999 (maxInstructions + 10)
1000 * sizeof(struct tgsi_full_instruction));
1001 maxInstructions += 10;
1002 }
1003
1004 memcpy(instructions + numInstructions,
1005 &parse.FullToken.FullInstruction,
1006 sizeof(instructions[0]));
1007
1008 numInstructions++;
1009 break;
1010
1011 case TGSI_TOKEN_TYPE_PROPERTY:
1012 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
1013 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1014 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1015 }
1016 }
1017 break;
1018
1019 default:
1020 assert( 0 );
1021 }
1022 }
1023 tgsi_parse_free (&parse);
1024
1025 FREE(mach->Declarations);
1026 mach->Declarations = declarations;
1027 mach->NumDeclarations = numDeclarations;
1028
1029 FREE(mach->Instructions);
1030 mach->Instructions = instructions;
1031 mach->NumInstructions = numInstructions;
1032 }
1033
1034
1035 struct tgsi_exec_machine *
1036 tgsi_exec_machine_create(enum pipe_shader_type shader_type)
1037 {
1038 struct tgsi_exec_machine *mach;
1039 uint i;
1040
1041 mach = align_malloc( sizeof *mach, 16 );
1042 if (!mach)
1043 goto fail;
1044
1045 memset(mach, 0, sizeof(*mach));
1046
1047 mach->ShaderType = shader_type;
1048 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1049 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1050 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1051
1052 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1053 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1054 if (!mach->Inputs || !mach->Outputs)
1055 goto fail;
1056
1057 /* Setup constants needed by the SSE2 executor. */
1058 for( i = 0; i < 4; i++ ) {
1059 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1060 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1061 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1062 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1063 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1064 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1065 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1066 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1067 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1068 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1069 }
1070
1071 #ifdef DEBUG
1072 /* silence warnings */
1073 (void) print_chan;
1074 (void) print_temp;
1075 #endif
1076
1077 return mach;
1078
1079 fail:
1080 if (mach) {
1081 align_free(mach->Inputs);
1082 align_free(mach->Outputs);
1083 align_free(mach);
1084 }
1085 return NULL;
1086 }
1087
1088
1089 void
1090 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1091 {
1092 if (mach) {
1093 FREE(mach->Instructions);
1094 FREE(mach->Declarations);
1095
1096 align_free(mach->Inputs);
1097 align_free(mach->Outputs);
1098
1099 align_free(mach);
1100 }
1101 }
1102
1103 static void
1104 micro_add(union tgsi_exec_channel *dst,
1105 const union tgsi_exec_channel *src0,
1106 const union tgsi_exec_channel *src1)
1107 {
1108 dst->f[0] = src0->f[0] + src1->f[0];
1109 dst->f[1] = src0->f[1] + src1->f[1];
1110 dst->f[2] = src0->f[2] + src1->f[2];
1111 dst->f[3] = src0->f[3] + src1->f[3];
1112 }
1113
1114 static void
1115 micro_div(
1116 union tgsi_exec_channel *dst,
1117 const union tgsi_exec_channel *src0,
1118 const union tgsi_exec_channel *src1 )
1119 {
1120 if (src1->f[0] != 0) {
1121 dst->f[0] = src0->f[0] / src1->f[0];
1122 }
1123 if (src1->f[1] != 0) {
1124 dst->f[1] = src0->f[1] / src1->f[1];
1125 }
1126 if (src1->f[2] != 0) {
1127 dst->f[2] = src0->f[2] / src1->f[2];
1128 }
1129 if (src1->f[3] != 0) {
1130 dst->f[3] = src0->f[3] / src1->f[3];
1131 }
1132 }
1133
1134 static void
1135 micro_lt(
1136 union tgsi_exec_channel *dst,
1137 const union tgsi_exec_channel *src0,
1138 const union tgsi_exec_channel *src1,
1139 const union tgsi_exec_channel *src2,
1140 const union tgsi_exec_channel *src3 )
1141 {
1142 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1143 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1144 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1145 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1146 }
1147
1148 static void
1149 micro_max(union tgsi_exec_channel *dst,
1150 const union tgsi_exec_channel *src0,
1151 const union tgsi_exec_channel *src1)
1152 {
1153 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1154 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1155 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1156 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1157 }
1158
1159 static void
1160 micro_min(union tgsi_exec_channel *dst,
1161 const union tgsi_exec_channel *src0,
1162 const union tgsi_exec_channel *src1)
1163 {
1164 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1165 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1166 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1167 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1168 }
1169
1170 static void
1171 micro_mul(union tgsi_exec_channel *dst,
1172 const union tgsi_exec_channel *src0,
1173 const union tgsi_exec_channel *src1)
1174 {
1175 dst->f[0] = src0->f[0] * src1->f[0];
1176 dst->f[1] = src0->f[1] * src1->f[1];
1177 dst->f[2] = src0->f[2] * src1->f[2];
1178 dst->f[3] = src0->f[3] * src1->f[3];
1179 }
1180
1181 static void
1182 micro_neg(
1183 union tgsi_exec_channel *dst,
1184 const union tgsi_exec_channel *src )
1185 {
1186 dst->f[0] = -src->f[0];
1187 dst->f[1] = -src->f[1];
1188 dst->f[2] = -src->f[2];
1189 dst->f[3] = -src->f[3];
1190 }
1191
1192 static void
1193 micro_pow(
1194 union tgsi_exec_channel *dst,
1195 const union tgsi_exec_channel *src0,
1196 const union tgsi_exec_channel *src1 )
1197 {
1198 #if FAST_MATH
1199 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1200 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1201 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1202 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1203 #else
1204 dst->f[0] = powf( src0->f[0], src1->f[0] );
1205 dst->f[1] = powf( src0->f[1], src1->f[1] );
1206 dst->f[2] = powf( src0->f[2], src1->f[2] );
1207 dst->f[3] = powf( src0->f[3], src1->f[3] );
1208 #endif
1209 }
1210
1211 static void
1212 micro_sub(union tgsi_exec_channel *dst,
1213 const union tgsi_exec_channel *src0,
1214 const union tgsi_exec_channel *src1)
1215 {
1216 dst->f[0] = src0->f[0] - src1->f[0];
1217 dst->f[1] = src0->f[1] - src1->f[1];
1218 dst->f[2] = src0->f[2] - src1->f[2];
1219 dst->f[3] = src0->f[3] - src1->f[3];
1220 }
1221
1222 static void
1223 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1224 const uint chan_index,
1225 const uint file,
1226 const uint swizzle,
1227 const union tgsi_exec_channel *index,
1228 const union tgsi_exec_channel *index2D,
1229 union tgsi_exec_channel *chan)
1230 {
1231 uint i;
1232
1233 assert(swizzle < 4);
1234
1235 switch (file) {
1236 case TGSI_FILE_CONSTANT:
1237 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1238 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1239 assert(mach->Consts[index2D->i[i]]);
1240
1241 if (index->i[i] < 0) {
1242 chan->u[i] = 0;
1243 } else {
1244 /* NOTE: copying the const value as a uint instead of float */
1245 const uint constbuf = index2D->i[i];
1246 const uint *buf = (const uint *)mach->Consts[constbuf];
1247 const int pos = index->i[i] * 4 + swizzle;
1248 /* const buffer bounds check */
1249 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1250 if (0) {
1251 /* Debug: print warning */
1252 static int count = 0;
1253 if (count++ < 100)
1254 debug_printf("TGSI Exec: const buffer index %d"
1255 " out of bounds\n", pos);
1256 }
1257 chan->u[i] = 0;
1258 }
1259 else
1260 chan->u[i] = buf[pos];
1261 }
1262 }
1263 break;
1264
1265 case TGSI_FILE_INPUT:
1266 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1267 /*
1268 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1269 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1270 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1271 index2D->i[i], index->i[i]);
1272 }*/
1273 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1274 assert(pos >= 0);
1275 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1276 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1277 }
1278 break;
1279
1280 case TGSI_FILE_SYSTEM_VALUE:
1281 /* XXX no swizzling at this point. Will be needed if we put
1282 * gl_FragCoord, for example, in a sys value register.
1283 */
1284 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1285 chan->u[i] = mach->SystemValue[index->i[i]].xyzw[swizzle].u[i];
1286 }
1287 break;
1288
1289 case TGSI_FILE_TEMPORARY:
1290 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1291 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1292 assert(index2D->i[i] == 0);
1293
1294 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1295 }
1296 break;
1297
1298 case TGSI_FILE_IMMEDIATE:
1299 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1300 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1301 assert(index2D->i[i] == 0);
1302
1303 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1304 }
1305 break;
1306
1307 case TGSI_FILE_ADDRESS:
1308 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1309 assert(index->i[i] >= 0);
1310 assert(index2D->i[i] == 0);
1311
1312 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1313 }
1314 break;
1315
1316 case TGSI_FILE_PREDICATE:
1317 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1318 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1319 assert(index2D->i[i] == 0);
1320
1321 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1322 }
1323 break;
1324
1325 case TGSI_FILE_OUTPUT:
1326 /* vertex/fragment output vars can be read too */
1327 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1328 assert(index->i[i] >= 0);
1329 assert(index2D->i[i] == 0);
1330
1331 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1332 }
1333 break;
1334
1335 default:
1336 assert(0);
1337 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1338 chan->u[i] = 0;
1339 }
1340 }
1341 }
1342
1343 static void
1344 fetch_source_d(const struct tgsi_exec_machine *mach,
1345 union tgsi_exec_channel *chan,
1346 const struct tgsi_full_src_register *reg,
1347 const uint chan_index,
1348 enum tgsi_exec_datatype src_datatype)
1349 {
1350 union tgsi_exec_channel index;
1351 union tgsi_exec_channel index2D;
1352 uint swizzle;
1353
1354 /* We start with a direct index into a register file.
1355 *
1356 * file[1],
1357 * where:
1358 * file = Register.File
1359 * [1] = Register.Index
1360 */
1361 index.i[0] =
1362 index.i[1] =
1363 index.i[2] =
1364 index.i[3] = reg->Register.Index;
1365
1366 /* There is an extra source register that indirectly subscripts
1367 * a register file. The direct index now becomes an offset
1368 * that is being added to the indirect register.
1369 *
1370 * file[ind[2].x+1],
1371 * where:
1372 * ind = Indirect.File
1373 * [2] = Indirect.Index
1374 * .x = Indirect.SwizzleX
1375 */
1376 if (reg->Register.Indirect) {
1377 union tgsi_exec_channel index2;
1378 union tgsi_exec_channel indir_index;
1379 const uint execmask = mach->ExecMask;
1380 uint i;
1381
1382 /* which address register (always zero now) */
1383 index2.i[0] =
1384 index2.i[1] =
1385 index2.i[2] =
1386 index2.i[3] = reg->Indirect.Index;
1387 /* get current value of address register[swizzle] */
1388 swizzle = reg->Indirect.Swizzle;
1389 fetch_src_file_channel(mach,
1390 chan_index,
1391 reg->Indirect.File,
1392 swizzle,
1393 &index2,
1394 &ZeroVec,
1395 &indir_index);
1396
1397 /* add value of address register to the offset */
1398 index.i[0] += indir_index.i[0];
1399 index.i[1] += indir_index.i[1];
1400 index.i[2] += indir_index.i[2];
1401 index.i[3] += indir_index.i[3];
1402
1403 /* for disabled execution channels, zero-out the index to
1404 * avoid using a potential garbage value.
1405 */
1406 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1407 if ((execmask & (1 << i)) == 0)
1408 index.i[i] = 0;
1409 }
1410 }
1411
1412 /* There is an extra source register that is a second
1413 * subscript to a register file. Effectively it means that
1414 * the register file is actually a 2D array of registers.
1415 *
1416 * file[3][1],
1417 * where:
1418 * [3] = Dimension.Index
1419 */
1420 if (reg->Register.Dimension) {
1421 index2D.i[0] =
1422 index2D.i[1] =
1423 index2D.i[2] =
1424 index2D.i[3] = reg->Dimension.Index;
1425
1426 /* Again, the second subscript index can be addressed indirectly
1427 * identically to the first one.
1428 * Nothing stops us from indirectly addressing the indirect register,
1429 * but there is no need for that, so we won't exercise it.
1430 *
1431 * file[ind[4].y+3][1],
1432 * where:
1433 * ind = DimIndirect.File
1434 * [4] = DimIndirect.Index
1435 * .y = DimIndirect.SwizzleX
1436 */
1437 if (reg->Dimension.Indirect) {
1438 union tgsi_exec_channel index2;
1439 union tgsi_exec_channel indir_index;
1440 const uint execmask = mach->ExecMask;
1441 uint i;
1442
1443 index2.i[0] =
1444 index2.i[1] =
1445 index2.i[2] =
1446 index2.i[3] = reg->DimIndirect.Index;
1447
1448 swizzle = reg->DimIndirect.Swizzle;
1449 fetch_src_file_channel(mach,
1450 chan_index,
1451 reg->DimIndirect.File,
1452 swizzle,
1453 &index2,
1454 &ZeroVec,
1455 &indir_index);
1456
1457 index2D.i[0] += indir_index.i[0];
1458 index2D.i[1] += indir_index.i[1];
1459 index2D.i[2] += indir_index.i[2];
1460 index2D.i[3] += indir_index.i[3];
1461
1462 /* for disabled execution channels, zero-out the index to
1463 * avoid using a potential garbage value.
1464 */
1465 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1466 if ((execmask & (1 << i)) == 0) {
1467 index2D.i[i] = 0;
1468 }
1469 }
1470 }
1471
1472 /* If by any chance there was a need for a 3D array of register
1473 * files, we would have to check whether Dimension is followed
1474 * by a dimension register and continue the saga.
1475 */
1476 } else {
1477 index2D.i[0] =
1478 index2D.i[1] =
1479 index2D.i[2] =
1480 index2D.i[3] = 0;
1481 }
1482
1483 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1484 fetch_src_file_channel(mach,
1485 chan_index,
1486 reg->Register.File,
1487 swizzle,
1488 &index,
1489 &index2D,
1490 chan);
1491 }
1492
1493 static void
1494 fetch_source(const struct tgsi_exec_machine *mach,
1495 union tgsi_exec_channel *chan,
1496 const struct tgsi_full_src_register *reg,
1497 const uint chan_index,
1498 enum tgsi_exec_datatype src_datatype)
1499 {
1500 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1501
1502 if (reg->Register.Absolute) {
1503 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1504 micro_abs(chan, chan);
1505 } else {
1506 micro_iabs(chan, chan);
1507 }
1508 }
1509
1510 if (reg->Register.Negate) {
1511 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1512 micro_neg(chan, chan);
1513 } else {
1514 micro_ineg(chan, chan);
1515 }
1516 }
1517 }
1518
1519 static union tgsi_exec_channel *
1520 store_dest_dstret(struct tgsi_exec_machine *mach,
1521 const union tgsi_exec_channel *chan,
1522 const struct tgsi_full_dst_register *reg,
1523 const struct tgsi_full_instruction *inst,
1524 uint chan_index,
1525 enum tgsi_exec_datatype dst_datatype)
1526 {
1527 uint i;
1528 static union tgsi_exec_channel null;
1529 union tgsi_exec_channel *dst;
1530 union tgsi_exec_channel index2D;
1531 uint execmask = mach->ExecMask;
1532 int offset = 0; /* indirection offset */
1533 int index;
1534
1535 /* for debugging */
1536 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1537 check_inf_or_nan(chan);
1538 }
1539
1540 /* There is an extra source register that indirectly subscripts
1541 * a register file. The direct index now becomes an offset
1542 * that is being added to the indirect register.
1543 *
1544 * file[ind[2].x+1],
1545 * where:
1546 * ind = Indirect.File
1547 * [2] = Indirect.Index
1548 * .x = Indirect.SwizzleX
1549 */
1550 if (reg->Register.Indirect) {
1551 union tgsi_exec_channel index;
1552 union tgsi_exec_channel indir_index;
1553 uint swizzle;
1554
1555 /* which address register (always zero for now) */
1556 index.i[0] =
1557 index.i[1] =
1558 index.i[2] =
1559 index.i[3] = reg->Indirect.Index;
1560
1561 /* get current value of address register[swizzle] */
1562 swizzle = reg->Indirect.Swizzle;
1563
1564 /* fetch values from the address/indirection register */
1565 fetch_src_file_channel(mach,
1566 chan_index,
1567 reg->Indirect.File,
1568 swizzle,
1569 &index,
1570 &ZeroVec,
1571 &indir_index);
1572
1573 /* save indirection offset */
1574 offset = indir_index.i[0];
1575 }
1576
1577 /* There is an extra source register that is a second
1578 * subscript to a register file. Effectively it means that
1579 * the register file is actually a 2D array of registers.
1580 *
1581 * file[3][1],
1582 * where:
1583 * [3] = Dimension.Index
1584 */
1585 if (reg->Register.Dimension) {
1586 index2D.i[0] =
1587 index2D.i[1] =
1588 index2D.i[2] =
1589 index2D.i[3] = reg->Dimension.Index;
1590
1591 /* Again, the second subscript index can be addressed indirectly
1592 * identically to the first one.
1593 * Nothing stops us from indirectly addressing the indirect register,
1594 * but there is no need for that, so we won't exercise it.
1595 *
1596 * file[ind[4].y+3][1],
1597 * where:
1598 * ind = DimIndirect.File
1599 * [4] = DimIndirect.Index
1600 * .y = DimIndirect.SwizzleX
1601 */
1602 if (reg->Dimension.Indirect) {
1603 union tgsi_exec_channel index2;
1604 union tgsi_exec_channel indir_index;
1605 const uint execmask = mach->ExecMask;
1606 unsigned swizzle;
1607 uint i;
1608
1609 index2.i[0] =
1610 index2.i[1] =
1611 index2.i[2] =
1612 index2.i[3] = reg->DimIndirect.Index;
1613
1614 swizzle = reg->DimIndirect.Swizzle;
1615 fetch_src_file_channel(mach,
1616 chan_index,
1617 reg->DimIndirect.File,
1618 swizzle,
1619 &index2,
1620 &ZeroVec,
1621 &indir_index);
1622
1623 index2D.i[0] += indir_index.i[0];
1624 index2D.i[1] += indir_index.i[1];
1625 index2D.i[2] += indir_index.i[2];
1626 index2D.i[3] += indir_index.i[3];
1627
1628 /* for disabled execution channels, zero-out the index to
1629 * avoid using a potential garbage value.
1630 */
1631 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1632 if ((execmask & (1 << i)) == 0) {
1633 index2D.i[i] = 0;
1634 }
1635 }
1636 }
1637
1638 /* If by any chance there was a need for a 3D array of register
1639 * files, we would have to check whether Dimension is followed
1640 * by a dimension register and continue the saga.
1641 */
1642 } else {
1643 index2D.i[0] =
1644 index2D.i[1] =
1645 index2D.i[2] =
1646 index2D.i[3] = 0;
1647 }
1648
1649 switch (reg->Register.File) {
1650 case TGSI_FILE_NULL:
1651 dst = &null;
1652 break;
1653
1654 case TGSI_FILE_OUTPUT:
1655 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1656 + reg->Register.Index;
1657 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1658 #if 0
1659 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1660 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1661 reg->Register.Index);
1662 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1663 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1664 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1665 if (execmask & (1 << i))
1666 debug_printf("%f, ", chan->f[i]);
1667 debug_printf(")\n");
1668 }
1669 #endif
1670 break;
1671
1672 case TGSI_FILE_TEMPORARY:
1673 index = reg->Register.Index;
1674 assert( index < TGSI_EXEC_NUM_TEMPS );
1675 dst = &mach->Temps[offset + index].xyzw[chan_index];
1676 break;
1677
1678 case TGSI_FILE_ADDRESS:
1679 index = reg->Register.Index;
1680 dst = &mach->Addrs[index].xyzw[chan_index];
1681 break;
1682
1683 case TGSI_FILE_PREDICATE:
1684 index = reg->Register.Index;
1685 assert(index < TGSI_EXEC_NUM_PREDS);
1686 dst = &mach->Predicates[index].xyzw[chan_index];
1687 break;
1688
1689 default:
1690 assert( 0 );
1691 return NULL;
1692 }
1693
1694 if (inst->Instruction.Predicate) {
1695 uint swizzle;
1696 union tgsi_exec_channel *pred;
1697
1698 switch (chan_index) {
1699 case TGSI_CHAN_X:
1700 swizzle = inst->Predicate.SwizzleX;
1701 break;
1702 case TGSI_CHAN_Y:
1703 swizzle = inst->Predicate.SwizzleY;
1704 break;
1705 case TGSI_CHAN_Z:
1706 swizzle = inst->Predicate.SwizzleZ;
1707 break;
1708 case TGSI_CHAN_W:
1709 swizzle = inst->Predicate.SwizzleW;
1710 break;
1711 default:
1712 assert(0);
1713 return NULL;
1714 }
1715
1716 assert(inst->Predicate.Index == 0);
1717
1718 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1719
1720 if (inst->Predicate.Negate) {
1721 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1722 if (pred->u[i]) {
1723 execmask &= ~(1 << i);
1724 }
1725 }
1726 } else {
1727 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1728 if (!pred->u[i]) {
1729 execmask &= ~(1 << i);
1730 }
1731 }
1732 }
1733 }
1734
1735 return dst;
1736 }
1737
1738 static void
1739 store_dest_double(struct tgsi_exec_machine *mach,
1740 const union tgsi_exec_channel *chan,
1741 const struct tgsi_full_dst_register *reg,
1742 const struct tgsi_full_instruction *inst,
1743 uint chan_index,
1744 enum tgsi_exec_datatype dst_datatype)
1745 {
1746 union tgsi_exec_channel *dst;
1747 const uint execmask = mach->ExecMask;
1748 int i;
1749
1750 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1751 dst_datatype);
1752 if (!dst)
1753 return;
1754
1755 /* doubles path */
1756 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1757 if (execmask & (1 << i))
1758 dst->i[i] = chan->i[i];
1759 }
1760
1761 static void
1762 store_dest(struct tgsi_exec_machine *mach,
1763 const union tgsi_exec_channel *chan,
1764 const struct tgsi_full_dst_register *reg,
1765 const struct tgsi_full_instruction *inst,
1766 uint chan_index,
1767 enum tgsi_exec_datatype dst_datatype)
1768 {
1769 union tgsi_exec_channel *dst;
1770 const uint execmask = mach->ExecMask;
1771 int i;
1772
1773 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1774 dst_datatype);
1775 if (!dst)
1776 return;
1777
1778 if (!inst->Instruction.Saturate) {
1779 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1780 if (execmask & (1 << i))
1781 dst->i[i] = chan->i[i];
1782 }
1783 else {
1784 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1785 if (execmask & (1 << i)) {
1786 if (chan->f[i] < 0.0f)
1787 dst->f[i] = 0.0f;
1788 else if (chan->f[i] > 1.0f)
1789 dst->f[i] = 1.0f;
1790 else
1791 dst->i[i] = chan->i[i];
1792 }
1793 }
1794 }
1795
1796 #define FETCH(VAL,INDEX,CHAN)\
1797 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1798
1799 #define IFETCH(VAL,INDEX,CHAN)\
1800 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1801
1802
1803 /**
1804 * Execute ARB-style KIL which is predicated by a src register.
1805 * Kill fragment if any of the four values is less than zero.
1806 */
1807 static void
1808 exec_kill_if(struct tgsi_exec_machine *mach,
1809 const struct tgsi_full_instruction *inst)
1810 {
1811 uint uniquemask;
1812 uint chan_index;
1813 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1814 union tgsi_exec_channel r[1];
1815
1816 /* This mask stores component bits that were already tested. */
1817 uniquemask = 0;
1818
1819 for (chan_index = 0; chan_index < 4; chan_index++)
1820 {
1821 uint swizzle;
1822 uint i;
1823
1824 /* unswizzle channel */
1825 swizzle = tgsi_util_get_full_src_register_swizzle (
1826 &inst->Src[0],
1827 chan_index);
1828
1829 /* check if the component has not been already tested */
1830 if (uniquemask & (1 << swizzle))
1831 continue;
1832 uniquemask |= 1 << swizzle;
1833
1834 FETCH(&r[0], 0, chan_index);
1835 for (i = 0; i < 4; i++)
1836 if (r[0].f[i] < 0.0f)
1837 kilmask |= 1 << i;
1838 }
1839
1840 /* restrict to fragments currently executing */
1841 kilmask &= mach->ExecMask;
1842
1843 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1844 }
1845
1846 /**
1847 * Unconditional fragment kill/discard.
1848 */
1849 static void
1850 exec_kill(struct tgsi_exec_machine *mach,
1851 const struct tgsi_full_instruction *inst)
1852 {
1853 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1854
1855 /* kill fragment for all fragments currently executing */
1856 kilmask = mach->ExecMask;
1857 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1858 }
1859
1860 static void
1861 emit_vertex(struct tgsi_exec_machine *mach)
1862 {
1863 /* FIXME: check for exec mask correctly
1864 unsigned i;
1865 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1866 if ((mach->ExecMask & (1 << i)))
1867 */
1868 if (mach->ExecMask) {
1869 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1870 return;
1871
1872 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1873 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1874 }
1875 }
1876
1877 static void
1878 emit_primitive(struct tgsi_exec_machine *mach)
1879 {
1880 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1881 /* FIXME: check for exec mask correctly
1882 unsigned i;
1883 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1884 if ((mach->ExecMask & (1 << i)))
1885 */
1886 if (mach->ExecMask) {
1887 ++(*prim_count);
1888 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1889 mach->Primitives[*prim_count] = 0;
1890 }
1891 }
1892
1893 static void
1894 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1895 {
1896 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1897 int emitted_verts =
1898 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1899 if (emitted_verts) {
1900 emit_primitive(mach);
1901 }
1902 }
1903 }
1904
1905
1906 /*
1907 * Fetch four texture samples using STR texture coordinates.
1908 */
1909 static void
1910 fetch_texel( struct tgsi_sampler *sampler,
1911 const unsigned sview_idx,
1912 const unsigned sampler_idx,
1913 const union tgsi_exec_channel *s,
1914 const union tgsi_exec_channel *t,
1915 const union tgsi_exec_channel *p,
1916 const union tgsi_exec_channel *c0,
1917 const union tgsi_exec_channel *c1,
1918 float derivs[3][2][TGSI_QUAD_SIZE],
1919 const int8_t offset[3],
1920 enum tgsi_sampler_control control,
1921 union tgsi_exec_channel *r,
1922 union tgsi_exec_channel *g,
1923 union tgsi_exec_channel *b,
1924 union tgsi_exec_channel *a )
1925 {
1926 uint j;
1927 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1928
1929 /* FIXME: handle explicit derivs, offsets */
1930 sampler->get_samples(sampler, sview_idx, sampler_idx,
1931 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1932
1933 for (j = 0; j < 4; j++) {
1934 r->f[j] = rgba[0][j];
1935 g->f[j] = rgba[1][j];
1936 b->f[j] = rgba[2][j];
1937 a->f[j] = rgba[3][j];
1938 }
1939 }
1940
1941
1942 #define TEX_MODIFIER_NONE 0
1943 #define TEX_MODIFIER_PROJECTED 1
1944 #define TEX_MODIFIER_LOD_BIAS 2
1945 #define TEX_MODIFIER_EXPLICIT_LOD 3
1946 #define TEX_MODIFIER_LEVEL_ZERO 4
1947 #define TEX_MODIFIER_GATHER 5
1948
1949 /*
1950 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1951 */
1952 static void
1953 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1954 const struct tgsi_full_instruction *inst,
1955 int8_t offsets[3])
1956 {
1957 if (inst->Texture.NumOffsets == 1) {
1958 union tgsi_exec_channel index;
1959 union tgsi_exec_channel offset[3];
1960 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1961 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1962 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1963 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1964 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1965 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1966 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1967 offsets[0] = offset[0].i[0];
1968 offsets[1] = offset[1].i[0];
1969 offsets[2] = offset[2].i[0];
1970 } else {
1971 assert(inst->Texture.NumOffsets == 0);
1972 offsets[0] = offsets[1] = offsets[2] = 0;
1973 }
1974 }
1975
1976
1977 /*
1978 * Fetch dx and dy values for one channel (s, t or r).
1979 * Put dx values into one float array, dy values into another.
1980 */
1981 static void
1982 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1983 const struct tgsi_full_instruction *inst,
1984 unsigned regdsrcx,
1985 unsigned chan,
1986 float derivs[2][TGSI_QUAD_SIZE])
1987 {
1988 union tgsi_exec_channel d;
1989 FETCH(&d, regdsrcx, chan);
1990 derivs[0][0] = d.f[0];
1991 derivs[0][1] = d.f[1];
1992 derivs[0][2] = d.f[2];
1993 derivs[0][3] = d.f[3];
1994 FETCH(&d, regdsrcx + 1, chan);
1995 derivs[1][0] = d.f[0];
1996 derivs[1][1] = d.f[1];
1997 derivs[1][2] = d.f[2];
1998 derivs[1][3] = d.f[3];
1999 }
2000
2001 static uint
2002 fetch_sampler_unit(struct tgsi_exec_machine *mach,
2003 const struct tgsi_full_instruction *inst,
2004 uint sampler)
2005 {
2006 uint unit = 0;
2007 int i;
2008 if (inst->Src[sampler].Register.Indirect) {
2009 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2010 union tgsi_exec_channel indir_index, index2;
2011 const uint execmask = mach->ExecMask;
2012 index2.i[0] =
2013 index2.i[1] =
2014 index2.i[2] =
2015 index2.i[3] = reg->Indirect.Index;
2016
2017 fetch_src_file_channel(mach,
2018 0,
2019 reg->Indirect.File,
2020 reg->Indirect.Swizzle,
2021 &index2,
2022 &ZeroVec,
2023 &indir_index);
2024 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2025 if (execmask & (1 << i)) {
2026 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2027 break;
2028 }
2029 }
2030
2031 } else {
2032 unit = inst->Src[sampler].Register.Index;
2033 }
2034 return unit;
2035 }
2036
2037 /*
2038 * execute a texture instruction.
2039 *
2040 * modifier is used to control the channel routing for the
2041 * instruction variants like proj, lod, and texture with lod bias.
2042 * sampler indicates which src register the sampler is contained in.
2043 */
2044 static void
2045 exec_tex(struct tgsi_exec_machine *mach,
2046 const struct tgsi_full_instruction *inst,
2047 uint modifier, uint sampler)
2048 {
2049 const union tgsi_exec_channel *args[5], *proj = NULL;
2050 union tgsi_exec_channel r[5];
2051 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2052 uint chan;
2053 uint unit;
2054 int8_t offsets[3];
2055 int dim, shadow_ref, i;
2056
2057 unit = fetch_sampler_unit(mach, inst, sampler);
2058 /* always fetch all 3 offsets, overkill but keeps code simple */
2059 fetch_texel_offsets(mach, inst, offsets);
2060
2061 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2062 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2063
2064 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2065 shadow_ref = tgsi_util_get_shadow_ref_src_index(inst->Texture.Texture);
2066
2067 assert(dim <= 4);
2068 if (shadow_ref >= 0)
2069 assert(shadow_ref >= dim && shadow_ref < Elements(args));
2070
2071 /* fetch modifier to the last argument */
2072 if (modifier != TEX_MODIFIER_NONE) {
2073 const int last = Elements(args) - 1;
2074
2075 /* fetch modifier from src0.w or src1.x */
2076 if (sampler == 1) {
2077 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2078 FETCH(&r[last], 0, TGSI_CHAN_W);
2079 }
2080 else {
2081 assert(shadow_ref != 4);
2082 FETCH(&r[last], 1, TGSI_CHAN_X);
2083 }
2084
2085 if (modifier != TEX_MODIFIER_PROJECTED) {
2086 args[last] = &r[last];
2087 }
2088 else {
2089 proj = &r[last];
2090 args[last] = &ZeroVec;
2091 }
2092
2093 /* point unused arguments to zero vector */
2094 for (i = dim; i < last; i++)
2095 args[i] = &ZeroVec;
2096
2097 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2098 control = TGSI_SAMPLER_LOD_EXPLICIT;
2099 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2100 control = TGSI_SAMPLER_LOD_BIAS;
2101 else if (modifier == TEX_MODIFIER_GATHER)
2102 control = TGSI_SAMPLER_GATHER;
2103 }
2104 else {
2105 for (i = dim; i < Elements(args); i++)
2106 args[i] = &ZeroVec;
2107 }
2108
2109 /* fetch coordinates */
2110 for (i = 0; i < dim; i++) {
2111 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2112
2113 if (proj)
2114 micro_div(&r[i], &r[i], proj);
2115
2116 args[i] = &r[i];
2117 }
2118
2119 /* fetch reference value */
2120 if (shadow_ref >= 0) {
2121 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2122
2123 if (proj)
2124 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2125
2126 args[shadow_ref] = &r[shadow_ref];
2127 }
2128
2129 fetch_texel(mach->Sampler, unit, unit,
2130 args[0], args[1], args[2], args[3], args[4],
2131 NULL, offsets, control,
2132 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2133
2134 #if 0
2135 debug_printf("fetch r: %g %g %g %g\n",
2136 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2137 debug_printf("fetch g: %g %g %g %g\n",
2138 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2139 debug_printf("fetch b: %g %g %g %g\n",
2140 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2141 debug_printf("fetch a: %g %g %g %g\n",
2142 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2143 #endif
2144
2145 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2146 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2147 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2148 }
2149 }
2150 }
2151
2152 static void
2153 exec_lodq(struct tgsi_exec_machine *mach,
2154 const struct tgsi_full_instruction *inst)
2155 {
2156 uint unit;
2157 int dim;
2158 int i;
2159 union tgsi_exec_channel coords[4];
2160 const union tgsi_exec_channel *args[Elements(coords)];
2161 union tgsi_exec_channel r[2];
2162
2163 unit = fetch_sampler_unit(mach, inst, 1);
2164 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2165 assert(dim <= Elements(coords));
2166 /* fetch coordinates */
2167 for (i = 0; i < dim; i++) {
2168 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2169 args[i] = &coords[i];
2170 }
2171 for (i = dim; i < Elements(coords); i++) {
2172 args[i] = &ZeroVec;
2173 }
2174 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2175 args[0]->f,
2176 args[1]->f,
2177 args[2]->f,
2178 args[3]->f,
2179 TGSI_SAMPLER_LOD_NONE,
2180 r[0].f,
2181 r[1].f);
2182
2183 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2184 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2185 TGSI_EXEC_DATA_FLOAT);
2186 }
2187 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2188 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2189 TGSI_EXEC_DATA_FLOAT);
2190 }
2191 }
2192
2193 static void
2194 exec_txd(struct tgsi_exec_machine *mach,
2195 const struct tgsi_full_instruction *inst)
2196 {
2197 union tgsi_exec_channel r[4];
2198 float derivs[3][2][TGSI_QUAD_SIZE];
2199 uint chan;
2200 uint unit;
2201 int8_t offsets[3];
2202
2203 unit = fetch_sampler_unit(mach, inst, 3);
2204 /* always fetch all 3 offsets, overkill but keeps code simple */
2205 fetch_texel_offsets(mach, inst, offsets);
2206
2207 switch (inst->Texture.Texture) {
2208 case TGSI_TEXTURE_1D:
2209 FETCH(&r[0], 0, TGSI_CHAN_X);
2210
2211 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2212
2213 fetch_texel(mach->Sampler, unit, unit,
2214 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2215 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2216 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2217 break;
2218
2219 case TGSI_TEXTURE_SHADOW1D:
2220 case TGSI_TEXTURE_1D_ARRAY:
2221 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2222 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2223 FETCH(&r[0], 0, TGSI_CHAN_X);
2224 FETCH(&r[1], 0, TGSI_CHAN_Y);
2225 FETCH(&r[2], 0, TGSI_CHAN_Z);
2226
2227 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2228
2229 fetch_texel(mach->Sampler, unit, unit,
2230 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2231 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2232 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2233 break;
2234
2235 case TGSI_TEXTURE_2D:
2236 case TGSI_TEXTURE_RECT:
2237 FETCH(&r[0], 0, TGSI_CHAN_X);
2238 FETCH(&r[1], 0, TGSI_CHAN_Y);
2239
2240 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2241 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2242
2243 fetch_texel(mach->Sampler, unit, unit,
2244 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2245 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2246 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2247 break;
2248
2249
2250 case TGSI_TEXTURE_SHADOW2D:
2251 case TGSI_TEXTURE_SHADOWRECT:
2252 case TGSI_TEXTURE_2D_ARRAY:
2253 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2254 /* only SHADOW2D_ARRAY actually needs W */
2255 FETCH(&r[0], 0, TGSI_CHAN_X);
2256 FETCH(&r[1], 0, TGSI_CHAN_Y);
2257 FETCH(&r[2], 0, TGSI_CHAN_Z);
2258 FETCH(&r[3], 0, TGSI_CHAN_W);
2259
2260 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2261 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2262
2263 fetch_texel(mach->Sampler, unit, unit,
2264 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2265 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2266 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2267 break;
2268
2269 case TGSI_TEXTURE_3D:
2270 case TGSI_TEXTURE_CUBE:
2271 case TGSI_TEXTURE_CUBE_ARRAY:
2272 case TGSI_TEXTURE_SHADOWCUBE:
2273 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2274 FETCH(&r[0], 0, TGSI_CHAN_X);
2275 FETCH(&r[1], 0, TGSI_CHAN_Y);
2276 FETCH(&r[2], 0, TGSI_CHAN_Z);
2277 FETCH(&r[3], 0, TGSI_CHAN_W);
2278
2279 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2280 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2281 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2282
2283 fetch_texel(mach->Sampler, unit, unit,
2284 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2285 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2286 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2287 break;
2288
2289 default:
2290 assert(0);
2291 }
2292
2293 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2294 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2295 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2296 }
2297 }
2298 }
2299
2300
2301 static void
2302 exec_txf(struct tgsi_exec_machine *mach,
2303 const struct tgsi_full_instruction *inst)
2304 {
2305 union tgsi_exec_channel r[4];
2306 uint chan;
2307 uint unit;
2308 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2309 int j;
2310 int8_t offsets[3];
2311 unsigned target;
2312
2313 unit = fetch_sampler_unit(mach, inst, 1);
2314 /* always fetch all 3 offsets, overkill but keeps code simple */
2315 fetch_texel_offsets(mach, inst, offsets);
2316
2317 IFETCH(&r[3], 0, TGSI_CHAN_W);
2318
2319 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2320 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2321 target = mach->SamplerViews[unit].Resource;
2322 }
2323 else {
2324 target = inst->Texture.Texture;
2325 }
2326 switch(target) {
2327 case TGSI_TEXTURE_3D:
2328 case TGSI_TEXTURE_2D_ARRAY:
2329 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2330 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2331 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2332 /* fallthrough */
2333 case TGSI_TEXTURE_2D:
2334 case TGSI_TEXTURE_RECT:
2335 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2336 case TGSI_TEXTURE_SHADOW2D:
2337 case TGSI_TEXTURE_SHADOWRECT:
2338 case TGSI_TEXTURE_1D_ARRAY:
2339 case TGSI_TEXTURE_2D_MSAA:
2340 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2341 /* fallthrough */
2342 case TGSI_TEXTURE_BUFFER:
2343 case TGSI_TEXTURE_1D:
2344 case TGSI_TEXTURE_SHADOW1D:
2345 IFETCH(&r[0], 0, TGSI_CHAN_X);
2346 break;
2347 default:
2348 assert(0);
2349 break;
2350 }
2351
2352 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2353 offsets, rgba);
2354
2355 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2356 r[0].f[j] = rgba[0][j];
2357 r[1].f[j] = rgba[1][j];
2358 r[2].f[j] = rgba[2][j];
2359 r[3].f[j] = rgba[3][j];
2360 }
2361
2362 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2363 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2364 unsigned char swizzles[4];
2365 swizzles[0] = inst->Src[1].Register.SwizzleX;
2366 swizzles[1] = inst->Src[1].Register.SwizzleY;
2367 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2368 swizzles[3] = inst->Src[1].Register.SwizzleW;
2369
2370 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2371 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2372 store_dest(mach, &r[swizzles[chan]],
2373 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2374 }
2375 }
2376 }
2377 else {
2378 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2379 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2380 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2381 }
2382 }
2383 }
2384 }
2385
2386 static void
2387 exec_txq(struct tgsi_exec_machine *mach,
2388 const struct tgsi_full_instruction *inst)
2389 {
2390 int result[4];
2391 union tgsi_exec_channel r[4], src;
2392 uint chan;
2393 uint unit;
2394 int i,j;
2395
2396 unit = fetch_sampler_unit(mach, inst, 1);
2397
2398 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2399
2400 /* XXX: This interface can't return per-pixel values */
2401 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2402
2403 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2404 for (j = 0; j < 4; j++) {
2405 r[j].i[i] = result[j];
2406 }
2407 }
2408
2409 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2410 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2411 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2412 TGSI_EXEC_DATA_INT);
2413 }
2414 }
2415 }
2416
2417 static void
2418 exec_sample(struct tgsi_exec_machine *mach,
2419 const struct tgsi_full_instruction *inst,
2420 uint modifier, boolean compare)
2421 {
2422 const uint resource_unit = inst->Src[1].Register.Index;
2423 const uint sampler_unit = inst->Src[2].Register.Index;
2424 union tgsi_exec_channel r[5], c1;
2425 const union tgsi_exec_channel *lod = &ZeroVec;
2426 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2427 uint chan;
2428 unsigned char swizzles[4];
2429 int8_t offsets[3];
2430
2431 /* always fetch all 3 offsets, overkill but keeps code simple */
2432 fetch_texel_offsets(mach, inst, offsets);
2433
2434 assert(modifier != TEX_MODIFIER_PROJECTED);
2435
2436 if (modifier != TEX_MODIFIER_NONE) {
2437 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2438 FETCH(&c1, 3, TGSI_CHAN_X);
2439 lod = &c1;
2440 control = TGSI_SAMPLER_LOD_BIAS;
2441 }
2442 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2443 FETCH(&c1, 3, TGSI_CHAN_X);
2444 lod = &c1;
2445 control = TGSI_SAMPLER_LOD_EXPLICIT;
2446 }
2447 else {
2448 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2449 control = TGSI_SAMPLER_LOD_ZERO;
2450 }
2451 }
2452
2453 FETCH(&r[0], 0, TGSI_CHAN_X);
2454
2455 switch (mach->SamplerViews[resource_unit].Resource) {
2456 case TGSI_TEXTURE_1D:
2457 if (compare) {
2458 FETCH(&r[2], 3, TGSI_CHAN_X);
2459 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2460 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2461 NULL, offsets, control,
2462 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2463 }
2464 else {
2465 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2466 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2467 NULL, offsets, control,
2468 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2469 }
2470 break;
2471
2472 case TGSI_TEXTURE_1D_ARRAY:
2473 case TGSI_TEXTURE_2D:
2474 case TGSI_TEXTURE_RECT:
2475 FETCH(&r[1], 0, TGSI_CHAN_Y);
2476 if (compare) {
2477 FETCH(&r[2], 3, TGSI_CHAN_X);
2478 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2479 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2480 NULL, offsets, control,
2481 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2482 }
2483 else {
2484 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2485 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2486 NULL, offsets, control,
2487 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2488 }
2489 break;
2490
2491 case TGSI_TEXTURE_2D_ARRAY:
2492 case TGSI_TEXTURE_3D:
2493 case TGSI_TEXTURE_CUBE:
2494 FETCH(&r[1], 0, TGSI_CHAN_Y);
2495 FETCH(&r[2], 0, TGSI_CHAN_Z);
2496 if(compare) {
2497 FETCH(&r[3], 3, TGSI_CHAN_X);
2498 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2499 &r[0], &r[1], &r[2], &r[3], lod,
2500 NULL, offsets, control,
2501 &r[0], &r[1], &r[2], &r[3]);
2502 }
2503 else {
2504 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2505 &r[0], &r[1], &r[2], &ZeroVec, lod,
2506 NULL, offsets, control,
2507 &r[0], &r[1], &r[2], &r[3]);
2508 }
2509 break;
2510
2511 case TGSI_TEXTURE_CUBE_ARRAY:
2512 FETCH(&r[1], 0, TGSI_CHAN_Y);
2513 FETCH(&r[2], 0, TGSI_CHAN_Z);
2514 FETCH(&r[3], 0, TGSI_CHAN_W);
2515 if(compare) {
2516 FETCH(&r[4], 3, TGSI_CHAN_X);
2517 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2518 &r[0], &r[1], &r[2], &r[3], &r[4],
2519 NULL, offsets, control,
2520 &r[0], &r[1], &r[2], &r[3]);
2521 }
2522 else {
2523 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2524 &r[0], &r[1], &r[2], &r[3], lod,
2525 NULL, offsets, control,
2526 &r[0], &r[1], &r[2], &r[3]);
2527 }
2528 break;
2529
2530
2531 default:
2532 assert(0);
2533 }
2534
2535 swizzles[0] = inst->Src[1].Register.SwizzleX;
2536 swizzles[1] = inst->Src[1].Register.SwizzleY;
2537 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2538 swizzles[3] = inst->Src[1].Register.SwizzleW;
2539
2540 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2541 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2542 store_dest(mach, &r[swizzles[chan]],
2543 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2544 }
2545 }
2546 }
2547
2548 static void
2549 exec_sample_d(struct tgsi_exec_machine *mach,
2550 const struct tgsi_full_instruction *inst)
2551 {
2552 const uint resource_unit = inst->Src[1].Register.Index;
2553 const uint sampler_unit = inst->Src[2].Register.Index;
2554 union tgsi_exec_channel r[4];
2555 float derivs[3][2][TGSI_QUAD_SIZE];
2556 uint chan;
2557 unsigned char swizzles[4];
2558 int8_t offsets[3];
2559
2560 /* always fetch all 3 offsets, overkill but keeps code simple */
2561 fetch_texel_offsets(mach, inst, offsets);
2562
2563 FETCH(&r[0], 0, TGSI_CHAN_X);
2564
2565 switch (mach->SamplerViews[resource_unit].Resource) {
2566 case TGSI_TEXTURE_1D:
2567 case TGSI_TEXTURE_1D_ARRAY:
2568 /* only 1D array actually needs Y */
2569 FETCH(&r[1], 0, TGSI_CHAN_Y);
2570
2571 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2572
2573 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2574 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2575 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2576 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2577 break;
2578
2579 case TGSI_TEXTURE_2D:
2580 case TGSI_TEXTURE_RECT:
2581 case TGSI_TEXTURE_2D_ARRAY:
2582 /* only 2D array actually needs Z */
2583 FETCH(&r[1], 0, TGSI_CHAN_Y);
2584 FETCH(&r[2], 0, TGSI_CHAN_Z);
2585
2586 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2587 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2588
2589 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2590 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2591 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2592 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2593 break;
2594
2595 case TGSI_TEXTURE_3D:
2596 case TGSI_TEXTURE_CUBE:
2597 case TGSI_TEXTURE_CUBE_ARRAY:
2598 /* only cube array actually needs W */
2599 FETCH(&r[1], 0, TGSI_CHAN_Y);
2600 FETCH(&r[2], 0, TGSI_CHAN_Z);
2601 FETCH(&r[3], 0, TGSI_CHAN_W);
2602
2603 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2604 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2605 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2606
2607 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2608 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2609 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2610 &r[0], &r[1], &r[2], &r[3]);
2611 break;
2612
2613 default:
2614 assert(0);
2615 }
2616
2617 swizzles[0] = inst->Src[1].Register.SwizzleX;
2618 swizzles[1] = inst->Src[1].Register.SwizzleY;
2619 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2620 swizzles[3] = inst->Src[1].Register.SwizzleW;
2621
2622 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2623 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2624 store_dest(mach, &r[swizzles[chan]],
2625 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2626 }
2627 }
2628 }
2629
2630
2631 /**
2632 * Evaluate a constant-valued coefficient at the position of the
2633 * current quad.
2634 */
2635 static void
2636 eval_constant_coef(
2637 struct tgsi_exec_machine *mach,
2638 unsigned attrib,
2639 unsigned chan )
2640 {
2641 unsigned i;
2642
2643 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2644 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2645 }
2646 }
2647
2648 /**
2649 * Evaluate a linear-valued coefficient at the position of the
2650 * current quad.
2651 */
2652 static void
2653 eval_linear_coef(
2654 struct tgsi_exec_machine *mach,
2655 unsigned attrib,
2656 unsigned chan )
2657 {
2658 const float x = mach->QuadPos.xyzw[0].f[0];
2659 const float y = mach->QuadPos.xyzw[1].f[0];
2660 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2661 const float dady = mach->InterpCoefs[attrib].dady[chan];
2662 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2663 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2664 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2665 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2666 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2667 }
2668
2669 /**
2670 * Evaluate a perspective-valued coefficient at the position of the
2671 * current quad.
2672 */
2673 static void
2674 eval_perspective_coef(
2675 struct tgsi_exec_machine *mach,
2676 unsigned attrib,
2677 unsigned chan )
2678 {
2679 const float x = mach->QuadPos.xyzw[0].f[0];
2680 const float y = mach->QuadPos.xyzw[1].f[0];
2681 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2682 const float dady = mach->InterpCoefs[attrib].dady[chan];
2683 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2684 const float *w = mach->QuadPos.xyzw[3].f;
2685 /* divide by W here */
2686 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2687 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2688 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2689 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2690 }
2691
2692
2693 typedef void (* eval_coef_func)(
2694 struct tgsi_exec_machine *mach,
2695 unsigned attrib,
2696 unsigned chan );
2697
2698 static void
2699 exec_declaration(struct tgsi_exec_machine *mach,
2700 const struct tgsi_full_declaration *decl)
2701 {
2702 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2703 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2704 return;
2705 }
2706
2707 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
2708 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2709 uint first, last, mask;
2710
2711 first = decl->Range.First;
2712 last = decl->Range.Last;
2713 mask = decl->Declaration.UsageMask;
2714
2715 /* XXX we could remove this special-case code since
2716 * mach->InterpCoefs[first].a0 should already have the
2717 * front/back-face value. But we should first update the
2718 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2719 * Then, we could remove the tgsi_exec_machine::Face field.
2720 */
2721 /* XXX make FACE a system value */
2722 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2723 uint i;
2724
2725 assert(decl->Semantic.Index == 0);
2726 assert(first == last);
2727
2728 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2729 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2730 }
2731 } else {
2732 eval_coef_func eval;
2733 uint i, j;
2734
2735 switch (decl->Interp.Interpolate) {
2736 case TGSI_INTERPOLATE_CONSTANT:
2737 eval = eval_constant_coef;
2738 break;
2739
2740 case TGSI_INTERPOLATE_LINEAR:
2741 eval = eval_linear_coef;
2742 break;
2743
2744 case TGSI_INTERPOLATE_PERSPECTIVE:
2745 eval = eval_perspective_coef;
2746 break;
2747
2748 case TGSI_INTERPOLATE_COLOR:
2749 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2750 break;
2751
2752 default:
2753 assert(0);
2754 return;
2755 }
2756
2757 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2758 if (mask & (1 << j)) {
2759 for (i = first; i <= last; i++) {
2760 eval(mach, i, j);
2761 }
2762 }
2763 }
2764 }
2765
2766 if (DEBUG_EXECUTION) {
2767 uint i, j;
2768 for (i = first; i <= last; ++i) {
2769 debug_printf("IN[%2u] = ", i);
2770 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2771 if (j > 0) {
2772 debug_printf(" ");
2773 }
2774 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2775 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2776 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2777 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2778 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2779 }
2780 }
2781 }
2782 }
2783 }
2784
2785 }
2786
2787 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2788 const union tgsi_exec_channel *src);
2789
2790 static void
2791 exec_scalar_unary(struct tgsi_exec_machine *mach,
2792 const struct tgsi_full_instruction *inst,
2793 micro_unary_op op,
2794 enum tgsi_exec_datatype dst_datatype,
2795 enum tgsi_exec_datatype src_datatype)
2796 {
2797 unsigned int chan;
2798 union tgsi_exec_channel src;
2799 union tgsi_exec_channel dst;
2800
2801 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2802 op(&dst, &src);
2803 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2804 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2805 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2806 }
2807 }
2808 }
2809
2810 static void
2811 exec_vector_unary(struct tgsi_exec_machine *mach,
2812 const struct tgsi_full_instruction *inst,
2813 micro_unary_op op,
2814 enum tgsi_exec_datatype dst_datatype,
2815 enum tgsi_exec_datatype src_datatype)
2816 {
2817 unsigned int chan;
2818 struct tgsi_exec_vector dst;
2819
2820 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2821 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2822 union tgsi_exec_channel src;
2823
2824 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2825 op(&dst.xyzw[chan], &src);
2826 }
2827 }
2828 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2829 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2830 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2831 }
2832 }
2833 }
2834
2835 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2836 const union tgsi_exec_channel *src0,
2837 const union tgsi_exec_channel *src1);
2838
2839 static void
2840 exec_scalar_binary(struct tgsi_exec_machine *mach,
2841 const struct tgsi_full_instruction *inst,
2842 micro_binary_op op,
2843 enum tgsi_exec_datatype dst_datatype,
2844 enum tgsi_exec_datatype src_datatype)
2845 {
2846 unsigned int chan;
2847 union tgsi_exec_channel src[2];
2848 union tgsi_exec_channel dst;
2849
2850 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2851 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2852 op(&dst, &src[0], &src[1]);
2853 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2854 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2855 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2856 }
2857 }
2858 }
2859
2860 static void
2861 exec_vector_binary(struct tgsi_exec_machine *mach,
2862 const struct tgsi_full_instruction *inst,
2863 micro_binary_op op,
2864 enum tgsi_exec_datatype dst_datatype,
2865 enum tgsi_exec_datatype src_datatype)
2866 {
2867 unsigned int chan;
2868 struct tgsi_exec_vector dst;
2869
2870 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2871 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2872 union tgsi_exec_channel src[2];
2873
2874 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2875 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2876 op(&dst.xyzw[chan], &src[0], &src[1]);
2877 }
2878 }
2879 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2880 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2881 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2882 }
2883 }
2884 }
2885
2886 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2887 const union tgsi_exec_channel *src0,
2888 const union tgsi_exec_channel *src1,
2889 const union tgsi_exec_channel *src2);
2890
2891 static void
2892 exec_vector_trinary(struct tgsi_exec_machine *mach,
2893 const struct tgsi_full_instruction *inst,
2894 micro_trinary_op op,
2895 enum tgsi_exec_datatype dst_datatype,
2896 enum tgsi_exec_datatype src_datatype)
2897 {
2898 unsigned int chan;
2899 struct tgsi_exec_vector dst;
2900
2901 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2902 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2903 union tgsi_exec_channel src[3];
2904
2905 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2906 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2907 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2908 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2909 }
2910 }
2911 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2912 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2913 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2914 }
2915 }
2916 }
2917
2918 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2919 const union tgsi_exec_channel *src0,
2920 const union tgsi_exec_channel *src1,
2921 const union tgsi_exec_channel *src2,
2922 const union tgsi_exec_channel *src3);
2923
2924 static void
2925 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2926 const struct tgsi_full_instruction *inst,
2927 micro_quaternary_op op,
2928 enum tgsi_exec_datatype dst_datatype,
2929 enum tgsi_exec_datatype src_datatype)
2930 {
2931 unsigned int chan;
2932 struct tgsi_exec_vector dst;
2933
2934 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2935 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2936 union tgsi_exec_channel src[4];
2937
2938 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2939 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2940 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2941 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2942 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2943 }
2944 }
2945 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2946 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2947 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2948 }
2949 }
2950 }
2951
2952 static void
2953 exec_dp3(struct tgsi_exec_machine *mach,
2954 const struct tgsi_full_instruction *inst)
2955 {
2956 unsigned int chan;
2957 union tgsi_exec_channel arg[3];
2958
2959 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2960 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2961 micro_mul(&arg[2], &arg[0], &arg[1]);
2962
2963 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2964 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2965 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2966 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2967 }
2968
2969 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2970 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2971 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2972 }
2973 }
2974 }
2975
2976 static void
2977 exec_dp4(struct tgsi_exec_machine *mach,
2978 const struct tgsi_full_instruction *inst)
2979 {
2980 unsigned int chan;
2981 union tgsi_exec_channel arg[3];
2982
2983 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2984 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2985 micro_mul(&arg[2], &arg[0], &arg[1]);
2986
2987 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2988 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2989 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2990 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2991 }
2992
2993 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2994 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2995 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2996 }
2997 }
2998 }
2999
3000 static void
3001 exec_dp2a(struct tgsi_exec_machine *mach,
3002 const struct tgsi_full_instruction *inst)
3003 {
3004 unsigned int chan;
3005 union tgsi_exec_channel arg[3];
3006
3007 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3008 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3009 micro_mul(&arg[2], &arg[0], &arg[1]);
3010
3011 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3012 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3013 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3014
3015 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3016 micro_add(&arg[0], &arg[0], &arg[1]);
3017
3018 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3019 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3020 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3021 }
3022 }
3023 }
3024
3025 static void
3026 exec_dph(struct tgsi_exec_machine *mach,
3027 const struct tgsi_full_instruction *inst)
3028 {
3029 unsigned int chan;
3030 union tgsi_exec_channel arg[3];
3031
3032 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3033 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3034 micro_mul(&arg[2], &arg[0], &arg[1]);
3035
3036 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3037 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3038 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3039
3040 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3041 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3042 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3043
3044 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3045 micro_add(&arg[0], &arg[0], &arg[1]);
3046
3047 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3048 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3049 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3050 }
3051 }
3052 }
3053
3054 static void
3055 exec_dp2(struct tgsi_exec_machine *mach,
3056 const struct tgsi_full_instruction *inst)
3057 {
3058 unsigned int chan;
3059 union tgsi_exec_channel arg[3];
3060
3061 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3062 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3063 micro_mul(&arg[2], &arg[0], &arg[1]);
3064
3065 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3066 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3067 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3068
3069 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3070 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3071 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3072 }
3073 }
3074 }
3075
3076 static void
3077 exec_pk2h(struct tgsi_exec_machine *mach,
3078 const struct tgsi_full_instruction *inst)
3079 {
3080 unsigned chan;
3081 union tgsi_exec_channel arg[2], dst;
3082
3083 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3084 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3085 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3086 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3087 (util_float_to_half(arg[1].f[chan]) << 16);
3088 }
3089 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3090 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3091 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3092 }
3093 }
3094 }
3095
3096 static void
3097 exec_up2h(struct tgsi_exec_machine *mach,
3098 const struct tgsi_full_instruction *inst)
3099 {
3100 unsigned chan;
3101 union tgsi_exec_channel arg, dst[2];
3102
3103 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3104 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3105 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3106 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3107 }
3108 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3109 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3110 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3111 }
3112 }
3113 }
3114
3115 static void
3116 exec_scs(struct tgsi_exec_machine *mach,
3117 const struct tgsi_full_instruction *inst)
3118 {
3119 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3120 union tgsi_exec_channel arg;
3121 union tgsi_exec_channel result;
3122
3123 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3124
3125 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3126 micro_cos(&result, &arg);
3127 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3128 }
3129 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3130 micro_sin(&result, &arg);
3131 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3132 }
3133 }
3134 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3135 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3136 }
3137 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3138 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3139 }
3140 }
3141
3142 static void
3143 exec_xpd(struct tgsi_exec_machine *mach,
3144 const struct tgsi_full_instruction *inst)
3145 {
3146 union tgsi_exec_channel r[6];
3147 union tgsi_exec_channel d[3];
3148
3149 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3150 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3151
3152 micro_mul(&r[2], &r[0], &r[1]);
3153
3154 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3155 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3156
3157 micro_mul(&r[5], &r[3], &r[4] );
3158 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3159
3160 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3161
3162 micro_mul(&r[3], &r[3], &r[2]);
3163
3164 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3165
3166 micro_mul(&r[1], &r[1], &r[5]);
3167 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3168
3169 micro_mul(&r[5], &r[5], &r[4]);
3170 micro_mul(&r[0], &r[0], &r[2]);
3171 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3172
3173 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3174 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3175 }
3176 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3177 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3178 }
3179 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3180 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3181 }
3182 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3183 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3184 }
3185 }
3186
3187 static void
3188 exec_dst(struct tgsi_exec_machine *mach,
3189 const struct tgsi_full_instruction *inst)
3190 {
3191 union tgsi_exec_channel r[2];
3192 union tgsi_exec_channel d[4];
3193
3194 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3195 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3196 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3197 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3198 }
3199 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3200 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3201 }
3202 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3203 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3204 }
3205
3206 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3207 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3208 }
3209 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3210 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3211 }
3212 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3213 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3214 }
3215 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3216 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3217 }
3218 }
3219
3220 static void
3221 exec_log(struct tgsi_exec_machine *mach,
3222 const struct tgsi_full_instruction *inst)
3223 {
3224 union tgsi_exec_channel r[3];
3225
3226 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3227 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3228 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3229 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3230 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3231 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3232 }
3233 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3234 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3235 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3236 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3237 }
3238 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3239 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3240 }
3241 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3242 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3243 }
3244 }
3245
3246 static void
3247 exec_exp(struct tgsi_exec_machine *mach,
3248 const struct tgsi_full_instruction *inst)
3249 {
3250 union tgsi_exec_channel r[3];
3251
3252 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3253 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3254 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3255 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3256 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3257 }
3258 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3259 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3260 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3261 }
3262 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3263 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3264 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3265 }
3266 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3267 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3268 }
3269 }
3270
3271 static void
3272 exec_lit(struct tgsi_exec_machine *mach,
3273 const struct tgsi_full_instruction *inst)
3274 {
3275 union tgsi_exec_channel r[3];
3276 union tgsi_exec_channel d[3];
3277
3278 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3279 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3280 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3281 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3282 micro_max(&r[1], &r[1], &ZeroVec);
3283
3284 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3285 micro_min(&r[2], &r[2], &P128Vec);
3286 micro_max(&r[2], &r[2], &M128Vec);
3287 micro_pow(&r[1], &r[1], &r[2]);
3288 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3289 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3290 }
3291 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3292 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3293 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3294 }
3295 }
3296 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3297 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3298 }
3299
3300 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3301 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3302 }
3303 }
3304
3305 static void
3306 exec_break(struct tgsi_exec_machine *mach)
3307 {
3308 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3309 /* turn off loop channels for each enabled exec channel */
3310 mach->LoopMask &= ~mach->ExecMask;
3311 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3312 UPDATE_EXEC_MASK(mach);
3313 } else {
3314 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3315
3316 mach->Switch.mask = 0x0;
3317
3318 UPDATE_EXEC_MASK(mach);
3319 }
3320 }
3321
3322 static void
3323 exec_switch(struct tgsi_exec_machine *mach,
3324 const struct tgsi_full_instruction *inst)
3325 {
3326 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3327 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3328
3329 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3330 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3331 mach->Switch.mask = 0x0;
3332 mach->Switch.defaultMask = 0x0;
3333
3334 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3335 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3336
3337 UPDATE_EXEC_MASK(mach);
3338 }
3339
3340 static void
3341 exec_case(struct tgsi_exec_machine *mach,
3342 const struct tgsi_full_instruction *inst)
3343 {
3344 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3345 union tgsi_exec_channel src;
3346 uint mask = 0;
3347
3348 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3349
3350 if (mach->Switch.selector.u[0] == src.u[0]) {
3351 mask |= 0x1;
3352 }
3353 if (mach->Switch.selector.u[1] == src.u[1]) {
3354 mask |= 0x2;
3355 }
3356 if (mach->Switch.selector.u[2] == src.u[2]) {
3357 mask |= 0x4;
3358 }
3359 if (mach->Switch.selector.u[3] == src.u[3]) {
3360 mask |= 0x8;
3361 }
3362
3363 mach->Switch.defaultMask |= mask;
3364
3365 mach->Switch.mask |= mask & prevMask;
3366
3367 UPDATE_EXEC_MASK(mach);
3368 }
3369
3370 /* FIXME: this will only work if default is last */
3371 static void
3372 exec_default(struct tgsi_exec_machine *mach)
3373 {
3374 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3375
3376 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3377
3378 UPDATE_EXEC_MASK(mach);
3379 }
3380
3381 static void
3382 exec_endswitch(struct tgsi_exec_machine *mach)
3383 {
3384 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3385 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3386
3387 UPDATE_EXEC_MASK(mach);
3388 }
3389
3390 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3391 const union tgsi_double_channel *src);
3392
3393 static void
3394 fetch_double_channel(struct tgsi_exec_machine *mach,
3395 union tgsi_double_channel *chan,
3396 const struct tgsi_full_src_register *reg,
3397 uint chan_0,
3398 uint chan_1)
3399 {
3400 union tgsi_exec_channel src[2];
3401 uint i;
3402
3403 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3404 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3405
3406 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3407 chan->u[i][0] = src[0].u[i];
3408 chan->u[i][1] = src[1].u[i];
3409 }
3410 if (reg->Register.Absolute) {
3411 micro_dabs(chan, chan);
3412 }
3413 if (reg->Register.Negate) {
3414 micro_dneg(chan, chan);
3415 }
3416 }
3417
3418 static void
3419 store_double_channel(struct tgsi_exec_machine *mach,
3420 const union tgsi_double_channel *chan,
3421 const struct tgsi_full_dst_register *reg,
3422 const struct tgsi_full_instruction *inst,
3423 uint chan_0,
3424 uint chan_1)
3425 {
3426 union tgsi_exec_channel dst[2];
3427 uint i;
3428 union tgsi_double_channel temp;
3429 const uint execmask = mach->ExecMask;
3430
3431 if (!inst->Instruction.Saturate) {
3432 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3433 if (execmask & (1 << i)) {
3434 dst[0].u[i] = chan->u[i][0];
3435 dst[1].u[i] = chan->u[i][1];
3436 }
3437 }
3438 else {
3439 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3440 if (execmask & (1 << i)) {
3441 if (chan->d[i] < 0.0)
3442 temp.d[i] = 0.0;
3443 else if (chan->d[i] > 1.0)
3444 temp.d[i] = 1.0;
3445 else
3446 temp.d[i] = chan->d[i];
3447
3448 dst[0].u[i] = temp.u[i][0];
3449 dst[1].u[i] = temp.u[i][1];
3450 }
3451 }
3452
3453 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3454 if (chan_1 != -1)
3455 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3456 }
3457
3458 static void
3459 exec_double_unary(struct tgsi_exec_machine *mach,
3460 const struct tgsi_full_instruction *inst,
3461 micro_dop op)
3462 {
3463 union tgsi_double_channel src;
3464 union tgsi_double_channel dst;
3465
3466 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3467 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3468 op(&dst, &src);
3469 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3470 }
3471 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3472 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3473 op(&dst, &src);
3474 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3475 }
3476 }
3477
3478 static void
3479 exec_double_binary(struct tgsi_exec_machine *mach,
3480 const struct tgsi_full_instruction *inst,
3481 micro_dop op,
3482 enum tgsi_exec_datatype dst_datatype)
3483 {
3484 union tgsi_double_channel src[2];
3485 union tgsi_double_channel dst;
3486 int first_dest_chan, second_dest_chan;
3487 int wmask;
3488
3489 wmask = inst->Dst[0].Register.WriteMask;
3490 /* these are & because of the way DSLT etc store their destinations */
3491 if (wmask & TGSI_WRITEMASK_XY) {
3492 first_dest_chan = TGSI_CHAN_X;
3493 second_dest_chan = TGSI_CHAN_Y;
3494 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3495 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3496 second_dest_chan = -1;
3497 }
3498
3499 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3500 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3501 op(&dst, src);
3502 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3503 }
3504
3505 if (wmask & TGSI_WRITEMASK_ZW) {
3506 first_dest_chan = TGSI_CHAN_Z;
3507 second_dest_chan = TGSI_CHAN_W;
3508 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3509 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3510 second_dest_chan = -1;
3511 }
3512
3513 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3514 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3515 op(&dst, src);
3516 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3517 }
3518 }
3519
3520 static void
3521 exec_double_trinary(struct tgsi_exec_machine *mach,
3522 const struct tgsi_full_instruction *inst,
3523 micro_dop op)
3524 {
3525 union tgsi_double_channel src[3];
3526 union tgsi_double_channel dst;
3527
3528 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3529 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3530 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3531 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3532 op(&dst, src);
3533 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3534 }
3535 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3536 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3537 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3538 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3539 op(&dst, src);
3540 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3541 }
3542 }
3543
3544 static void
3545 exec_f2d(struct tgsi_exec_machine *mach,
3546 const struct tgsi_full_instruction *inst)
3547 {
3548 union tgsi_exec_channel src;
3549 union tgsi_double_channel dst;
3550
3551 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3552 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3553 micro_f2d(&dst, &src);
3554 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3555 }
3556 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3557 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3558 micro_f2d(&dst, &src);
3559 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3560 }
3561 }
3562
3563 static void
3564 exec_d2f(struct tgsi_exec_machine *mach,
3565 const struct tgsi_full_instruction *inst)
3566 {
3567 union tgsi_double_channel src;
3568 union tgsi_exec_channel dst;
3569 int wm = inst->Dst[0].Register.WriteMask;
3570 int i;
3571 int bit;
3572 for (i = 0; i < 2; i++) {
3573 bit = ffs(wm);
3574 if (bit) {
3575 wm &= ~(1 << (bit - 1));
3576 if (i == 0)
3577 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3578 else
3579 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3580 micro_d2f(&dst, &src);
3581 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3582 }
3583 }
3584 }
3585
3586 static void
3587 exec_i2d(struct tgsi_exec_machine *mach,
3588 const struct tgsi_full_instruction *inst)
3589 {
3590 union tgsi_exec_channel src;
3591 union tgsi_double_channel dst;
3592
3593 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3594 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3595 micro_i2d(&dst, &src);
3596 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3597 }
3598 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3599 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3600 micro_i2d(&dst, &src);
3601 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3602 }
3603 }
3604
3605 static void
3606 exec_d2i(struct tgsi_exec_machine *mach,
3607 const struct tgsi_full_instruction *inst)
3608 {
3609 union tgsi_double_channel src;
3610 union tgsi_exec_channel dst;
3611 int wm = inst->Dst[0].Register.WriteMask;
3612 int i;
3613 int bit;
3614 for (i = 0; i < 2; i++) {
3615 bit = ffs(wm);
3616 if (bit) {
3617 wm &= ~(1 << (bit - 1));
3618 if (i == 0)
3619 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3620 else
3621 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3622 micro_d2i(&dst, &src);
3623 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3624 }
3625 }
3626 }
3627 static void
3628 exec_u2d(struct tgsi_exec_machine *mach,
3629 const struct tgsi_full_instruction *inst)
3630 {
3631 union tgsi_exec_channel src;
3632 union tgsi_double_channel dst;
3633
3634 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3635 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3636 micro_u2d(&dst, &src);
3637 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3638 }
3639 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3640 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3641 micro_u2d(&dst, &src);
3642 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3643 }
3644 }
3645
3646 static void
3647 exec_d2u(struct tgsi_exec_machine *mach,
3648 const struct tgsi_full_instruction *inst)
3649 {
3650 union tgsi_double_channel src;
3651 union tgsi_exec_channel dst;
3652 int wm = inst->Dst[0].Register.WriteMask;
3653 int i;
3654 int bit;
3655 for (i = 0; i < 2; i++) {
3656 bit = ffs(wm);
3657 if (bit) {
3658 wm &= ~(1 << (bit - 1));
3659 if (i == 0)
3660 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3661 else
3662 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3663 micro_d2u(&dst, &src);
3664 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3665 }
3666 }
3667 }
3668
3669 static void
3670 exec_dldexp(struct tgsi_exec_machine *mach,
3671 const struct tgsi_full_instruction *inst)
3672 {
3673 union tgsi_double_channel src0;
3674 union tgsi_exec_channel src1;
3675 union tgsi_double_channel dst;
3676 int wmask;
3677
3678 wmask = inst->Dst[0].Register.WriteMask;
3679 if (wmask & TGSI_WRITEMASK_XY) {
3680 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3681 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3682 micro_dldexp(&dst, &src0, &src1);
3683 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3684 }
3685
3686 if (wmask & TGSI_WRITEMASK_ZW) {
3687 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3688 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3689 micro_dldexp(&dst, &src0, &src1);
3690 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3691 }
3692 }
3693
3694 static void
3695 exec_dfracexp(struct tgsi_exec_machine *mach,
3696 const struct tgsi_full_instruction *inst)
3697 {
3698 union tgsi_double_channel src;
3699 union tgsi_double_channel dst;
3700 union tgsi_exec_channel dst_exp;
3701
3702 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3703 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3704 micro_dfracexp(&dst, &dst_exp, &src);
3705 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3706 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3707 }
3708 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3709 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3710 micro_dfracexp(&dst, &dst_exp, &src);
3711 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3712 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3713 }
3714 }
3715
3716 static int
3717 get_image_coord_dim(unsigned tgsi_tex)
3718 {
3719 int dim;
3720 switch (tgsi_tex) {
3721 case TGSI_TEXTURE_BUFFER:
3722 case TGSI_TEXTURE_1D:
3723 dim = 1;
3724 break;
3725 case TGSI_TEXTURE_2D:
3726 case TGSI_TEXTURE_RECT:
3727 case TGSI_TEXTURE_1D_ARRAY:
3728 case TGSI_TEXTURE_2D_MSAA:
3729 dim = 2;
3730 break;
3731 case TGSI_TEXTURE_3D:
3732 case TGSI_TEXTURE_CUBE:
3733 case TGSI_TEXTURE_2D_ARRAY:
3734 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3735 case TGSI_TEXTURE_CUBE_ARRAY:
3736 dim = 3;
3737 break;
3738 default:
3739 assert(!"unknown texture target");
3740 dim = 0;
3741 break;
3742 }
3743
3744 return dim;
3745 }
3746
3747 static int
3748 get_image_coord_sample(unsigned tgsi_tex)
3749 {
3750 int sample = 0;
3751 switch (tgsi_tex) {
3752 case TGSI_TEXTURE_2D_MSAA:
3753 sample = 3;
3754 break;
3755 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3756 sample = 4;
3757 break;
3758 default:
3759 break;
3760 }
3761 return sample;
3762 }
3763
3764 static void
3765 exec_load_img(struct tgsi_exec_machine *mach,
3766 const struct tgsi_full_instruction *inst)
3767 {
3768 union tgsi_exec_channel r[4], sample_r;
3769 uint unit;
3770 int sample;
3771 int i, j;
3772 int dim;
3773 uint chan;
3774 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3775 struct tgsi_image_params params;
3776 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3777
3778 unit = fetch_sampler_unit(mach, inst, 0);
3779 dim = get_image_coord_dim(inst->Memory.Texture);
3780 sample = get_image_coord_sample(inst->Memory.Texture);
3781 assert(dim <= 3);
3782
3783 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3784 params.unit = unit;
3785 params.tgsi_tex_instr = inst->Memory.Texture;
3786 params.format = inst->Memory.Format;
3787
3788 for (i = 0; i < dim; i++) {
3789 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3790 }
3791
3792 if (sample)
3793 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3794
3795 mach->Image->load(mach->Image, &params,
3796 r[0].i, r[1].i, r[2].i, sample_r.i,
3797 rgba);
3798 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3799 r[0].f[j] = rgba[0][j];
3800 r[1].f[j] = rgba[1][j];
3801 r[2].f[j] = rgba[2][j];
3802 r[3].f[j] = rgba[3][j];
3803 }
3804 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3805 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3806 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3807 }
3808 }
3809 }
3810
3811 static void
3812 exec_load_buf(struct tgsi_exec_machine *mach,
3813 const struct tgsi_full_instruction *inst)
3814 {
3815 union tgsi_exec_channel r[4];
3816 uint unit;
3817 int j;
3818 uint chan;
3819 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3820 struct tgsi_buffer_params params;
3821 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3822
3823 unit = fetch_sampler_unit(mach, inst, 0);
3824
3825 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3826 params.unit = unit;
3827 IFETCH(&r[0], 1, TGSI_CHAN_X);
3828
3829 mach->Buffer->load(mach->Buffer, &params,
3830 r[0].i, rgba);
3831 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3832 r[0].f[j] = rgba[0][j];
3833 r[1].f[j] = rgba[1][j];
3834 r[2].f[j] = rgba[2][j];
3835 r[3].f[j] = rgba[3][j];
3836 }
3837 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3838 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3839 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3840 }
3841 }
3842 }
3843
3844 static void
3845 exec_load_mem(struct tgsi_exec_machine *mach,
3846 const struct tgsi_full_instruction *inst)
3847 {
3848 union tgsi_exec_channel r[3];
3849 uint chan;
3850 char *ptr = mach->LocalMem;
3851 uint32_t offset;
3852 int j;
3853
3854 IFETCH(&r[0], 1, TGSI_CHAN_X);
3855 if (r[0].u[0] >= mach->LocalMemSize)
3856 return;
3857
3858 offset = r[0].u[0];
3859 ptr += offset;
3860
3861 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3862 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3863 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3864 memcpy(&r[chan].u[j], ptr + (4 * chan), 4);
3865 }
3866 }
3867 }
3868
3869 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3870 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3871 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3872 }
3873 }
3874 }
3875
3876 static void
3877 exec_load(struct tgsi_exec_machine *mach,
3878 const struct tgsi_full_instruction *inst)
3879 {
3880 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
3881 exec_load_img(mach, inst);
3882 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
3883 exec_load_buf(mach, inst);
3884 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
3885 exec_load_mem(mach, inst);
3886 }
3887
3888 static void
3889 exec_store_img(struct tgsi_exec_machine *mach,
3890 const struct tgsi_full_instruction *inst)
3891 {
3892 union tgsi_exec_channel r[3], sample_r;
3893 union tgsi_exec_channel value[4];
3894 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3895 struct tgsi_image_params params;
3896 int dim;
3897 int sample;
3898 int i, j;
3899 uint unit;
3900 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3901 unit = inst->Dst[0].Register.Index;
3902 dim = get_image_coord_dim(inst->Memory.Texture);
3903 sample = get_image_coord_sample(inst->Memory.Texture);
3904 assert(dim <= 3);
3905
3906 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3907 params.unit = unit;
3908 params.tgsi_tex_instr = inst->Memory.Texture;
3909 params.format = inst->Memory.Format;
3910
3911 for (i = 0; i < dim; i++) {
3912 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
3913 }
3914
3915 for (i = 0; i < 4; i++) {
3916 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3917 }
3918 if (sample)
3919 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
3920
3921 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3922 rgba[0][j] = value[0].f[j];
3923 rgba[1][j] = value[1].f[j];
3924 rgba[2][j] = value[2].f[j];
3925 rgba[3][j] = value[3].f[j];
3926 }
3927
3928 mach->Image->store(mach->Image, &params,
3929 r[0].i, r[1].i, r[2].i, sample_r.i,
3930 rgba);
3931 }
3932
3933 static void
3934 exec_store_buf(struct tgsi_exec_machine *mach,
3935 const struct tgsi_full_instruction *inst)
3936 {
3937 union tgsi_exec_channel r[3];
3938 union tgsi_exec_channel value[4];
3939 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3940 struct tgsi_buffer_params params;
3941 int i, j;
3942 uint unit;
3943 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3944
3945 unit = inst->Dst[0].Register.Index;
3946
3947 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3948 params.unit = unit;
3949 params.writemask = inst->Dst[0].Register.WriteMask;
3950
3951 IFETCH(&r[0], 0, TGSI_CHAN_X);
3952 for (i = 0; i < 4; i++) {
3953 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3954 }
3955
3956 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3957 rgba[0][j] = value[0].f[j];
3958 rgba[1][j] = value[1].f[j];
3959 rgba[2][j] = value[2].f[j];
3960 rgba[3][j] = value[3].f[j];
3961 }
3962
3963 mach->Buffer->store(mach->Buffer, &params,
3964 r[0].i,
3965 rgba);
3966 }
3967
3968 static void
3969 exec_store_mem(struct tgsi_exec_machine *mach,
3970 const struct tgsi_full_instruction *inst)
3971 {
3972 union tgsi_exec_channel r[3];
3973 union tgsi_exec_channel value[4];
3974 uint i, chan;
3975 char *ptr = mach->LocalMem;
3976 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3977 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3978
3979 IFETCH(&r[0], 0, TGSI_CHAN_X);
3980
3981 for (i = 0; i < 4; i++) {
3982 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3983 }
3984
3985 if (r[0].u[0] >= mach->LocalMemSize)
3986 return;
3987 ptr += r[0].u[0];
3988
3989 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3990 if (execmask & (1 << i)) {
3991 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3992 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3993 memcpy(ptr + (chan * 4), &value[chan].u[0], 4);
3994 }
3995 }
3996 }
3997 }
3998 }
3999
4000 static void
4001 exec_store(struct tgsi_exec_machine *mach,
4002 const struct tgsi_full_instruction *inst)
4003 {
4004 if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE)
4005 exec_store_img(mach, inst);
4006 else if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
4007 exec_store_buf(mach, inst);
4008 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
4009 exec_store_mem(mach, inst);
4010 }
4011
4012 static void
4013 exec_atomop_img(struct tgsi_exec_machine *mach,
4014 const struct tgsi_full_instruction *inst)
4015 {
4016 union tgsi_exec_channel r[4], sample_r;
4017 union tgsi_exec_channel value[4], value2[4];
4018 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4019 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4020 struct tgsi_image_params params;
4021 int dim;
4022 int sample;
4023 int i, j;
4024 uint unit, chan;
4025 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4026 unit = fetch_sampler_unit(mach, inst, 0);
4027 dim = get_image_coord_dim(inst->Memory.Texture);
4028 sample = get_image_coord_sample(inst->Memory.Texture);
4029 assert(dim <= 3);
4030
4031 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4032 params.unit = unit;
4033 params.tgsi_tex_instr = inst->Memory.Texture;
4034 params.format = inst->Memory.Format;
4035
4036 for (i = 0; i < dim; i++) {
4037 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
4038 }
4039
4040 for (i = 0; i < 4; i++) {
4041 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4042 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4043 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4044 }
4045 if (sample)
4046 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
4047
4048 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4049 rgba[0][j] = value[0].f[j];
4050 rgba[1][j] = value[1].f[j];
4051 rgba[2][j] = value[2].f[j];
4052 rgba[3][j] = value[3].f[j];
4053 }
4054 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4055 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4056 rgba2[0][j] = value2[0].f[j];
4057 rgba2[1][j] = value2[1].f[j];
4058 rgba2[2][j] = value2[2].f[j];
4059 rgba2[3][j] = value2[3].f[j];
4060 }
4061 }
4062
4063 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
4064 r[0].i, r[1].i, r[2].i, sample_r.i,
4065 rgba, rgba2);
4066
4067 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4068 r[0].f[j] = rgba[0][j];
4069 r[1].f[j] = rgba[1][j];
4070 r[2].f[j] = rgba[2][j];
4071 r[3].f[j] = rgba[3][j];
4072 }
4073 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4074 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4075 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4076 }
4077 }
4078 }
4079
4080 static void
4081 exec_atomop_buf(struct tgsi_exec_machine *mach,
4082 const struct tgsi_full_instruction *inst)
4083 {
4084 union tgsi_exec_channel r[4];
4085 union tgsi_exec_channel value[4], value2[4];
4086 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4087 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4088 struct tgsi_buffer_params params;
4089 int i, j;
4090 uint unit, chan;
4091 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4092
4093 unit = fetch_sampler_unit(mach, inst, 0);
4094
4095 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4096 params.unit = unit;
4097 params.writemask = inst->Dst[0].Register.WriteMask;
4098
4099 IFETCH(&r[0], 1, TGSI_CHAN_X);
4100
4101 for (i = 0; i < 4; i++) {
4102 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4103 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4104 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4105 }
4106
4107 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4108 rgba[0][j] = value[0].f[j];
4109 rgba[1][j] = value[1].f[j];
4110 rgba[2][j] = value[2].f[j];
4111 rgba[3][j] = value[3].f[j];
4112 }
4113 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4114 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4115 rgba2[0][j] = value2[0].f[j];
4116 rgba2[1][j] = value2[1].f[j];
4117 rgba2[2][j] = value2[2].f[j];
4118 rgba2[3][j] = value2[3].f[j];
4119 }
4120 }
4121
4122 mach->Buffer->op(mach->Buffer, &params, inst->Instruction.Opcode,
4123 r[0].i,
4124 rgba, rgba2);
4125
4126 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4127 r[0].f[j] = rgba[0][j];
4128 r[1].f[j] = rgba[1][j];
4129 r[2].f[j] = rgba[2][j];
4130 r[3].f[j] = rgba[3][j];
4131 }
4132 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4133 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4134 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4135 }
4136 }
4137 }
4138
4139 static void
4140 exec_atomop_mem(struct tgsi_exec_machine *mach,
4141 const struct tgsi_full_instruction *inst)
4142 {
4143 union tgsi_exec_channel r[4];
4144 union tgsi_exec_channel value[4], value2[4];
4145 char *ptr = mach->LocalMem;
4146 uint32_t val;
4147 uint chan, i;
4148 uint32_t offset;
4149 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4150 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4151 IFETCH(&r[0], 1, TGSI_CHAN_X);
4152
4153 if (r[0].u[0] >= mach->LocalMemSize)
4154 return;
4155
4156 offset = r[0].u[0];
4157 ptr += offset;
4158 for (i = 0; i < 4; i++) {
4159 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4160 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4161 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4162 }
4163
4164 memcpy(&r[0].u[0], ptr, 4);
4165 val = r[0].u[0];
4166 switch (inst->Instruction.Opcode) {
4167 case TGSI_OPCODE_ATOMUADD:
4168 val += value[0].u[0];
4169 break;
4170 case TGSI_OPCODE_ATOMXOR:
4171 val ^= value[0].u[0];
4172 break;
4173 case TGSI_OPCODE_ATOMOR:
4174 val |= value[0].u[0];
4175 break;
4176 case TGSI_OPCODE_ATOMAND:
4177 val &= value[0].u[0];
4178 break;
4179 case TGSI_OPCODE_ATOMUMIN:
4180 val = MIN2(val, value[0].u[0]);
4181 break;
4182 case TGSI_OPCODE_ATOMUMAX:
4183 val = MAX2(val, value[0].u[0]);
4184 break;
4185 case TGSI_OPCODE_ATOMIMIN:
4186 val = MIN2(r[0].i[0], value[0].i[0]);
4187 break;
4188 case TGSI_OPCODE_ATOMIMAX:
4189 val = MAX2(r[0].i[0], value[0].i[0]);
4190 break;
4191 case TGSI_OPCODE_ATOMXCHG:
4192 val = value[0].i[0];
4193 break;
4194 case TGSI_OPCODE_ATOMCAS:
4195 if (val == value[0].u[0])
4196 val = value2[0].u[0];
4197 break;
4198 default:
4199 break;
4200 }
4201 for (i = 0; i < TGSI_QUAD_SIZE; i++)
4202 if (execmask & (1 << i))
4203 memcpy(ptr, &val, 4);
4204
4205 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4206 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4207 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4208 }
4209 }
4210 }
4211
4212 static void
4213 exec_atomop(struct tgsi_exec_machine *mach,
4214 const struct tgsi_full_instruction *inst)
4215 {
4216 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4217 exec_atomop_img(mach, inst);
4218 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
4219 exec_atomop_buf(mach, inst);
4220 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
4221 exec_atomop_mem(mach, inst);
4222 }
4223
4224 static void
4225 exec_resq_img(struct tgsi_exec_machine *mach,
4226 const struct tgsi_full_instruction *inst)
4227 {
4228 int result[4];
4229 union tgsi_exec_channel r[4];
4230 uint unit;
4231 int i, chan, j;
4232 struct tgsi_image_params params;
4233 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4234
4235 unit = fetch_sampler_unit(mach, inst, 0);
4236
4237 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4238 params.unit = unit;
4239 params.tgsi_tex_instr = inst->Memory.Texture;
4240 params.format = inst->Memory.Format;
4241
4242 mach->Image->get_dims(mach->Image, &params, result);
4243
4244 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4245 for (j = 0; j < 4; j++) {
4246 r[j].i[i] = result[j];
4247 }
4248 }
4249
4250 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4251 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4252 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4253 TGSI_EXEC_DATA_INT);
4254 }
4255 }
4256 }
4257
4258 static void
4259 exec_resq_buf(struct tgsi_exec_machine *mach,
4260 const struct tgsi_full_instruction *inst)
4261 {
4262 int result;
4263 union tgsi_exec_channel r[4];
4264 uint unit;
4265 int i, chan;
4266 struct tgsi_buffer_params params;
4267 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4268
4269 unit = fetch_sampler_unit(mach, inst, 0);
4270
4271 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4272 params.unit = unit;
4273
4274 mach->Buffer->get_dims(mach->Buffer, &params, &result);
4275
4276 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4277 r[0].i[i] = result;
4278 }
4279
4280 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4281 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4282 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4283 TGSI_EXEC_DATA_INT);
4284 }
4285 }
4286 }
4287
4288 static void
4289 exec_resq(struct tgsi_exec_machine *mach,
4290 const struct tgsi_full_instruction *inst)
4291 {
4292 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4293 exec_resq_img(mach, inst);
4294 else
4295 exec_resq_buf(mach, inst);
4296 }
4297
4298 static void
4299 micro_i2f(union tgsi_exec_channel *dst,
4300 const union tgsi_exec_channel *src)
4301 {
4302 dst->f[0] = (float)src->i[0];
4303 dst->f[1] = (float)src->i[1];
4304 dst->f[2] = (float)src->i[2];
4305 dst->f[3] = (float)src->i[3];
4306 }
4307
4308 static void
4309 micro_not(union tgsi_exec_channel *dst,
4310 const union tgsi_exec_channel *src)
4311 {
4312 dst->u[0] = ~src->u[0];
4313 dst->u[1] = ~src->u[1];
4314 dst->u[2] = ~src->u[2];
4315 dst->u[3] = ~src->u[3];
4316 }
4317
4318 static void
4319 micro_shl(union tgsi_exec_channel *dst,
4320 const union tgsi_exec_channel *src0,
4321 const union tgsi_exec_channel *src1)
4322 {
4323 unsigned masked_count;
4324 masked_count = src1->u[0] & 0x1f;
4325 dst->u[0] = src0->u[0] << masked_count;
4326 masked_count = src1->u[1] & 0x1f;
4327 dst->u[1] = src0->u[1] << masked_count;
4328 masked_count = src1->u[2] & 0x1f;
4329 dst->u[2] = src0->u[2] << masked_count;
4330 masked_count = src1->u[3] & 0x1f;
4331 dst->u[3] = src0->u[3] << masked_count;
4332 }
4333
4334 static void
4335 micro_and(union tgsi_exec_channel *dst,
4336 const union tgsi_exec_channel *src0,
4337 const union tgsi_exec_channel *src1)
4338 {
4339 dst->u[0] = src0->u[0] & src1->u[0];
4340 dst->u[1] = src0->u[1] & src1->u[1];
4341 dst->u[2] = src0->u[2] & src1->u[2];
4342 dst->u[3] = src0->u[3] & src1->u[3];
4343 }
4344
4345 static void
4346 micro_or(union tgsi_exec_channel *dst,
4347 const union tgsi_exec_channel *src0,
4348 const union tgsi_exec_channel *src1)
4349 {
4350 dst->u[0] = src0->u[0] | src1->u[0];
4351 dst->u[1] = src0->u[1] | src1->u[1];
4352 dst->u[2] = src0->u[2] | src1->u[2];
4353 dst->u[3] = src0->u[3] | src1->u[3];
4354 }
4355
4356 static void
4357 micro_xor(union tgsi_exec_channel *dst,
4358 const union tgsi_exec_channel *src0,
4359 const union tgsi_exec_channel *src1)
4360 {
4361 dst->u[0] = src0->u[0] ^ src1->u[0];
4362 dst->u[1] = src0->u[1] ^ src1->u[1];
4363 dst->u[2] = src0->u[2] ^ src1->u[2];
4364 dst->u[3] = src0->u[3] ^ src1->u[3];
4365 }
4366
4367 static void
4368 micro_mod(union tgsi_exec_channel *dst,
4369 const union tgsi_exec_channel *src0,
4370 const union tgsi_exec_channel *src1)
4371 {
4372 dst->i[0] = src0->i[0] % src1->i[0];
4373 dst->i[1] = src0->i[1] % src1->i[1];
4374 dst->i[2] = src0->i[2] % src1->i[2];
4375 dst->i[3] = src0->i[3] % src1->i[3];
4376 }
4377
4378 static void
4379 micro_f2i(union tgsi_exec_channel *dst,
4380 const union tgsi_exec_channel *src)
4381 {
4382 dst->i[0] = (int)src->f[0];
4383 dst->i[1] = (int)src->f[1];
4384 dst->i[2] = (int)src->f[2];
4385 dst->i[3] = (int)src->f[3];
4386 }
4387
4388 static void
4389 micro_fseq(union tgsi_exec_channel *dst,
4390 const union tgsi_exec_channel *src0,
4391 const union tgsi_exec_channel *src1)
4392 {
4393 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4394 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4395 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4396 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4397 }
4398
4399 static void
4400 micro_fsge(union tgsi_exec_channel *dst,
4401 const union tgsi_exec_channel *src0,
4402 const union tgsi_exec_channel *src1)
4403 {
4404 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4405 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4406 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4407 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4408 }
4409
4410 static void
4411 micro_fslt(union tgsi_exec_channel *dst,
4412 const union tgsi_exec_channel *src0,
4413 const union tgsi_exec_channel *src1)
4414 {
4415 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4416 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4417 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4418 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4419 }
4420
4421 static void
4422 micro_fsne(union tgsi_exec_channel *dst,
4423 const union tgsi_exec_channel *src0,
4424 const union tgsi_exec_channel *src1)
4425 {
4426 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4427 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4428 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4429 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4430 }
4431
4432 static void
4433 micro_idiv(union tgsi_exec_channel *dst,
4434 const union tgsi_exec_channel *src0,
4435 const union tgsi_exec_channel *src1)
4436 {
4437 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4438 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4439 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4440 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4441 }
4442
4443 static void
4444 micro_imax(union tgsi_exec_channel *dst,
4445 const union tgsi_exec_channel *src0,
4446 const union tgsi_exec_channel *src1)
4447 {
4448 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4449 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4450 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4451 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4452 }
4453
4454 static void
4455 micro_imin(union tgsi_exec_channel *dst,
4456 const union tgsi_exec_channel *src0,
4457 const union tgsi_exec_channel *src1)
4458 {
4459 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4460 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4461 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4462 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4463 }
4464
4465 static void
4466 micro_isge(union tgsi_exec_channel *dst,
4467 const union tgsi_exec_channel *src0,
4468 const union tgsi_exec_channel *src1)
4469 {
4470 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4471 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4472 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4473 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4474 }
4475
4476 static void
4477 micro_ishr(union tgsi_exec_channel *dst,
4478 const union tgsi_exec_channel *src0,
4479 const union tgsi_exec_channel *src1)
4480 {
4481 unsigned masked_count;
4482 masked_count = src1->i[0] & 0x1f;
4483 dst->i[0] = src0->i[0] >> masked_count;
4484 masked_count = src1->i[1] & 0x1f;
4485 dst->i[1] = src0->i[1] >> masked_count;
4486 masked_count = src1->i[2] & 0x1f;
4487 dst->i[2] = src0->i[2] >> masked_count;
4488 masked_count = src1->i[3] & 0x1f;
4489 dst->i[3] = src0->i[3] >> masked_count;
4490 }
4491
4492 static void
4493 micro_islt(union tgsi_exec_channel *dst,
4494 const union tgsi_exec_channel *src0,
4495 const union tgsi_exec_channel *src1)
4496 {
4497 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4498 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4499 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4500 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4501 }
4502
4503 static void
4504 micro_f2u(union tgsi_exec_channel *dst,
4505 const union tgsi_exec_channel *src)
4506 {
4507 dst->u[0] = (uint)src->f[0];
4508 dst->u[1] = (uint)src->f[1];
4509 dst->u[2] = (uint)src->f[2];
4510 dst->u[3] = (uint)src->f[3];
4511 }
4512
4513 static void
4514 micro_u2f(union tgsi_exec_channel *dst,
4515 const union tgsi_exec_channel *src)
4516 {
4517 dst->f[0] = (float)src->u[0];
4518 dst->f[1] = (float)src->u[1];
4519 dst->f[2] = (float)src->u[2];
4520 dst->f[3] = (float)src->u[3];
4521 }
4522
4523 static void
4524 micro_uadd(union tgsi_exec_channel *dst,
4525 const union tgsi_exec_channel *src0,
4526 const union tgsi_exec_channel *src1)
4527 {
4528 dst->u[0] = src0->u[0] + src1->u[0];
4529 dst->u[1] = src0->u[1] + src1->u[1];
4530 dst->u[2] = src0->u[2] + src1->u[2];
4531 dst->u[3] = src0->u[3] + src1->u[3];
4532 }
4533
4534 static void
4535 micro_udiv(union tgsi_exec_channel *dst,
4536 const union tgsi_exec_channel *src0,
4537 const union tgsi_exec_channel *src1)
4538 {
4539 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4540 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4541 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4542 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4543 }
4544
4545 static void
4546 micro_umad(union tgsi_exec_channel *dst,
4547 const union tgsi_exec_channel *src0,
4548 const union tgsi_exec_channel *src1,
4549 const union tgsi_exec_channel *src2)
4550 {
4551 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4552 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4553 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4554 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4555 }
4556
4557 static void
4558 micro_umax(union tgsi_exec_channel *dst,
4559 const union tgsi_exec_channel *src0,
4560 const union tgsi_exec_channel *src1)
4561 {
4562 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4563 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4564 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4565 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4566 }
4567
4568 static void
4569 micro_umin(union tgsi_exec_channel *dst,
4570 const union tgsi_exec_channel *src0,
4571 const union tgsi_exec_channel *src1)
4572 {
4573 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4574 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4575 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4576 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4577 }
4578
4579 static void
4580 micro_umod(union tgsi_exec_channel *dst,
4581 const union tgsi_exec_channel *src0,
4582 const union tgsi_exec_channel *src1)
4583 {
4584 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4585 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4586 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4587 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4588 }
4589
4590 static void
4591 micro_umul(union tgsi_exec_channel *dst,
4592 const union tgsi_exec_channel *src0,
4593 const union tgsi_exec_channel *src1)
4594 {
4595 dst->u[0] = src0->u[0] * src1->u[0];
4596 dst->u[1] = src0->u[1] * src1->u[1];
4597 dst->u[2] = src0->u[2] * src1->u[2];
4598 dst->u[3] = src0->u[3] * src1->u[3];
4599 }
4600
4601 static void
4602 micro_imul_hi(union tgsi_exec_channel *dst,
4603 const union tgsi_exec_channel *src0,
4604 const union tgsi_exec_channel *src1)
4605 {
4606 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4607 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4608 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4609 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4610 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4611 #undef I64M
4612 }
4613
4614 static void
4615 micro_umul_hi(union tgsi_exec_channel *dst,
4616 const union tgsi_exec_channel *src0,
4617 const union tgsi_exec_channel *src1)
4618 {
4619 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4620 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4621 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4622 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4623 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4624 #undef U64M
4625 }
4626
4627 static void
4628 micro_useq(union tgsi_exec_channel *dst,
4629 const union tgsi_exec_channel *src0,
4630 const union tgsi_exec_channel *src1)
4631 {
4632 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4633 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4634 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4635 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4636 }
4637
4638 static void
4639 micro_usge(union tgsi_exec_channel *dst,
4640 const union tgsi_exec_channel *src0,
4641 const union tgsi_exec_channel *src1)
4642 {
4643 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4644 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4645 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4646 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4647 }
4648
4649 static void
4650 micro_ushr(union tgsi_exec_channel *dst,
4651 const union tgsi_exec_channel *src0,
4652 const union tgsi_exec_channel *src1)
4653 {
4654 unsigned masked_count;
4655 masked_count = src1->u[0] & 0x1f;
4656 dst->u[0] = src0->u[0] >> masked_count;
4657 masked_count = src1->u[1] & 0x1f;
4658 dst->u[1] = src0->u[1] >> masked_count;
4659 masked_count = src1->u[2] & 0x1f;
4660 dst->u[2] = src0->u[2] >> masked_count;
4661 masked_count = src1->u[3] & 0x1f;
4662 dst->u[3] = src0->u[3] >> masked_count;
4663 }
4664
4665 static void
4666 micro_uslt(union tgsi_exec_channel *dst,
4667 const union tgsi_exec_channel *src0,
4668 const union tgsi_exec_channel *src1)
4669 {
4670 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4671 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4672 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4673 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4674 }
4675
4676 static void
4677 micro_usne(union tgsi_exec_channel *dst,
4678 const union tgsi_exec_channel *src0,
4679 const union tgsi_exec_channel *src1)
4680 {
4681 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4682 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4683 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4684 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4685 }
4686
4687 static void
4688 micro_uarl(union tgsi_exec_channel *dst,
4689 const union tgsi_exec_channel *src)
4690 {
4691 dst->i[0] = src->u[0];
4692 dst->i[1] = src->u[1];
4693 dst->i[2] = src->u[2];
4694 dst->i[3] = src->u[3];
4695 }
4696
4697 static void
4698 micro_ucmp(union tgsi_exec_channel *dst,
4699 const union tgsi_exec_channel *src0,
4700 const union tgsi_exec_channel *src1,
4701 const union tgsi_exec_channel *src2)
4702 {
4703 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4704 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4705 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4706 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4707 }
4708
4709 /**
4710 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4711 */
4712 static void
4713 micro_ibfe(union tgsi_exec_channel *dst,
4714 const union tgsi_exec_channel *src0,
4715 const union tgsi_exec_channel *src1,
4716 const union tgsi_exec_channel *src2)
4717 {
4718 int i;
4719 for (i = 0; i < 4; i++) {
4720 int width = src2->i[i] & 0x1f;
4721 int offset = src1->i[i] & 0x1f;
4722 if (width == 0)
4723 dst->i[i] = 0;
4724 else if (width + offset < 32)
4725 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4726 else
4727 dst->i[i] = src0->i[i] >> offset;
4728 }
4729 }
4730
4731 /**
4732 * Unsigned bitfield extract
4733 */
4734 static void
4735 micro_ubfe(union tgsi_exec_channel *dst,
4736 const union tgsi_exec_channel *src0,
4737 const union tgsi_exec_channel *src1,
4738 const union tgsi_exec_channel *src2)
4739 {
4740 int i;
4741 for (i = 0; i < 4; i++) {
4742 int width = src2->u[i] & 0x1f;
4743 int offset = src1->u[i] & 0x1f;
4744 if (width == 0)
4745 dst->u[i] = 0;
4746 else if (width + offset < 32)
4747 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4748 else
4749 dst->u[i] = src0->u[i] >> offset;
4750 }
4751 }
4752
4753 /**
4754 * Bitfield insert: copy low bits from src1 into a region of src0.
4755 */
4756 static void
4757 micro_bfi(union tgsi_exec_channel *dst,
4758 const union tgsi_exec_channel *src0,
4759 const union tgsi_exec_channel *src1,
4760 const union tgsi_exec_channel *src2,
4761 const union tgsi_exec_channel *src3)
4762 {
4763 int i;
4764 for (i = 0; i < 4; i++) {
4765 int width = src3->u[i] & 0x1f;
4766 int offset = src2->u[i] & 0x1f;
4767 int bitmask = ((1 << width) - 1) << offset;
4768 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4769 }
4770 }
4771
4772 static void
4773 micro_brev(union tgsi_exec_channel *dst,
4774 const union tgsi_exec_channel *src)
4775 {
4776 dst->u[0] = util_bitreverse(src->u[0]);
4777 dst->u[1] = util_bitreverse(src->u[1]);
4778 dst->u[2] = util_bitreverse(src->u[2]);
4779 dst->u[3] = util_bitreverse(src->u[3]);
4780 }
4781
4782 static void
4783 micro_popc(union tgsi_exec_channel *dst,
4784 const union tgsi_exec_channel *src)
4785 {
4786 dst->u[0] = util_bitcount(src->u[0]);
4787 dst->u[1] = util_bitcount(src->u[1]);
4788 dst->u[2] = util_bitcount(src->u[2]);
4789 dst->u[3] = util_bitcount(src->u[3]);
4790 }
4791
4792 static void
4793 micro_lsb(union tgsi_exec_channel *dst,
4794 const union tgsi_exec_channel *src)
4795 {
4796 dst->i[0] = ffs(src->u[0]) - 1;
4797 dst->i[1] = ffs(src->u[1]) - 1;
4798 dst->i[2] = ffs(src->u[2]) - 1;
4799 dst->i[3] = ffs(src->u[3]) - 1;
4800 }
4801
4802 static void
4803 micro_imsb(union tgsi_exec_channel *dst,
4804 const union tgsi_exec_channel *src)
4805 {
4806 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4807 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4808 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4809 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4810 }
4811
4812 static void
4813 micro_umsb(union tgsi_exec_channel *dst,
4814 const union tgsi_exec_channel *src)
4815 {
4816 dst->i[0] = util_last_bit(src->u[0]) - 1;
4817 dst->i[1] = util_last_bit(src->u[1]) - 1;
4818 dst->i[2] = util_last_bit(src->u[2]) - 1;
4819 dst->i[3] = util_last_bit(src->u[3]) - 1;
4820 }
4821
4822 static void
4823 exec_instruction(
4824 struct tgsi_exec_machine *mach,
4825 const struct tgsi_full_instruction *inst,
4826 int *pc )
4827 {
4828 union tgsi_exec_channel r[10];
4829
4830 (*pc)++;
4831
4832 switch (inst->Instruction.Opcode) {
4833 case TGSI_OPCODE_ARL:
4834 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4835 break;
4836
4837 case TGSI_OPCODE_MOV:
4838 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4839 break;
4840
4841 case TGSI_OPCODE_LIT:
4842 exec_lit(mach, inst);
4843 break;
4844
4845 case TGSI_OPCODE_RCP:
4846 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4847 break;
4848
4849 case TGSI_OPCODE_RSQ:
4850 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4851 break;
4852
4853 case TGSI_OPCODE_EXP:
4854 exec_exp(mach, inst);
4855 break;
4856
4857 case TGSI_OPCODE_LOG:
4858 exec_log(mach, inst);
4859 break;
4860
4861 case TGSI_OPCODE_MUL:
4862 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4863 break;
4864
4865 case TGSI_OPCODE_ADD:
4866 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4867 break;
4868
4869 case TGSI_OPCODE_DP3:
4870 exec_dp3(mach, inst);
4871 break;
4872
4873 case TGSI_OPCODE_DP4:
4874 exec_dp4(mach, inst);
4875 break;
4876
4877 case TGSI_OPCODE_DST:
4878 exec_dst(mach, inst);
4879 break;
4880
4881 case TGSI_OPCODE_MIN:
4882 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4883 break;
4884
4885 case TGSI_OPCODE_MAX:
4886 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4887 break;
4888
4889 case TGSI_OPCODE_SLT:
4890 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4891 break;
4892
4893 case TGSI_OPCODE_SGE:
4894 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4895 break;
4896
4897 case TGSI_OPCODE_MAD:
4898 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4899 break;
4900
4901 case TGSI_OPCODE_SUB:
4902 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4903 break;
4904
4905 case TGSI_OPCODE_LRP:
4906 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4907 break;
4908
4909 case TGSI_OPCODE_SQRT:
4910 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4911 break;
4912
4913 case TGSI_OPCODE_DP2A:
4914 exec_dp2a(mach, inst);
4915 break;
4916
4917 case TGSI_OPCODE_FRC:
4918 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4919 break;
4920
4921 case TGSI_OPCODE_CLAMP:
4922 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4923 break;
4924
4925 case TGSI_OPCODE_FLR:
4926 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4927 break;
4928
4929 case TGSI_OPCODE_ROUND:
4930 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4931 break;
4932
4933 case TGSI_OPCODE_EX2:
4934 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4935 break;
4936
4937 case TGSI_OPCODE_LG2:
4938 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4939 break;
4940
4941 case TGSI_OPCODE_POW:
4942 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4943 break;
4944
4945 case TGSI_OPCODE_XPD:
4946 exec_xpd(mach, inst);
4947 break;
4948
4949 case TGSI_OPCODE_ABS:
4950 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4951 break;
4952
4953 case TGSI_OPCODE_DPH:
4954 exec_dph(mach, inst);
4955 break;
4956
4957 case TGSI_OPCODE_COS:
4958 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4959 break;
4960
4961 case TGSI_OPCODE_DDX:
4962 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4963 break;
4964
4965 case TGSI_OPCODE_DDY:
4966 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4967 break;
4968
4969 case TGSI_OPCODE_KILL:
4970 exec_kill (mach, inst);
4971 break;
4972
4973 case TGSI_OPCODE_KILL_IF:
4974 exec_kill_if (mach, inst);
4975 break;
4976
4977 case TGSI_OPCODE_PK2H:
4978 exec_pk2h(mach, inst);
4979 break;
4980
4981 case TGSI_OPCODE_PK2US:
4982 assert (0);
4983 break;
4984
4985 case TGSI_OPCODE_PK4B:
4986 assert (0);
4987 break;
4988
4989 case TGSI_OPCODE_PK4UB:
4990 assert (0);
4991 break;
4992
4993 case TGSI_OPCODE_SEQ:
4994 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4995 break;
4996
4997 case TGSI_OPCODE_SGT:
4998 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4999 break;
5000
5001 case TGSI_OPCODE_SIN:
5002 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5003 break;
5004
5005 case TGSI_OPCODE_SLE:
5006 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5007 break;
5008
5009 case TGSI_OPCODE_SNE:
5010 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5011 break;
5012
5013 case TGSI_OPCODE_TEX:
5014 /* simple texture lookup */
5015 /* src[0] = texcoord */
5016 /* src[1] = sampler unit */
5017 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
5018 break;
5019
5020 case TGSI_OPCODE_TXB:
5021 /* Texture lookup with lod bias */
5022 /* src[0] = texcoord (src[0].w = LOD bias) */
5023 /* src[1] = sampler unit */
5024 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
5025 break;
5026
5027 case TGSI_OPCODE_TXD:
5028 /* Texture lookup with explict partial derivatives */
5029 /* src[0] = texcoord */
5030 /* src[1] = d[strq]/dx */
5031 /* src[2] = d[strq]/dy */
5032 /* src[3] = sampler unit */
5033 exec_txd(mach, inst);
5034 break;
5035
5036 case TGSI_OPCODE_TXL:
5037 /* Texture lookup with explit LOD */
5038 /* src[0] = texcoord (src[0].w = LOD) */
5039 /* src[1] = sampler unit */
5040 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
5041 break;
5042
5043 case TGSI_OPCODE_TXP:
5044 /* Texture lookup with projection */
5045 /* src[0] = texcoord (src[0].w = projection) */
5046 /* src[1] = sampler unit */
5047 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
5048 break;
5049
5050 case TGSI_OPCODE_TG4:
5051 /* src[0] = texcoord */
5052 /* src[1] = component */
5053 /* src[2] = sampler unit */
5054 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
5055 break;
5056
5057 case TGSI_OPCODE_LODQ:
5058 /* src[0] = texcoord */
5059 /* src[1] = sampler unit */
5060 exec_lodq(mach, inst);
5061 break;
5062
5063 case TGSI_OPCODE_UP2H:
5064 exec_up2h(mach, inst);
5065 break;
5066
5067 case TGSI_OPCODE_UP2US:
5068 assert (0);
5069 break;
5070
5071 case TGSI_OPCODE_UP4B:
5072 assert (0);
5073 break;
5074
5075 case TGSI_OPCODE_UP4UB:
5076 assert (0);
5077 break;
5078
5079 case TGSI_OPCODE_ARR:
5080 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5081 break;
5082
5083 case TGSI_OPCODE_CAL:
5084 /* skip the call if no execution channels are enabled */
5085 if (mach->ExecMask) {
5086 /* do the call */
5087
5088 /* First, record the depths of the execution stacks.
5089 * This is important for deeply nested/looped return statements.
5090 * We have to unwind the stacks by the correct amount. For a
5091 * real code generator, we could determine the number of entries
5092 * to pop off each stack with simple static analysis and avoid
5093 * implementing this data structure at run time.
5094 */
5095 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
5096 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
5097 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
5098 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
5099 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
5100 /* note that PC was already incremented above */
5101 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
5102
5103 mach->CallStackTop++;
5104
5105 /* Second, push the Cond, Loop, Cont, Func stacks */
5106 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5107 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5108 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5109 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
5110 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5111 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
5112
5113 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5114 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5115 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5116 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
5117 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5118 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
5119
5120 /* Finally, jump to the subroutine. The label is a pointer
5121 * (an instruction number) to the BGNSUB instruction.
5122 */
5123 *pc = inst->Label.Label;
5124 assert(mach->Instructions[*pc].Instruction.Opcode
5125 == TGSI_OPCODE_BGNSUB);
5126 }
5127 break;
5128
5129 case TGSI_OPCODE_RET:
5130 mach->FuncMask &= ~mach->ExecMask;
5131 UPDATE_EXEC_MASK(mach);
5132
5133 if (mach->FuncMask == 0x0) {
5134 /* really return now (otherwise, keep executing */
5135
5136 if (mach->CallStackTop == 0) {
5137 /* returning from main() */
5138 mach->CondStackTop = 0;
5139 mach->LoopStackTop = 0;
5140 *pc = -1;
5141 return;
5142 }
5143
5144 assert(mach->CallStackTop > 0);
5145 mach->CallStackTop--;
5146
5147 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5148 mach->CondMask = mach->CondStack[mach->CondStackTop];
5149
5150 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5151 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5152
5153 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5154 mach->ContMask = mach->ContStack[mach->ContStackTop];
5155
5156 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5157 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5158
5159 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5160 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5161
5162 assert(mach->FuncStackTop > 0);
5163 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5164
5165 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5166
5167 UPDATE_EXEC_MASK(mach);
5168 }
5169 break;
5170
5171 case TGSI_OPCODE_SSG:
5172 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5173 break;
5174
5175 case TGSI_OPCODE_CMP:
5176 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5177 break;
5178
5179 case TGSI_OPCODE_SCS:
5180 exec_scs(mach, inst);
5181 break;
5182
5183 case TGSI_OPCODE_DIV:
5184 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5185 break;
5186
5187 case TGSI_OPCODE_DP2:
5188 exec_dp2(mach, inst);
5189 break;
5190
5191 case TGSI_OPCODE_IF:
5192 /* push CondMask */
5193 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5194 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5195 FETCH( &r[0], 0, TGSI_CHAN_X );
5196 /* update CondMask */
5197 if( ! r[0].f[0] ) {
5198 mach->CondMask &= ~0x1;
5199 }
5200 if( ! r[0].f[1] ) {
5201 mach->CondMask &= ~0x2;
5202 }
5203 if( ! r[0].f[2] ) {
5204 mach->CondMask &= ~0x4;
5205 }
5206 if( ! r[0].f[3] ) {
5207 mach->CondMask &= ~0x8;
5208 }
5209 UPDATE_EXEC_MASK(mach);
5210 /* Todo: If CondMask==0, jump to ELSE */
5211 break;
5212
5213 case TGSI_OPCODE_UIF:
5214 /* push CondMask */
5215 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5216 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5217 IFETCH( &r[0], 0, TGSI_CHAN_X );
5218 /* update CondMask */
5219 if( ! r[0].u[0] ) {
5220 mach->CondMask &= ~0x1;
5221 }
5222 if( ! r[0].u[1] ) {
5223 mach->CondMask &= ~0x2;
5224 }
5225 if( ! r[0].u[2] ) {
5226 mach->CondMask &= ~0x4;
5227 }
5228 if( ! r[0].u[3] ) {
5229 mach->CondMask &= ~0x8;
5230 }
5231 UPDATE_EXEC_MASK(mach);
5232 /* Todo: If CondMask==0, jump to ELSE */
5233 break;
5234
5235 case TGSI_OPCODE_ELSE:
5236 /* invert CondMask wrt previous mask */
5237 {
5238 uint prevMask;
5239 assert(mach->CondStackTop > 0);
5240 prevMask = mach->CondStack[mach->CondStackTop - 1];
5241 mach->CondMask = ~mach->CondMask & prevMask;
5242 UPDATE_EXEC_MASK(mach);
5243 /* Todo: If CondMask==0, jump to ENDIF */
5244 }
5245 break;
5246
5247 case TGSI_OPCODE_ENDIF:
5248 /* pop CondMask */
5249 assert(mach->CondStackTop > 0);
5250 mach->CondMask = mach->CondStack[--mach->CondStackTop];
5251 UPDATE_EXEC_MASK(mach);
5252 break;
5253
5254 case TGSI_OPCODE_END:
5255 /* make sure we end primitives which haven't
5256 * been explicitly emitted */
5257 conditional_emit_primitive(mach);
5258 /* halt execution */
5259 *pc = -1;
5260 break;
5261
5262 case TGSI_OPCODE_PUSHA:
5263 assert (0);
5264 break;
5265
5266 case TGSI_OPCODE_POPA:
5267 assert (0);
5268 break;
5269
5270 case TGSI_OPCODE_CEIL:
5271 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5272 break;
5273
5274 case TGSI_OPCODE_I2F:
5275 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5276 break;
5277
5278 case TGSI_OPCODE_NOT:
5279 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5280 break;
5281
5282 case TGSI_OPCODE_TRUNC:
5283 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5284 break;
5285
5286 case TGSI_OPCODE_SHL:
5287 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5288 break;
5289
5290 case TGSI_OPCODE_AND:
5291 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5292 break;
5293
5294 case TGSI_OPCODE_OR:
5295 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5296 break;
5297
5298 case TGSI_OPCODE_MOD:
5299 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5300 break;
5301
5302 case TGSI_OPCODE_XOR:
5303 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5304 break;
5305
5306 case TGSI_OPCODE_SAD:
5307 assert (0);
5308 break;
5309
5310 case TGSI_OPCODE_TXF:
5311 exec_txf(mach, inst);
5312 break;
5313
5314 case TGSI_OPCODE_TXQ:
5315 exec_txq(mach, inst);
5316 break;
5317
5318 case TGSI_OPCODE_EMIT:
5319 emit_vertex(mach);
5320 break;
5321
5322 case TGSI_OPCODE_ENDPRIM:
5323 emit_primitive(mach);
5324 break;
5325
5326 case TGSI_OPCODE_BGNLOOP:
5327 /* push LoopMask and ContMasks */
5328 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5329 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5330 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5331 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5332
5333 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5334 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5335 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
5336 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5337 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
5338 break;
5339
5340 case TGSI_OPCODE_ENDLOOP:
5341 /* Restore ContMask, but don't pop */
5342 assert(mach->ContStackTop > 0);
5343 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
5344 UPDATE_EXEC_MASK(mach);
5345 if (mach->ExecMask) {
5346 /* repeat loop: jump to instruction just past BGNLOOP */
5347 assert(mach->LoopLabelStackTop > 0);
5348 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5349 }
5350 else {
5351 /* exit loop: pop LoopMask */
5352 assert(mach->LoopStackTop > 0);
5353 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5354 /* pop ContMask */
5355 assert(mach->ContStackTop > 0);
5356 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5357 assert(mach->LoopLabelStackTop > 0);
5358 --mach->LoopLabelStackTop;
5359
5360 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5361 }
5362 UPDATE_EXEC_MASK(mach);
5363 break;
5364
5365 case TGSI_OPCODE_BRK:
5366 exec_break(mach);
5367 break;
5368
5369 case TGSI_OPCODE_CONT:
5370 /* turn off cont channels for each enabled exec channel */
5371 mach->ContMask &= ~mach->ExecMask;
5372 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5373 UPDATE_EXEC_MASK(mach);
5374 break;
5375
5376 case TGSI_OPCODE_BGNSUB:
5377 /* no-op */
5378 break;
5379
5380 case TGSI_OPCODE_ENDSUB:
5381 /*
5382 * XXX: This really should be a no-op. We should never reach this opcode.
5383 */
5384
5385 assert(mach->CallStackTop > 0);
5386 mach->CallStackTop--;
5387
5388 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5389 mach->CondMask = mach->CondStack[mach->CondStackTop];
5390
5391 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5392 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5393
5394 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5395 mach->ContMask = mach->ContStack[mach->ContStackTop];
5396
5397 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5398 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5399
5400 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5401 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5402
5403 assert(mach->FuncStackTop > 0);
5404 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5405
5406 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5407
5408 UPDATE_EXEC_MASK(mach);
5409 break;
5410
5411 case TGSI_OPCODE_NOP:
5412 break;
5413
5414 case TGSI_OPCODE_BREAKC:
5415 IFETCH(&r[0], 0, TGSI_CHAN_X);
5416 /* update CondMask */
5417 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
5418 mach->LoopMask &= ~0x1;
5419 }
5420 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
5421 mach->LoopMask &= ~0x2;
5422 }
5423 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
5424 mach->LoopMask &= ~0x4;
5425 }
5426 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
5427 mach->LoopMask &= ~0x8;
5428 }
5429 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5430 UPDATE_EXEC_MASK(mach);
5431 break;
5432
5433 case TGSI_OPCODE_F2I:
5434 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5435 break;
5436
5437 case TGSI_OPCODE_FSEQ:
5438 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5439 break;
5440
5441 case TGSI_OPCODE_FSGE:
5442 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5443 break;
5444
5445 case TGSI_OPCODE_FSLT:
5446 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5447 break;
5448
5449 case TGSI_OPCODE_FSNE:
5450 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5451 break;
5452
5453 case TGSI_OPCODE_IDIV:
5454 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5455 break;
5456
5457 case TGSI_OPCODE_IMAX:
5458 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5459 break;
5460
5461 case TGSI_OPCODE_IMIN:
5462 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5463 break;
5464
5465 case TGSI_OPCODE_INEG:
5466 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5467 break;
5468
5469 case TGSI_OPCODE_ISGE:
5470 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5471 break;
5472
5473 case TGSI_OPCODE_ISHR:
5474 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5475 break;
5476
5477 case TGSI_OPCODE_ISLT:
5478 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5479 break;
5480
5481 case TGSI_OPCODE_F2U:
5482 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5483 break;
5484
5485 case TGSI_OPCODE_U2F:
5486 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5487 break;
5488
5489 case TGSI_OPCODE_UADD:
5490 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5491 break;
5492
5493 case TGSI_OPCODE_UDIV:
5494 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5495 break;
5496
5497 case TGSI_OPCODE_UMAD:
5498 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5499 break;
5500
5501 case TGSI_OPCODE_UMAX:
5502 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5503 break;
5504
5505 case TGSI_OPCODE_UMIN:
5506 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5507 break;
5508
5509 case TGSI_OPCODE_UMOD:
5510 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5511 break;
5512
5513 case TGSI_OPCODE_UMUL:
5514 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5515 break;
5516
5517 case TGSI_OPCODE_IMUL_HI:
5518 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5519 break;
5520
5521 case TGSI_OPCODE_UMUL_HI:
5522 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5523 break;
5524
5525 case TGSI_OPCODE_USEQ:
5526 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5527 break;
5528
5529 case TGSI_OPCODE_USGE:
5530 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5531 break;
5532
5533 case TGSI_OPCODE_USHR:
5534 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5535 break;
5536
5537 case TGSI_OPCODE_USLT:
5538 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5539 break;
5540
5541 case TGSI_OPCODE_USNE:
5542 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5543 break;
5544
5545 case TGSI_OPCODE_SWITCH:
5546 exec_switch(mach, inst);
5547 break;
5548
5549 case TGSI_OPCODE_CASE:
5550 exec_case(mach, inst);
5551 break;
5552
5553 case TGSI_OPCODE_DEFAULT:
5554 exec_default(mach);
5555 break;
5556
5557 case TGSI_OPCODE_ENDSWITCH:
5558 exec_endswitch(mach);
5559 break;
5560
5561 case TGSI_OPCODE_SAMPLE_I:
5562 exec_txf(mach, inst);
5563 break;
5564
5565 case TGSI_OPCODE_SAMPLE_I_MS:
5566 exec_txf(mach, inst);
5567 break;
5568
5569 case TGSI_OPCODE_SAMPLE:
5570 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5571 break;
5572
5573 case TGSI_OPCODE_SAMPLE_B:
5574 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5575 break;
5576
5577 case TGSI_OPCODE_SAMPLE_C:
5578 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5579 break;
5580
5581 case TGSI_OPCODE_SAMPLE_C_LZ:
5582 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5583 break;
5584
5585 case TGSI_OPCODE_SAMPLE_D:
5586 exec_sample_d(mach, inst);
5587 break;
5588
5589 case TGSI_OPCODE_SAMPLE_L:
5590 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5591 break;
5592
5593 case TGSI_OPCODE_GATHER4:
5594 assert(0);
5595 break;
5596
5597 case TGSI_OPCODE_SVIEWINFO:
5598 exec_txq(mach, inst);
5599 break;
5600
5601 case TGSI_OPCODE_SAMPLE_POS:
5602 assert(0);
5603 break;
5604
5605 case TGSI_OPCODE_SAMPLE_INFO:
5606 assert(0);
5607 break;
5608
5609 case TGSI_OPCODE_UARL:
5610 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5611 break;
5612
5613 case TGSI_OPCODE_UCMP:
5614 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5615 break;
5616
5617 case TGSI_OPCODE_IABS:
5618 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5619 break;
5620
5621 case TGSI_OPCODE_ISSG:
5622 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5623 break;
5624
5625 case TGSI_OPCODE_TEX2:
5626 /* simple texture lookup */
5627 /* src[0] = texcoord */
5628 /* src[1] = compare */
5629 /* src[2] = sampler unit */
5630 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5631 break;
5632 case TGSI_OPCODE_TXB2:
5633 /* simple texture lookup */
5634 /* src[0] = texcoord */
5635 /* src[1] = bias */
5636 /* src[2] = sampler unit */
5637 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5638 break;
5639 case TGSI_OPCODE_TXL2:
5640 /* simple texture lookup */
5641 /* src[0] = texcoord */
5642 /* src[1] = lod */
5643 /* src[2] = sampler unit */
5644 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5645 break;
5646
5647 case TGSI_OPCODE_IBFE:
5648 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5649 break;
5650 case TGSI_OPCODE_UBFE:
5651 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5652 break;
5653 case TGSI_OPCODE_BFI:
5654 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5655 break;
5656 case TGSI_OPCODE_BREV:
5657 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5658 break;
5659 case TGSI_OPCODE_POPC:
5660 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5661 break;
5662 case TGSI_OPCODE_LSB:
5663 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5664 break;
5665 case TGSI_OPCODE_IMSB:
5666 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5667 break;
5668 case TGSI_OPCODE_UMSB:
5669 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5670 break;
5671
5672 case TGSI_OPCODE_F2D:
5673 exec_f2d(mach, inst);
5674 break;
5675
5676 case TGSI_OPCODE_D2F:
5677 exec_d2f(mach, inst);
5678 break;
5679
5680 case TGSI_OPCODE_DABS:
5681 exec_double_unary(mach, inst, micro_dabs);
5682 break;
5683
5684 case TGSI_OPCODE_DNEG:
5685 exec_double_unary(mach, inst, micro_dneg);
5686 break;
5687
5688 case TGSI_OPCODE_DADD:
5689 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5690 break;
5691
5692 case TGSI_OPCODE_DMUL:
5693 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5694 break;
5695
5696 case TGSI_OPCODE_DMAX:
5697 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5698 break;
5699
5700 case TGSI_OPCODE_DMIN:
5701 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5702 break;
5703
5704 case TGSI_OPCODE_DSLT:
5705 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5706 break;
5707
5708 case TGSI_OPCODE_DSGE:
5709 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5710 break;
5711
5712 case TGSI_OPCODE_DSEQ:
5713 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5714 break;
5715
5716 case TGSI_OPCODE_DSNE:
5717 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5718 break;
5719
5720 case TGSI_OPCODE_DRCP:
5721 exec_double_unary(mach, inst, micro_drcp);
5722 break;
5723
5724 case TGSI_OPCODE_DSQRT:
5725 exec_double_unary(mach, inst, micro_dsqrt);
5726 break;
5727
5728 case TGSI_OPCODE_DRSQ:
5729 exec_double_unary(mach, inst, micro_drsq);
5730 break;
5731
5732 case TGSI_OPCODE_DMAD:
5733 exec_double_trinary(mach, inst, micro_dmad);
5734 break;
5735
5736 case TGSI_OPCODE_DFRAC:
5737 exec_double_unary(mach, inst, micro_dfrac);
5738 break;
5739
5740 case TGSI_OPCODE_DLDEXP:
5741 exec_dldexp(mach, inst);
5742 break;
5743
5744 case TGSI_OPCODE_DFRACEXP:
5745 exec_dfracexp(mach, inst);
5746 break;
5747
5748 case TGSI_OPCODE_I2D:
5749 exec_i2d(mach, inst);
5750 break;
5751
5752 case TGSI_OPCODE_D2I:
5753 exec_d2i(mach, inst);
5754 break;
5755
5756 case TGSI_OPCODE_U2D:
5757 exec_u2d(mach, inst);
5758 break;
5759
5760 case TGSI_OPCODE_D2U:
5761 exec_d2u(mach, inst);
5762 break;
5763
5764 case TGSI_OPCODE_LOAD:
5765 exec_load(mach, inst);
5766 break;
5767
5768 case TGSI_OPCODE_STORE:
5769 exec_store(mach, inst);
5770 break;
5771
5772 case TGSI_OPCODE_ATOMUADD:
5773 case TGSI_OPCODE_ATOMXCHG:
5774 case TGSI_OPCODE_ATOMCAS:
5775 case TGSI_OPCODE_ATOMAND:
5776 case TGSI_OPCODE_ATOMOR:
5777 case TGSI_OPCODE_ATOMXOR:
5778 case TGSI_OPCODE_ATOMUMIN:
5779 case TGSI_OPCODE_ATOMUMAX:
5780 case TGSI_OPCODE_ATOMIMIN:
5781 case TGSI_OPCODE_ATOMIMAX:
5782 exec_atomop(mach, inst);
5783 break;
5784
5785 case TGSI_OPCODE_RESQ:
5786 exec_resq(mach, inst);
5787 break;
5788 case TGSI_OPCODE_BARRIER:
5789 case TGSI_OPCODE_MEMBAR:
5790 break;
5791 default:
5792 assert( 0 );
5793 }
5794 }
5795
5796 static void
5797 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine *mach)
5798 {
5799 uint default_mask = 0xf;
5800
5801 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5802 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5803
5804 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
5805 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5806 mach->Primitives[0] = 0;
5807 /* GS runs on a single primitive for now */
5808 default_mask = 0x1;
5809 }
5810
5811 if (mach->NonHelperMask == 0)
5812 mach->NonHelperMask = default_mask;
5813 mach->CondMask = default_mask;
5814 mach->LoopMask = default_mask;
5815 mach->ContMask = default_mask;
5816 mach->FuncMask = default_mask;
5817 mach->ExecMask = default_mask;
5818
5819 mach->Switch.mask = default_mask;
5820
5821 assert(mach->CondStackTop == 0);
5822 assert(mach->LoopStackTop == 0);
5823 assert(mach->ContStackTop == 0);
5824 assert(mach->SwitchStackTop == 0);
5825 assert(mach->BreakStackTop == 0);
5826 assert(mach->CallStackTop == 0);
5827 }
5828
5829 /**
5830 * Run TGSI interpreter.
5831 * \return bitmask of "alive" quad components
5832 */
5833 uint
5834 tgsi_exec_machine_run( struct tgsi_exec_machine *mach, int start_pc )
5835 {
5836 uint i;
5837 int pc = 0;
5838
5839 tgsi_exec_machine_setup_masks(mach);
5840
5841 /* execute declarations (interpolants) */
5842 for (i = 0; i < mach->NumDeclarations; i++) {
5843 exec_declaration( mach, mach->Declarations+i );
5844 }
5845
5846 {
5847 #if DEBUG_EXECUTION
5848 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5849 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5850 uint inst = 1;
5851
5852 memset(mach->Temps, 0, sizeof(temps));
5853 memset(mach->Outputs, 0, sizeof(outputs));
5854 memset(temps, 0, sizeof(temps));
5855 memset(outputs, 0, sizeof(outputs));
5856 #endif
5857
5858 /* execute instructions, until pc is set to -1 */
5859 while (pc != -1) {
5860
5861 #if DEBUG_EXECUTION
5862 uint i;
5863
5864 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
5865 #endif
5866
5867 assert(pc < (int) mach->NumInstructions);
5868 exec_instruction(mach, mach->Instructions + pc, &pc);
5869
5870 #if DEBUG_EXECUTION
5871 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5872 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5873 uint j;
5874
5875 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5876 debug_printf("TEMP[%2u] = ", i);
5877 for (j = 0; j < 4; j++) {
5878 if (j > 0) {
5879 debug_printf(" ");
5880 }
5881 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5882 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5883 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5884 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5885 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5886 }
5887 }
5888 }
5889 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5890 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5891 uint j;
5892
5893 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5894 debug_printf("OUT[%2u] = ", i);
5895 for (j = 0; j < 4; j++) {
5896 if (j > 0) {
5897 debug_printf(" ");
5898 }
5899 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5900 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5901 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5902 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5903 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5904 }
5905 }
5906 }
5907 #endif
5908 }
5909 }
5910
5911 #if 0
5912 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5913 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
5914 /*
5915 * Scale back depth component.
5916 */
5917 for (i = 0; i < 4; i++)
5918 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5919 }
5920 #endif
5921
5922 /* Strictly speaking, these assertions aren't really needed but they
5923 * can potentially catch some bugs in the control flow code.
5924 */
5925 assert(mach->CondStackTop == 0);
5926 assert(mach->LoopStackTop == 0);
5927 assert(mach->ContStackTop == 0);
5928 assert(mach->SwitchStackTop == 0);
5929 assert(mach->BreakStackTop == 0);
5930 assert(mach->CallStackTop == 0);
5931
5932 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5933 }