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tgsi: fix sample_d emit for arrays
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 static void
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
78 {
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
83 }
84
85 static void
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
93 }
94
95 static void
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 }
104
105 static void
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
113 }
114
115 static void
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
120 {
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 }
126
127 static void
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 }
138
139 static void
140 micro_cnd(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
144 {
145 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
146 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
147 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
148 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
149 }
150
151 static void
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
154 {
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
159 }
160
161 static void
162 micro_ddx(union tgsi_exec_channel *dst,
163 const union tgsi_exec_channel *src)
164 {
165 dst->f[0] =
166 dst->f[1] =
167 dst->f[2] =
168 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
169 }
170
171 static void
172 micro_ddy(union tgsi_exec_channel *dst,
173 const union tgsi_exec_channel *src)
174 {
175 dst->f[0] =
176 dst->f[1] =
177 dst->f[2] =
178 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
179 }
180
181 static void
182 micro_exp2(union tgsi_exec_channel *dst,
183 const union tgsi_exec_channel *src)
184 {
185 #if FAST_MATH
186 dst->f[0] = util_fast_exp2(src->f[0]);
187 dst->f[1] = util_fast_exp2(src->f[1]);
188 dst->f[2] = util_fast_exp2(src->f[2]);
189 dst->f[3] = util_fast_exp2(src->f[3]);
190 #else
191 #if DEBUG
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
193 uint i;
194 union tgsi_exec_channel clamped;
195
196 for (i = 0; i < 4; i++) {
197 if (src->f[i] > 127.99999f) {
198 clamped.f[i] = 127.99999f;
199 } else if (src->f[i] < -126.99999f) {
200 clamped.f[i] = -126.99999f;
201 } else {
202 clamped.f[i] = src->f[i];
203 }
204 }
205 src = &clamped;
206 #endif /* DEBUG */
207
208 dst->f[0] = powf(2.0f, src->f[0]);
209 dst->f[1] = powf(2.0f, src->f[1]);
210 dst->f[2] = powf(2.0f, src->f[2]);
211 dst->f[3] = powf(2.0f, src->f[3]);
212 #endif /* FAST_MATH */
213 }
214
215 static void
216 micro_flr(union tgsi_exec_channel *dst,
217 const union tgsi_exec_channel *src)
218 {
219 dst->f[0] = floorf(src->f[0]);
220 dst->f[1] = floorf(src->f[1]);
221 dst->f[2] = floorf(src->f[2]);
222 dst->f[3] = floorf(src->f[3]);
223 }
224
225 static void
226 micro_frc(union tgsi_exec_channel *dst,
227 const union tgsi_exec_channel *src)
228 {
229 dst->f[0] = src->f[0] - floorf(src->f[0]);
230 dst->f[1] = src->f[1] - floorf(src->f[1]);
231 dst->f[2] = src->f[2] - floorf(src->f[2]);
232 dst->f[3] = src->f[3] - floorf(src->f[3]);
233 }
234
235 static void
236 micro_iabs(union tgsi_exec_channel *dst,
237 const union tgsi_exec_channel *src)
238 {
239 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
240 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
241 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
242 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
243 }
244
245 static void
246 micro_ineg(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src)
248 {
249 dst->i[0] = -src->i[0];
250 dst->i[1] = -src->i[1];
251 dst->i[2] = -src->i[2];
252 dst->i[3] = -src->i[3];
253 }
254
255 static void
256 micro_lg2(union tgsi_exec_channel *dst,
257 const union tgsi_exec_channel *src)
258 {
259 #if FAST_MATH
260 dst->f[0] = util_fast_log2(src->f[0]);
261 dst->f[1] = util_fast_log2(src->f[1]);
262 dst->f[2] = util_fast_log2(src->f[2]);
263 dst->f[3] = util_fast_log2(src->f[3]);
264 #else
265 dst->f[0] = logf(src->f[0]) * 1.442695f;
266 dst->f[1] = logf(src->f[1]) * 1.442695f;
267 dst->f[2] = logf(src->f[2]) * 1.442695f;
268 dst->f[3] = logf(src->f[3]) * 1.442695f;
269 #endif
270 }
271
272 static void
273 micro_lrp(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
277 {
278 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
279 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
280 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
281 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
282 }
283
284 static void
285 micro_mad(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src0,
287 const union tgsi_exec_channel *src1,
288 const union tgsi_exec_channel *src2)
289 {
290 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
291 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
292 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
293 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
294 }
295
296 static void
297 micro_mov(union tgsi_exec_channel *dst,
298 const union tgsi_exec_channel *src)
299 {
300 dst->u[0] = src->u[0];
301 dst->u[1] = src->u[1];
302 dst->u[2] = src->u[2];
303 dst->u[3] = src->u[3];
304 }
305
306 static void
307 micro_rcp(union tgsi_exec_channel *dst,
308 const union tgsi_exec_channel *src)
309 {
310 #if 0 /* for debugging */
311 assert(src->f[0] != 0.0f);
312 assert(src->f[1] != 0.0f);
313 assert(src->f[2] != 0.0f);
314 assert(src->f[3] != 0.0f);
315 #endif
316 dst->f[0] = 1.0f / src->f[0];
317 dst->f[1] = 1.0f / src->f[1];
318 dst->f[2] = 1.0f / src->f[2];
319 dst->f[3] = 1.0f / src->f[3];
320 }
321
322 static void
323 micro_rnd(union tgsi_exec_channel *dst,
324 const union tgsi_exec_channel *src)
325 {
326 dst->f[0] = floorf(src->f[0] + 0.5f);
327 dst->f[1] = floorf(src->f[1] + 0.5f);
328 dst->f[2] = floorf(src->f[2] + 0.5f);
329 dst->f[3] = floorf(src->f[3] + 0.5f);
330 }
331
332 static void
333 micro_rsq(union tgsi_exec_channel *dst,
334 const union tgsi_exec_channel *src)
335 {
336 #if 0 /* for debugging */
337 assert(src->f[0] != 0.0f);
338 assert(src->f[1] != 0.0f);
339 assert(src->f[2] != 0.0f);
340 assert(src->f[3] != 0.0f);
341 #endif
342 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
343 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
344 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
345 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
346 }
347
348 static void
349 micro_sqrt(union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src)
351 {
352 dst->f[0] = sqrtf(fabsf(src->f[0]));
353 dst->f[1] = sqrtf(fabsf(src->f[1]));
354 dst->f[2] = sqrtf(fabsf(src->f[2]));
355 dst->f[3] = sqrtf(fabsf(src->f[3]));
356 }
357
358 static void
359 micro_seq(union tgsi_exec_channel *dst,
360 const union tgsi_exec_channel *src0,
361 const union tgsi_exec_channel *src1)
362 {
363 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
364 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
365 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
366 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
367 }
368
369 static void
370 micro_sge(union tgsi_exec_channel *dst,
371 const union tgsi_exec_channel *src0,
372 const union tgsi_exec_channel *src1)
373 {
374 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
375 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
376 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
377 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
378 }
379
380 static void
381 micro_sgn(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
385 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
386 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
387 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
388 }
389
390 static void
391 micro_isgn(union tgsi_exec_channel *dst,
392 const union tgsi_exec_channel *src)
393 {
394 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
395 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
396 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
397 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
398 }
399
400 static void
401 micro_sgt(union tgsi_exec_channel *dst,
402 const union tgsi_exec_channel *src0,
403 const union tgsi_exec_channel *src1)
404 {
405 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
406 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
407 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
408 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
409 }
410
411 static void
412 micro_sin(union tgsi_exec_channel *dst,
413 const union tgsi_exec_channel *src)
414 {
415 dst->f[0] = sinf(src->f[0]);
416 dst->f[1] = sinf(src->f[1]);
417 dst->f[2] = sinf(src->f[2]);
418 dst->f[3] = sinf(src->f[3]);
419 }
420
421 static void
422 micro_sle(union tgsi_exec_channel *dst,
423 const union tgsi_exec_channel *src0,
424 const union tgsi_exec_channel *src1)
425 {
426 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
427 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
428 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
429 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
430 }
431
432 static void
433 micro_slt(union tgsi_exec_channel *dst,
434 const union tgsi_exec_channel *src0,
435 const union tgsi_exec_channel *src1)
436 {
437 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
438 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
439 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
440 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
441 }
442
443 static void
444 micro_sne(union tgsi_exec_channel *dst,
445 const union tgsi_exec_channel *src0,
446 const union tgsi_exec_channel *src1)
447 {
448 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
449 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
450 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
451 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
452 }
453
454 static void
455 micro_sfl(union tgsi_exec_channel *dst)
456 {
457 dst->f[0] = 0.0f;
458 dst->f[1] = 0.0f;
459 dst->f[2] = 0.0f;
460 dst->f[3] = 0.0f;
461 }
462
463 static void
464 micro_str(union tgsi_exec_channel *dst)
465 {
466 dst->f[0] = 1.0f;
467 dst->f[1] = 1.0f;
468 dst->f[2] = 1.0f;
469 dst->f[3] = 1.0f;
470 }
471
472 static void
473 micro_trunc(union tgsi_exec_channel *dst,
474 const union tgsi_exec_channel *src)
475 {
476 dst->f[0] = (float)(int)src->f[0];
477 dst->f[1] = (float)(int)src->f[1];
478 dst->f[2] = (float)(int)src->f[2];
479 dst->f[3] = (float)(int)src->f[3];
480 }
481
482
483 enum tgsi_exec_datatype {
484 TGSI_EXEC_DATA_FLOAT,
485 TGSI_EXEC_DATA_INT,
486 TGSI_EXEC_DATA_UINT
487 };
488
489 /*
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
491 */
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
498
499
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
503
504
505 static const union tgsi_exec_channel ZeroVec =
506 { { 0.0, 0.0, 0.0, 0.0 } };
507
508 static const union tgsi_exec_channel OneVec = {
509 {1.0f, 1.0f, 1.0f, 1.0f}
510 };
511
512 static const union tgsi_exec_channel P128Vec = {
513 {128.0f, 128.0f, 128.0f, 128.0f}
514 };
515
516 static const union tgsi_exec_channel M128Vec = {
517 {-128.0f, -128.0f, -128.0f, -128.0f}
518 };
519
520
521 /**
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
525 * them.
526 */
527 static INLINE void
528 check_inf_or_nan(const union tgsi_exec_channel *chan)
529 {
530 assert(!util_is_inf_or_nan((chan)->f[0]));
531 assert(!util_is_inf_or_nan((chan)->f[1]));
532 assert(!util_is_inf_or_nan((chan)->f[2]));
533 assert(!util_is_inf_or_nan((chan)->f[3]));
534 }
535
536
537 #ifdef DEBUG
538 static void
539 print_chan(const char *msg, const union tgsi_exec_channel *chan)
540 {
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
543 }
544 #endif
545
546
547 #ifdef DEBUG
548 static void
549 print_temp(const struct tgsi_exec_machine *mach, uint index)
550 {
551 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
552 int i;
553 debug_printf("Temp[%u] =\n", index);
554 for (i = 0; i < 4; i++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
556 "XYZW"[i],
557 tmp->xyzw[i].f[0],
558 tmp->xyzw[i].f[1],
559 tmp->xyzw[i].f[2],
560 tmp->xyzw[i].f[3]);
561 }
562 }
563 #endif
564
565
566 void
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
568 unsigned num_bufs,
569 const void **bufs,
570 const unsigned *buf_sizes)
571 {
572 unsigned i;
573
574 for (i = 0; i < num_bufs; i++) {
575 mach->Consts[i] = bufs[i];
576 mach->ConstsSize[i] = buf_sizes[i];
577 }
578 }
579
580
581 /**
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
584 * Example:
585 * MOV T, T.yxwz;
586 * This would expand into:
587 * MOV t0, t1;
588 * MOV t1, t0;
589 * MOV t2, t3;
590 * MOV t3, t2;
591 * The second instruction will have the wrong value for t0 if executed as-is.
592 */
593 boolean
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
595 {
596 uint i, chan;
597
598 uint writemask = inst->Dst[0].Register.WriteMask;
599 if (writemask == TGSI_WRITEMASK_X ||
600 writemask == TGSI_WRITEMASK_Y ||
601 writemask == TGSI_WRITEMASK_Z ||
602 writemask == TGSI_WRITEMASK_W ||
603 writemask == TGSI_WRITEMASK_NONE) {
604 /* no chance of data dependency */
605 return FALSE;
606 }
607
608 /* loop over src regs */
609 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
610 if ((inst->Src[i].Register.File ==
611 inst->Dst[0].Register.File) &&
612 ((inst->Src[i].Register.Index ==
613 inst->Dst[0].Register.Index) ||
614 inst->Src[i].Register.Indirect ||
615 inst->Dst[0].Register.Indirect)) {
616 /* loop over dest channels */
617 uint channelsWritten = 0x0;
618 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
619 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
622 if (channelsWritten & (1 << swizzle)) {
623 return TRUE;
624 }
625
626 channelsWritten |= (1 << chan);
627 }
628 }
629 }
630 }
631 return FALSE;
632 }
633
634
635 /**
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
639 */
640 void
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine *mach,
643 const struct tgsi_token *tokens,
644 struct tgsi_sampler *sampler)
645 {
646 uint k;
647 struct tgsi_parse_context parse;
648 struct tgsi_full_instruction *instructions;
649 struct tgsi_full_declaration *declarations;
650 uint maxInstructions = 10, numInstructions = 0;
651 uint maxDeclarations = 10, numDeclarations = 0;
652
653 #if 0
654 tgsi_dump(tokens, 0);
655 #endif
656
657 util_init_math();
658
659
660 mach->Tokens = tokens;
661 mach->Sampler = sampler;
662
663 if (!tokens) {
664 /* unbind and free all */
665 FREE(mach->Declarations);
666 mach->Declarations = NULL;
667 mach->NumDeclarations = 0;
668
669 FREE(mach->Instructions);
670 mach->Instructions = NULL;
671 mach->NumInstructions = 0;
672
673 return;
674 }
675
676 k = tgsi_parse_init (&parse, mach->Tokens);
677 if (k != TGSI_PARSE_OK) {
678 debug_printf( "Problem parsing!\n" );
679 return;
680 }
681
682 mach->Processor = parse.FullHeader.Processor.Processor;
683 mach->ImmLimit = 0;
684 mach->NumOutputs = 0;
685
686 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
687 !mach->UsedGeometryShader) {
688 struct tgsi_exec_vector *inputs;
689 struct tgsi_exec_vector *outputs;
690
691 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
692 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
693 16);
694
695 if (!inputs)
696 return;
697
698 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
699 TGSI_MAX_TOTAL_VERTICES, 16);
700
701 if (!outputs) {
702 align_free(inputs);
703 return;
704 }
705
706 align_free(mach->Inputs);
707 align_free(mach->Outputs);
708
709 mach->Inputs = inputs;
710 mach->Outputs = outputs;
711 mach->UsedGeometryShader = TRUE;
712 }
713
714 declarations = (struct tgsi_full_declaration *)
715 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
716
717 if (!declarations) {
718 return;
719 }
720
721 instructions = (struct tgsi_full_instruction *)
722 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
723
724 if (!instructions) {
725 FREE( declarations );
726 return;
727 }
728
729 while( !tgsi_parse_end_of_tokens( &parse ) ) {
730 uint i;
731
732 tgsi_parse_token( &parse );
733 switch( parse.FullToken.Token.Type ) {
734 case TGSI_TOKEN_TYPE_DECLARATION:
735 /* save expanded declaration */
736 if (numDeclarations == maxDeclarations) {
737 declarations = REALLOC(declarations,
738 maxDeclarations
739 * sizeof(struct tgsi_full_declaration),
740 (maxDeclarations + 10)
741 * sizeof(struct tgsi_full_declaration));
742 maxDeclarations += 10;
743 }
744 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
745 unsigned reg;
746 for (reg = parse.FullToken.FullDeclaration.Range.First;
747 reg <= parse.FullToken.FullDeclaration.Range.Last;
748 ++reg) {
749 ++mach->NumOutputs;
750 }
751 }
752 if (parse.FullToken.FullDeclaration.Declaration.File ==
753 TGSI_FILE_IMMEDIATE_ARRAY) {
754 unsigned reg;
755 struct tgsi_full_declaration *decl =
756 &parse.FullToken.FullDeclaration;
757 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
758 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
759 for( i = 0; i < 4; i++ ) {
760 int idx = reg * 4 + i;
761 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
762 }
763 }
764 }
765 memcpy(declarations + numDeclarations,
766 &parse.FullToken.FullDeclaration,
767 sizeof(declarations[0]));
768 numDeclarations++;
769 break;
770
771 case TGSI_TOKEN_TYPE_IMMEDIATE:
772 {
773 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
774 assert( size <= 4 );
775 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
776
777 for( i = 0; i < size; i++ ) {
778 mach->Imms[mach->ImmLimit][i] =
779 parse.FullToken.FullImmediate.u[i].Float;
780 }
781 mach->ImmLimit += 1;
782 }
783 break;
784
785 case TGSI_TOKEN_TYPE_INSTRUCTION:
786
787 /* save expanded instruction */
788 if (numInstructions == maxInstructions) {
789 instructions = REALLOC(instructions,
790 maxInstructions
791 * sizeof(struct tgsi_full_instruction),
792 (maxInstructions + 10)
793 * sizeof(struct tgsi_full_instruction));
794 maxInstructions += 10;
795 }
796
797 memcpy(instructions + numInstructions,
798 &parse.FullToken.FullInstruction,
799 sizeof(instructions[0]));
800
801 numInstructions++;
802 break;
803
804 case TGSI_TOKEN_TYPE_PROPERTY:
805 break;
806
807 default:
808 assert( 0 );
809 }
810 }
811 tgsi_parse_free (&parse);
812
813 FREE(mach->Declarations);
814 mach->Declarations = declarations;
815 mach->NumDeclarations = numDeclarations;
816
817 FREE(mach->Instructions);
818 mach->Instructions = instructions;
819 mach->NumInstructions = numInstructions;
820 }
821
822
823 struct tgsi_exec_machine *
824 tgsi_exec_machine_create( void )
825 {
826 struct tgsi_exec_machine *mach;
827 uint i;
828
829 mach = align_malloc( sizeof *mach, 16 );
830 if (!mach)
831 goto fail;
832
833 memset(mach, 0, sizeof(*mach));
834
835 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
836 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
837 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
838
839 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
840 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
841 if (!mach->Inputs || !mach->Outputs)
842 goto fail;
843
844 /* Setup constants needed by the SSE2 executor. */
845 for( i = 0; i < 4; i++ ) {
846 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
847 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
848 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
849 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
850 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
851 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
852 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
853 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
854 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
855 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
856 }
857
858 #ifdef DEBUG
859 /* silence warnings */
860 (void) print_chan;
861 (void) print_temp;
862 #endif
863
864 return mach;
865
866 fail:
867 if (mach) {
868 align_free(mach->Inputs);
869 align_free(mach->Outputs);
870 align_free(mach);
871 }
872 return NULL;
873 }
874
875
876 void
877 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
878 {
879 if (mach) {
880 FREE(mach->Instructions);
881 FREE(mach->Declarations);
882
883 align_free(mach->Inputs);
884 align_free(mach->Outputs);
885
886 align_free(mach);
887 }
888 }
889
890 static void
891 micro_add(union tgsi_exec_channel *dst,
892 const union tgsi_exec_channel *src0,
893 const union tgsi_exec_channel *src1)
894 {
895 dst->f[0] = src0->f[0] + src1->f[0];
896 dst->f[1] = src0->f[1] + src1->f[1];
897 dst->f[2] = src0->f[2] + src1->f[2];
898 dst->f[3] = src0->f[3] + src1->f[3];
899 }
900
901 static void
902 micro_div(
903 union tgsi_exec_channel *dst,
904 const union tgsi_exec_channel *src0,
905 const union tgsi_exec_channel *src1 )
906 {
907 if (src1->f[0] != 0) {
908 dst->f[0] = src0->f[0] / src1->f[0];
909 }
910 if (src1->f[1] != 0) {
911 dst->f[1] = src0->f[1] / src1->f[1];
912 }
913 if (src1->f[2] != 0) {
914 dst->f[2] = src0->f[2] / src1->f[2];
915 }
916 if (src1->f[3] != 0) {
917 dst->f[3] = src0->f[3] / src1->f[3];
918 }
919 }
920
921 static void
922 micro_rcc(union tgsi_exec_channel *dst,
923 const union tgsi_exec_channel *src)
924 {
925 uint i;
926
927 for (i = 0; i < 4; i++) {
928 float recip = 1.0f / src->f[i];
929
930 if (recip > 0.0f) {
931 if (recip > 1.884467e+019f) {
932 dst->f[i] = 1.884467e+019f;
933 }
934 else if (recip < 5.42101e-020f) {
935 dst->f[i] = 5.42101e-020f;
936 }
937 else {
938 dst->f[i] = recip;
939 }
940 }
941 else {
942 if (recip < -1.884467e+019f) {
943 dst->f[i] = -1.884467e+019f;
944 }
945 else if (recip > -5.42101e-020f) {
946 dst->f[i] = -5.42101e-020f;
947 }
948 else {
949 dst->f[i] = recip;
950 }
951 }
952 }
953 }
954
955 static void
956 micro_lt(
957 union tgsi_exec_channel *dst,
958 const union tgsi_exec_channel *src0,
959 const union tgsi_exec_channel *src1,
960 const union tgsi_exec_channel *src2,
961 const union tgsi_exec_channel *src3 )
962 {
963 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
964 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
965 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
966 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
967 }
968
969 static void
970 micro_max(union tgsi_exec_channel *dst,
971 const union tgsi_exec_channel *src0,
972 const union tgsi_exec_channel *src1)
973 {
974 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
975 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
976 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
977 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
978 }
979
980 static void
981 micro_min(union tgsi_exec_channel *dst,
982 const union tgsi_exec_channel *src0,
983 const union tgsi_exec_channel *src1)
984 {
985 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
986 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
987 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
988 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
989 }
990
991 static void
992 micro_mul(union tgsi_exec_channel *dst,
993 const union tgsi_exec_channel *src0,
994 const union tgsi_exec_channel *src1)
995 {
996 dst->f[0] = src0->f[0] * src1->f[0];
997 dst->f[1] = src0->f[1] * src1->f[1];
998 dst->f[2] = src0->f[2] * src1->f[2];
999 dst->f[3] = src0->f[3] * src1->f[3];
1000 }
1001
1002 static void
1003 micro_neg(
1004 union tgsi_exec_channel *dst,
1005 const union tgsi_exec_channel *src )
1006 {
1007 dst->f[0] = -src->f[0];
1008 dst->f[1] = -src->f[1];
1009 dst->f[2] = -src->f[2];
1010 dst->f[3] = -src->f[3];
1011 }
1012
1013 static void
1014 micro_pow(
1015 union tgsi_exec_channel *dst,
1016 const union tgsi_exec_channel *src0,
1017 const union tgsi_exec_channel *src1 )
1018 {
1019 #if FAST_MATH
1020 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1021 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1022 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1023 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1024 #else
1025 dst->f[0] = powf( src0->f[0], src1->f[0] );
1026 dst->f[1] = powf( src0->f[1], src1->f[1] );
1027 dst->f[2] = powf( src0->f[2], src1->f[2] );
1028 dst->f[3] = powf( src0->f[3], src1->f[3] );
1029 #endif
1030 }
1031
1032 static void
1033 micro_sub(union tgsi_exec_channel *dst,
1034 const union tgsi_exec_channel *src0,
1035 const union tgsi_exec_channel *src1)
1036 {
1037 dst->f[0] = src0->f[0] - src1->f[0];
1038 dst->f[1] = src0->f[1] - src1->f[1];
1039 dst->f[2] = src0->f[2] - src1->f[2];
1040 dst->f[3] = src0->f[3] - src1->f[3];
1041 }
1042
1043 static void
1044 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1045 const uint chan_index,
1046 const uint file,
1047 const uint swizzle,
1048 const union tgsi_exec_channel *index,
1049 const union tgsi_exec_channel *index2D,
1050 union tgsi_exec_channel *chan)
1051 {
1052 uint i;
1053
1054 assert(swizzle < 4);
1055
1056 switch (file) {
1057 case TGSI_FILE_CONSTANT:
1058 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1059 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1060 assert(mach->Consts[index2D->i[i]]);
1061
1062 if (index->i[i] < 0) {
1063 chan->u[i] = 0;
1064 } else {
1065 /* NOTE: copying the const value as a uint instead of float */
1066 const uint constbuf = index2D->i[i];
1067 const uint *buf = (const uint *)mach->Consts[constbuf];
1068 const int pos = index->i[i] * 4 + swizzle;
1069 /* const buffer bounds check */
1070 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1071 if (0) {
1072 /* Debug: print warning */
1073 static int count = 0;
1074 if (count++ < 100)
1075 debug_printf("TGSI Exec: const buffer index %d"
1076 " out of bounds\n", pos);
1077 }
1078 chan->u[i] = 0;
1079 }
1080 else
1081 chan->u[i] = buf[pos];
1082 }
1083 }
1084 break;
1085
1086 case TGSI_FILE_INPUT:
1087 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1088 /*
1089 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1090 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1091 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1092 index2D->i[i], index->i[i]);
1093 }*/
1094 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1095 assert(pos >= 0);
1096 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1097 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1098 }
1099 break;
1100
1101 case TGSI_FILE_SYSTEM_VALUE:
1102 /* XXX no swizzling at this point. Will be needed if we put
1103 * gl_FragCoord, for example, in a sys value register.
1104 */
1105 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1106 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1107 }
1108 break;
1109
1110 case TGSI_FILE_TEMPORARY:
1111 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1112 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1113 assert(index2D->i[i] == 0);
1114
1115 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1116 }
1117 break;
1118
1119 case TGSI_FILE_TEMPORARY_ARRAY:
1120 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1121 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1122 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1123
1124 chan->u[i] =
1125 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1126 }
1127 break;
1128
1129 case TGSI_FILE_IMMEDIATE:
1130 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1131 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1132 assert(index2D->i[i] == 0);
1133
1134 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1135 }
1136 break;
1137
1138 case TGSI_FILE_IMMEDIATE_ARRAY:
1139 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1140 assert(index2D->i[i] == 0);
1141
1142 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1143 }
1144 break;
1145
1146 case TGSI_FILE_ADDRESS:
1147 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1148 assert(index->i[i] >= 0);
1149 assert(index2D->i[i] == 0);
1150
1151 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1152 }
1153 break;
1154
1155 case TGSI_FILE_PREDICATE:
1156 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1157 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1158 assert(index2D->i[i] == 0);
1159
1160 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1161 }
1162 break;
1163
1164 case TGSI_FILE_OUTPUT:
1165 /* vertex/fragment output vars can be read too */
1166 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1167 assert(index->i[i] >= 0);
1168 assert(index2D->i[i] == 0);
1169
1170 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1171 }
1172 break;
1173
1174 default:
1175 assert(0);
1176 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1177 chan->u[i] = 0;
1178 }
1179 }
1180 }
1181
1182 static void
1183 fetch_source(const struct tgsi_exec_machine *mach,
1184 union tgsi_exec_channel *chan,
1185 const struct tgsi_full_src_register *reg,
1186 const uint chan_index,
1187 enum tgsi_exec_datatype src_datatype)
1188 {
1189 union tgsi_exec_channel index;
1190 union tgsi_exec_channel index2D;
1191 uint swizzle;
1192
1193 /* We start with a direct index into a register file.
1194 *
1195 * file[1],
1196 * where:
1197 * file = Register.File
1198 * [1] = Register.Index
1199 */
1200 index.i[0] =
1201 index.i[1] =
1202 index.i[2] =
1203 index.i[3] = reg->Register.Index;
1204
1205 /* There is an extra source register that indirectly subscripts
1206 * a register file. The direct index now becomes an offset
1207 * that is being added to the indirect register.
1208 *
1209 * file[ind[2].x+1],
1210 * where:
1211 * ind = Indirect.File
1212 * [2] = Indirect.Index
1213 * .x = Indirect.SwizzleX
1214 */
1215 if (reg->Register.Indirect) {
1216 union tgsi_exec_channel index2;
1217 union tgsi_exec_channel indir_index;
1218 const uint execmask = mach->ExecMask;
1219 uint i;
1220
1221 /* which address register (always zero now) */
1222 index2.i[0] =
1223 index2.i[1] =
1224 index2.i[2] =
1225 index2.i[3] = reg->Indirect.Index;
1226 /* get current value of address register[swizzle] */
1227 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, TGSI_CHAN_X );
1228 fetch_src_file_channel(mach,
1229 chan_index,
1230 reg->Indirect.File,
1231 swizzle,
1232 &index2,
1233 &ZeroVec,
1234 &indir_index);
1235
1236 /* add value of address register to the offset */
1237 index.i[0] += indir_index.i[0];
1238 index.i[1] += indir_index.i[1];
1239 index.i[2] += indir_index.i[2];
1240 index.i[3] += indir_index.i[3];
1241
1242 /* for disabled execution channels, zero-out the index to
1243 * avoid using a potential garbage value.
1244 */
1245 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1246 if ((execmask & (1 << i)) == 0)
1247 index.i[i] = 0;
1248 }
1249 }
1250
1251 /* There is an extra source register that is a second
1252 * subscript to a register file. Effectively it means that
1253 * the register file is actually a 2D array of registers.
1254 *
1255 * file[3][1],
1256 * where:
1257 * [3] = Dimension.Index
1258 */
1259 if (reg->Register.Dimension) {
1260 index2D.i[0] =
1261 index2D.i[1] =
1262 index2D.i[2] =
1263 index2D.i[3] = reg->Dimension.Index;
1264
1265 /* Again, the second subscript index can be addressed indirectly
1266 * identically to the first one.
1267 * Nothing stops us from indirectly addressing the indirect register,
1268 * but there is no need for that, so we won't exercise it.
1269 *
1270 * file[ind[4].y+3][1],
1271 * where:
1272 * ind = DimIndirect.File
1273 * [4] = DimIndirect.Index
1274 * .y = DimIndirect.SwizzleX
1275 */
1276 if (reg->Dimension.Indirect) {
1277 union tgsi_exec_channel index2;
1278 union tgsi_exec_channel indir_index;
1279 const uint execmask = mach->ExecMask;
1280 uint i;
1281
1282 index2.i[0] =
1283 index2.i[1] =
1284 index2.i[2] =
1285 index2.i[3] = reg->DimIndirect.Index;
1286
1287 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, TGSI_CHAN_X );
1288 fetch_src_file_channel(mach,
1289 chan_index,
1290 reg->DimIndirect.File,
1291 swizzle,
1292 &index2,
1293 &ZeroVec,
1294 &indir_index);
1295
1296 index2D.i[0] += indir_index.i[0];
1297 index2D.i[1] += indir_index.i[1];
1298 index2D.i[2] += indir_index.i[2];
1299 index2D.i[3] += indir_index.i[3];
1300
1301 /* for disabled execution channels, zero-out the index to
1302 * avoid using a potential garbage value.
1303 */
1304 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1305 if ((execmask & (1 << i)) == 0) {
1306 index2D.i[i] = 0;
1307 }
1308 }
1309 }
1310
1311 /* If by any chance there was a need for a 3D array of register
1312 * files, we would have to check whether Dimension is followed
1313 * by a dimension register and continue the saga.
1314 */
1315 } else {
1316 index2D.i[0] =
1317 index2D.i[1] =
1318 index2D.i[2] =
1319 index2D.i[3] = 0;
1320 }
1321
1322 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1323 fetch_src_file_channel(mach,
1324 chan_index,
1325 reg->Register.File,
1326 swizzle,
1327 &index,
1328 &index2D,
1329 chan);
1330
1331 if (reg->Register.Absolute) {
1332 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1333 micro_abs(chan, chan);
1334 } else {
1335 micro_iabs(chan, chan);
1336 }
1337 }
1338
1339 if (reg->Register.Negate) {
1340 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1341 micro_neg(chan, chan);
1342 } else {
1343 micro_ineg(chan, chan);
1344 }
1345 }
1346 }
1347
1348 static void
1349 store_dest(struct tgsi_exec_machine *mach,
1350 const union tgsi_exec_channel *chan,
1351 const struct tgsi_full_dst_register *reg,
1352 const struct tgsi_full_instruction *inst,
1353 uint chan_index,
1354 enum tgsi_exec_datatype dst_datatype)
1355 {
1356 uint i;
1357 union tgsi_exec_channel null;
1358 union tgsi_exec_channel *dst;
1359 union tgsi_exec_channel index2D;
1360 uint execmask = mach->ExecMask;
1361 int offset = 0; /* indirection offset */
1362 int index;
1363
1364 /* for debugging */
1365 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1366 check_inf_or_nan(chan);
1367 }
1368
1369 /* There is an extra source register that indirectly subscripts
1370 * a register file. The direct index now becomes an offset
1371 * that is being added to the indirect register.
1372 *
1373 * file[ind[2].x+1],
1374 * where:
1375 * ind = Indirect.File
1376 * [2] = Indirect.Index
1377 * .x = Indirect.SwizzleX
1378 */
1379 if (reg->Register.Indirect) {
1380 union tgsi_exec_channel index;
1381 union tgsi_exec_channel indir_index;
1382 uint swizzle;
1383
1384 /* which address register (always zero for now) */
1385 index.i[0] =
1386 index.i[1] =
1387 index.i[2] =
1388 index.i[3] = reg->Indirect.Index;
1389
1390 /* get current value of address register[swizzle] */
1391 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, TGSI_CHAN_X );
1392
1393 /* fetch values from the address/indirection register */
1394 fetch_src_file_channel(mach,
1395 chan_index,
1396 reg->Indirect.File,
1397 swizzle,
1398 &index,
1399 &ZeroVec,
1400 &indir_index);
1401
1402 /* save indirection offset */
1403 offset = indir_index.i[0];
1404 }
1405
1406 /* There is an extra source register that is a second
1407 * subscript to a register file. Effectively it means that
1408 * the register file is actually a 2D array of registers.
1409 *
1410 * file[3][1],
1411 * where:
1412 * [3] = Dimension.Index
1413 */
1414 if (reg->Register.Dimension) {
1415 index2D.i[0] =
1416 index2D.i[1] =
1417 index2D.i[2] =
1418 index2D.i[3] = reg->Dimension.Index;
1419
1420 /* Again, the second subscript index can be addressed indirectly
1421 * identically to the first one.
1422 * Nothing stops us from indirectly addressing the indirect register,
1423 * but there is no need for that, so we won't exercise it.
1424 *
1425 * file[ind[4].y+3][1],
1426 * where:
1427 * ind = DimIndirect.File
1428 * [4] = DimIndirect.Index
1429 * .y = DimIndirect.SwizzleX
1430 */
1431 if (reg->Dimension.Indirect) {
1432 union tgsi_exec_channel index2;
1433 union tgsi_exec_channel indir_index;
1434 const uint execmask = mach->ExecMask;
1435 unsigned swizzle;
1436 uint i;
1437
1438 index2.i[0] =
1439 index2.i[1] =
1440 index2.i[2] =
1441 index2.i[3] = reg->DimIndirect.Index;
1442
1443 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, TGSI_CHAN_X );
1444 fetch_src_file_channel(mach,
1445 chan_index,
1446 reg->DimIndirect.File,
1447 swizzle,
1448 &index2,
1449 &ZeroVec,
1450 &indir_index);
1451
1452 index2D.i[0] += indir_index.i[0];
1453 index2D.i[1] += indir_index.i[1];
1454 index2D.i[2] += indir_index.i[2];
1455 index2D.i[3] += indir_index.i[3];
1456
1457 /* for disabled execution channels, zero-out the index to
1458 * avoid using a potential garbage value.
1459 */
1460 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1461 if ((execmask & (1 << i)) == 0) {
1462 index2D.i[i] = 0;
1463 }
1464 }
1465 }
1466
1467 /* If by any chance there was a need for a 3D array of register
1468 * files, we would have to check whether Dimension is followed
1469 * by a dimension register and continue the saga.
1470 */
1471 } else {
1472 index2D.i[0] =
1473 index2D.i[1] =
1474 index2D.i[2] =
1475 index2D.i[3] = 0;
1476 }
1477
1478 switch (reg->Register.File) {
1479 case TGSI_FILE_NULL:
1480 dst = &null;
1481 break;
1482
1483 case TGSI_FILE_OUTPUT:
1484 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1485 + reg->Register.Index;
1486 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1487 #if 0
1488 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1489 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1490 reg->Register.Index);
1491 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1492 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1493 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1494 if (execmask & (1 << i))
1495 debug_printf("%f, ", chan->f[i]);
1496 debug_printf(")\n");
1497 }
1498 #endif
1499 break;
1500
1501 case TGSI_FILE_TEMPORARY:
1502 index = reg->Register.Index;
1503 assert( index < TGSI_EXEC_NUM_TEMPS );
1504 dst = &mach->Temps[offset + index].xyzw[chan_index];
1505 break;
1506
1507 case TGSI_FILE_TEMPORARY_ARRAY:
1508 index = reg->Register.Index;
1509 assert( index < TGSI_EXEC_NUM_TEMPS );
1510 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1511 /* XXX we use index2D.i[0] here but somehow we might
1512 * end up with someone trying to store indirectly in
1513 * different buffers */
1514 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1515 break;
1516
1517 case TGSI_FILE_ADDRESS:
1518 index = reg->Register.Index;
1519 dst = &mach->Addrs[index].xyzw[chan_index];
1520 break;
1521
1522 case TGSI_FILE_PREDICATE:
1523 index = reg->Register.Index;
1524 assert(index < TGSI_EXEC_NUM_PREDS);
1525 dst = &mach->Predicates[index].xyzw[chan_index];
1526 break;
1527
1528 default:
1529 assert( 0 );
1530 return;
1531 }
1532
1533 if (inst->Instruction.Predicate) {
1534 uint swizzle;
1535 union tgsi_exec_channel *pred;
1536
1537 switch (chan_index) {
1538 case TGSI_CHAN_X:
1539 swizzle = inst->Predicate.SwizzleX;
1540 break;
1541 case TGSI_CHAN_Y:
1542 swizzle = inst->Predicate.SwizzleY;
1543 break;
1544 case TGSI_CHAN_Z:
1545 swizzle = inst->Predicate.SwizzleZ;
1546 break;
1547 case TGSI_CHAN_W:
1548 swizzle = inst->Predicate.SwizzleW;
1549 break;
1550 default:
1551 assert(0);
1552 return;
1553 }
1554
1555 assert(inst->Predicate.Index == 0);
1556
1557 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1558
1559 if (inst->Predicate.Negate) {
1560 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1561 if (pred->u[i]) {
1562 execmask &= ~(1 << i);
1563 }
1564 }
1565 } else {
1566 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1567 if (!pred->u[i]) {
1568 execmask &= ~(1 << i);
1569 }
1570 }
1571 }
1572 }
1573
1574 switch (inst->Instruction.Saturate) {
1575 case TGSI_SAT_NONE:
1576 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1577 if (execmask & (1 << i))
1578 dst->i[i] = chan->i[i];
1579 break;
1580
1581 case TGSI_SAT_ZERO_ONE:
1582 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1583 if (execmask & (1 << i)) {
1584 if (chan->f[i] < 0.0f)
1585 dst->f[i] = 0.0f;
1586 else if (chan->f[i] > 1.0f)
1587 dst->f[i] = 1.0f;
1588 else
1589 dst->i[i] = chan->i[i];
1590 }
1591 break;
1592
1593 case TGSI_SAT_MINUS_PLUS_ONE:
1594 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1595 if (execmask & (1 << i)) {
1596 if (chan->f[i] < -1.0f)
1597 dst->f[i] = -1.0f;
1598 else if (chan->f[i] > 1.0f)
1599 dst->f[i] = 1.0f;
1600 else
1601 dst->i[i] = chan->i[i];
1602 }
1603 break;
1604
1605 default:
1606 assert( 0 );
1607 }
1608 }
1609
1610 #define FETCH(VAL,INDEX,CHAN)\
1611 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1612
1613 #define IFETCH(VAL,INDEX,CHAN)\
1614 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1615
1616
1617 /**
1618 * Execute ARB-style KIL which is predicated by a src register.
1619 * Kill fragment if any of the four values is less than zero.
1620 */
1621 static void
1622 exec_kil(struct tgsi_exec_machine *mach,
1623 const struct tgsi_full_instruction *inst)
1624 {
1625 uint uniquemask;
1626 uint chan_index;
1627 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1628 union tgsi_exec_channel r[1];
1629
1630 /* This mask stores component bits that were already tested. */
1631 uniquemask = 0;
1632
1633 for (chan_index = 0; chan_index < 4; chan_index++)
1634 {
1635 uint swizzle;
1636 uint i;
1637
1638 /* unswizzle channel */
1639 swizzle = tgsi_util_get_full_src_register_swizzle (
1640 &inst->Src[0],
1641 chan_index);
1642
1643 /* check if the component has not been already tested */
1644 if (uniquemask & (1 << swizzle))
1645 continue;
1646 uniquemask |= 1 << swizzle;
1647
1648 FETCH(&r[0], 0, chan_index);
1649 for (i = 0; i < 4; i++)
1650 if (r[0].f[i] < 0.0f)
1651 kilmask |= 1 << i;
1652 }
1653
1654 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1655 }
1656
1657 /**
1658 * Execute NVIDIA-style KIL which is predicated by a condition code.
1659 * Kill fragment if the condition code is TRUE.
1660 */
1661 static void
1662 exec_kilp(struct tgsi_exec_machine *mach,
1663 const struct tgsi_full_instruction *inst)
1664 {
1665 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1666
1667 /* "unconditional" kil */
1668 kilmask = mach->ExecMask;
1669 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1670 }
1671
1672 static void
1673 emit_vertex(struct tgsi_exec_machine *mach)
1674 {
1675 /* FIXME: check for exec mask correctly
1676 unsigned i;
1677 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1678 if ((mach->ExecMask & (1 << i)))
1679 */
1680 if (mach->ExecMask) {
1681 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1682 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1683 }
1684 }
1685
1686 static void
1687 emit_primitive(struct tgsi_exec_machine *mach)
1688 {
1689 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1690 /* FIXME: check for exec mask correctly
1691 unsigned i;
1692 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1693 if ((mach->ExecMask & (1 << i)))
1694 */
1695 if (mach->ExecMask) {
1696 ++(*prim_count);
1697 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1698 mach->Primitives[*prim_count] = 0;
1699 }
1700 }
1701
1702 static void
1703 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1704 {
1705 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1706 int emitted_verts =
1707 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1708 if (emitted_verts) {
1709 emit_primitive(mach);
1710 }
1711 }
1712 }
1713
1714
1715 /*
1716 * Fetch four texture samples using STR texture coordinates.
1717 */
1718 static void
1719 fetch_texel( struct tgsi_sampler *sampler,
1720 const unsigned sview_idx,
1721 const unsigned sampler_idx,
1722 const union tgsi_exec_channel *s,
1723 const union tgsi_exec_channel *t,
1724 const union tgsi_exec_channel *p,
1725 const union tgsi_exec_channel *c0,
1726 const union tgsi_exec_channel *c1,
1727 float derivs[3][2][TGSI_QUAD_SIZE],
1728 const int8_t offset[3],
1729 enum tgsi_sampler_control control,
1730 union tgsi_exec_channel *r,
1731 union tgsi_exec_channel *g,
1732 union tgsi_exec_channel *b,
1733 union tgsi_exec_channel *a )
1734 {
1735 uint j;
1736 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1737
1738 /* FIXME: handle explicit derivs, offsets */
1739 sampler->get_samples(sampler, sview_idx, sampler_idx,
1740 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1741
1742 for (j = 0; j < 4; j++) {
1743 r->f[j] = rgba[0][j];
1744 g->f[j] = rgba[1][j];
1745 b->f[j] = rgba[2][j];
1746 a->f[j] = rgba[3][j];
1747 }
1748 }
1749
1750
1751 #define TEX_MODIFIER_NONE 0
1752 #define TEX_MODIFIER_PROJECTED 1
1753 #define TEX_MODIFIER_LOD_BIAS 2
1754 #define TEX_MODIFIER_EXPLICIT_LOD 3
1755 #define TEX_MODIFIER_LEVEL_ZERO 4
1756
1757
1758 /*
1759 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1760 */
1761 static void
1762 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1763 const struct tgsi_full_instruction *inst,
1764 int8_t offsets[3])
1765 {
1766 if (inst->Texture.NumOffsets == 1) {
1767 union tgsi_exec_channel index;
1768 union tgsi_exec_channel offset[3];
1769 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1770 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1771 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1772 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1773 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1774 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1775 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1776 offsets[0] = offset[0].i[0];
1777 offsets[1] = offset[1].i[0];
1778 offsets[2] = offset[2].i[0];
1779 } else {
1780 assert(inst->Texture.NumOffsets == 0);
1781 offsets[0] = offsets[1] = offsets[2] = 0;
1782 }
1783 }
1784
1785
1786 /*
1787 * Fetch dx and dy values for one channel (s, t or r).
1788 * Put dx values into one float array, dy values into another.
1789 */
1790 static void
1791 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1792 const struct tgsi_full_instruction *inst,
1793 unsigned regdsrcx,
1794 unsigned chan,
1795 float derivs[2][TGSI_QUAD_SIZE])
1796 {
1797 union tgsi_exec_channel d;
1798 FETCH(&d, regdsrcx, chan);
1799 derivs[0][0] = d.f[0];
1800 derivs[0][1] = d.f[1];
1801 derivs[0][2] = d.f[2];
1802 derivs[0][3] = d.f[3];
1803 FETCH(&d, regdsrcx + 1, chan);
1804 derivs[1][0] = d.f[0];
1805 derivs[1][1] = d.f[1];
1806 derivs[1][2] = d.f[2];
1807 derivs[1][3] = d.f[3];
1808 }
1809
1810
1811 /*
1812 * execute a texture instruction.
1813 *
1814 * modifier is used to control the channel routing for the\
1815 * instruction variants like proj, lod, and texture with lod bias.
1816 * sampler indicates which src register the sampler is contained in.
1817 */
1818 static void
1819 exec_tex(struct tgsi_exec_machine *mach,
1820 const struct tgsi_full_instruction *inst,
1821 uint modifier, uint sampler)
1822 {
1823 const uint unit = inst->Src[sampler].Register.Index;
1824 union tgsi_exec_channel r[4], cubearraycomp, cubelod;
1825 const union tgsi_exec_channel *lod = &ZeroVec;
1826 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1827 uint chan;
1828 int8_t offsets[3];
1829
1830 /* always fetch all 3 offsets, overkill but keeps code simple */
1831 fetch_texel_offsets(mach, inst, offsets);
1832
1833 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1834
1835 if (modifier != TEX_MODIFIER_NONE && (sampler == 1)) {
1836 FETCH(&r[3], 0, TGSI_CHAN_W);
1837 if (modifier != TEX_MODIFIER_PROJECTED) {
1838 lod = &r[3];
1839 }
1840 }
1841
1842 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1843 control = tgsi_sampler_lod_explicit;
1844 } else if (modifier == TEX_MODIFIER_LOD_BIAS){
1845 control = tgsi_sampler_lod_bias;
1846 }
1847
1848 switch (inst->Texture.Texture) {
1849 case TGSI_TEXTURE_1D:
1850 FETCH(&r[0], 0, TGSI_CHAN_X);
1851
1852 if (modifier == TEX_MODIFIER_PROJECTED) {
1853 micro_div(&r[0], &r[0], &r[3]);
1854 }
1855
1856 fetch_texel(mach->Sampler, unit, unit,
1857 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
1858 NULL, offsets, control,
1859 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1860 break;
1861
1862 case TGSI_TEXTURE_SHADOW1D:
1863 FETCH(&r[0], 0, TGSI_CHAN_X);
1864 FETCH(&r[2], 0, TGSI_CHAN_Z);
1865
1866 if (modifier == TEX_MODIFIER_PROJECTED) {
1867 micro_div(&r[0], &r[0], &r[3]);
1868 micro_div(&r[2], &r[2], &r[3]);
1869 }
1870
1871 fetch_texel(mach->Sampler, unit, unit,
1872 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
1873 NULL, offsets, control,
1874 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1875 break;
1876
1877 case TGSI_TEXTURE_2D:
1878 case TGSI_TEXTURE_RECT:
1879 FETCH(&r[0], 0, TGSI_CHAN_X);
1880 FETCH(&r[1], 0, TGSI_CHAN_Y);
1881
1882 if (modifier == TEX_MODIFIER_PROJECTED) {
1883 micro_div(&r[0], &r[0], &r[3]);
1884 micro_div(&r[1], &r[1], &r[3]);
1885 }
1886
1887 fetch_texel(mach->Sampler, unit, unit,
1888 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
1889 NULL, offsets, control,
1890 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1891 break;
1892
1893 case TGSI_TEXTURE_SHADOW2D:
1894 case TGSI_TEXTURE_SHADOWRECT:
1895 FETCH(&r[0], 0, TGSI_CHAN_X);
1896 FETCH(&r[1], 0, TGSI_CHAN_Y);
1897 FETCH(&r[2], 0, TGSI_CHAN_Z);
1898
1899 if (modifier == TEX_MODIFIER_PROJECTED) {
1900 micro_div(&r[0], &r[0], &r[3]);
1901 micro_div(&r[1], &r[1], &r[3]);
1902 micro_div(&r[2], &r[2], &r[3]);
1903 }
1904
1905 fetch_texel(mach->Sampler, unit, unit,
1906 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
1907 NULL, offsets, control,
1908 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1909 break;
1910
1911 case TGSI_TEXTURE_1D_ARRAY:
1912 FETCH(&r[0], 0, TGSI_CHAN_X);
1913 FETCH(&r[1], 0, TGSI_CHAN_Y);
1914
1915 if (modifier == TEX_MODIFIER_PROJECTED) {
1916 micro_div(&r[0], &r[0], &r[3]);
1917 }
1918
1919 fetch_texel(mach->Sampler, unit, unit,
1920 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
1921 NULL, offsets, control,
1922 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1923 break;
1924 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1925 FETCH(&r[0], 0, TGSI_CHAN_X);
1926 FETCH(&r[1], 0, TGSI_CHAN_Y);
1927 FETCH(&r[2], 0, TGSI_CHAN_Z);
1928
1929 if (modifier == TEX_MODIFIER_PROJECTED) {
1930 micro_div(&r[0], &r[0], &r[3]);
1931 micro_div(&r[2], &r[2], &r[3]);
1932 }
1933
1934 fetch_texel(mach->Sampler, unit, unit,
1935 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
1936 NULL, offsets, control,
1937 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1938 break;
1939
1940 case TGSI_TEXTURE_2D_ARRAY:
1941 FETCH(&r[0], 0, TGSI_CHAN_X);
1942 FETCH(&r[1], 0, TGSI_CHAN_Y);
1943 FETCH(&r[2], 0, TGSI_CHAN_Z);
1944
1945 if (modifier == TEX_MODIFIER_PROJECTED) {
1946 micro_div(&r[0], &r[0], &r[3]);
1947 micro_div(&r[1], &r[1], &r[3]);
1948 }
1949
1950 fetch_texel(mach->Sampler, unit, unit,
1951 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
1952 NULL, offsets, control,
1953 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1954 break;
1955 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1956 case TGSI_TEXTURE_SHADOWCUBE:
1957 FETCH(&r[0], 0, TGSI_CHAN_X);
1958 FETCH(&r[1], 0, TGSI_CHAN_Y);
1959 FETCH(&r[2], 0, TGSI_CHAN_Z);
1960 FETCH(&r[3], 0, TGSI_CHAN_W);
1961
1962 fetch_texel(mach->Sampler, unit, unit,
1963 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* S, T, P, C, LOD */
1964 NULL, offsets, control,
1965 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1966 break;
1967 case TGSI_TEXTURE_CUBE_ARRAY:
1968 FETCH(&r[0], 0, TGSI_CHAN_X);
1969 FETCH(&r[1], 0, TGSI_CHAN_Y);
1970 FETCH(&r[2], 0, TGSI_CHAN_Z);
1971 FETCH(&r[3], 0, TGSI_CHAN_W);
1972
1973 if (modifier == TEX_MODIFIER_EXPLICIT_LOD ||
1974 modifier == TEX_MODIFIER_LOD_BIAS)
1975 FETCH(&cubelod, 1, TGSI_CHAN_X);
1976 else
1977 cubelod = ZeroVec;
1978
1979 fetch_texel(mach->Sampler, unit, unit,
1980 &r[0], &r[1], &r[2], &r[3], &cubelod, /* S, T, P, C, LOD */
1981 NULL, offsets, control,
1982 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1983 break;
1984 case TGSI_TEXTURE_3D:
1985 case TGSI_TEXTURE_CUBE:
1986 FETCH(&r[0], 0, TGSI_CHAN_X);
1987 FETCH(&r[1], 0, TGSI_CHAN_Y);
1988 FETCH(&r[2], 0, TGSI_CHAN_Z);
1989
1990 if (modifier == TEX_MODIFIER_PROJECTED) {
1991 micro_div(&r[0], &r[0], &r[3]);
1992 micro_div(&r[1], &r[1], &r[3]);
1993 micro_div(&r[2], &r[2], &r[3]);
1994 }
1995
1996 fetch_texel(mach->Sampler, unit, unit,
1997 &r[0], &r[1], &r[2], &ZeroVec, lod,
1998 NULL, offsets, control,
1999 &r[0], &r[1], &r[2], &r[3]);
2000 break;
2001
2002 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2003 FETCH(&r[0], 0, TGSI_CHAN_X);
2004 FETCH(&r[1], 0, TGSI_CHAN_Y);
2005 FETCH(&r[2], 0, TGSI_CHAN_Z);
2006 FETCH(&r[3], 0, TGSI_CHAN_W);
2007
2008 FETCH(&cubearraycomp, 1, TGSI_CHAN_X);
2009
2010 fetch_texel(mach->Sampler, unit, unit,
2011 &r[0], &r[1], &r[2], &r[3], &cubearraycomp, /* S, T, P, C, LOD */
2012 NULL, offsets, control,
2013 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2014 break;
2015 default:
2016 assert(0);
2017 }
2018
2019 #if 0
2020 debug_printf("fetch r: %g %g %g %g\n",
2021 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2022 debug_printf("fetch g: %g %g %g %g\n",
2023 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2024 debug_printf("fetch b: %g %g %g %g\n",
2025 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2026 debug_printf("fetch a: %g %g %g %g\n",
2027 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2028 #endif
2029
2030 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2031 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2032 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2033 }
2034 }
2035 }
2036
2037
2038 static void
2039 exec_txd(struct tgsi_exec_machine *mach,
2040 const struct tgsi_full_instruction *inst)
2041 {
2042 const uint unit = inst->Src[3].Register.Index;
2043 union tgsi_exec_channel r[4];
2044 float derivs[3][2][TGSI_QUAD_SIZE];
2045 uint chan;
2046 int8_t offsets[3];
2047
2048 /* always fetch all 3 offsets, overkill but keeps code simple */
2049 fetch_texel_offsets(mach, inst, offsets);
2050
2051 switch (inst->Texture.Texture) {
2052 case TGSI_TEXTURE_1D:
2053 FETCH(&r[0], 0, TGSI_CHAN_X);
2054
2055 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2056
2057 fetch_texel(mach->Sampler, unit, unit,
2058 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2059 derivs, offsets, tgsi_sampler_derivs_explicit,
2060 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2061 break;
2062
2063 case TGSI_TEXTURE_SHADOW1D:
2064 case TGSI_TEXTURE_1D_ARRAY:
2065 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2066 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2067 FETCH(&r[0], 0, TGSI_CHAN_X);
2068 FETCH(&r[1], 0, TGSI_CHAN_Y);
2069 FETCH(&r[2], 0, TGSI_CHAN_Z);
2070
2071 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2072
2073 fetch_texel(mach->Sampler, unit, unit,
2074 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2075 derivs, offsets, tgsi_sampler_derivs_explicit,
2076 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2077 break;
2078
2079 case TGSI_TEXTURE_2D:
2080 case TGSI_TEXTURE_RECT:
2081 FETCH(&r[0], 0, TGSI_CHAN_X);
2082 FETCH(&r[1], 0, TGSI_CHAN_Y);
2083
2084 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2085 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2086
2087 fetch_texel(mach->Sampler, unit, unit,
2088 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2089 derivs, offsets, tgsi_sampler_derivs_explicit,
2090 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2091 break;
2092
2093
2094 case TGSI_TEXTURE_SHADOW2D:
2095 case TGSI_TEXTURE_SHADOWRECT:
2096 case TGSI_TEXTURE_2D_ARRAY:
2097 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2098 /* only SHADOW2D_ARRAY actually needs W */
2099 FETCH(&r[0], 0, TGSI_CHAN_X);
2100 FETCH(&r[1], 0, TGSI_CHAN_Y);
2101 FETCH(&r[2], 0, TGSI_CHAN_Z);
2102 FETCH(&r[3], 0, TGSI_CHAN_W);
2103
2104 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2105 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2106
2107 fetch_texel(mach->Sampler, unit, unit,
2108 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2109 derivs, offsets, tgsi_sampler_derivs_explicit,
2110 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2111 break;
2112
2113 case TGSI_TEXTURE_3D:
2114 case TGSI_TEXTURE_CUBE:
2115 case TGSI_TEXTURE_CUBE_ARRAY:
2116 /* only TEXTURE_CUBE_ARRAY actually needs W */
2117 FETCH(&r[0], 0, TGSI_CHAN_X);
2118 FETCH(&r[1], 0, TGSI_CHAN_Y);
2119 FETCH(&r[2], 0, TGSI_CHAN_Z);
2120 FETCH(&r[3], 0, TGSI_CHAN_W);
2121
2122 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2123 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2124 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2125
2126 fetch_texel(mach->Sampler, unit, unit,
2127 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2128 derivs, offsets, tgsi_sampler_derivs_explicit,
2129 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2130 break;
2131
2132 default:
2133 assert(0);
2134 }
2135
2136 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2137 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2138 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2139 }
2140 }
2141 }
2142
2143
2144 static void
2145 exec_txf(struct tgsi_exec_machine *mach,
2146 const struct tgsi_full_instruction *inst)
2147 {
2148 const uint unit = inst->Src[1].Register.Index;
2149 union tgsi_exec_channel r[4];
2150 uint chan;
2151 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2152 int j;
2153 int8_t offsets[3];
2154 unsigned target;
2155
2156 /* always fetch all 3 offsets, overkill but keeps code simple */
2157 fetch_texel_offsets(mach, inst, offsets);
2158
2159 IFETCH(&r[3], 0, TGSI_CHAN_W);
2160
2161 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2162 target = mach->SamplerViews[unit].Resource;
2163 }
2164 else {
2165 target = inst->Texture.Texture;
2166 }
2167 switch(target) {
2168 case TGSI_TEXTURE_3D:
2169 case TGSI_TEXTURE_2D_ARRAY:
2170 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2171 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2172 /* fallthrough */
2173 case TGSI_TEXTURE_2D:
2174 case TGSI_TEXTURE_RECT:
2175 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2176 case TGSI_TEXTURE_SHADOW2D:
2177 case TGSI_TEXTURE_SHADOWRECT:
2178 case TGSI_TEXTURE_1D_ARRAY:
2179 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2180 /* fallthrough */
2181 case TGSI_TEXTURE_BUFFER:
2182 case TGSI_TEXTURE_1D:
2183 case TGSI_TEXTURE_SHADOW1D:
2184 IFETCH(&r[0], 0, TGSI_CHAN_X);
2185 break;
2186 default:
2187 assert(0);
2188 break;
2189 }
2190
2191 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2192 offsets, rgba);
2193
2194 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2195 r[0].f[j] = rgba[0][j];
2196 r[1].f[j] = rgba[1][j];
2197 r[2].f[j] = rgba[2][j];
2198 r[3].f[j] = rgba[3][j];
2199 }
2200
2201 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2202 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2203 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2204 }
2205 }
2206 }
2207
2208 static void
2209 exec_txq(struct tgsi_exec_machine *mach,
2210 const struct tgsi_full_instruction *inst)
2211 {
2212 const uint unit = inst->Src[1].Register.Index;
2213 int result[4];
2214 union tgsi_exec_channel r[4], src;
2215 uint chan;
2216 int i,j;
2217
2218 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2219
2220 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2221
2222 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2223 for (j = 0; j < 4; j++) {
2224 r[j].i[i] = result[j];
2225 }
2226 }
2227
2228 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2229 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2230 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2231 TGSI_EXEC_DATA_INT);
2232 }
2233 }
2234 }
2235
2236 static void
2237 exec_sample(struct tgsi_exec_machine *mach,
2238 const struct tgsi_full_instruction *inst,
2239 uint modifier, boolean compare)
2240 {
2241 const uint resource_unit = inst->Src[1].Register.Index;
2242 const uint sampler_unit = inst->Src[2].Register.Index;
2243 union tgsi_exec_channel r[4], c1;
2244 const union tgsi_exec_channel *lod = &ZeroVec;
2245 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2246 uint chan;
2247 int8_t offsets[3];
2248
2249 /* always fetch all 3 offsets, overkill but keeps code simple */
2250 fetch_texel_offsets(mach, inst, offsets);
2251
2252 assert(modifier != TEX_MODIFIER_PROJECTED);
2253
2254 if (modifier != TEX_MODIFIER_NONE) {
2255 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2256 FETCH(&c1, 3, TGSI_CHAN_X);
2257 lod = &c1;
2258 control = tgsi_sampler_lod_bias;
2259 }
2260 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2261 FETCH(&c1, 3, TGSI_CHAN_X);
2262 lod = &c1;
2263 control = tgsi_sampler_lod_explicit;
2264 }
2265 else {
2266 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2267 control = tgsi_sampler_lod_zero;
2268 }
2269 }
2270
2271 FETCH(&r[0], 0, TGSI_CHAN_X);
2272
2273 switch (mach->SamplerViews[resource_unit].Resource) {
2274 case TGSI_TEXTURE_1D:
2275 if (compare) {
2276 FETCH(&r[2], 3, TGSI_CHAN_X);
2277 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2278 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2279 NULL, offsets, control,
2280 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2281 }
2282 else {
2283 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2284 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2285 NULL, offsets, control,
2286 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2287 }
2288 break;
2289
2290 case TGSI_TEXTURE_1D_ARRAY:
2291 case TGSI_TEXTURE_2D:
2292 case TGSI_TEXTURE_RECT:
2293 FETCH(&r[1], 0, TGSI_CHAN_Y);
2294 if (compare) {
2295 FETCH(&r[2], 3, TGSI_CHAN_X);
2296 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2297 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2298 NULL, offsets, control,
2299 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2300 }
2301 else {
2302 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2303 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2304 NULL, offsets, control,
2305 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2306 }
2307 break;
2308
2309 case TGSI_TEXTURE_2D_ARRAY:
2310 case TGSI_TEXTURE_3D:
2311 case TGSI_TEXTURE_CUBE:
2312 FETCH(&r[1], 0, TGSI_CHAN_Y);
2313 FETCH(&r[2], 0, TGSI_CHAN_Z);
2314 if(compare) {
2315 FETCH(&r[3], 3, TGSI_CHAN_X);
2316 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2317 &r[0], &r[1], &r[2], &r[3], lod,
2318 NULL, offsets, control,
2319 &r[0], &r[1], &r[2], &r[3]);
2320 }
2321 else {
2322 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2323 &r[0], &r[1], &r[2], &ZeroVec, lod,
2324 NULL, offsets, control,
2325 &r[0], &r[1], &r[2], &r[3]);
2326 }
2327 break;
2328
2329 case TGSI_TEXTURE_CUBE_ARRAY:
2330 FETCH(&r[1], 0, TGSI_CHAN_Y);
2331 FETCH(&r[2], 0, TGSI_CHAN_Z);
2332 FETCH(&r[3], 0, TGSI_CHAN_W);
2333 if(compare) {
2334 FETCH(&r[4], 3, TGSI_CHAN_X);
2335 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2336 &r[0], &r[1], &r[2], &r[3], &r[4],
2337 NULL, offsets, control,
2338 &r[0], &r[1], &r[2], &r[3]);
2339 }
2340 else {
2341 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2342 &r[0], &r[1], &r[2], &r[3], lod,
2343 NULL, offsets, control,
2344 &r[0], &r[1], &r[2], &r[3]);
2345 }
2346 break;
2347
2348
2349 default:
2350 assert(0);
2351 }
2352
2353 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2354 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2355 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2356 }
2357 }
2358 }
2359
2360 static void
2361 exec_sample_d(struct tgsi_exec_machine *mach,
2362 const struct tgsi_full_instruction *inst)
2363 {
2364 const uint resource_unit = inst->Src[1].Register.Index;
2365 const uint sampler_unit = inst->Src[2].Register.Index;
2366 union tgsi_exec_channel r[4];
2367 float derivs[3][2][TGSI_QUAD_SIZE];
2368 uint chan;
2369 int8_t offsets[3];
2370
2371 /* always fetch all 3 offsets, overkill but keeps code simple */
2372 fetch_texel_offsets(mach, inst, offsets);
2373
2374 FETCH(&r[0], 0, TGSI_CHAN_X);
2375
2376 switch (mach->SamplerViews[resource_unit].Resource) {
2377 case TGSI_TEXTURE_1D:
2378 case TGSI_TEXTURE_1D_ARRAY:
2379 /* only 1D array actually needs Y */
2380 FETCH(&r[1], 0, TGSI_CHAN_Y);
2381
2382 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2383
2384 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2385 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2386 derivs, offsets, tgsi_sampler_derivs_explicit,
2387 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2388 break;
2389
2390 case TGSI_TEXTURE_2D:
2391 case TGSI_TEXTURE_RECT:
2392 case TGSI_TEXTURE_2D_ARRAY:
2393 /* only 2D array actually needs Z */
2394 FETCH(&r[1], 0, TGSI_CHAN_Y);
2395 FETCH(&r[2], 0, TGSI_CHAN_Z);
2396
2397 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2398 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2399
2400 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2401 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2402 derivs, offsets, tgsi_sampler_derivs_explicit,
2403 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2404 break;
2405
2406 case TGSI_TEXTURE_3D:
2407 case TGSI_TEXTURE_CUBE:
2408 case TGSI_TEXTURE_CUBE_ARRAY:
2409 /* only cube array actually needs W */
2410 FETCH(&r[1], 0, TGSI_CHAN_Y);
2411 FETCH(&r[2], 0, TGSI_CHAN_Z);
2412 FETCH(&r[3], 0, TGSI_CHAN_W);
2413
2414 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2415 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2416 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2417
2418 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2419 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2420 derivs, offsets, tgsi_sampler_derivs_explicit,
2421 &r[0], &r[1], &r[2], &r[3]);
2422 break;
2423
2424 default:
2425 assert(0);
2426 }
2427
2428 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2429 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2430 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2431 }
2432 }
2433 }
2434
2435
2436 /**
2437 * Evaluate a constant-valued coefficient at the position of the
2438 * current quad.
2439 */
2440 static void
2441 eval_constant_coef(
2442 struct tgsi_exec_machine *mach,
2443 unsigned attrib,
2444 unsigned chan )
2445 {
2446 unsigned i;
2447
2448 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2449 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2450 }
2451 }
2452
2453 /**
2454 * Evaluate a linear-valued coefficient at the position of the
2455 * current quad.
2456 */
2457 static void
2458 eval_linear_coef(
2459 struct tgsi_exec_machine *mach,
2460 unsigned attrib,
2461 unsigned chan )
2462 {
2463 const float x = mach->QuadPos.xyzw[0].f[0];
2464 const float y = mach->QuadPos.xyzw[1].f[0];
2465 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2466 const float dady = mach->InterpCoefs[attrib].dady[chan];
2467 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2468 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2469 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2470 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2471 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2472 }
2473
2474 /**
2475 * Evaluate a perspective-valued coefficient at the position of the
2476 * current quad.
2477 */
2478 static void
2479 eval_perspective_coef(
2480 struct tgsi_exec_machine *mach,
2481 unsigned attrib,
2482 unsigned chan )
2483 {
2484 const float x = mach->QuadPos.xyzw[0].f[0];
2485 const float y = mach->QuadPos.xyzw[1].f[0];
2486 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2487 const float dady = mach->InterpCoefs[attrib].dady[chan];
2488 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2489 const float *w = mach->QuadPos.xyzw[3].f;
2490 /* divide by W here */
2491 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2492 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2493 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2494 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2495 }
2496
2497
2498 typedef void (* eval_coef_func)(
2499 struct tgsi_exec_machine *mach,
2500 unsigned attrib,
2501 unsigned chan );
2502
2503 static void
2504 exec_declaration(struct tgsi_exec_machine *mach,
2505 const struct tgsi_full_declaration *decl)
2506 {
2507 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2508 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2509 return;
2510 }
2511
2512 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2513 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2514 uint first, last, mask;
2515
2516 first = decl->Range.First;
2517 last = decl->Range.Last;
2518 mask = decl->Declaration.UsageMask;
2519
2520 /* XXX we could remove this special-case code since
2521 * mach->InterpCoefs[first].a0 should already have the
2522 * front/back-face value. But we should first update the
2523 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2524 * Then, we could remove the tgsi_exec_machine::Face field.
2525 */
2526 /* XXX make FACE a system value */
2527 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2528 uint i;
2529
2530 assert(decl->Semantic.Index == 0);
2531 assert(first == last);
2532
2533 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2534 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2535 }
2536 } else {
2537 eval_coef_func eval;
2538 uint i, j;
2539
2540 switch (decl->Interp.Interpolate) {
2541 case TGSI_INTERPOLATE_CONSTANT:
2542 eval = eval_constant_coef;
2543 break;
2544
2545 case TGSI_INTERPOLATE_LINEAR:
2546 eval = eval_linear_coef;
2547 break;
2548
2549 case TGSI_INTERPOLATE_PERSPECTIVE:
2550 eval = eval_perspective_coef;
2551 break;
2552
2553 case TGSI_INTERPOLATE_COLOR:
2554 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2555 break;
2556
2557 default:
2558 assert(0);
2559 return;
2560 }
2561
2562 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2563 if (mask & (1 << j)) {
2564 for (i = first; i <= last; i++) {
2565 eval(mach, i, j);
2566 }
2567 }
2568 }
2569 }
2570
2571 if (DEBUG_EXECUTION) {
2572 uint i, j;
2573 for (i = first; i <= last; ++i) {
2574 debug_printf("IN[%2u] = ", i);
2575 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2576 if (j > 0) {
2577 debug_printf(" ");
2578 }
2579 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2580 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2581 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2582 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2583 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2584 }
2585 }
2586 }
2587 }
2588 }
2589
2590 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2591 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2592 }
2593 }
2594
2595
2596 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2597
2598 static void
2599 exec_vector(struct tgsi_exec_machine *mach,
2600 const struct tgsi_full_instruction *inst,
2601 micro_op op,
2602 enum tgsi_exec_datatype dst_datatype)
2603 {
2604 unsigned int chan;
2605
2606 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2607 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2608 union tgsi_exec_channel dst;
2609
2610 op(&dst);
2611 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2612 }
2613 }
2614 }
2615
2616 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2617 const union tgsi_exec_channel *src);
2618
2619 static void
2620 exec_scalar_unary(struct tgsi_exec_machine *mach,
2621 const struct tgsi_full_instruction *inst,
2622 micro_unary_op op,
2623 enum tgsi_exec_datatype dst_datatype,
2624 enum tgsi_exec_datatype src_datatype)
2625 {
2626 unsigned int chan;
2627 union tgsi_exec_channel src;
2628 union tgsi_exec_channel dst;
2629
2630 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2631 op(&dst, &src);
2632 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2633 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2634 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2635 }
2636 }
2637 }
2638
2639 static void
2640 exec_vector_unary(struct tgsi_exec_machine *mach,
2641 const struct tgsi_full_instruction *inst,
2642 micro_unary_op op,
2643 enum tgsi_exec_datatype dst_datatype,
2644 enum tgsi_exec_datatype src_datatype)
2645 {
2646 unsigned int chan;
2647 struct tgsi_exec_vector dst;
2648
2649 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2650 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2651 union tgsi_exec_channel src;
2652
2653 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2654 op(&dst.xyzw[chan], &src);
2655 }
2656 }
2657 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2658 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2659 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2660 }
2661 }
2662 }
2663
2664 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2665 const union tgsi_exec_channel *src0,
2666 const union tgsi_exec_channel *src1);
2667
2668 static void
2669 exec_scalar_binary(struct tgsi_exec_machine *mach,
2670 const struct tgsi_full_instruction *inst,
2671 micro_binary_op op,
2672 enum tgsi_exec_datatype dst_datatype,
2673 enum tgsi_exec_datatype src_datatype)
2674 {
2675 unsigned int chan;
2676 union tgsi_exec_channel src[2];
2677 union tgsi_exec_channel dst;
2678
2679 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2680 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_Y, src_datatype);
2681 op(&dst, &src[0], &src[1]);
2682 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2683 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2684 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2685 }
2686 }
2687 }
2688
2689 static void
2690 exec_vector_binary(struct tgsi_exec_machine *mach,
2691 const struct tgsi_full_instruction *inst,
2692 micro_binary_op op,
2693 enum tgsi_exec_datatype dst_datatype,
2694 enum tgsi_exec_datatype src_datatype)
2695 {
2696 unsigned int chan;
2697 struct tgsi_exec_vector dst;
2698
2699 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2700 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2701 union tgsi_exec_channel src[2];
2702
2703 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2704 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2705 op(&dst.xyzw[chan], &src[0], &src[1]);
2706 }
2707 }
2708 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2709 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2710 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2711 }
2712 }
2713 }
2714
2715 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2716 const union tgsi_exec_channel *src0,
2717 const union tgsi_exec_channel *src1,
2718 const union tgsi_exec_channel *src2);
2719
2720 static void
2721 exec_vector_trinary(struct tgsi_exec_machine *mach,
2722 const struct tgsi_full_instruction *inst,
2723 micro_trinary_op op,
2724 enum tgsi_exec_datatype dst_datatype,
2725 enum tgsi_exec_datatype src_datatype)
2726 {
2727 unsigned int chan;
2728 struct tgsi_exec_vector dst;
2729
2730 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2731 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2732 union tgsi_exec_channel src[3];
2733
2734 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2735 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2736 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2737 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2738 }
2739 }
2740 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2741 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2742 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2743 }
2744 }
2745 }
2746
2747 static void
2748 exec_dp3(struct tgsi_exec_machine *mach,
2749 const struct tgsi_full_instruction *inst)
2750 {
2751 unsigned int chan;
2752 union tgsi_exec_channel arg[3];
2753
2754 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2755 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2756 micro_mul(&arg[2], &arg[0], &arg[1]);
2757
2758 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2759 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2760 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2761 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2762 }
2763
2764 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2765 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2766 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2767 }
2768 }
2769 }
2770
2771 static void
2772 exec_dp4(struct tgsi_exec_machine *mach,
2773 const struct tgsi_full_instruction *inst)
2774 {
2775 unsigned int chan;
2776 union tgsi_exec_channel arg[3];
2777
2778 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2779 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2780 micro_mul(&arg[2], &arg[0], &arg[1]);
2781
2782 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2783 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2784 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2785 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2786 }
2787
2788 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2789 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2790 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2791 }
2792 }
2793 }
2794
2795 static void
2796 exec_dp2a(struct tgsi_exec_machine *mach,
2797 const struct tgsi_full_instruction *inst)
2798 {
2799 unsigned int chan;
2800 union tgsi_exec_channel arg[3];
2801
2802 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2803 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2804 micro_mul(&arg[2], &arg[0], &arg[1]);
2805
2806 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2807 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2808 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2809
2810 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2811 micro_add(&arg[0], &arg[0], &arg[1]);
2812
2813 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2814 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2815 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2816 }
2817 }
2818 }
2819
2820 static void
2821 exec_dph(struct tgsi_exec_machine *mach,
2822 const struct tgsi_full_instruction *inst)
2823 {
2824 unsigned int chan;
2825 union tgsi_exec_channel arg[3];
2826
2827 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2828 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2829 micro_mul(&arg[2], &arg[0], &arg[1]);
2830
2831 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2832 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2833 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2834
2835 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2836 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2837 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2838
2839 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2840 micro_add(&arg[0], &arg[0], &arg[1]);
2841
2842 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2843 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2844 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2845 }
2846 }
2847 }
2848
2849 static void
2850 exec_dp2(struct tgsi_exec_machine *mach,
2851 const struct tgsi_full_instruction *inst)
2852 {
2853 unsigned int chan;
2854 union tgsi_exec_channel arg[3];
2855
2856 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2857 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2858 micro_mul(&arg[2], &arg[0], &arg[1]);
2859
2860 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2861 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2862 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2863
2864 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2865 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2866 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2867 }
2868 }
2869 }
2870
2871 static void
2872 exec_nrm4(struct tgsi_exec_machine *mach,
2873 const struct tgsi_full_instruction *inst)
2874 {
2875 unsigned int chan;
2876 union tgsi_exec_channel arg[4];
2877 union tgsi_exec_channel scale;
2878
2879 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2880 micro_mul(&scale, &arg[0], &arg[0]);
2881
2882 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2883 union tgsi_exec_channel product;
2884
2885 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2886 micro_mul(&product, &arg[chan], &arg[chan]);
2887 micro_add(&scale, &scale, &product);
2888 }
2889
2890 micro_rsq(&scale, &scale);
2891
2892 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2893 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2894 micro_mul(&arg[chan], &arg[chan], &scale);
2895 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2896 }
2897 }
2898 }
2899
2900 static void
2901 exec_nrm3(struct tgsi_exec_machine *mach,
2902 const struct tgsi_full_instruction *inst)
2903 {
2904 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2905 unsigned int chan;
2906 union tgsi_exec_channel arg[3];
2907 union tgsi_exec_channel scale;
2908
2909 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2910 micro_mul(&scale, &arg[0], &arg[0]);
2911
2912 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2913 union tgsi_exec_channel product;
2914
2915 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2916 micro_mul(&product, &arg[chan], &arg[chan]);
2917 micro_add(&scale, &scale, &product);
2918 }
2919
2920 micro_rsq(&scale, &scale);
2921
2922 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2923 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2924 micro_mul(&arg[chan], &arg[chan], &scale);
2925 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2926 }
2927 }
2928 }
2929
2930 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2931 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2932 }
2933 }
2934
2935 static void
2936 exec_scs(struct tgsi_exec_machine *mach,
2937 const struct tgsi_full_instruction *inst)
2938 {
2939 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2940 union tgsi_exec_channel arg;
2941 union tgsi_exec_channel result;
2942
2943 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2944
2945 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2946 micro_cos(&result, &arg);
2947 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2948 }
2949 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2950 micro_sin(&result, &arg);
2951 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2952 }
2953 }
2954 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2955 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2956 }
2957 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2958 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2959 }
2960 }
2961
2962 static void
2963 exec_x2d(struct tgsi_exec_machine *mach,
2964 const struct tgsi_full_instruction *inst)
2965 {
2966 union tgsi_exec_channel r[4];
2967 union tgsi_exec_channel d[2];
2968
2969 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2970 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2971 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2972 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2973 micro_mul(&r[2], &r[2], &r[0]);
2974 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2975 micro_mul(&r[3], &r[3], &r[1]);
2976 micro_add(&r[2], &r[2], &r[3]);
2977 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2978 micro_add(&d[0], &r[2], &r[3]);
2979 }
2980 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2981 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2982 micro_mul(&r[2], &r[2], &r[0]);
2983 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2984 micro_mul(&r[3], &r[3], &r[1]);
2985 micro_add(&r[2], &r[2], &r[3]);
2986 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2987 micro_add(&d[1], &r[2], &r[3]);
2988 }
2989 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2990 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2991 }
2992 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2993 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2994 }
2995 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2996 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2997 }
2998 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2999 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3000 }
3001 }
3002
3003 static void
3004 exec_rfl(struct tgsi_exec_machine *mach,
3005 const struct tgsi_full_instruction *inst)
3006 {
3007 union tgsi_exec_channel r[9];
3008
3009 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
3010 /* r0 = dp3(src0, src0) */
3011 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3012 micro_mul(&r[0], &r[2], &r[2]);
3013 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3014 micro_mul(&r[8], &r[4], &r[4]);
3015 micro_add(&r[0], &r[0], &r[8]);
3016 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3017 micro_mul(&r[8], &r[6], &r[6]);
3018 micro_add(&r[0], &r[0], &r[8]);
3019
3020 /* r1 = dp3(src0, src1) */
3021 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3022 micro_mul(&r[1], &r[2], &r[3]);
3023 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3024 micro_mul(&r[8], &r[4], &r[5]);
3025 micro_add(&r[1], &r[1], &r[8]);
3026 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3027 micro_mul(&r[8], &r[6], &r[7]);
3028 micro_add(&r[1], &r[1], &r[8]);
3029
3030 /* r1 = 2 * r1 / r0 */
3031 micro_add(&r[1], &r[1], &r[1]);
3032 micro_div(&r[1], &r[1], &r[0]);
3033
3034 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3035 micro_mul(&r[2], &r[2], &r[1]);
3036 micro_sub(&r[2], &r[2], &r[3]);
3037 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3038 }
3039 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3040 micro_mul(&r[4], &r[4], &r[1]);
3041 micro_sub(&r[4], &r[4], &r[5]);
3042 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3043 }
3044 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3045 micro_mul(&r[6], &r[6], &r[1]);
3046 micro_sub(&r[6], &r[6], &r[7]);
3047 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3048 }
3049 }
3050 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3051 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3052 }
3053 }
3054
3055 static void
3056 exec_xpd(struct tgsi_exec_machine *mach,
3057 const struct tgsi_full_instruction *inst)
3058 {
3059 union tgsi_exec_channel r[6];
3060 union tgsi_exec_channel d[3];
3061
3062 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3063 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3064
3065 micro_mul(&r[2], &r[0], &r[1]);
3066
3067 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3068 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3069
3070 micro_mul(&r[5], &r[3], &r[4] );
3071 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3072
3073 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3074
3075 micro_mul(&r[3], &r[3], &r[2]);
3076
3077 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3078
3079 micro_mul(&r[1], &r[1], &r[5]);
3080 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3081
3082 micro_mul(&r[5], &r[5], &r[4]);
3083 micro_mul(&r[0], &r[0], &r[2]);
3084 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3085
3086 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3087 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3088 }
3089 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3090 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3091 }
3092 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3093 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3094 }
3095 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3096 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3097 }
3098 }
3099
3100 static void
3101 exec_dst(struct tgsi_exec_machine *mach,
3102 const struct tgsi_full_instruction *inst)
3103 {
3104 union tgsi_exec_channel r[2];
3105 union tgsi_exec_channel d[4];
3106
3107 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3108 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3109 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3110 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3111 }
3112 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3113 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3114 }
3115 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3116 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3117 }
3118
3119 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3120 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3121 }
3122 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3123 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3124 }
3125 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3126 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3127 }
3128 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3129 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3130 }
3131 }
3132
3133 static void
3134 exec_log(struct tgsi_exec_machine *mach,
3135 const struct tgsi_full_instruction *inst)
3136 {
3137 union tgsi_exec_channel r[3];
3138
3139 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3140 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3141 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3142 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3143 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3144 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3145 }
3146 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3147 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3148 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3149 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3150 }
3151 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3152 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3153 }
3154 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3155 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3156 }
3157 }
3158
3159 static void
3160 exec_exp(struct tgsi_exec_machine *mach,
3161 const struct tgsi_full_instruction *inst)
3162 {
3163 union tgsi_exec_channel r[3];
3164
3165 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3166 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3167 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3168 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3169 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3170 }
3171 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3172 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3173 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3174 }
3175 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3176 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3177 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3178 }
3179 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3180 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3181 }
3182 }
3183
3184 static void
3185 exec_lit(struct tgsi_exec_machine *mach,
3186 const struct tgsi_full_instruction *inst)
3187 {
3188 union tgsi_exec_channel r[3];
3189 union tgsi_exec_channel d[3];
3190
3191 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3192 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3193 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3194 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3195 micro_max(&r[1], &r[1], &ZeroVec);
3196
3197 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3198 micro_min(&r[2], &r[2], &P128Vec);
3199 micro_max(&r[2], &r[2], &M128Vec);
3200 micro_pow(&r[1], &r[1], &r[2]);
3201 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3202 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3203 }
3204 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3205 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3206 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3207 }
3208 }
3209 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3210 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3211 }
3212
3213 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3214 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3215 }
3216 }
3217
3218 static void
3219 exec_break(struct tgsi_exec_machine *mach)
3220 {
3221 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3222 /* turn off loop channels for each enabled exec channel */
3223 mach->LoopMask &= ~mach->ExecMask;
3224 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3225 UPDATE_EXEC_MASK(mach);
3226 } else {
3227 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3228
3229 mach->Switch.mask = 0x0;
3230
3231 UPDATE_EXEC_MASK(mach);
3232 }
3233 }
3234
3235 static void
3236 exec_switch(struct tgsi_exec_machine *mach,
3237 const struct tgsi_full_instruction *inst)
3238 {
3239 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3240 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3241
3242 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3243 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3244 mach->Switch.mask = 0x0;
3245 mach->Switch.defaultMask = 0x0;
3246
3247 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3248 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3249
3250 UPDATE_EXEC_MASK(mach);
3251 }
3252
3253 static void
3254 exec_case(struct tgsi_exec_machine *mach,
3255 const struct tgsi_full_instruction *inst)
3256 {
3257 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3258 union tgsi_exec_channel src;
3259 uint mask = 0;
3260
3261 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3262
3263 if (mach->Switch.selector.u[0] == src.u[0]) {
3264 mask |= 0x1;
3265 }
3266 if (mach->Switch.selector.u[1] == src.u[1]) {
3267 mask |= 0x2;
3268 }
3269 if (mach->Switch.selector.u[2] == src.u[2]) {
3270 mask |= 0x4;
3271 }
3272 if (mach->Switch.selector.u[3] == src.u[3]) {
3273 mask |= 0x8;
3274 }
3275
3276 mach->Switch.defaultMask |= mask;
3277
3278 mach->Switch.mask |= mask & prevMask;
3279
3280 UPDATE_EXEC_MASK(mach);
3281 }
3282
3283 static void
3284 exec_default(struct tgsi_exec_machine *mach)
3285 {
3286 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3287
3288 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3289
3290 UPDATE_EXEC_MASK(mach);
3291 }
3292
3293 static void
3294 exec_endswitch(struct tgsi_exec_machine *mach)
3295 {
3296 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3297 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3298
3299 UPDATE_EXEC_MASK(mach);
3300 }
3301
3302 static void
3303 micro_i2f(union tgsi_exec_channel *dst,
3304 const union tgsi_exec_channel *src)
3305 {
3306 dst->f[0] = (float)src->i[0];
3307 dst->f[1] = (float)src->i[1];
3308 dst->f[2] = (float)src->i[2];
3309 dst->f[3] = (float)src->i[3];
3310 }
3311
3312 static void
3313 micro_not(union tgsi_exec_channel *dst,
3314 const union tgsi_exec_channel *src)
3315 {
3316 dst->u[0] = ~src->u[0];
3317 dst->u[1] = ~src->u[1];
3318 dst->u[2] = ~src->u[2];
3319 dst->u[3] = ~src->u[3];
3320 }
3321
3322 static void
3323 micro_shl(union tgsi_exec_channel *dst,
3324 const union tgsi_exec_channel *src0,
3325 const union tgsi_exec_channel *src1)
3326 {
3327 dst->u[0] = src0->u[0] << src1->u[0];
3328 dst->u[1] = src0->u[1] << src1->u[1];
3329 dst->u[2] = src0->u[2] << src1->u[2];
3330 dst->u[3] = src0->u[3] << src1->u[3];
3331 }
3332
3333 static void
3334 micro_and(union tgsi_exec_channel *dst,
3335 const union tgsi_exec_channel *src0,
3336 const union tgsi_exec_channel *src1)
3337 {
3338 dst->u[0] = src0->u[0] & src1->u[0];
3339 dst->u[1] = src0->u[1] & src1->u[1];
3340 dst->u[2] = src0->u[2] & src1->u[2];
3341 dst->u[3] = src0->u[3] & src1->u[3];
3342 }
3343
3344 static void
3345 micro_or(union tgsi_exec_channel *dst,
3346 const union tgsi_exec_channel *src0,
3347 const union tgsi_exec_channel *src1)
3348 {
3349 dst->u[0] = src0->u[0] | src1->u[0];
3350 dst->u[1] = src0->u[1] | src1->u[1];
3351 dst->u[2] = src0->u[2] | src1->u[2];
3352 dst->u[3] = src0->u[3] | src1->u[3];
3353 }
3354
3355 static void
3356 micro_xor(union tgsi_exec_channel *dst,
3357 const union tgsi_exec_channel *src0,
3358 const union tgsi_exec_channel *src1)
3359 {
3360 dst->u[0] = src0->u[0] ^ src1->u[0];
3361 dst->u[1] = src0->u[1] ^ src1->u[1];
3362 dst->u[2] = src0->u[2] ^ src1->u[2];
3363 dst->u[3] = src0->u[3] ^ src1->u[3];
3364 }
3365
3366 static void
3367 micro_mod(union tgsi_exec_channel *dst,
3368 const union tgsi_exec_channel *src0,
3369 const union tgsi_exec_channel *src1)
3370 {
3371 dst->i[0] = src0->i[0] % src1->i[0];
3372 dst->i[1] = src0->i[1] % src1->i[1];
3373 dst->i[2] = src0->i[2] % src1->i[2];
3374 dst->i[3] = src0->i[3] % src1->i[3];
3375 }
3376
3377 static void
3378 micro_f2i(union tgsi_exec_channel *dst,
3379 const union tgsi_exec_channel *src)
3380 {
3381 dst->i[0] = (int)src->f[0];
3382 dst->i[1] = (int)src->f[1];
3383 dst->i[2] = (int)src->f[2];
3384 dst->i[3] = (int)src->f[3];
3385 }
3386
3387 static void
3388 micro_idiv(union tgsi_exec_channel *dst,
3389 const union tgsi_exec_channel *src0,
3390 const union tgsi_exec_channel *src1)
3391 {
3392 dst->i[0] = src0->i[0] / src1->i[0];
3393 dst->i[1] = src0->i[1] / src1->i[1];
3394 dst->i[2] = src0->i[2] / src1->i[2];
3395 dst->i[3] = src0->i[3] / src1->i[3];
3396 }
3397
3398 static void
3399 micro_imax(union tgsi_exec_channel *dst,
3400 const union tgsi_exec_channel *src0,
3401 const union tgsi_exec_channel *src1)
3402 {
3403 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3404 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3405 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3406 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3407 }
3408
3409 static void
3410 micro_imin(union tgsi_exec_channel *dst,
3411 const union tgsi_exec_channel *src0,
3412 const union tgsi_exec_channel *src1)
3413 {
3414 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3415 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3416 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3417 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3418 }
3419
3420 static void
3421 micro_isge(union tgsi_exec_channel *dst,
3422 const union tgsi_exec_channel *src0,
3423 const union tgsi_exec_channel *src1)
3424 {
3425 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3426 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3427 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3428 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3429 }
3430
3431 static void
3432 micro_ishr(union tgsi_exec_channel *dst,
3433 const union tgsi_exec_channel *src0,
3434 const union tgsi_exec_channel *src1)
3435 {
3436 dst->i[0] = src0->i[0] >> src1->i[0];
3437 dst->i[1] = src0->i[1] >> src1->i[1];
3438 dst->i[2] = src0->i[2] >> src1->i[2];
3439 dst->i[3] = src0->i[3] >> src1->i[3];
3440 }
3441
3442 static void
3443 micro_islt(union tgsi_exec_channel *dst,
3444 const union tgsi_exec_channel *src0,
3445 const union tgsi_exec_channel *src1)
3446 {
3447 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3448 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3449 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3450 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3451 }
3452
3453 static void
3454 micro_f2u(union tgsi_exec_channel *dst,
3455 const union tgsi_exec_channel *src)
3456 {
3457 dst->u[0] = (uint)src->f[0];
3458 dst->u[1] = (uint)src->f[1];
3459 dst->u[2] = (uint)src->f[2];
3460 dst->u[3] = (uint)src->f[3];
3461 }
3462
3463 static void
3464 micro_u2f(union tgsi_exec_channel *dst,
3465 const union tgsi_exec_channel *src)
3466 {
3467 dst->f[0] = (float)src->u[0];
3468 dst->f[1] = (float)src->u[1];
3469 dst->f[2] = (float)src->u[2];
3470 dst->f[3] = (float)src->u[3];
3471 }
3472
3473 static void
3474 micro_uadd(union tgsi_exec_channel *dst,
3475 const union tgsi_exec_channel *src0,
3476 const union tgsi_exec_channel *src1)
3477 {
3478 dst->u[0] = src0->u[0] + src1->u[0];
3479 dst->u[1] = src0->u[1] + src1->u[1];
3480 dst->u[2] = src0->u[2] + src1->u[2];
3481 dst->u[3] = src0->u[3] + src1->u[3];
3482 }
3483
3484 static void
3485 micro_udiv(union tgsi_exec_channel *dst,
3486 const union tgsi_exec_channel *src0,
3487 const union tgsi_exec_channel *src1)
3488 {
3489 dst->u[0] = src0->u[0] / src1->u[0];
3490 dst->u[1] = src0->u[1] / src1->u[1];
3491 dst->u[2] = src0->u[2] / src1->u[2];
3492 dst->u[3] = src0->u[3] / src1->u[3];
3493 }
3494
3495 static void
3496 micro_umad(union tgsi_exec_channel *dst,
3497 const union tgsi_exec_channel *src0,
3498 const union tgsi_exec_channel *src1,
3499 const union tgsi_exec_channel *src2)
3500 {
3501 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3502 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3503 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3504 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3505 }
3506
3507 static void
3508 micro_umax(union tgsi_exec_channel *dst,
3509 const union tgsi_exec_channel *src0,
3510 const union tgsi_exec_channel *src1)
3511 {
3512 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3513 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3514 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3515 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3516 }
3517
3518 static void
3519 micro_umin(union tgsi_exec_channel *dst,
3520 const union tgsi_exec_channel *src0,
3521 const union tgsi_exec_channel *src1)
3522 {
3523 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3524 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3525 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3526 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3527 }
3528
3529 static void
3530 micro_umod(union tgsi_exec_channel *dst,
3531 const union tgsi_exec_channel *src0,
3532 const union tgsi_exec_channel *src1)
3533 {
3534 dst->u[0] = src0->u[0] % src1->u[0];
3535 dst->u[1] = src0->u[1] % src1->u[1];
3536 dst->u[2] = src0->u[2] % src1->u[2];
3537 dst->u[3] = src0->u[3] % src1->u[3];
3538 }
3539
3540 static void
3541 micro_umul(union tgsi_exec_channel *dst,
3542 const union tgsi_exec_channel *src0,
3543 const union tgsi_exec_channel *src1)
3544 {
3545 dst->u[0] = src0->u[0] * src1->u[0];
3546 dst->u[1] = src0->u[1] * src1->u[1];
3547 dst->u[2] = src0->u[2] * src1->u[2];
3548 dst->u[3] = src0->u[3] * src1->u[3];
3549 }
3550
3551 static void
3552 micro_useq(union tgsi_exec_channel *dst,
3553 const union tgsi_exec_channel *src0,
3554 const union tgsi_exec_channel *src1)
3555 {
3556 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3557 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3558 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3559 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3560 }
3561
3562 static void
3563 micro_usge(union tgsi_exec_channel *dst,
3564 const union tgsi_exec_channel *src0,
3565 const union tgsi_exec_channel *src1)
3566 {
3567 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3568 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3569 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3570 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3571 }
3572
3573 static void
3574 micro_ushr(union tgsi_exec_channel *dst,
3575 const union tgsi_exec_channel *src0,
3576 const union tgsi_exec_channel *src1)
3577 {
3578 dst->u[0] = src0->u[0] >> src1->u[0];
3579 dst->u[1] = src0->u[1] >> src1->u[1];
3580 dst->u[2] = src0->u[2] >> src1->u[2];
3581 dst->u[3] = src0->u[3] >> src1->u[3];
3582 }
3583
3584 static void
3585 micro_uslt(union tgsi_exec_channel *dst,
3586 const union tgsi_exec_channel *src0,
3587 const union tgsi_exec_channel *src1)
3588 {
3589 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3590 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3591 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3592 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3593 }
3594
3595 static void
3596 micro_usne(union tgsi_exec_channel *dst,
3597 const union tgsi_exec_channel *src0,
3598 const union tgsi_exec_channel *src1)
3599 {
3600 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3601 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3602 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3603 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3604 }
3605
3606 static void
3607 micro_uarl(union tgsi_exec_channel *dst,
3608 const union tgsi_exec_channel *src)
3609 {
3610 dst->i[0] = src->u[0];
3611 dst->i[1] = src->u[1];
3612 dst->i[2] = src->u[2];
3613 dst->i[3] = src->u[3];
3614 }
3615
3616 static void
3617 micro_ucmp(union tgsi_exec_channel *dst,
3618 const union tgsi_exec_channel *src0,
3619 const union tgsi_exec_channel *src1,
3620 const union tgsi_exec_channel *src2)
3621 {
3622 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3623 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3624 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3625 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3626 }
3627
3628 static void
3629 exec_instruction(
3630 struct tgsi_exec_machine *mach,
3631 const struct tgsi_full_instruction *inst,
3632 int *pc )
3633 {
3634 union tgsi_exec_channel r[10];
3635
3636 (*pc)++;
3637
3638 switch (inst->Instruction.Opcode) {
3639 case TGSI_OPCODE_ARL:
3640 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3641 break;
3642
3643 case TGSI_OPCODE_MOV:
3644 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3645 break;
3646
3647 case TGSI_OPCODE_LIT:
3648 exec_lit(mach, inst);
3649 break;
3650
3651 case TGSI_OPCODE_RCP:
3652 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3653 break;
3654
3655 case TGSI_OPCODE_RSQ:
3656 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3657 break;
3658
3659 case TGSI_OPCODE_EXP:
3660 exec_exp(mach, inst);
3661 break;
3662
3663 case TGSI_OPCODE_LOG:
3664 exec_log(mach, inst);
3665 break;
3666
3667 case TGSI_OPCODE_MUL:
3668 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3669 break;
3670
3671 case TGSI_OPCODE_ADD:
3672 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3673 break;
3674
3675 case TGSI_OPCODE_DP3:
3676 exec_dp3(mach, inst);
3677 break;
3678
3679 case TGSI_OPCODE_DP4:
3680 exec_dp4(mach, inst);
3681 break;
3682
3683 case TGSI_OPCODE_DST:
3684 exec_dst(mach, inst);
3685 break;
3686
3687 case TGSI_OPCODE_MIN:
3688 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3689 break;
3690
3691 case TGSI_OPCODE_MAX:
3692 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3693 break;
3694
3695 case TGSI_OPCODE_SLT:
3696 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3697 break;
3698
3699 case TGSI_OPCODE_SGE:
3700 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3701 break;
3702
3703 case TGSI_OPCODE_MAD:
3704 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3705 break;
3706
3707 case TGSI_OPCODE_SUB:
3708 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3709 break;
3710
3711 case TGSI_OPCODE_LRP:
3712 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3713 break;
3714
3715 case TGSI_OPCODE_CND:
3716 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3717 break;
3718
3719 case TGSI_OPCODE_SQRT:
3720 exec_vector_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3721 break;
3722
3723 case TGSI_OPCODE_DP2A:
3724 exec_dp2a(mach, inst);
3725 break;
3726
3727 case TGSI_OPCODE_FRC:
3728 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3729 break;
3730
3731 case TGSI_OPCODE_CLAMP:
3732 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3733 break;
3734
3735 case TGSI_OPCODE_FLR:
3736 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3737 break;
3738
3739 case TGSI_OPCODE_ROUND:
3740 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3741 break;
3742
3743 case TGSI_OPCODE_EX2:
3744 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3745 break;
3746
3747 case TGSI_OPCODE_LG2:
3748 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3749 break;
3750
3751 case TGSI_OPCODE_POW:
3752 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3753 break;
3754
3755 case TGSI_OPCODE_XPD:
3756 exec_xpd(mach, inst);
3757 break;
3758
3759 case TGSI_OPCODE_ABS:
3760 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3761 break;
3762
3763 case TGSI_OPCODE_RCC:
3764 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3765 break;
3766
3767 case TGSI_OPCODE_DPH:
3768 exec_dph(mach, inst);
3769 break;
3770
3771 case TGSI_OPCODE_COS:
3772 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3773 break;
3774
3775 case TGSI_OPCODE_DDX:
3776 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3777 break;
3778
3779 case TGSI_OPCODE_DDY:
3780 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3781 break;
3782
3783 case TGSI_OPCODE_KILP:
3784 exec_kilp (mach, inst);
3785 break;
3786
3787 case TGSI_OPCODE_KIL:
3788 exec_kil (mach, inst);
3789 break;
3790
3791 case TGSI_OPCODE_PK2H:
3792 assert (0);
3793 break;
3794
3795 case TGSI_OPCODE_PK2US:
3796 assert (0);
3797 break;
3798
3799 case TGSI_OPCODE_PK4B:
3800 assert (0);
3801 break;
3802
3803 case TGSI_OPCODE_PK4UB:
3804 assert (0);
3805 break;
3806
3807 case TGSI_OPCODE_RFL:
3808 exec_rfl(mach, inst);
3809 break;
3810
3811 case TGSI_OPCODE_SEQ:
3812 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3813 break;
3814
3815 case TGSI_OPCODE_SFL:
3816 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3817 break;
3818
3819 case TGSI_OPCODE_SGT:
3820 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3821 break;
3822
3823 case TGSI_OPCODE_SIN:
3824 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3825 break;
3826
3827 case TGSI_OPCODE_SLE:
3828 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3829 break;
3830
3831 case TGSI_OPCODE_SNE:
3832 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3833 break;
3834
3835 case TGSI_OPCODE_STR:
3836 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3837 break;
3838
3839 case TGSI_OPCODE_TEX:
3840 /* simple texture lookup */
3841 /* src[0] = texcoord */
3842 /* src[1] = sampler unit */
3843 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3844 break;
3845
3846 case TGSI_OPCODE_TXB:
3847 /* Texture lookup with lod bias */
3848 /* src[0] = texcoord (src[0].w = LOD bias) */
3849 /* src[1] = sampler unit */
3850 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3851 break;
3852
3853 case TGSI_OPCODE_TXD:
3854 /* Texture lookup with explict partial derivatives */
3855 /* src[0] = texcoord */
3856 /* src[1] = d[strq]/dx */
3857 /* src[2] = d[strq]/dy */
3858 /* src[3] = sampler unit */
3859 exec_txd(mach, inst);
3860 break;
3861
3862 case TGSI_OPCODE_TXL:
3863 /* Texture lookup with explit LOD */
3864 /* src[0] = texcoord (src[0].w = LOD) */
3865 /* src[1] = sampler unit */
3866 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3867 break;
3868
3869 case TGSI_OPCODE_TXP:
3870 /* Texture lookup with projection */
3871 /* src[0] = texcoord (src[0].w = projection) */
3872 /* src[1] = sampler unit */
3873 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3874 break;
3875
3876 case TGSI_OPCODE_UP2H:
3877 assert (0);
3878 break;
3879
3880 case TGSI_OPCODE_UP2US:
3881 assert (0);
3882 break;
3883
3884 case TGSI_OPCODE_UP4B:
3885 assert (0);
3886 break;
3887
3888 case TGSI_OPCODE_UP4UB:
3889 assert (0);
3890 break;
3891
3892 case TGSI_OPCODE_X2D:
3893 exec_x2d(mach, inst);
3894 break;
3895
3896 case TGSI_OPCODE_ARA:
3897 assert (0);
3898 break;
3899
3900 case TGSI_OPCODE_ARR:
3901 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3902 break;
3903
3904 case TGSI_OPCODE_BRA:
3905 assert (0);
3906 break;
3907
3908 case TGSI_OPCODE_CAL:
3909 /* skip the call if no execution channels are enabled */
3910 if (mach->ExecMask) {
3911 /* do the call */
3912
3913 /* First, record the depths of the execution stacks.
3914 * This is important for deeply nested/looped return statements.
3915 * We have to unwind the stacks by the correct amount. For a
3916 * real code generator, we could determine the number of entries
3917 * to pop off each stack with simple static analysis and avoid
3918 * implementing this data structure at run time.
3919 */
3920 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3921 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3922 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3923 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3924 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3925 /* note that PC was already incremented above */
3926 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3927
3928 mach->CallStackTop++;
3929
3930 /* Second, push the Cond, Loop, Cont, Func stacks */
3931 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3932 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3933 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3934 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3935 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3936 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3937
3938 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3939 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3940 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3941 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3942 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3943 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3944
3945 /* Finally, jump to the subroutine */
3946 *pc = inst->Label.Label;
3947 }
3948 break;
3949
3950 case TGSI_OPCODE_RET:
3951 mach->FuncMask &= ~mach->ExecMask;
3952 UPDATE_EXEC_MASK(mach);
3953
3954 if (mach->FuncMask == 0x0) {
3955 /* really return now (otherwise, keep executing */
3956
3957 if (mach->CallStackTop == 0) {
3958 /* returning from main() */
3959 mach->CondStackTop = 0;
3960 mach->LoopStackTop = 0;
3961 *pc = -1;
3962 return;
3963 }
3964
3965 assert(mach->CallStackTop > 0);
3966 mach->CallStackTop--;
3967
3968 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3969 mach->CondMask = mach->CondStack[mach->CondStackTop];
3970
3971 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3972 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3973
3974 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3975 mach->ContMask = mach->ContStack[mach->ContStackTop];
3976
3977 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3978 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3979
3980 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3981 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3982
3983 assert(mach->FuncStackTop > 0);
3984 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3985
3986 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3987
3988 UPDATE_EXEC_MASK(mach);
3989 }
3990 break;
3991
3992 case TGSI_OPCODE_SSG:
3993 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3994 break;
3995
3996 case TGSI_OPCODE_CMP:
3997 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3998 break;
3999
4000 case TGSI_OPCODE_SCS:
4001 exec_scs(mach, inst);
4002 break;
4003
4004 case TGSI_OPCODE_NRM:
4005 exec_nrm3(mach, inst);
4006 break;
4007
4008 case TGSI_OPCODE_NRM4:
4009 exec_nrm4(mach, inst);
4010 break;
4011
4012 case TGSI_OPCODE_DIV:
4013 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4014 break;
4015
4016 case TGSI_OPCODE_DP2:
4017 exec_dp2(mach, inst);
4018 break;
4019
4020 case TGSI_OPCODE_IF:
4021 /* push CondMask */
4022 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4023 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4024 FETCH( &r[0], 0, TGSI_CHAN_X );
4025 /* update CondMask */
4026 if( ! r[0].u[0] ) {
4027 mach->CondMask &= ~0x1;
4028 }
4029 if( ! r[0].u[1] ) {
4030 mach->CondMask &= ~0x2;
4031 }
4032 if( ! r[0].u[2] ) {
4033 mach->CondMask &= ~0x4;
4034 }
4035 if( ! r[0].u[3] ) {
4036 mach->CondMask &= ~0x8;
4037 }
4038 UPDATE_EXEC_MASK(mach);
4039 /* Todo: If CondMask==0, jump to ELSE */
4040 break;
4041
4042 case TGSI_OPCODE_ELSE:
4043 /* invert CondMask wrt previous mask */
4044 {
4045 uint prevMask;
4046 assert(mach->CondStackTop > 0);
4047 prevMask = mach->CondStack[mach->CondStackTop - 1];
4048 mach->CondMask = ~mach->CondMask & prevMask;
4049 UPDATE_EXEC_MASK(mach);
4050 /* Todo: If CondMask==0, jump to ENDIF */
4051 }
4052 break;
4053
4054 case TGSI_OPCODE_ENDIF:
4055 /* pop CondMask */
4056 assert(mach->CondStackTop > 0);
4057 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4058 UPDATE_EXEC_MASK(mach);
4059 break;
4060
4061 case TGSI_OPCODE_END:
4062 /* make sure we end primitives which haven't
4063 * been explicitly emitted */
4064 conditional_emit_primitive(mach);
4065 /* halt execution */
4066 *pc = -1;
4067 break;
4068
4069 case TGSI_OPCODE_PUSHA:
4070 assert (0);
4071 break;
4072
4073 case TGSI_OPCODE_POPA:
4074 assert (0);
4075 break;
4076
4077 case TGSI_OPCODE_CEIL:
4078 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4079 break;
4080
4081 case TGSI_OPCODE_I2F:
4082 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4083 break;
4084
4085 case TGSI_OPCODE_NOT:
4086 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4087 break;
4088
4089 case TGSI_OPCODE_TRUNC:
4090 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4091 break;
4092
4093 case TGSI_OPCODE_SHL:
4094 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4095 break;
4096
4097 case TGSI_OPCODE_AND:
4098 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4099 break;
4100
4101 case TGSI_OPCODE_OR:
4102 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4103 break;
4104
4105 case TGSI_OPCODE_MOD:
4106 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4107 break;
4108
4109 case TGSI_OPCODE_XOR:
4110 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4111 break;
4112
4113 case TGSI_OPCODE_SAD:
4114 assert (0);
4115 break;
4116
4117 case TGSI_OPCODE_TXF:
4118 exec_txf(mach, inst);
4119 break;
4120
4121 case TGSI_OPCODE_TXQ:
4122 exec_txq(mach, inst);
4123 break;
4124
4125 case TGSI_OPCODE_EMIT:
4126 emit_vertex(mach);
4127 break;
4128
4129 case TGSI_OPCODE_ENDPRIM:
4130 emit_primitive(mach);
4131 break;
4132
4133 case TGSI_OPCODE_BGNLOOP:
4134 /* push LoopMask and ContMasks */
4135 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4136 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4137 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4138 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4139
4140 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4141 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4142 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4143 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4144 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4145 break;
4146
4147 case TGSI_OPCODE_ENDLOOP:
4148 /* Restore ContMask, but don't pop */
4149 assert(mach->ContStackTop > 0);
4150 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4151 UPDATE_EXEC_MASK(mach);
4152 if (mach->ExecMask) {
4153 /* repeat loop: jump to instruction just past BGNLOOP */
4154 assert(mach->LoopLabelStackTop > 0);
4155 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4156 }
4157 else {
4158 /* exit loop: pop LoopMask */
4159 assert(mach->LoopStackTop > 0);
4160 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4161 /* pop ContMask */
4162 assert(mach->ContStackTop > 0);
4163 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4164 assert(mach->LoopLabelStackTop > 0);
4165 --mach->LoopLabelStackTop;
4166
4167 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4168 }
4169 UPDATE_EXEC_MASK(mach);
4170 break;
4171
4172 case TGSI_OPCODE_BRK:
4173 exec_break(mach);
4174 break;
4175
4176 case TGSI_OPCODE_CONT:
4177 /* turn off cont channels for each enabled exec channel */
4178 mach->ContMask &= ~mach->ExecMask;
4179 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4180 UPDATE_EXEC_MASK(mach);
4181 break;
4182
4183 case TGSI_OPCODE_BGNSUB:
4184 /* no-op */
4185 break;
4186
4187 case TGSI_OPCODE_ENDSUB:
4188 /*
4189 * XXX: This really should be a no-op. We should never reach this opcode.
4190 */
4191
4192 assert(mach->CallStackTop > 0);
4193 mach->CallStackTop--;
4194
4195 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4196 mach->CondMask = mach->CondStack[mach->CondStackTop];
4197
4198 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4199 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4200
4201 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4202 mach->ContMask = mach->ContStack[mach->ContStackTop];
4203
4204 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4205 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4206
4207 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4208 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4209
4210 assert(mach->FuncStackTop > 0);
4211 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4212
4213 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4214
4215 UPDATE_EXEC_MASK(mach);
4216 break;
4217
4218 case TGSI_OPCODE_NOP:
4219 break;
4220
4221 case TGSI_OPCODE_BREAKC:
4222 FETCH(&r[0], 0, TGSI_CHAN_X);
4223 /* update CondMask */
4224 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4225 mach->LoopMask &= ~0x1;
4226 }
4227 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4228 mach->LoopMask &= ~0x2;
4229 }
4230 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4231 mach->LoopMask &= ~0x4;
4232 }
4233 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4234 mach->LoopMask &= ~0x8;
4235 }
4236 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4237 UPDATE_EXEC_MASK(mach);
4238 break;
4239
4240 case TGSI_OPCODE_F2I:
4241 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4242 break;
4243
4244 case TGSI_OPCODE_IDIV:
4245 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4246 break;
4247
4248 case TGSI_OPCODE_IMAX:
4249 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4250 break;
4251
4252 case TGSI_OPCODE_IMIN:
4253 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4254 break;
4255
4256 case TGSI_OPCODE_INEG:
4257 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4258 break;
4259
4260 case TGSI_OPCODE_ISGE:
4261 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4262 break;
4263
4264 case TGSI_OPCODE_ISHR:
4265 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4266 break;
4267
4268 case TGSI_OPCODE_ISLT:
4269 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4270 break;
4271
4272 case TGSI_OPCODE_F2U:
4273 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4274 break;
4275
4276 case TGSI_OPCODE_U2F:
4277 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4278 break;
4279
4280 case TGSI_OPCODE_UADD:
4281 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4282 break;
4283
4284 case TGSI_OPCODE_UDIV:
4285 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4286 break;
4287
4288 case TGSI_OPCODE_UMAD:
4289 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4290 break;
4291
4292 case TGSI_OPCODE_UMAX:
4293 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4294 break;
4295
4296 case TGSI_OPCODE_UMIN:
4297 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4298 break;
4299
4300 case TGSI_OPCODE_UMOD:
4301 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4302 break;
4303
4304 case TGSI_OPCODE_UMUL:
4305 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4306 break;
4307
4308 case TGSI_OPCODE_USEQ:
4309 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4310 break;
4311
4312 case TGSI_OPCODE_USGE:
4313 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4314 break;
4315
4316 case TGSI_OPCODE_USHR:
4317 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4318 break;
4319
4320 case TGSI_OPCODE_USLT:
4321 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4322 break;
4323
4324 case TGSI_OPCODE_USNE:
4325 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4326 break;
4327
4328 case TGSI_OPCODE_SWITCH:
4329 exec_switch(mach, inst);
4330 break;
4331
4332 case TGSI_OPCODE_CASE:
4333 exec_case(mach, inst);
4334 break;
4335
4336 case TGSI_OPCODE_DEFAULT:
4337 exec_default(mach);
4338 break;
4339
4340 case TGSI_OPCODE_ENDSWITCH:
4341 exec_endswitch(mach);
4342 break;
4343
4344 case TGSI_OPCODE_SAMPLE_I:
4345 exec_txf(mach, inst);
4346 break;
4347
4348 case TGSI_OPCODE_SAMPLE_I_MS:
4349 assert(0);
4350 break;
4351
4352 case TGSI_OPCODE_SAMPLE:
4353 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4354 break;
4355
4356 case TGSI_OPCODE_SAMPLE_B:
4357 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4358 break;
4359
4360 case TGSI_OPCODE_SAMPLE_C:
4361 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4362 break;
4363
4364 case TGSI_OPCODE_SAMPLE_C_LZ:
4365 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4366 break;
4367
4368 case TGSI_OPCODE_SAMPLE_D:
4369 exec_sample_d(mach, inst);
4370 break;
4371
4372 case TGSI_OPCODE_SAMPLE_L:
4373 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4374 break;
4375
4376 case TGSI_OPCODE_GATHER4:
4377 assert(0);
4378 break;
4379
4380 case TGSI_OPCODE_SVIEWINFO:
4381 exec_txq(mach, inst);
4382 break;
4383
4384 case TGSI_OPCODE_SAMPLE_POS:
4385 assert(0);
4386 break;
4387
4388 case TGSI_OPCODE_SAMPLE_INFO:
4389 assert(0);
4390 break;
4391
4392 case TGSI_OPCODE_UARL:
4393 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4394 break;
4395
4396 case TGSI_OPCODE_UCMP:
4397 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4398 break;
4399
4400 case TGSI_OPCODE_IABS:
4401 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4402 break;
4403
4404 case TGSI_OPCODE_ISSG:
4405 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4406 break;
4407
4408 case TGSI_OPCODE_TEX2:
4409 /* simple texture lookup */
4410 /* src[0] = texcoord */
4411 /* src[1] = compare */
4412 /* src[2] = sampler unit */
4413 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4414 break;
4415 case TGSI_OPCODE_TXB2:
4416 /* simple texture lookup */
4417 /* src[0] = texcoord */
4418 /* src[1] = bias */
4419 /* src[2] = sampler unit */
4420 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4421 break;
4422 case TGSI_OPCODE_TXL2:
4423 /* simple texture lookup */
4424 /* src[0] = texcoord */
4425 /* src[1] = lod */
4426 /* src[2] = sampler unit */
4427 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4428 break;
4429 default:
4430 assert( 0 );
4431 }
4432 }
4433
4434
4435 /**
4436 * Run TGSI interpreter.
4437 * \return bitmask of "alive" quad components
4438 */
4439 uint
4440 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4441 {
4442 uint i;
4443 int pc = 0;
4444
4445 mach->CondMask = 0xf;
4446 mach->LoopMask = 0xf;
4447 mach->ContMask = 0xf;
4448 mach->FuncMask = 0xf;
4449 mach->ExecMask = 0xf;
4450
4451 mach->Switch.mask = 0xf;
4452
4453 assert(mach->CondStackTop == 0);
4454 assert(mach->LoopStackTop == 0);
4455 assert(mach->ContStackTop == 0);
4456 assert(mach->SwitchStackTop == 0);
4457 assert(mach->BreakStackTop == 0);
4458 assert(mach->CallStackTop == 0);
4459
4460 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4461 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4462
4463 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4464 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4465 mach->Primitives[0] = 0;
4466 }
4467
4468 /* execute declarations (interpolants) */
4469 for (i = 0; i < mach->NumDeclarations; i++) {
4470 exec_declaration( mach, mach->Declarations+i );
4471 }
4472
4473 {
4474 #if DEBUG_EXECUTION
4475 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4476 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4477 uint inst = 1;
4478
4479 memset(mach->Temps, 0, sizeof(temps));
4480 memset(mach->Outputs, 0, sizeof(outputs));
4481 memset(temps, 0, sizeof(temps));
4482 memset(outputs, 0, sizeof(outputs));
4483 #endif
4484
4485 /* execute instructions, until pc is set to -1 */
4486 while (pc != -1) {
4487
4488 #if DEBUG_EXECUTION
4489 uint i;
4490
4491 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4492 #endif
4493
4494 assert(pc < (int) mach->NumInstructions);
4495 exec_instruction(mach, mach->Instructions + pc, &pc);
4496
4497 #if DEBUG_EXECUTION
4498 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4499 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4500 uint j;
4501
4502 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4503 debug_printf("TEMP[%2u] = ", i);
4504 for (j = 0; j < 4; j++) {
4505 if (j > 0) {
4506 debug_printf(" ");
4507 }
4508 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4509 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4510 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4511 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4512 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4513 }
4514 }
4515 }
4516 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4517 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4518 uint j;
4519
4520 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4521 debug_printf("OUT[%2u] = ", i);
4522 for (j = 0; j < 4; j++) {
4523 if (j > 0) {
4524 debug_printf(" ");
4525 }
4526 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4527 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4528 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4529 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4530 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4531 }
4532 }
4533 }
4534 #endif
4535 }
4536 }
4537
4538 #if 0
4539 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4540 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4541 /*
4542 * Scale back depth component.
4543 */
4544 for (i = 0; i < 4; i++)
4545 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4546 }
4547 #endif
4548
4549 /* Strictly speaking, these assertions aren't really needed but they
4550 * can potentially catch some bugs in the control flow code.
4551 */
4552 assert(mach->CondStackTop == 0);
4553 assert(mach->LoopStackTop == 0);
4554 assert(mach->ContStackTop == 0);
4555 assert(mach->SwitchStackTop == 0);
4556 assert(mach->BreakStackTop == 0);
4557 assert(mach->CallStackTop == 0);
4558
4559 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4560 }