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tgsi: support 2d indirect addressing
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
381 {
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
386 }
387
388 static void
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
391 {
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
396 }
397
398 static void
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
402 {
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
407 }
408
409 static void
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_trunc(union tgsi_exec_channel *dst,
433 const union tgsi_exec_channel *src)
434 {
435 dst->f[0] = (float)(int)src->f[0];
436 dst->f[1] = (float)(int)src->f[1];
437 dst->f[2] = (float)(int)src->f[2];
438 dst->f[3] = (float)(int)src->f[3];
439 }
440
441
442 #define CHAN_X 0
443 #define CHAN_Y 1
444 #define CHAN_Z 2
445 #define CHAN_W 3
446
447 enum tgsi_exec_datatype {
448 TGSI_EXEC_DATA_FLOAT,
449 TGSI_EXEC_DATA_INT,
450 TGSI_EXEC_DATA_UINT
451 };
452
453 /*
454 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
455 */
456 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
457 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
458 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
459 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
460 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
461 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
462 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
463 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
464 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
465 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
466 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
467 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
468 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
469 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
470 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
471 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
472 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
473 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
474 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
475 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
476 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
477 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
478 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
479 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
480 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
481 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
482 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
483 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
484 #define TEMP_R0 TGSI_EXEC_TEMP_R0
485 #define TEMP_P0 TGSI_EXEC_TEMP_P0
486
487 #define IS_CHANNEL_ENABLED(INST, CHAN)\
488 ((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
489
490 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
491 ((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
492
493 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
494 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
495 if (IS_CHANNEL_ENABLED( INST, CHAN ))
496
497 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
498 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
499 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
500
501
502 /** The execution mask depends on the conditional mask and the loop mask */
503 #define UPDATE_EXEC_MASK(MACH) \
504 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
505
506
507 static const union tgsi_exec_channel ZeroVec =
508 { { 0.0, 0.0, 0.0, 0.0 } };
509
510 static const union tgsi_exec_channel OneVec = {
511 {1.0f, 1.0f, 1.0f, 1.0f}
512 };
513
514
515 /**
516 * Assert that none of the float values in 'chan' are infinite or NaN.
517 * NaN and Inf may occur normally during program execution and should
518 * not lead to crashes, etc. But when debugging, it's helpful to catch
519 * them.
520 */
521 static INLINE void
522 check_inf_or_nan(const union tgsi_exec_channel *chan)
523 {
524 assert(!util_is_inf_or_nan((chan)->f[0]));
525 assert(!util_is_inf_or_nan((chan)->f[1]));
526 assert(!util_is_inf_or_nan((chan)->f[2]));
527 assert(!util_is_inf_or_nan((chan)->f[3]));
528 }
529
530
531 #ifdef DEBUG
532 static void
533 print_chan(const char *msg, const union tgsi_exec_channel *chan)
534 {
535 debug_printf("%s = {%f, %f, %f, %f}\n",
536 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
537 }
538 #endif
539
540
541 #ifdef DEBUG
542 static void
543 print_temp(const struct tgsi_exec_machine *mach, uint index)
544 {
545 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
546 int i;
547 debug_printf("Temp[%u] =\n", index);
548 for (i = 0; i < 4; i++) {
549 debug_printf(" %c: { %f, %f, %f, %f }\n",
550 "XYZW"[i],
551 tmp->xyzw[i].f[0],
552 tmp->xyzw[i].f[1],
553 tmp->xyzw[i].f[2],
554 tmp->xyzw[i].f[3]);
555 }
556 }
557 #endif
558
559
560 /**
561 * Check if there's a potential src/dst register data dependency when
562 * using SOA execution.
563 * Example:
564 * MOV T, T.yxwz;
565 * This would expand into:
566 * MOV t0, t1;
567 * MOV t1, t0;
568 * MOV t2, t3;
569 * MOV t3, t2;
570 * The second instruction will have the wrong value for t0 if executed as-is.
571 */
572 boolean
573 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
574 {
575 uint i, chan;
576
577 uint writemask = inst->Dst[0].Register.WriteMask;
578 if (writemask == TGSI_WRITEMASK_X ||
579 writemask == TGSI_WRITEMASK_Y ||
580 writemask == TGSI_WRITEMASK_Z ||
581 writemask == TGSI_WRITEMASK_W ||
582 writemask == TGSI_WRITEMASK_NONE) {
583 /* no chance of data dependency */
584 return FALSE;
585 }
586
587 /* loop over src regs */
588 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
589 if ((inst->Src[i].Register.File ==
590 inst->Dst[0].Register.File) &&
591 (inst->Src[i].Register.Index ==
592 inst->Dst[0].Register.Index)) {
593 /* loop over dest channels */
594 uint channelsWritten = 0x0;
595 FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
596 /* check if we're reading a channel that's been written */
597 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
598 if (channelsWritten & (1 << swizzle)) {
599 return TRUE;
600 }
601
602 channelsWritten |= (1 << chan);
603 }
604 }
605 }
606 return FALSE;
607 }
608
609
610 /**
611 * Initialize machine state by expanding tokens to full instructions,
612 * allocating temporary storage, setting up constants, etc.
613 * After this, we can call tgsi_exec_machine_run() many times.
614 */
615 void
616 tgsi_exec_machine_bind_shader(
617 struct tgsi_exec_machine *mach,
618 const struct tgsi_token *tokens,
619 uint numSamplers,
620 struct tgsi_sampler **samplers)
621 {
622 uint k;
623 struct tgsi_parse_context parse;
624 struct tgsi_full_instruction *instructions;
625 struct tgsi_full_declaration *declarations;
626 uint maxInstructions = 10, numInstructions = 0;
627 uint maxDeclarations = 10, numDeclarations = 0;
628
629 #if 0
630 tgsi_dump(tokens, 0);
631 #endif
632
633 util_init_math();
634
635 mach->Tokens = tokens;
636 mach->Samplers = samplers;
637
638 if (!tokens) {
639 /* unbind and free all */
640 if (mach->Declarations) {
641 FREE( mach->Declarations );
642 }
643 mach->Declarations = NULL;
644 mach->NumDeclarations = 0;
645
646 if (mach->Instructions) {
647 FREE( mach->Instructions );
648 }
649 mach->Instructions = NULL;
650 mach->NumInstructions = 0;
651
652 return;
653 }
654
655 k = tgsi_parse_init (&parse, mach->Tokens);
656 if (k != TGSI_PARSE_OK) {
657 debug_printf( "Problem parsing!\n" );
658 return;
659 }
660
661 mach->Processor = parse.FullHeader.Processor.Processor;
662 mach->ImmLimit = 0;
663
664 declarations = (struct tgsi_full_declaration *)
665 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
666
667 if (!declarations) {
668 return;
669 }
670
671 instructions = (struct tgsi_full_instruction *)
672 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
673
674 if (!instructions) {
675 FREE( declarations );
676 return;
677 }
678
679 while( !tgsi_parse_end_of_tokens( &parse ) ) {
680 uint i;
681
682 tgsi_parse_token( &parse );
683 switch( parse.FullToken.Token.Type ) {
684 case TGSI_TOKEN_TYPE_DECLARATION:
685 /* save expanded declaration */
686 if (numDeclarations == maxDeclarations) {
687 declarations = REALLOC(declarations,
688 maxDeclarations
689 * sizeof(struct tgsi_full_declaration),
690 (maxDeclarations + 10)
691 * sizeof(struct tgsi_full_declaration));
692 maxDeclarations += 10;
693 }
694 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
695 unsigned reg;
696 for (reg = parse.FullToken.FullDeclaration.Range.First;
697 reg <= parse.FullToken.FullDeclaration.Range.Last;
698 ++reg) {
699 ++mach->NumOutputs;
700 }
701 }
702 memcpy(declarations + numDeclarations,
703 &parse.FullToken.FullDeclaration,
704 sizeof(declarations[0]));
705 numDeclarations++;
706 break;
707
708 case TGSI_TOKEN_TYPE_IMMEDIATE:
709 {
710 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
711 assert( size <= 4 );
712 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
713
714 for( i = 0; i < size; i++ ) {
715 mach->Imms[mach->ImmLimit][i] =
716 parse.FullToken.FullImmediate.u[i].Float;
717 }
718 mach->ImmLimit += 1;
719 }
720 break;
721
722 case TGSI_TOKEN_TYPE_INSTRUCTION:
723
724 /* save expanded instruction */
725 if (numInstructions == maxInstructions) {
726 instructions = REALLOC(instructions,
727 maxInstructions
728 * sizeof(struct tgsi_full_instruction),
729 (maxInstructions + 10)
730 * sizeof(struct tgsi_full_instruction));
731 maxInstructions += 10;
732 }
733
734 memcpy(instructions + numInstructions,
735 &parse.FullToken.FullInstruction,
736 sizeof(instructions[0]));
737
738 numInstructions++;
739 break;
740
741 case TGSI_TOKEN_TYPE_PROPERTY:
742 break;
743
744 default:
745 assert( 0 );
746 }
747 }
748 tgsi_parse_free (&parse);
749
750 if (mach->Declarations) {
751 FREE( mach->Declarations );
752 }
753 mach->Declarations = declarations;
754 mach->NumDeclarations = numDeclarations;
755
756 if (mach->Instructions) {
757 FREE( mach->Instructions );
758 }
759 mach->Instructions = instructions;
760 mach->NumInstructions = numInstructions;
761 }
762
763
764 struct tgsi_exec_machine *
765 tgsi_exec_machine_create( void )
766 {
767 struct tgsi_exec_machine *mach;
768 uint i;
769
770 mach = align_malloc( sizeof *mach, 16 );
771 if (!mach)
772 goto fail;
773
774 memset(mach, 0, sizeof(*mach));
775
776 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
777 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
778 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
779
780 /* Setup constants. */
781 for( i = 0; i < 4; i++ ) {
782 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
783 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
784 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
785 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
786 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
787 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
788 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
789 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
790 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
791 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
792 }
793
794 #ifdef DEBUG
795 /* silence warnings */
796 (void) print_chan;
797 (void) print_temp;
798 #endif
799
800 return mach;
801
802 fail:
803 align_free(mach);
804 return NULL;
805 }
806
807
808 void
809 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
810 {
811 if (mach) {
812 if (mach->Instructions)
813 FREE(mach->Instructions);
814 if (mach->Declarations)
815 FREE(mach->Declarations);
816 }
817
818 align_free(mach);
819 }
820
821 static void
822 micro_add(union tgsi_exec_channel *dst,
823 const union tgsi_exec_channel *src0,
824 const union tgsi_exec_channel *src1)
825 {
826 dst->f[0] = src0->f[0] + src1->f[0];
827 dst->f[1] = src0->f[1] + src1->f[1];
828 dst->f[2] = src0->f[2] + src1->f[2];
829 dst->f[3] = src0->f[3] + src1->f[3];
830 }
831
832 static void
833 micro_div(
834 union tgsi_exec_channel *dst,
835 const union tgsi_exec_channel *src0,
836 const union tgsi_exec_channel *src1 )
837 {
838 if (src1->f[0] != 0) {
839 dst->f[0] = src0->f[0] / src1->f[0];
840 }
841 if (src1->f[1] != 0) {
842 dst->f[1] = src0->f[1] / src1->f[1];
843 }
844 if (src1->f[2] != 0) {
845 dst->f[2] = src0->f[2] / src1->f[2];
846 }
847 if (src1->f[3] != 0) {
848 dst->f[3] = src0->f[3] / src1->f[3];
849 }
850 }
851
852 static void
853 micro_float_clamp(union tgsi_exec_channel *dst,
854 const union tgsi_exec_channel *src)
855 {
856 uint i;
857
858 for (i = 0; i < 4; i++) {
859 if (src->f[i] > 0.0f) {
860 if (src->f[i] > 1.884467e+019f)
861 dst->f[i] = 1.884467e+019f;
862 else if (src->f[i] < 5.42101e-020f)
863 dst->f[i] = 5.42101e-020f;
864 else
865 dst->f[i] = src->f[i];
866 }
867 else {
868 if (src->f[i] < -1.884467e+019f)
869 dst->f[i] = -1.884467e+019f;
870 else if (src->f[i] > -5.42101e-020f)
871 dst->f[i] = -5.42101e-020f;
872 else
873 dst->f[i] = src->f[i];
874 }
875 }
876 }
877
878 static void
879 micro_lt(
880 union tgsi_exec_channel *dst,
881 const union tgsi_exec_channel *src0,
882 const union tgsi_exec_channel *src1,
883 const union tgsi_exec_channel *src2,
884 const union tgsi_exec_channel *src3 )
885 {
886 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
887 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
888 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
889 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
890 }
891
892 static void
893 micro_max(union tgsi_exec_channel *dst,
894 const union tgsi_exec_channel *src0,
895 const union tgsi_exec_channel *src1)
896 {
897 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
898 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
899 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
900 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
901 }
902
903 static void
904 micro_min(union tgsi_exec_channel *dst,
905 const union tgsi_exec_channel *src0,
906 const union tgsi_exec_channel *src1)
907 {
908 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
909 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
910 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
911 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
912 }
913
914 static void
915 micro_mul(union tgsi_exec_channel *dst,
916 const union tgsi_exec_channel *src0,
917 const union tgsi_exec_channel *src1)
918 {
919 dst->f[0] = src0->f[0] * src1->f[0];
920 dst->f[1] = src0->f[1] * src1->f[1];
921 dst->f[2] = src0->f[2] * src1->f[2];
922 dst->f[3] = src0->f[3] * src1->f[3];
923 }
924
925 #if 0
926 static void
927 micro_imul64(
928 union tgsi_exec_channel *dst0,
929 union tgsi_exec_channel *dst1,
930 const union tgsi_exec_channel *src0,
931 const union tgsi_exec_channel *src1 )
932 {
933 dst1->i[0] = src0->i[0] * src1->i[0];
934 dst1->i[1] = src0->i[1] * src1->i[1];
935 dst1->i[2] = src0->i[2] * src1->i[2];
936 dst1->i[3] = src0->i[3] * src1->i[3];
937 dst0->i[0] = 0;
938 dst0->i[1] = 0;
939 dst0->i[2] = 0;
940 dst0->i[3] = 0;
941 }
942 #endif
943
944 #if 0
945 static void
946 micro_umul64(
947 union tgsi_exec_channel *dst0,
948 union tgsi_exec_channel *dst1,
949 const union tgsi_exec_channel *src0,
950 const union tgsi_exec_channel *src1 )
951 {
952 dst1->u[0] = src0->u[0] * src1->u[0];
953 dst1->u[1] = src0->u[1] * src1->u[1];
954 dst1->u[2] = src0->u[2] * src1->u[2];
955 dst1->u[3] = src0->u[3] * src1->u[3];
956 dst0->u[0] = 0;
957 dst0->u[1] = 0;
958 dst0->u[2] = 0;
959 dst0->u[3] = 0;
960 }
961 #endif
962
963
964 #if 0
965 static void
966 micro_movc(
967 union tgsi_exec_channel *dst,
968 const union tgsi_exec_channel *src0,
969 const union tgsi_exec_channel *src1,
970 const union tgsi_exec_channel *src2 )
971 {
972 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
973 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
974 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
975 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
976 }
977 #endif
978
979 static void
980 micro_neg(
981 union tgsi_exec_channel *dst,
982 const union tgsi_exec_channel *src )
983 {
984 dst->f[0] = -src->f[0];
985 dst->f[1] = -src->f[1];
986 dst->f[2] = -src->f[2];
987 dst->f[3] = -src->f[3];
988 }
989
990 static void
991 micro_pow(
992 union tgsi_exec_channel *dst,
993 const union tgsi_exec_channel *src0,
994 const union tgsi_exec_channel *src1 )
995 {
996 #if FAST_MATH
997 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
998 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
999 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1000 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1001 #else
1002 dst->f[0] = powf( src0->f[0], src1->f[0] );
1003 dst->f[1] = powf( src0->f[1], src1->f[1] );
1004 dst->f[2] = powf( src0->f[2], src1->f[2] );
1005 dst->f[3] = powf( src0->f[3], src1->f[3] );
1006 #endif
1007 }
1008
1009 static void
1010 micro_sub(union tgsi_exec_channel *dst,
1011 const union tgsi_exec_channel *src0,
1012 const union tgsi_exec_channel *src1)
1013 {
1014 dst->f[0] = src0->f[0] - src1->f[0];
1015 dst->f[1] = src0->f[1] - src1->f[1];
1016 dst->f[2] = src0->f[2] - src1->f[2];
1017 dst->f[3] = src0->f[3] - src1->f[3];
1018 }
1019
1020 static void
1021 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1022 const uint file,
1023 const uint swizzle,
1024 const union tgsi_exec_channel *index,
1025 const union tgsi_exec_channel *index2D,
1026 union tgsi_exec_channel *chan)
1027 {
1028 uint i;
1029
1030 switch (file) {
1031 case TGSI_FILE_CONSTANT:
1032 for (i = 0; i < QUAD_SIZE; i++) {
1033 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1034 assert(mach->Consts[index2D->i[i]]);
1035
1036 if (index->i[i] < 0) {
1037 chan->u[i] = 0;
1038 } else {
1039 const uint *p = (const uint *)mach->Consts[index2D->i[i]];
1040
1041 chan->u[i] = p[index->i[i] * 4 + swizzle];
1042 }
1043 }
1044 break;
1045
1046 case TGSI_FILE_INPUT:
1047 case TGSI_FILE_SYSTEM_VALUE:
1048 for (i = 0; i < QUAD_SIZE; i++) {
1049 /*
1050 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1051 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1052 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1053 index2D->i[i], index->i[i]);
1054 }*/
1055 chan->u[i] = mach->Inputs[index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i]].xyzw[swizzle].u[i];
1056 }
1057 break;
1058
1059 case TGSI_FILE_TEMPORARY:
1060 for (i = 0; i < QUAD_SIZE; i++) {
1061 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1062 assert(index2D->i[i] == 0);
1063
1064 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1065 }
1066 break;
1067
1068 case TGSI_FILE_IMMEDIATE:
1069 for (i = 0; i < QUAD_SIZE; i++) {
1070 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1071 assert(index2D->i[i] == 0);
1072
1073 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1074 }
1075 break;
1076
1077 case TGSI_FILE_ADDRESS:
1078 for (i = 0; i < QUAD_SIZE; i++) {
1079 assert(index->i[i] >= 0);
1080 assert(index2D->i[i] == 0);
1081
1082 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1083 }
1084 break;
1085
1086 case TGSI_FILE_PREDICATE:
1087 for (i = 0; i < QUAD_SIZE; i++) {
1088 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1089 assert(index2D->i[i] == 0);
1090
1091 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1092 }
1093 break;
1094
1095 case TGSI_FILE_OUTPUT:
1096 /* vertex/fragment output vars can be read too */
1097 for (i = 0; i < QUAD_SIZE; i++) {
1098 assert(index->i[i] >= 0);
1099 assert(index2D->i[i] == 0);
1100
1101 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1102 }
1103 break;
1104
1105 default:
1106 assert(0);
1107 for (i = 0; i < QUAD_SIZE; i++) {
1108 chan->u[i] = 0;
1109 }
1110 }
1111 }
1112
1113 static void
1114 fetch_source(const struct tgsi_exec_machine *mach,
1115 union tgsi_exec_channel *chan,
1116 const struct tgsi_full_src_register *reg,
1117 const uint chan_index,
1118 enum tgsi_exec_datatype src_datatype)
1119 {
1120 union tgsi_exec_channel index;
1121 union tgsi_exec_channel index2D;
1122 uint swizzle;
1123
1124 /* We start with a direct index into a register file.
1125 *
1126 * file[1],
1127 * where:
1128 * file = Register.File
1129 * [1] = Register.Index
1130 */
1131 index.i[0] =
1132 index.i[1] =
1133 index.i[2] =
1134 index.i[3] = reg->Register.Index;
1135
1136 /* There is an extra source register that indirectly subscripts
1137 * a register file. The direct index now becomes an offset
1138 * that is being added to the indirect register.
1139 *
1140 * file[ind[2].x+1],
1141 * where:
1142 * ind = Indirect.File
1143 * [2] = Indirect.Index
1144 * .x = Indirect.SwizzleX
1145 */
1146 if (reg->Register.Indirect) {
1147 union tgsi_exec_channel index2;
1148 union tgsi_exec_channel indir_index;
1149 const uint execmask = mach->ExecMask;
1150 uint i;
1151
1152 /* which address register (always zero now) */
1153 index2.i[0] =
1154 index2.i[1] =
1155 index2.i[2] =
1156 index2.i[3] = reg->Indirect.Index;
1157
1158 /* get current value of address register[swizzle] */
1159 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1160 fetch_src_file_channel(mach,
1161 reg->Indirect.File,
1162 swizzle,
1163 &index2,
1164 &ZeroVec,
1165 &indir_index);
1166
1167 /* add value of address register to the offset */
1168 index.i[0] += indir_index.i[0];
1169 index.i[1] += indir_index.i[1];
1170 index.i[2] += indir_index.i[2];
1171 index.i[3] += indir_index.i[3];
1172
1173 /* for disabled execution channels, zero-out the index to
1174 * avoid using a potential garbage value.
1175 */
1176 for (i = 0; i < QUAD_SIZE; i++) {
1177 if ((execmask & (1 << i)) == 0)
1178 index.i[i] = 0;
1179 }
1180 }
1181
1182 /* There is an extra source register that is a second
1183 * subscript to a register file. Effectively it means that
1184 * the register file is actually a 2D array of registers.
1185 *
1186 * file[3][1],
1187 * where:
1188 * [3] = Dimension.Index
1189 */
1190 if (reg->Register.Dimension) {
1191 index2D.i[0] =
1192 index2D.i[1] =
1193 index2D.i[2] =
1194 index2D.i[3] = reg->Dimension.Index;
1195
1196 /* Again, the second subscript index can be addressed indirectly
1197 * identically to the first one.
1198 * Nothing stops us from indirectly addressing the indirect register,
1199 * but there is no need for that, so we won't exercise it.
1200 *
1201 * file[ind[4].y+3][1],
1202 * where:
1203 * ind = DimIndirect.File
1204 * [4] = DimIndirect.Index
1205 * .y = DimIndirect.SwizzleX
1206 */
1207 if (reg->Dimension.Indirect) {
1208 union tgsi_exec_channel index2;
1209 union tgsi_exec_channel indir_index;
1210 const uint execmask = mach->ExecMask;
1211 uint i;
1212
1213 index2.i[0] =
1214 index2.i[1] =
1215 index2.i[2] =
1216 index2.i[3] = reg->DimIndirect.Index;
1217
1218 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1219 fetch_src_file_channel(mach,
1220 reg->DimIndirect.File,
1221 swizzle,
1222 &index2,
1223 &ZeroVec,
1224 &indir_index);
1225
1226 index2D.i[0] += indir_index.i[0];
1227 index2D.i[1] += indir_index.i[1];
1228 index2D.i[2] += indir_index.i[2];
1229 index2D.i[3] += indir_index.i[3];
1230
1231 /* for disabled execution channels, zero-out the index to
1232 * avoid using a potential garbage value.
1233 */
1234 for (i = 0; i < QUAD_SIZE; i++) {
1235 if ((execmask & (1 << i)) == 0) {
1236 index2D.i[i] = 0;
1237 }
1238 }
1239 }
1240
1241 /* If by any chance there was a need for a 3D array of register
1242 * files, we would have to check whether Dimension is followed
1243 * by a dimension register and continue the saga.
1244 */
1245 } else {
1246 index2D.i[0] =
1247 index2D.i[1] =
1248 index2D.i[2] =
1249 index2D.i[3] = 0;
1250 }
1251
1252 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1253 fetch_src_file_channel(mach,
1254 reg->Register.File,
1255 swizzle,
1256 &index,
1257 &index2D,
1258 chan);
1259
1260 if (reg->Register.Absolute) {
1261 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1262 micro_abs(chan, chan);
1263 } else {
1264 micro_iabs(chan, chan);
1265 }
1266 }
1267
1268 if (reg->Register.Negate) {
1269 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1270 micro_neg(chan, chan);
1271 } else {
1272 micro_ineg(chan, chan);
1273 }
1274 }
1275 }
1276
1277 static void
1278 store_dest(struct tgsi_exec_machine *mach,
1279 const union tgsi_exec_channel *chan,
1280 const struct tgsi_full_dst_register *reg,
1281 const struct tgsi_full_instruction *inst,
1282 uint chan_index,
1283 enum tgsi_exec_datatype dst_datatype)
1284 {
1285 uint i;
1286 union tgsi_exec_channel null;
1287 union tgsi_exec_channel *dst;
1288 uint execmask = mach->ExecMask;
1289 int offset = 0; /* indirection offset */
1290 int index;
1291
1292 /* for debugging */
1293 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1294 check_inf_or_nan(chan);
1295 }
1296
1297 /* There is an extra source register that indirectly subscripts
1298 * a register file. The direct index now becomes an offset
1299 * that is being added to the indirect register.
1300 *
1301 * file[ind[2].x+1],
1302 * where:
1303 * ind = Indirect.File
1304 * [2] = Indirect.Index
1305 * .x = Indirect.SwizzleX
1306 */
1307 if (reg->Register.Indirect) {
1308 union tgsi_exec_channel index;
1309 union tgsi_exec_channel indir_index;
1310 uint swizzle;
1311
1312 /* which address register (always zero for now) */
1313 index.i[0] =
1314 index.i[1] =
1315 index.i[2] =
1316 index.i[3] = reg->Indirect.Index;
1317
1318 /* get current value of address register[swizzle] */
1319 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1320
1321 /* fetch values from the address/indirection register */
1322 fetch_src_file_channel(mach,
1323 reg->Indirect.File,
1324 swizzle,
1325 &index,
1326 &ZeroVec,
1327 &indir_index);
1328
1329 /* save indirection offset */
1330 offset = indir_index.i[0];
1331 }
1332
1333 switch (reg->Register.File) {
1334 case TGSI_FILE_NULL:
1335 dst = &null;
1336 break;
1337
1338 case TGSI_FILE_OUTPUT:
1339 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1340 + reg->Register.Index;
1341 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1342 #if 0
1343 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1344 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1345 for (i = 0; i < QUAD_SIZE; i++)
1346 if (execmask & (1 << i))
1347 fprintf(stderr, "%f, ", chan->f[i]);
1348 fprintf(stderr, ")\n");
1349 }
1350 #endif
1351 break;
1352
1353 case TGSI_FILE_TEMPORARY:
1354 index = reg->Register.Index;
1355 assert( index < TGSI_EXEC_NUM_TEMPS );
1356 dst = &mach->Temps[offset + index].xyzw[chan_index];
1357 break;
1358
1359 case TGSI_FILE_ADDRESS:
1360 index = reg->Register.Index;
1361 dst = &mach->Addrs[index].xyzw[chan_index];
1362 break;
1363
1364 case TGSI_FILE_PREDICATE:
1365 index = reg->Register.Index;
1366 assert(index < TGSI_EXEC_NUM_PREDS);
1367 dst = &mach->Predicates[index].xyzw[chan_index];
1368 break;
1369
1370 default:
1371 assert( 0 );
1372 return;
1373 }
1374
1375 if (inst->Instruction.Predicate) {
1376 uint swizzle;
1377 union tgsi_exec_channel *pred;
1378
1379 switch (chan_index) {
1380 case CHAN_X:
1381 swizzle = inst->Predicate.SwizzleX;
1382 break;
1383 case CHAN_Y:
1384 swizzle = inst->Predicate.SwizzleY;
1385 break;
1386 case CHAN_Z:
1387 swizzle = inst->Predicate.SwizzleZ;
1388 break;
1389 case CHAN_W:
1390 swizzle = inst->Predicate.SwizzleW;
1391 break;
1392 default:
1393 assert(0);
1394 return;
1395 }
1396
1397 assert(inst->Predicate.Index == 0);
1398
1399 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1400
1401 if (inst->Predicate.Negate) {
1402 for (i = 0; i < QUAD_SIZE; i++) {
1403 if (pred->u[i]) {
1404 execmask &= ~(1 << i);
1405 }
1406 }
1407 } else {
1408 for (i = 0; i < QUAD_SIZE; i++) {
1409 if (!pred->u[i]) {
1410 execmask &= ~(1 << i);
1411 }
1412 }
1413 }
1414 }
1415
1416 switch (inst->Instruction.Saturate) {
1417 case TGSI_SAT_NONE:
1418 for (i = 0; i < QUAD_SIZE; i++)
1419 if (execmask & (1 << i))
1420 dst->i[i] = chan->i[i];
1421 break;
1422
1423 case TGSI_SAT_ZERO_ONE:
1424 for (i = 0; i < QUAD_SIZE; i++)
1425 if (execmask & (1 << i)) {
1426 if (chan->f[i] < 0.0f)
1427 dst->f[i] = 0.0f;
1428 else if (chan->f[i] > 1.0f)
1429 dst->f[i] = 1.0f;
1430 else
1431 dst->i[i] = chan->i[i];
1432 }
1433 break;
1434
1435 case TGSI_SAT_MINUS_PLUS_ONE:
1436 for (i = 0; i < QUAD_SIZE; i++)
1437 if (execmask & (1 << i)) {
1438 if (chan->f[i] < -1.0f)
1439 dst->f[i] = -1.0f;
1440 else if (chan->f[i] > 1.0f)
1441 dst->f[i] = 1.0f;
1442 else
1443 dst->i[i] = chan->i[i];
1444 }
1445 break;
1446
1447 default:
1448 assert( 0 );
1449 }
1450 }
1451
1452 #define FETCH(VAL,INDEX,CHAN)\
1453 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1454
1455 #define STORE(VAL,INDEX,CHAN)\
1456 store_dest(mach, VAL, &inst->Dst[INDEX], inst, CHAN, TGSI_EXEC_DATA_FLOAT)
1457
1458
1459 /**
1460 * Execute ARB-style KIL which is predicated by a src register.
1461 * Kill fragment if any of the four values is less than zero.
1462 */
1463 static void
1464 exec_kil(struct tgsi_exec_machine *mach,
1465 const struct tgsi_full_instruction *inst)
1466 {
1467 uint uniquemask;
1468 uint chan_index;
1469 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1470 union tgsi_exec_channel r[1];
1471
1472 /* This mask stores component bits that were already tested. */
1473 uniquemask = 0;
1474
1475 for (chan_index = 0; chan_index < 4; chan_index++)
1476 {
1477 uint swizzle;
1478 uint i;
1479
1480 /* unswizzle channel */
1481 swizzle = tgsi_util_get_full_src_register_swizzle (
1482 &inst->Src[0],
1483 chan_index);
1484
1485 /* check if the component has not been already tested */
1486 if (uniquemask & (1 << swizzle))
1487 continue;
1488 uniquemask |= 1 << swizzle;
1489
1490 FETCH(&r[0], 0, chan_index);
1491 for (i = 0; i < 4; i++)
1492 if (r[0].f[i] < 0.0f)
1493 kilmask |= 1 << i;
1494 }
1495
1496 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1497 }
1498
1499 /**
1500 * Execute NVIDIA-style KIL which is predicated by a condition code.
1501 * Kill fragment if the condition code is TRUE.
1502 */
1503 static void
1504 exec_kilp(struct tgsi_exec_machine *mach,
1505 const struct tgsi_full_instruction *inst)
1506 {
1507 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1508
1509 /* "unconditional" kil */
1510 kilmask = mach->ExecMask;
1511 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1512 }
1513
1514 static void
1515 emit_vertex(struct tgsi_exec_machine *mach)
1516 {
1517 /* FIXME: check for exec mask correctly
1518 unsigned i;
1519 for (i = 0; i < QUAD_SIZE; ++i) {
1520 if ((mach->ExecMask & (1 << i)))
1521 */
1522 if (mach->ExecMask) {
1523 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1524 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1525 }
1526 }
1527
1528 static void
1529 emit_primitive(struct tgsi_exec_machine *mach)
1530 {
1531 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1532 /* FIXME: check for exec mask correctly
1533 unsigned i;
1534 for (i = 0; i < QUAD_SIZE; ++i) {
1535 if ((mach->ExecMask & (1 << i)))
1536 */
1537 if (mach->ExecMask) {
1538 ++(*prim_count);
1539 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1540 mach->Primitives[*prim_count] = 0;
1541 }
1542 }
1543
1544 /*
1545 * Fetch four texture samples using STR texture coordinates.
1546 */
1547 static void
1548 fetch_texel( struct tgsi_sampler *sampler,
1549 const union tgsi_exec_channel *s,
1550 const union tgsi_exec_channel *t,
1551 const union tgsi_exec_channel *p,
1552 const union tgsi_exec_channel *c0,
1553 enum tgsi_sampler_control control,
1554 union tgsi_exec_channel *r,
1555 union tgsi_exec_channel *g,
1556 union tgsi_exec_channel *b,
1557 union tgsi_exec_channel *a )
1558 {
1559 uint j;
1560 float rgba[NUM_CHANNELS][QUAD_SIZE];
1561
1562 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1563
1564 for (j = 0; j < 4; j++) {
1565 r->f[j] = rgba[0][j];
1566 g->f[j] = rgba[1][j];
1567 b->f[j] = rgba[2][j];
1568 a->f[j] = rgba[3][j];
1569 }
1570 }
1571
1572
1573 #define TEX_MODIFIER_NONE 0
1574 #define TEX_MODIFIER_PROJECTED 1
1575 #define TEX_MODIFIER_LOD_BIAS 2
1576 #define TEX_MODIFIER_EXPLICIT_LOD 3
1577
1578
1579 static void
1580 exec_tex(struct tgsi_exec_machine *mach,
1581 const struct tgsi_full_instruction *inst,
1582 uint modifier)
1583 {
1584 const uint unit = inst->Src[1].Register.Index;
1585 union tgsi_exec_channel r[4];
1586 const union tgsi_exec_channel *lod = &ZeroVec;
1587 enum tgsi_sampler_control control;
1588 uint chan_index;
1589
1590 if (modifier != TEX_MODIFIER_NONE) {
1591 FETCH(&r[3], 0, CHAN_W);
1592 if (modifier != TEX_MODIFIER_PROJECTED) {
1593 lod = &r[3];
1594 }
1595 }
1596
1597 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1598 control = tgsi_sampler_lod_explicit;
1599 } else {
1600 control = tgsi_sampler_lod_bias;
1601 }
1602
1603 switch (inst->Texture.Texture) {
1604 case TGSI_TEXTURE_1D:
1605 case TGSI_TEXTURE_SHADOW1D:
1606 FETCH(&r[0], 0, CHAN_X);
1607
1608 if (modifier == TEX_MODIFIER_PROJECTED) {
1609 micro_div(&r[0], &r[0], &r[3]);
1610 }
1611
1612 fetch_texel(mach->Samplers[unit],
1613 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1614 control,
1615 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1616 break;
1617
1618 case TGSI_TEXTURE_2D:
1619 case TGSI_TEXTURE_RECT:
1620 case TGSI_TEXTURE_SHADOW2D:
1621 case TGSI_TEXTURE_SHADOWRECT:
1622 FETCH(&r[0], 0, CHAN_X);
1623 FETCH(&r[1], 0, CHAN_Y);
1624 FETCH(&r[2], 0, CHAN_Z);
1625
1626 if (modifier == TEX_MODIFIER_PROJECTED) {
1627 micro_div(&r[0], &r[0], &r[3]);
1628 micro_div(&r[1], &r[1], &r[3]);
1629 micro_div(&r[2], &r[2], &r[3]);
1630 }
1631
1632 fetch_texel(mach->Samplers[unit],
1633 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1634 control,
1635 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1636 break;
1637
1638 case TGSI_TEXTURE_3D:
1639 case TGSI_TEXTURE_CUBE:
1640 FETCH(&r[0], 0, CHAN_X);
1641 FETCH(&r[1], 0, CHAN_Y);
1642 FETCH(&r[2], 0, CHAN_Z);
1643
1644 if (modifier == TEX_MODIFIER_PROJECTED) {
1645 micro_div(&r[0], &r[0], &r[3]);
1646 micro_div(&r[1], &r[1], &r[3]);
1647 micro_div(&r[2], &r[2], &r[3]);
1648 }
1649
1650 fetch_texel(mach->Samplers[unit],
1651 &r[0], &r[1], &r[2], lod,
1652 control,
1653 &r[0], &r[1], &r[2], &r[3]);
1654 break;
1655
1656 default:
1657 assert(0);
1658 }
1659
1660 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1661 STORE(&r[chan_index], 0, chan_index);
1662 }
1663 }
1664
1665 static void
1666 exec_txd(struct tgsi_exec_machine *mach,
1667 const struct tgsi_full_instruction *inst)
1668 {
1669 const uint unit = inst->Src[3].Register.Index;
1670 union tgsi_exec_channel r[4];
1671 uint chan_index;
1672
1673 /*
1674 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1675 */
1676
1677 switch (inst->Texture.Texture) {
1678 case TGSI_TEXTURE_1D:
1679 case TGSI_TEXTURE_SHADOW1D:
1680
1681 FETCH(&r[0], 0, CHAN_X);
1682
1683 fetch_texel(mach->Samplers[unit],
1684 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1685 tgsi_sampler_lod_bias,
1686 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1687 break;
1688
1689 case TGSI_TEXTURE_2D:
1690 case TGSI_TEXTURE_RECT:
1691 case TGSI_TEXTURE_SHADOW2D:
1692 case TGSI_TEXTURE_SHADOWRECT:
1693
1694 FETCH(&r[0], 0, CHAN_X);
1695 FETCH(&r[1], 0, CHAN_Y);
1696 FETCH(&r[2], 0, CHAN_Z);
1697
1698 fetch_texel(mach->Samplers[unit],
1699 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1700 tgsi_sampler_lod_bias,
1701 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1702 break;
1703
1704 case TGSI_TEXTURE_3D:
1705 case TGSI_TEXTURE_CUBE:
1706
1707 FETCH(&r[0], 0, CHAN_X);
1708 FETCH(&r[1], 0, CHAN_Y);
1709 FETCH(&r[2], 0, CHAN_Z);
1710
1711 fetch_texel(mach->Samplers[unit],
1712 &r[0], &r[1], &r[2], &ZeroVec,
1713 tgsi_sampler_lod_bias,
1714 &r[0], &r[1], &r[2], &r[3]);
1715 break;
1716
1717 default:
1718 assert(0);
1719 }
1720
1721 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1722 STORE(&r[chan_index], 0, chan_index);
1723 }
1724 }
1725
1726
1727 /**
1728 * Evaluate a constant-valued coefficient at the position of the
1729 * current quad.
1730 */
1731 static void
1732 eval_constant_coef(
1733 struct tgsi_exec_machine *mach,
1734 unsigned attrib,
1735 unsigned chan )
1736 {
1737 unsigned i;
1738
1739 for( i = 0; i < QUAD_SIZE; i++ ) {
1740 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1741 }
1742 }
1743
1744 /**
1745 * Evaluate a linear-valued coefficient at the position of the
1746 * current quad.
1747 */
1748 static void
1749 eval_linear_coef(
1750 struct tgsi_exec_machine *mach,
1751 unsigned attrib,
1752 unsigned chan )
1753 {
1754 const float x = mach->QuadPos.xyzw[0].f[0];
1755 const float y = mach->QuadPos.xyzw[1].f[0];
1756 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1757 const float dady = mach->InterpCoefs[attrib].dady[chan];
1758 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1759 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1760 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1761 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1762 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1763 }
1764
1765 /**
1766 * Evaluate a perspective-valued coefficient at the position of the
1767 * current quad.
1768 */
1769 static void
1770 eval_perspective_coef(
1771 struct tgsi_exec_machine *mach,
1772 unsigned attrib,
1773 unsigned chan )
1774 {
1775 const float x = mach->QuadPos.xyzw[0].f[0];
1776 const float y = mach->QuadPos.xyzw[1].f[0];
1777 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1778 const float dady = mach->InterpCoefs[attrib].dady[chan];
1779 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1780 const float *w = mach->QuadPos.xyzw[3].f;
1781 /* divide by W here */
1782 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1783 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1784 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1785 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1786 }
1787
1788
1789 typedef void (* eval_coef_func)(
1790 struct tgsi_exec_machine *mach,
1791 unsigned attrib,
1792 unsigned chan );
1793
1794 static void
1795 exec_declaration(struct tgsi_exec_machine *mach,
1796 const struct tgsi_full_declaration *decl)
1797 {
1798 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
1799 if (decl->Declaration.File == TGSI_FILE_INPUT ||
1800 decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1801 uint first, last, mask;
1802
1803 first = decl->Range.First;
1804 last = decl->Range.Last;
1805 mask = decl->Declaration.UsageMask;
1806
1807 /* XXX we could remove this special-case code since
1808 * mach->InterpCoefs[first].a0 should already have the
1809 * front/back-face value. But we should first update the
1810 * ureg code to emit the right UsageMask value (WRITEMASK_X).
1811 * Then, we could remove the tgsi_exec_machine::Face field.
1812 */
1813 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1814 uint i;
1815
1816 assert(decl->Semantic.Index == 0);
1817 assert(first == last);
1818
1819 for (i = 0; i < QUAD_SIZE; i++) {
1820 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
1821 }
1822 } else {
1823 eval_coef_func eval;
1824 uint i, j;
1825
1826 switch (decl->Declaration.Interpolate) {
1827 case TGSI_INTERPOLATE_CONSTANT:
1828 eval = eval_constant_coef;
1829 break;
1830
1831 case TGSI_INTERPOLATE_LINEAR:
1832 eval = eval_linear_coef;
1833 break;
1834
1835 case TGSI_INTERPOLATE_PERSPECTIVE:
1836 eval = eval_perspective_coef;
1837 break;
1838
1839 default:
1840 assert(0);
1841 return;
1842 }
1843
1844 for (j = 0; j < NUM_CHANNELS; j++) {
1845 if (mask & (1 << j)) {
1846 for (i = first; i <= last; i++) {
1847 eval(mach, i, j);
1848 }
1849 }
1850 }
1851 }
1852 }
1853 }
1854 }
1855
1856 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
1857 const union tgsi_exec_channel *src);
1858
1859 static void
1860 exec_scalar_unary(struct tgsi_exec_machine *mach,
1861 const struct tgsi_full_instruction *inst,
1862 micro_unary_op op,
1863 enum tgsi_exec_datatype dst_datatype,
1864 enum tgsi_exec_datatype src_datatype)
1865 {
1866 unsigned int chan;
1867 union tgsi_exec_channel src;
1868 union tgsi_exec_channel dst;
1869
1870 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
1871 op(&dst, &src);
1872 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1873 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1874 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
1875 }
1876 }
1877 }
1878
1879 static void
1880 exec_vector_unary(struct tgsi_exec_machine *mach,
1881 const struct tgsi_full_instruction *inst,
1882 micro_unary_op op,
1883 enum tgsi_exec_datatype dst_datatype,
1884 enum tgsi_exec_datatype src_datatype)
1885 {
1886 unsigned int chan;
1887 struct tgsi_exec_vector dst;
1888
1889 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1890 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1891 union tgsi_exec_channel src;
1892
1893 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
1894 op(&dst.xyzw[chan], &src);
1895 }
1896 }
1897 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1898 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1899 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1900 }
1901 }
1902 }
1903
1904 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
1905 const union tgsi_exec_channel *src0,
1906 const union tgsi_exec_channel *src1);
1907
1908 static void
1909 exec_vector_binary(struct tgsi_exec_machine *mach,
1910 const struct tgsi_full_instruction *inst,
1911 micro_binary_op op,
1912 enum tgsi_exec_datatype dst_datatype,
1913 enum tgsi_exec_datatype src_datatype)
1914 {
1915 unsigned int chan;
1916 struct tgsi_exec_vector dst;
1917
1918 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1919 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1920 union tgsi_exec_channel src[2];
1921
1922 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
1923 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
1924 op(&dst.xyzw[chan], &src[0], &src[1]);
1925 }
1926 }
1927 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1928 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1929 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1930 }
1931 }
1932 }
1933
1934 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
1935 const union tgsi_exec_channel *src0,
1936 const union tgsi_exec_channel *src1,
1937 const union tgsi_exec_channel *src2);
1938
1939 static void
1940 exec_vector_trinary(struct tgsi_exec_machine *mach,
1941 const struct tgsi_full_instruction *inst,
1942 micro_trinary_op op,
1943 enum tgsi_exec_datatype dst_datatype,
1944 enum tgsi_exec_datatype src_datatype)
1945 {
1946 unsigned int chan;
1947 struct tgsi_exec_vector dst;
1948
1949 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1950 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1951 union tgsi_exec_channel src[3];
1952
1953 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
1954 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
1955 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
1956 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
1957 }
1958 }
1959 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1960 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1961 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1962 }
1963 }
1964 }
1965
1966 static void
1967 exec_dp3(struct tgsi_exec_machine *mach,
1968 const struct tgsi_full_instruction *inst)
1969 {
1970 unsigned int chan;
1971 union tgsi_exec_channel arg[3];
1972
1973 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1974 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1975 micro_mul(&arg[2], &arg[0], &arg[1]);
1976
1977 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
1978 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
1979 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
1980 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
1981 }
1982
1983 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1984 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1985 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1986 }
1987 }
1988 }
1989
1990 static void
1991 exec_dp4(struct tgsi_exec_machine *mach,
1992 const struct tgsi_full_instruction *inst)
1993 {
1994 unsigned int chan;
1995 union tgsi_exec_channel arg[3];
1996
1997 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1998 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1999 micro_mul(&arg[2], &arg[0], &arg[1]);
2000
2001 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2002 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2003 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2004 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2005 }
2006
2007 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2008 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2009 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2010 }
2011 }
2012 }
2013
2014 static void
2015 exec_dp2a(struct tgsi_exec_machine *mach,
2016 const struct tgsi_full_instruction *inst)
2017 {
2018 unsigned int chan;
2019 union tgsi_exec_channel arg[3];
2020
2021 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2022 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2023 micro_mul(&arg[2], &arg[0], &arg[1]);
2024
2025 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2026 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2027 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2028
2029 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2030 micro_add(&arg[0], &arg[0], &arg[1]);
2031
2032 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2033 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2034 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2035 }
2036 }
2037 }
2038
2039 static void
2040 exec_dph(struct tgsi_exec_machine *mach,
2041 const struct tgsi_full_instruction *inst)
2042 {
2043 unsigned int chan;
2044 union tgsi_exec_channel arg[3];
2045
2046 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2047 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2048 micro_mul(&arg[2], &arg[0], &arg[1]);
2049
2050 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2051 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2052 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2053
2054 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2055 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2056 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2057
2058 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2059 micro_add(&arg[0], &arg[0], &arg[1]);
2060
2061 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2062 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2063 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2064 }
2065 }
2066 }
2067
2068 static void
2069 exec_dp2(struct tgsi_exec_machine *mach,
2070 const struct tgsi_full_instruction *inst)
2071 {
2072 unsigned int chan;
2073 union tgsi_exec_channel arg[3];
2074
2075 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2076 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2077 micro_mul(&arg[2], &arg[0], &arg[1]);
2078
2079 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2080 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2081 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2082
2083 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2084 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2085 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2086 }
2087 }
2088 }
2089
2090 static void
2091 exec_nrm4(struct tgsi_exec_machine *mach,
2092 const struct tgsi_full_instruction *inst)
2093 {
2094 unsigned int chan;
2095 union tgsi_exec_channel arg[4];
2096 union tgsi_exec_channel scale;
2097
2098 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2099 micro_mul(&scale, &arg[0], &arg[0]);
2100
2101 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2102 union tgsi_exec_channel product;
2103
2104 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2105 micro_mul(&product, &arg[chan], &arg[chan]);
2106 micro_add(&scale, &scale, &product);
2107 }
2108
2109 micro_rsq(&scale, &scale);
2110
2111 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2112 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2113 micro_mul(&arg[chan], &arg[chan], &scale);
2114 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2115 }
2116 }
2117 }
2118
2119 static void
2120 exec_nrm3(struct tgsi_exec_machine *mach,
2121 const struct tgsi_full_instruction *inst)
2122 {
2123 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2124 unsigned int chan;
2125 union tgsi_exec_channel arg[3];
2126 union tgsi_exec_channel scale;
2127
2128 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2129 micro_mul(&scale, &arg[0], &arg[0]);
2130
2131 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2132 union tgsi_exec_channel product;
2133
2134 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2135 micro_mul(&product, &arg[chan], &arg[chan]);
2136 micro_add(&scale, &scale, &product);
2137 }
2138
2139 micro_rsq(&scale, &scale);
2140
2141 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2142 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2143 micro_mul(&arg[chan], &arg[chan], &scale);
2144 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2145 }
2146 }
2147 }
2148
2149 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2150 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2151 }
2152 }
2153
2154 static void
2155 exec_break(struct tgsi_exec_machine *mach)
2156 {
2157 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2158 /* turn off loop channels for each enabled exec channel */
2159 mach->LoopMask &= ~mach->ExecMask;
2160 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2161 UPDATE_EXEC_MASK(mach);
2162 } else {
2163 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2164
2165 mach->Switch.mask = 0x0;
2166
2167 UPDATE_EXEC_MASK(mach);
2168 }
2169 }
2170
2171 static void
2172 exec_switch(struct tgsi_exec_machine *mach,
2173 const struct tgsi_full_instruction *inst)
2174 {
2175 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2176 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2177
2178 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2179 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2180 mach->Switch.mask = 0x0;
2181 mach->Switch.defaultMask = 0x0;
2182
2183 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2184 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2185
2186 UPDATE_EXEC_MASK(mach);
2187 }
2188
2189 static void
2190 exec_case(struct tgsi_exec_machine *mach,
2191 const struct tgsi_full_instruction *inst)
2192 {
2193 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2194 union tgsi_exec_channel src;
2195 uint mask = 0;
2196
2197 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2198
2199 if (mach->Switch.selector.u[0] == src.u[0]) {
2200 mask |= 0x1;
2201 }
2202 if (mach->Switch.selector.u[1] == src.u[1]) {
2203 mask |= 0x2;
2204 }
2205 if (mach->Switch.selector.u[2] == src.u[2]) {
2206 mask |= 0x4;
2207 }
2208 if (mach->Switch.selector.u[3] == src.u[3]) {
2209 mask |= 0x8;
2210 }
2211
2212 mach->Switch.defaultMask |= mask;
2213
2214 mach->Switch.mask |= mask & prevMask;
2215
2216 UPDATE_EXEC_MASK(mach);
2217 }
2218
2219 static void
2220 exec_default(struct tgsi_exec_machine *mach)
2221 {
2222 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2223
2224 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2225
2226 UPDATE_EXEC_MASK(mach);
2227 }
2228
2229 static void
2230 exec_endswitch(struct tgsi_exec_machine *mach)
2231 {
2232 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2233 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2234
2235 UPDATE_EXEC_MASK(mach);
2236 }
2237
2238 static void
2239 micro_i2f(union tgsi_exec_channel *dst,
2240 const union tgsi_exec_channel *src)
2241 {
2242 dst->f[0] = (float)src->i[0];
2243 dst->f[1] = (float)src->i[1];
2244 dst->f[2] = (float)src->i[2];
2245 dst->f[3] = (float)src->i[3];
2246 }
2247
2248 static void
2249 micro_not(union tgsi_exec_channel *dst,
2250 const union tgsi_exec_channel *src)
2251 {
2252 dst->u[0] = ~src->u[0];
2253 dst->u[1] = ~src->u[1];
2254 dst->u[2] = ~src->u[2];
2255 dst->u[3] = ~src->u[3];
2256 }
2257
2258 static void
2259 micro_shl(union tgsi_exec_channel *dst,
2260 const union tgsi_exec_channel *src0,
2261 const union tgsi_exec_channel *src1)
2262 {
2263 dst->u[0] = src0->u[0] << src1->u[0];
2264 dst->u[1] = src0->u[1] << src1->u[1];
2265 dst->u[2] = src0->u[2] << src1->u[2];
2266 dst->u[3] = src0->u[3] << src1->u[3];
2267 }
2268
2269 static void
2270 micro_and(union tgsi_exec_channel *dst,
2271 const union tgsi_exec_channel *src0,
2272 const union tgsi_exec_channel *src1)
2273 {
2274 dst->u[0] = src0->u[0] & src1->u[0];
2275 dst->u[1] = src0->u[1] & src1->u[1];
2276 dst->u[2] = src0->u[2] & src1->u[2];
2277 dst->u[3] = src0->u[3] & src1->u[3];
2278 }
2279
2280 static void
2281 micro_or(union tgsi_exec_channel *dst,
2282 const union tgsi_exec_channel *src0,
2283 const union tgsi_exec_channel *src1)
2284 {
2285 dst->u[0] = src0->u[0] | src1->u[0];
2286 dst->u[1] = src0->u[1] | src1->u[1];
2287 dst->u[2] = src0->u[2] | src1->u[2];
2288 dst->u[3] = src0->u[3] | src1->u[3];
2289 }
2290
2291 static void
2292 micro_xor(union tgsi_exec_channel *dst,
2293 const union tgsi_exec_channel *src0,
2294 const union tgsi_exec_channel *src1)
2295 {
2296 dst->u[0] = src0->u[0] ^ src1->u[0];
2297 dst->u[1] = src0->u[1] ^ src1->u[1];
2298 dst->u[2] = src0->u[2] ^ src1->u[2];
2299 dst->u[3] = src0->u[3] ^ src1->u[3];
2300 }
2301
2302 static void
2303 micro_f2i(union tgsi_exec_channel *dst,
2304 const union tgsi_exec_channel *src)
2305 {
2306 dst->i[0] = (int)src->f[0];
2307 dst->i[1] = (int)src->f[1];
2308 dst->i[2] = (int)src->f[2];
2309 dst->i[3] = (int)src->f[3];
2310 }
2311
2312 static void
2313 micro_idiv(union tgsi_exec_channel *dst,
2314 const union tgsi_exec_channel *src0,
2315 const union tgsi_exec_channel *src1)
2316 {
2317 dst->i[0] = src0->i[0] / src1->i[0];
2318 dst->i[1] = src0->i[1] / src1->i[1];
2319 dst->i[2] = src0->i[2] / src1->i[2];
2320 dst->i[3] = src0->i[3] / src1->i[3];
2321 }
2322
2323 static void
2324 micro_imax(union tgsi_exec_channel *dst,
2325 const union tgsi_exec_channel *src0,
2326 const union tgsi_exec_channel *src1)
2327 {
2328 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
2329 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
2330 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
2331 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
2332 }
2333
2334 static void
2335 micro_imin(union tgsi_exec_channel *dst,
2336 const union tgsi_exec_channel *src0,
2337 const union tgsi_exec_channel *src1)
2338 {
2339 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
2340 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
2341 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
2342 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
2343 }
2344
2345 static void
2346 micro_isge(union tgsi_exec_channel *dst,
2347 const union tgsi_exec_channel *src0,
2348 const union tgsi_exec_channel *src1)
2349 {
2350 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
2351 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
2352 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
2353 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
2354 }
2355
2356 static void
2357 micro_ishr(union tgsi_exec_channel *dst,
2358 const union tgsi_exec_channel *src0,
2359 const union tgsi_exec_channel *src1)
2360 {
2361 dst->i[0] = src0->i[0] >> src1->i[0];
2362 dst->i[1] = src0->i[1] >> src1->i[1];
2363 dst->i[2] = src0->i[2] >> src1->i[2];
2364 dst->i[3] = src0->i[3] >> src1->i[3];
2365 }
2366
2367 static void
2368 micro_islt(union tgsi_exec_channel *dst,
2369 const union tgsi_exec_channel *src0,
2370 const union tgsi_exec_channel *src1)
2371 {
2372 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
2373 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
2374 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
2375 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
2376 }
2377
2378 static void
2379 micro_f2u(union tgsi_exec_channel *dst,
2380 const union tgsi_exec_channel *src)
2381 {
2382 dst->u[0] = (uint)src->f[0];
2383 dst->u[1] = (uint)src->f[1];
2384 dst->u[2] = (uint)src->f[2];
2385 dst->u[3] = (uint)src->f[3];
2386 }
2387
2388 static void
2389 micro_u2f(union tgsi_exec_channel *dst,
2390 const union tgsi_exec_channel *src)
2391 {
2392 dst->f[0] = (float)src->u[0];
2393 dst->f[1] = (float)src->u[1];
2394 dst->f[2] = (float)src->u[2];
2395 dst->f[3] = (float)src->u[3];
2396 }
2397
2398 static void
2399 micro_uadd(union tgsi_exec_channel *dst,
2400 const union tgsi_exec_channel *src0,
2401 const union tgsi_exec_channel *src1)
2402 {
2403 dst->u[0] = src0->u[0] + src1->u[0];
2404 dst->u[1] = src0->u[1] + src1->u[1];
2405 dst->u[2] = src0->u[2] + src1->u[2];
2406 dst->u[3] = src0->u[3] + src1->u[3];
2407 }
2408
2409 static void
2410 micro_udiv(union tgsi_exec_channel *dst,
2411 const union tgsi_exec_channel *src0,
2412 const union tgsi_exec_channel *src1)
2413 {
2414 dst->u[0] = src0->u[0] / src1->u[0];
2415 dst->u[1] = src0->u[1] / src1->u[1];
2416 dst->u[2] = src0->u[2] / src1->u[2];
2417 dst->u[3] = src0->u[3] / src1->u[3];
2418 }
2419
2420 static void
2421 micro_umad(union tgsi_exec_channel *dst,
2422 const union tgsi_exec_channel *src0,
2423 const union tgsi_exec_channel *src1,
2424 const union tgsi_exec_channel *src2)
2425 {
2426 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
2427 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
2428 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
2429 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
2430 }
2431
2432 static void
2433 micro_umax(union tgsi_exec_channel *dst,
2434 const union tgsi_exec_channel *src0,
2435 const union tgsi_exec_channel *src1)
2436 {
2437 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
2438 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
2439 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
2440 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
2441 }
2442
2443 static void
2444 micro_umin(union tgsi_exec_channel *dst,
2445 const union tgsi_exec_channel *src0,
2446 const union tgsi_exec_channel *src1)
2447 {
2448 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
2449 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
2450 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
2451 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
2452 }
2453
2454 static void
2455 micro_umod(union tgsi_exec_channel *dst,
2456 const union tgsi_exec_channel *src0,
2457 const union tgsi_exec_channel *src1)
2458 {
2459 dst->u[0] = src0->u[0] % src1->u[0];
2460 dst->u[1] = src0->u[1] % src1->u[1];
2461 dst->u[2] = src0->u[2] % src1->u[2];
2462 dst->u[3] = src0->u[3] % src1->u[3];
2463 }
2464
2465 static void
2466 micro_umul(union tgsi_exec_channel *dst,
2467 const union tgsi_exec_channel *src0,
2468 const union tgsi_exec_channel *src1)
2469 {
2470 dst->u[0] = src0->u[0] * src1->u[0];
2471 dst->u[1] = src0->u[1] * src1->u[1];
2472 dst->u[2] = src0->u[2] * src1->u[2];
2473 dst->u[3] = src0->u[3] * src1->u[3];
2474 }
2475
2476 static void
2477 micro_useq(union tgsi_exec_channel *dst,
2478 const union tgsi_exec_channel *src0,
2479 const union tgsi_exec_channel *src1)
2480 {
2481 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
2482 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
2483 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
2484 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
2485 }
2486
2487 static void
2488 micro_usge(union tgsi_exec_channel *dst,
2489 const union tgsi_exec_channel *src0,
2490 const union tgsi_exec_channel *src1)
2491 {
2492 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
2493 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
2494 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
2495 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
2496 }
2497
2498 static void
2499 micro_ushr(union tgsi_exec_channel *dst,
2500 const union tgsi_exec_channel *src0,
2501 const union tgsi_exec_channel *src1)
2502 {
2503 dst->u[0] = src0->u[0] >> src1->u[0];
2504 dst->u[1] = src0->u[1] >> src1->u[1];
2505 dst->u[2] = src0->u[2] >> src1->u[2];
2506 dst->u[3] = src0->u[3] >> src1->u[3];
2507 }
2508
2509 static void
2510 micro_uslt(union tgsi_exec_channel *dst,
2511 const union tgsi_exec_channel *src0,
2512 const union tgsi_exec_channel *src1)
2513 {
2514 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
2515 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
2516 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
2517 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
2518 }
2519
2520 static void
2521 micro_usne(union tgsi_exec_channel *dst,
2522 const union tgsi_exec_channel *src0,
2523 const union tgsi_exec_channel *src1)
2524 {
2525 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
2526 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
2527 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
2528 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
2529 }
2530
2531 static void
2532 exec_instruction(
2533 struct tgsi_exec_machine *mach,
2534 const struct tgsi_full_instruction *inst,
2535 int *pc )
2536 {
2537 uint chan_index;
2538 union tgsi_exec_channel r[10];
2539 union tgsi_exec_channel d[8];
2540
2541 (*pc)++;
2542
2543 switch (inst->Instruction.Opcode) {
2544 case TGSI_OPCODE_ARL:
2545 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2546 break;
2547
2548 case TGSI_OPCODE_MOV:
2549 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
2550 break;
2551
2552 case TGSI_OPCODE_LIT:
2553 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2554 FETCH( &r[0], 0, CHAN_X );
2555 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2556 micro_max(&d[CHAN_Y], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2557 }
2558
2559 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2560 FETCH( &r[1], 0, CHAN_Y );
2561 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2562
2563 FETCH( &r[2], 0, CHAN_W );
2564 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
2565 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
2566 micro_pow( &r[1], &r[1], &r[2] );
2567 micro_lt(&d[CHAN_Z], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2568 }
2569
2570 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2571 STORE(&d[CHAN_Y], 0, CHAN_Y);
2572 }
2573 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2574 STORE(&d[CHAN_Z], 0, CHAN_Z);
2575 }
2576 }
2577 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2578 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
2579 }
2580 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2581 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2582 }
2583 break;
2584
2585 case TGSI_OPCODE_RCP:
2586 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2587 break;
2588
2589 case TGSI_OPCODE_RSQ:
2590 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2591 break;
2592
2593 case TGSI_OPCODE_EXP:
2594 FETCH( &r[0], 0, CHAN_X );
2595 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
2596 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2597 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
2598 STORE( &r[2], 0, CHAN_X ); /* store r2 */
2599 }
2600 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2601 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
2602 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
2603 }
2604 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2605 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
2606 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
2607 }
2608 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2609 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2610 }
2611 break;
2612
2613 case TGSI_OPCODE_LOG:
2614 FETCH( &r[0], 0, CHAN_X );
2615 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
2616 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
2617 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
2618 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2619 STORE( &r[0], 0, CHAN_X );
2620 }
2621 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2622 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
2623 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
2624 STORE( &r[0], 0, CHAN_Y );
2625 }
2626 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2627 STORE( &r[1], 0, CHAN_Z );
2628 }
2629 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2630 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2631 }
2632 break;
2633
2634 case TGSI_OPCODE_MUL:
2635 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2636 break;
2637
2638 case TGSI_OPCODE_ADD:
2639 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2640 break;
2641
2642 case TGSI_OPCODE_DP3:
2643 exec_dp3(mach, inst);
2644 break;
2645
2646 case TGSI_OPCODE_DP4:
2647 exec_dp4(mach, inst);
2648 break;
2649
2650 case TGSI_OPCODE_DST:
2651 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2652 FETCH( &r[0], 0, CHAN_Y );
2653 FETCH( &r[1], 1, CHAN_Y);
2654 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2655 }
2656 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2657 FETCH(&d[CHAN_Z], 0, CHAN_Z);
2658 }
2659 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2660 FETCH(&d[CHAN_W], 1, CHAN_W);
2661 }
2662
2663 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2664 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X);
2665 }
2666 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2667 STORE(&d[CHAN_Y], 0, CHAN_Y);
2668 }
2669 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2670 STORE(&d[CHAN_Z], 0, CHAN_Z);
2671 }
2672 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2673 STORE(&d[CHAN_W], 0, CHAN_W);
2674 }
2675 break;
2676
2677 case TGSI_OPCODE_MIN:
2678 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2679 break;
2680
2681 case TGSI_OPCODE_MAX:
2682 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2683 break;
2684
2685 case TGSI_OPCODE_SLT:
2686 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2687 break;
2688
2689 case TGSI_OPCODE_SGE:
2690 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2691 break;
2692
2693 case TGSI_OPCODE_MAD:
2694 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2695 break;
2696
2697 case TGSI_OPCODE_SUB:
2698 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2699 break;
2700
2701 case TGSI_OPCODE_LRP:
2702 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2703 break;
2704
2705 case TGSI_OPCODE_CND:
2706 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2707 break;
2708
2709 case TGSI_OPCODE_DP2A:
2710 exec_dp2a(mach, inst);
2711 break;
2712
2713 case TGSI_OPCODE_FRC:
2714 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2715 break;
2716
2717 case TGSI_OPCODE_CLAMP:
2718 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2719 break;
2720
2721 case TGSI_OPCODE_FLR:
2722 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2723 break;
2724
2725 case TGSI_OPCODE_ROUND:
2726 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2727 break;
2728
2729 case TGSI_OPCODE_EX2:
2730 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2731 break;
2732
2733 case TGSI_OPCODE_LG2:
2734 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2735 break;
2736
2737 case TGSI_OPCODE_POW:
2738 FETCH(&r[0], 0, CHAN_X);
2739 FETCH(&r[1], 1, CHAN_X);
2740
2741 micro_pow( &r[0], &r[0], &r[1] );
2742
2743 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2744 STORE( &r[0], 0, chan_index );
2745 }
2746 break;
2747
2748 case TGSI_OPCODE_XPD:
2749 FETCH(&r[0], 0, CHAN_Y);
2750 FETCH(&r[1], 1, CHAN_Z);
2751
2752 micro_mul( &r[2], &r[0], &r[1] );
2753
2754 FETCH(&r[3], 0, CHAN_Z);
2755 FETCH(&r[4], 1, CHAN_Y);
2756
2757 micro_mul( &r[5], &r[3], &r[4] );
2758 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2759
2760 FETCH(&r[2], 1, CHAN_X);
2761
2762 micro_mul( &r[3], &r[3], &r[2] );
2763
2764 FETCH(&r[5], 0, CHAN_X);
2765
2766 micro_mul( &r[1], &r[1], &r[5] );
2767 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2768
2769 micro_mul( &r[5], &r[5], &r[4] );
2770 micro_mul( &r[0], &r[0], &r[2] );
2771 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2772
2773 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2774 STORE(&d[CHAN_X], 0, CHAN_X);
2775 }
2776 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2777 STORE(&d[CHAN_Y], 0, CHAN_Y);
2778 }
2779 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2780 STORE(&d[CHAN_Z], 0, CHAN_Z);
2781 }
2782 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2783 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2784 }
2785 break;
2786
2787 case TGSI_OPCODE_ABS:
2788 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2789 break;
2790
2791 case TGSI_OPCODE_RCC:
2792 FETCH(&r[0], 0, CHAN_X);
2793 micro_div(&r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0]);
2794 micro_float_clamp(&r[0], &r[0]);
2795 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2796 STORE(&r[0], 0, chan_index);
2797 }
2798 break;
2799
2800 case TGSI_OPCODE_DPH:
2801 exec_dph(mach, inst);
2802 break;
2803
2804 case TGSI_OPCODE_COS:
2805 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2806 break;
2807
2808 case TGSI_OPCODE_DDX:
2809 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2810 break;
2811
2812 case TGSI_OPCODE_DDY:
2813 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2814 break;
2815
2816 case TGSI_OPCODE_KILP:
2817 exec_kilp (mach, inst);
2818 break;
2819
2820 case TGSI_OPCODE_KIL:
2821 exec_kil (mach, inst);
2822 break;
2823
2824 case TGSI_OPCODE_PK2H:
2825 assert (0);
2826 break;
2827
2828 case TGSI_OPCODE_PK2US:
2829 assert (0);
2830 break;
2831
2832 case TGSI_OPCODE_PK4B:
2833 assert (0);
2834 break;
2835
2836 case TGSI_OPCODE_PK4UB:
2837 assert (0);
2838 break;
2839
2840 case TGSI_OPCODE_RFL:
2841 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2842 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2843 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2844 /* r0 = dp3(src0, src0) */
2845 FETCH(&r[2], 0, CHAN_X);
2846 micro_mul(&r[0], &r[2], &r[2]);
2847 FETCH(&r[4], 0, CHAN_Y);
2848 micro_mul(&r[8], &r[4], &r[4]);
2849 micro_add(&r[0], &r[0], &r[8]);
2850 FETCH(&r[6], 0, CHAN_Z);
2851 micro_mul(&r[8], &r[6], &r[6]);
2852 micro_add(&r[0], &r[0], &r[8]);
2853
2854 /* r1 = dp3(src0, src1) */
2855 FETCH(&r[3], 1, CHAN_X);
2856 micro_mul(&r[1], &r[2], &r[3]);
2857 FETCH(&r[5], 1, CHAN_Y);
2858 micro_mul(&r[8], &r[4], &r[5]);
2859 micro_add(&r[1], &r[1], &r[8]);
2860 FETCH(&r[7], 1, CHAN_Z);
2861 micro_mul(&r[8], &r[6], &r[7]);
2862 micro_add(&r[1], &r[1], &r[8]);
2863
2864 /* r1 = 2 * r1 / r0 */
2865 micro_add(&r[1], &r[1], &r[1]);
2866 micro_div(&r[1], &r[1], &r[0]);
2867
2868 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2869 micro_mul(&r[2], &r[2], &r[1]);
2870 micro_sub(&r[2], &r[2], &r[3]);
2871 STORE(&r[2], 0, CHAN_X);
2872 }
2873 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2874 micro_mul(&r[4], &r[4], &r[1]);
2875 micro_sub(&r[4], &r[4], &r[5]);
2876 STORE(&r[4], 0, CHAN_Y);
2877 }
2878 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2879 micro_mul(&r[6], &r[6], &r[1]);
2880 micro_sub(&r[6], &r[6], &r[7]);
2881 STORE(&r[6], 0, CHAN_Z);
2882 }
2883 }
2884 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2885 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
2886 }
2887 break;
2888
2889 case TGSI_OPCODE_SEQ:
2890 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2891 break;
2892
2893 case TGSI_OPCODE_SFL:
2894 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2895 STORE(&mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, chan_index);
2896 }
2897 break;
2898
2899 case TGSI_OPCODE_SGT:
2900 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2901 break;
2902
2903 case TGSI_OPCODE_SIN:
2904 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2905 break;
2906
2907 case TGSI_OPCODE_SLE:
2908 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2909 break;
2910
2911 case TGSI_OPCODE_SNE:
2912 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2913 break;
2914
2915 case TGSI_OPCODE_STR:
2916 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2917 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, chan_index);
2918 }
2919 break;
2920
2921 case TGSI_OPCODE_TEX:
2922 /* simple texture lookup */
2923 /* src[0] = texcoord */
2924 /* src[1] = sampler unit */
2925 exec_tex(mach, inst, TEX_MODIFIER_NONE);
2926 break;
2927
2928 case TGSI_OPCODE_TXB:
2929 /* Texture lookup with lod bias */
2930 /* src[0] = texcoord (src[0].w = LOD bias) */
2931 /* src[1] = sampler unit */
2932 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
2933 break;
2934
2935 case TGSI_OPCODE_TXD:
2936 /* Texture lookup with explict partial derivatives */
2937 /* src[0] = texcoord */
2938 /* src[1] = d[strq]/dx */
2939 /* src[2] = d[strq]/dy */
2940 /* src[3] = sampler unit */
2941 exec_txd(mach, inst);
2942 break;
2943
2944 case TGSI_OPCODE_TXL:
2945 /* Texture lookup with explit LOD */
2946 /* src[0] = texcoord (src[0].w = LOD) */
2947 /* src[1] = sampler unit */
2948 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
2949 break;
2950
2951 case TGSI_OPCODE_TXP:
2952 /* Texture lookup with projection */
2953 /* src[0] = texcoord (src[0].w = projection) */
2954 /* src[1] = sampler unit */
2955 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
2956 break;
2957
2958 case TGSI_OPCODE_UP2H:
2959 assert (0);
2960 break;
2961
2962 case TGSI_OPCODE_UP2US:
2963 assert (0);
2964 break;
2965
2966 case TGSI_OPCODE_UP4B:
2967 assert (0);
2968 break;
2969
2970 case TGSI_OPCODE_UP4UB:
2971 assert (0);
2972 break;
2973
2974 case TGSI_OPCODE_X2D:
2975 FETCH(&r[0], 1, CHAN_X);
2976 FETCH(&r[1], 1, CHAN_Y);
2977 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2978 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2979 FETCH(&r[2], 2, CHAN_X);
2980 micro_mul(&r[2], &r[2], &r[0]);
2981 FETCH(&r[3], 2, CHAN_Y);
2982 micro_mul(&r[3], &r[3], &r[1]);
2983 micro_add(&r[2], &r[2], &r[3]);
2984 FETCH(&r[3], 0, CHAN_X);
2985 micro_add(&d[CHAN_X], &r[2], &r[3]);
2986
2987 }
2988 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2989 IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2990 FETCH(&r[2], 2, CHAN_Z);
2991 micro_mul(&r[2], &r[2], &r[0]);
2992 FETCH(&r[3], 2, CHAN_W);
2993 micro_mul(&r[3], &r[3], &r[1]);
2994 micro_add(&r[2], &r[2], &r[3]);
2995 FETCH(&r[3], 0, CHAN_Y);
2996 micro_add(&d[CHAN_Y], &r[2], &r[3]);
2997
2998 }
2999 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3000 STORE(&d[CHAN_X], 0, CHAN_X);
3001 }
3002 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3003 STORE(&d[CHAN_Y], 0, CHAN_Y);
3004 }
3005 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3006 STORE(&d[CHAN_X], 0, CHAN_Z);
3007 }
3008 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
3009 STORE(&d[CHAN_Y], 0, CHAN_W);
3010 }
3011 break;
3012
3013 case TGSI_OPCODE_ARA:
3014 assert (0);
3015 break;
3016
3017 case TGSI_OPCODE_ARR:
3018 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3019 break;
3020
3021 case TGSI_OPCODE_BRA:
3022 assert (0);
3023 break;
3024
3025 case TGSI_OPCODE_CAL:
3026 /* skip the call if no execution channels are enabled */
3027 if (mach->ExecMask) {
3028 /* do the call */
3029
3030 /* First, record the depths of the execution stacks.
3031 * This is important for deeply nested/looped return statements.
3032 * We have to unwind the stacks by the correct amount. For a
3033 * real code generator, we could determine the number of entries
3034 * to pop off each stack with simple static analysis and avoid
3035 * implementing this data structure at run time.
3036 */
3037 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3038 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3039 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3040 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3041 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3042 /* note that PC was already incremented above */
3043 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3044
3045 mach->CallStackTop++;
3046
3047 /* Second, push the Cond, Loop, Cont, Func stacks */
3048 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3049 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3050 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3051 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3052 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3053 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3054
3055 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3056 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3057 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3058 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3059 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3060 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3061
3062 /* Finally, jump to the subroutine */
3063 *pc = inst->Label.Label;
3064 }
3065 break;
3066
3067 case TGSI_OPCODE_RET:
3068 mach->FuncMask &= ~mach->ExecMask;
3069 UPDATE_EXEC_MASK(mach);
3070
3071 if (mach->FuncMask == 0x0) {
3072 /* really return now (otherwise, keep executing */
3073
3074 if (mach->CallStackTop == 0) {
3075 /* returning from main() */
3076 *pc = -1;
3077 return;
3078 }
3079
3080 assert(mach->CallStackTop > 0);
3081 mach->CallStackTop--;
3082
3083 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3084 mach->CondMask = mach->CondStack[mach->CondStackTop];
3085
3086 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3087 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3088
3089 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3090 mach->ContMask = mach->ContStack[mach->ContStackTop];
3091
3092 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3093 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3094
3095 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3096 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3097
3098 assert(mach->FuncStackTop > 0);
3099 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3100
3101 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3102
3103 UPDATE_EXEC_MASK(mach);
3104 }
3105 break;
3106
3107 case TGSI_OPCODE_SSG:
3108 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3109 break;
3110
3111 case TGSI_OPCODE_CMP:
3112 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3113 break;
3114
3115 case TGSI_OPCODE_SCS:
3116 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
3117 FETCH( &r[0], 0, CHAN_X );
3118 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3119 micro_cos(&r[1], &r[0]);
3120 STORE(&r[1], 0, CHAN_X);
3121 }
3122 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3123 micro_sin(&r[1], &r[0]);
3124 STORE(&r[1], 0, CHAN_Y);
3125 }
3126 }
3127 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
3128 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
3129 }
3130 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
3131 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
3132 }
3133 break;
3134
3135 case TGSI_OPCODE_NRM:
3136 exec_nrm3(mach, inst);
3137 break;
3138
3139 case TGSI_OPCODE_NRM4:
3140 exec_nrm4(mach, inst);
3141 break;
3142
3143 case TGSI_OPCODE_DIV:
3144 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3145 break;
3146
3147 case TGSI_OPCODE_DP2:
3148 exec_dp2(mach, inst);
3149 break;
3150
3151 case TGSI_OPCODE_IF:
3152 /* push CondMask */
3153 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3154 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3155 FETCH( &r[0], 0, CHAN_X );
3156 /* update CondMask */
3157 if( ! r[0].u[0] ) {
3158 mach->CondMask &= ~0x1;
3159 }
3160 if( ! r[0].u[1] ) {
3161 mach->CondMask &= ~0x2;
3162 }
3163 if( ! r[0].u[2] ) {
3164 mach->CondMask &= ~0x4;
3165 }
3166 if( ! r[0].u[3] ) {
3167 mach->CondMask &= ~0x8;
3168 }
3169 UPDATE_EXEC_MASK(mach);
3170 /* Todo: If CondMask==0, jump to ELSE */
3171 break;
3172
3173 case TGSI_OPCODE_ELSE:
3174 /* invert CondMask wrt previous mask */
3175 {
3176 uint prevMask;
3177 assert(mach->CondStackTop > 0);
3178 prevMask = mach->CondStack[mach->CondStackTop - 1];
3179 mach->CondMask = ~mach->CondMask & prevMask;
3180 UPDATE_EXEC_MASK(mach);
3181 /* Todo: If CondMask==0, jump to ENDIF */
3182 }
3183 break;
3184
3185 case TGSI_OPCODE_ENDIF:
3186 /* pop CondMask */
3187 assert(mach->CondStackTop > 0);
3188 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3189 UPDATE_EXEC_MASK(mach);
3190 break;
3191
3192 case TGSI_OPCODE_END:
3193 /* halt execution */
3194 *pc = -1;
3195 break;
3196
3197 case TGSI_OPCODE_PUSHA:
3198 assert (0);
3199 break;
3200
3201 case TGSI_OPCODE_POPA:
3202 assert (0);
3203 break;
3204
3205 case TGSI_OPCODE_CEIL:
3206 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3207 break;
3208
3209 case TGSI_OPCODE_I2F:
3210 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3211 break;
3212
3213 case TGSI_OPCODE_NOT:
3214 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3215 break;
3216
3217 case TGSI_OPCODE_TRUNC:
3218 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3219 break;
3220
3221 case TGSI_OPCODE_SHL:
3222 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3223 break;
3224
3225 case TGSI_OPCODE_AND:
3226 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3227 break;
3228
3229 case TGSI_OPCODE_OR:
3230 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3231 break;
3232
3233 case TGSI_OPCODE_MOD:
3234 assert (0);
3235 break;
3236
3237 case TGSI_OPCODE_XOR:
3238 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3239 break;
3240
3241 case TGSI_OPCODE_SAD:
3242 assert (0);
3243 break;
3244
3245 case TGSI_OPCODE_TXF:
3246 assert (0);
3247 break;
3248
3249 case TGSI_OPCODE_TXQ:
3250 assert (0);
3251 break;
3252
3253 case TGSI_OPCODE_EMIT:
3254 emit_vertex(mach);
3255 break;
3256
3257 case TGSI_OPCODE_ENDPRIM:
3258 emit_primitive(mach);
3259 break;
3260
3261 case TGSI_OPCODE_BGNLOOP:
3262 /* push LoopMask and ContMasks */
3263 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3264 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3265 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3266 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3267
3268 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3269 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3270 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3271 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3272 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3273 break;
3274
3275 case TGSI_OPCODE_ENDLOOP:
3276 /* Restore ContMask, but don't pop */
3277 assert(mach->ContStackTop > 0);
3278 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3279 UPDATE_EXEC_MASK(mach);
3280 if (mach->ExecMask) {
3281 /* repeat loop: jump to instruction just past BGNLOOP */
3282 assert(mach->LoopLabelStackTop > 0);
3283 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3284 }
3285 else {
3286 /* exit loop: pop LoopMask */
3287 assert(mach->LoopStackTop > 0);
3288 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3289 /* pop ContMask */
3290 assert(mach->ContStackTop > 0);
3291 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3292 assert(mach->LoopLabelStackTop > 0);
3293 --mach->LoopLabelStackTop;
3294
3295 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3296 }
3297 UPDATE_EXEC_MASK(mach);
3298 break;
3299
3300 case TGSI_OPCODE_BRK:
3301 exec_break(mach);
3302 break;
3303
3304 case TGSI_OPCODE_CONT:
3305 /* turn off cont channels for each enabled exec channel */
3306 mach->ContMask &= ~mach->ExecMask;
3307 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3308 UPDATE_EXEC_MASK(mach);
3309 break;
3310
3311 case TGSI_OPCODE_BGNSUB:
3312 /* no-op */
3313 break;
3314
3315 case TGSI_OPCODE_ENDSUB:
3316 /*
3317 * XXX: This really should be a no-op. We should never reach this opcode.
3318 */
3319
3320 assert(mach->CallStackTop > 0);
3321 mach->CallStackTop--;
3322
3323 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3324 mach->CondMask = mach->CondStack[mach->CondStackTop];
3325
3326 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3327 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3328
3329 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3330 mach->ContMask = mach->ContStack[mach->ContStackTop];
3331
3332 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3333 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3334
3335 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3336 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3337
3338 assert(mach->FuncStackTop > 0);
3339 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3340
3341 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3342
3343 UPDATE_EXEC_MASK(mach);
3344 break;
3345
3346 case TGSI_OPCODE_NOP:
3347 break;
3348
3349 case TGSI_OPCODE_BREAKC:
3350 FETCH(&r[0], 0, CHAN_X);
3351 /* update CondMask */
3352 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3353 mach->LoopMask &= ~0x1;
3354 }
3355 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3356 mach->LoopMask &= ~0x2;
3357 }
3358 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3359 mach->LoopMask &= ~0x4;
3360 }
3361 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3362 mach->LoopMask &= ~0x8;
3363 }
3364 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3365 UPDATE_EXEC_MASK(mach);
3366 break;
3367
3368 case TGSI_OPCODE_F2I:
3369 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3370 break;
3371
3372 case TGSI_OPCODE_IDIV:
3373 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3374 break;
3375
3376 case TGSI_OPCODE_IMAX:
3377 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3378 break;
3379
3380 case TGSI_OPCODE_IMIN:
3381 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3382 break;
3383
3384 case TGSI_OPCODE_INEG:
3385 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3386 break;
3387
3388 case TGSI_OPCODE_ISGE:
3389 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3390 break;
3391
3392 case TGSI_OPCODE_ISHR:
3393 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3394 break;
3395
3396 case TGSI_OPCODE_ISLT:
3397 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3398 break;
3399
3400 case TGSI_OPCODE_F2U:
3401 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3402 break;
3403
3404 case TGSI_OPCODE_U2F:
3405 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
3406 break;
3407
3408 case TGSI_OPCODE_UADD:
3409 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3410 break;
3411
3412 case TGSI_OPCODE_UDIV:
3413 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3414 break;
3415
3416 case TGSI_OPCODE_UMAD:
3417 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3418 break;
3419
3420 case TGSI_OPCODE_UMAX:
3421 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3422 break;
3423
3424 case TGSI_OPCODE_UMIN:
3425 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3426 break;
3427
3428 case TGSI_OPCODE_UMOD:
3429 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3430 break;
3431
3432 case TGSI_OPCODE_UMUL:
3433 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3434 break;
3435
3436 case TGSI_OPCODE_USEQ:
3437 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3438 break;
3439
3440 case TGSI_OPCODE_USGE:
3441 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3442 break;
3443
3444 case TGSI_OPCODE_USHR:
3445 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3446 break;
3447
3448 case TGSI_OPCODE_USLT:
3449 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3450 break;
3451
3452 case TGSI_OPCODE_USNE:
3453 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3454 break;
3455
3456 case TGSI_OPCODE_SWITCH:
3457 exec_switch(mach, inst);
3458 break;
3459
3460 case TGSI_OPCODE_CASE:
3461 exec_case(mach, inst);
3462 break;
3463
3464 case TGSI_OPCODE_DEFAULT:
3465 exec_default(mach);
3466 break;
3467
3468 case TGSI_OPCODE_ENDSWITCH:
3469 exec_endswitch(mach);
3470 break;
3471
3472 default:
3473 assert( 0 );
3474 }
3475 }
3476
3477
3478 #define DEBUG_EXECUTION 0
3479
3480
3481 /**
3482 * Run TGSI interpreter.
3483 * \return bitmask of "alive" quad components
3484 */
3485 uint
3486 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3487 {
3488 uint i;
3489 int pc = 0;
3490
3491 mach->CondMask = 0xf;
3492 mach->LoopMask = 0xf;
3493 mach->ContMask = 0xf;
3494 mach->FuncMask = 0xf;
3495 mach->ExecMask = 0xf;
3496
3497 mach->Switch.mask = 0xf;
3498
3499 assert(mach->CondStackTop == 0);
3500 assert(mach->LoopStackTop == 0);
3501 assert(mach->ContStackTop == 0);
3502 assert(mach->SwitchStackTop == 0);
3503 assert(mach->BreakStackTop == 0);
3504 assert(mach->CallStackTop == 0);
3505
3506 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3507 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3508
3509 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3510 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3511 mach->Primitives[0] = 0;
3512 }
3513
3514 for (i = 0; i < QUAD_SIZE; i++) {
3515 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
3516 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
3517 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
3518 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
3519 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
3520 }
3521
3522 /* execute declarations (interpolants) */
3523 for (i = 0; i < mach->NumDeclarations; i++) {
3524 exec_declaration( mach, mach->Declarations+i );
3525 }
3526
3527 {
3528 #if DEBUG_EXECUTION
3529 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
3530 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
3531 uint inst = 1;
3532
3533 memcpy(temps, mach->Temps, sizeof(temps));
3534 memcpy(outputs, mach->Outputs, sizeof(outputs));
3535 #endif
3536
3537 /* execute instructions, until pc is set to -1 */
3538 while (pc != -1) {
3539
3540 #if DEBUG_EXECUTION
3541 uint i;
3542
3543 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
3544 #endif
3545
3546 assert(pc < (int) mach->NumInstructions);
3547 exec_instruction(mach, mach->Instructions + pc, &pc);
3548
3549 #if DEBUG_EXECUTION
3550 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
3551 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
3552 uint j;
3553
3554 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
3555 debug_printf("TEMP[%2u] = ", i);
3556 for (j = 0; j < 4; j++) {
3557 if (j > 0) {
3558 debug_printf(" ");
3559 }
3560 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3561 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
3562 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
3563 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
3564 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
3565 }
3566 }
3567 }
3568 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
3569 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
3570 uint j;
3571
3572 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
3573 debug_printf("OUT[%2u] = ", i);
3574 for (j = 0; j < 4; j++) {
3575 if (j > 0) {
3576 debug_printf(" ");
3577 }
3578 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3579 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
3580 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
3581 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
3582 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
3583 }
3584 }
3585 }
3586 #endif
3587 }
3588 }
3589
3590 #if 0
3591 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3592 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3593 /*
3594 * Scale back depth component.
3595 */
3596 for (i = 0; i < 4; i++)
3597 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3598 }
3599 #endif
3600
3601 assert(mach->CondStackTop == 0);
3602 assert(mach->LoopStackTop == 0);
3603 assert(mach->ContStackTop == 0);
3604 assert(mach->SwitchStackTop == 0);
3605 assert(mach->BreakStackTop == 0);
3606 assert(mach->CallStackTop == 0);
3607
3608 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3609 }