1 /**************************************************************************
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
73 micro_abs(union tgsi_exec_channel
*dst
,
74 const union tgsi_exec_channel
*src
)
76 dst
->f
[0] = fabsf(src
->f
[0]);
77 dst
->f
[1] = fabsf(src
->f
[1]);
78 dst
->f
[2] = fabsf(src
->f
[2]);
79 dst
->f
[3] = fabsf(src
->f
[3]);
83 micro_arl(union tgsi_exec_channel
*dst
,
84 const union tgsi_exec_channel
*src
)
86 dst
->i
[0] = (int)floorf(src
->f
[0]);
87 dst
->i
[1] = (int)floorf(src
->f
[1]);
88 dst
->i
[2] = (int)floorf(src
->f
[2]);
89 dst
->i
[3] = (int)floorf(src
->f
[3]);
93 micro_arr(union tgsi_exec_channel
*dst
,
94 const union tgsi_exec_channel
*src
)
96 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
97 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
98 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
99 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
103 micro_ceil(union tgsi_exec_channel
*dst
,
104 const union tgsi_exec_channel
*src
)
106 dst
->f
[0] = ceilf(src
->f
[0]);
107 dst
->f
[1] = ceilf(src
->f
[1]);
108 dst
->f
[2] = ceilf(src
->f
[2]);
109 dst
->f
[3] = ceilf(src
->f
[3]);
113 micro_clamp(union tgsi_exec_channel
*dst
,
114 const union tgsi_exec_channel
*src0
,
115 const union tgsi_exec_channel
*src1
,
116 const union tgsi_exec_channel
*src2
)
118 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
119 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
120 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
121 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
125 micro_cmp(union tgsi_exec_channel
*dst
,
126 const union tgsi_exec_channel
*src0
,
127 const union tgsi_exec_channel
*src1
,
128 const union tgsi_exec_channel
*src2
)
130 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
131 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
132 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
133 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
137 micro_cnd(union tgsi_exec_channel
*dst
,
138 const union tgsi_exec_channel
*src0
,
139 const union tgsi_exec_channel
*src1
,
140 const union tgsi_exec_channel
*src2
)
142 dst
->f
[0] = src2
->f
[0] > 0.5f
? src0
->f
[0] : src1
->f
[0];
143 dst
->f
[1] = src2
->f
[1] > 0.5f
? src0
->f
[1] : src1
->f
[1];
144 dst
->f
[2] = src2
->f
[2] > 0.5f
? src0
->f
[2] : src1
->f
[2];
145 dst
->f
[3] = src2
->f
[3] > 0.5f
? src0
->f
[3] : src1
->f
[3];
149 micro_cos(union tgsi_exec_channel
*dst
,
150 const union tgsi_exec_channel
*src
)
152 dst
->f
[0] = cosf(src
->f
[0]);
153 dst
->f
[1] = cosf(src
->f
[1]);
154 dst
->f
[2] = cosf(src
->f
[2]);
155 dst
->f
[3] = cosf(src
->f
[3]);
159 micro_ddx(union tgsi_exec_channel
*dst
,
160 const union tgsi_exec_channel
*src
)
165 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
169 micro_ddy(union tgsi_exec_channel
*dst
,
170 const union tgsi_exec_channel
*src
)
175 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
179 micro_exp2(union tgsi_exec_channel
*dst
,
180 const union tgsi_exec_channel
*src
)
183 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
184 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
185 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
186 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
191 union tgsi_exec_channel clamped
;
193 for (i
= 0; i
< 4; i
++) {
194 if (src
->f
[i
] > 127.99999f
) {
195 clamped
.f
[i
] = 127.99999f
;
196 } else if (src
->f
[i
] < -126.99999f
) {
197 clamped
.f
[i
] = -126.99999f
;
199 clamped
.f
[i
] = src
->f
[i
];
205 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
206 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
207 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
208 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
209 #endif /* FAST_MATH */
213 micro_flr(union tgsi_exec_channel
*dst
,
214 const union tgsi_exec_channel
*src
)
216 dst
->f
[0] = floorf(src
->f
[0]);
217 dst
->f
[1] = floorf(src
->f
[1]);
218 dst
->f
[2] = floorf(src
->f
[2]);
219 dst
->f
[3] = floorf(src
->f
[3]);
223 micro_frc(union tgsi_exec_channel
*dst
,
224 const union tgsi_exec_channel
*src
)
226 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
227 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
228 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
229 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
233 micro_iabs(union tgsi_exec_channel
*dst
,
234 const union tgsi_exec_channel
*src
)
236 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
237 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
238 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
239 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
243 micro_ineg(union tgsi_exec_channel
*dst
,
244 const union tgsi_exec_channel
*src
)
246 dst
->i
[0] = -src
->i
[0];
247 dst
->i
[1] = -src
->i
[1];
248 dst
->i
[2] = -src
->i
[2];
249 dst
->i
[3] = -src
->i
[3];
253 micro_lg2(union tgsi_exec_channel
*dst
,
254 const union tgsi_exec_channel
*src
)
257 dst
->f
[0] = util_fast_log2(src
->f
[0]);
258 dst
->f
[1] = util_fast_log2(src
->f
[1]);
259 dst
->f
[2] = util_fast_log2(src
->f
[2]);
260 dst
->f
[3] = util_fast_log2(src
->f
[3]);
262 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
263 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
264 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
265 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
270 micro_lrp(union tgsi_exec_channel
*dst
,
271 const union tgsi_exec_channel
*src0
,
272 const union tgsi_exec_channel
*src1
,
273 const union tgsi_exec_channel
*src2
)
275 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
276 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
277 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
278 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
282 micro_mad(union tgsi_exec_channel
*dst
,
283 const union tgsi_exec_channel
*src0
,
284 const union tgsi_exec_channel
*src1
,
285 const union tgsi_exec_channel
*src2
)
287 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
288 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
289 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
290 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
294 micro_mov(union tgsi_exec_channel
*dst
,
295 const union tgsi_exec_channel
*src
)
297 dst
->u
[0] = src
->u
[0];
298 dst
->u
[1] = src
->u
[1];
299 dst
->u
[2] = src
->u
[2];
300 dst
->u
[3] = src
->u
[3];
304 micro_rcp(union tgsi_exec_channel
*dst
,
305 const union tgsi_exec_channel
*src
)
307 #if 0 /* for debugging */
308 assert(src
->f
[0] != 0.0f
);
309 assert(src
->f
[1] != 0.0f
);
310 assert(src
->f
[2] != 0.0f
);
311 assert(src
->f
[3] != 0.0f
);
313 dst
->f
[0] = 1.0f
/ src
->f
[0];
314 dst
->f
[1] = 1.0f
/ src
->f
[1];
315 dst
->f
[2] = 1.0f
/ src
->f
[2];
316 dst
->f
[3] = 1.0f
/ src
->f
[3];
320 micro_rnd(union tgsi_exec_channel
*dst
,
321 const union tgsi_exec_channel
*src
)
323 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
324 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
325 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
326 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
330 micro_rsq(union tgsi_exec_channel
*dst
,
331 const union tgsi_exec_channel
*src
)
333 #if 0 /* for debugging */
334 assert(src
->f
[0] != 0.0f
);
335 assert(src
->f
[1] != 0.0f
);
336 assert(src
->f
[2] != 0.0f
);
337 assert(src
->f
[3] != 0.0f
);
339 dst
->f
[0] = 1.0f
/ sqrtf(fabsf(src
->f
[0]));
340 dst
->f
[1] = 1.0f
/ sqrtf(fabsf(src
->f
[1]));
341 dst
->f
[2] = 1.0f
/ sqrtf(fabsf(src
->f
[2]));
342 dst
->f
[3] = 1.0f
/ sqrtf(fabsf(src
->f
[3]));
346 micro_seq(union tgsi_exec_channel
*dst
,
347 const union tgsi_exec_channel
*src0
,
348 const union tgsi_exec_channel
*src1
)
350 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
351 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
352 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
353 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
357 micro_sge(union tgsi_exec_channel
*dst
,
358 const union tgsi_exec_channel
*src0
,
359 const union tgsi_exec_channel
*src1
)
361 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
362 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
363 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
364 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
368 micro_sgn(union tgsi_exec_channel
*dst
,
369 const union tgsi_exec_channel
*src
)
371 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
372 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
373 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
374 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
378 micro_isgn(union tgsi_exec_channel
*dst
,
379 const union tgsi_exec_channel
*src
)
381 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
382 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
383 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
384 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
388 micro_sgt(union tgsi_exec_channel
*dst
,
389 const union tgsi_exec_channel
*src0
,
390 const union tgsi_exec_channel
*src1
)
392 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
393 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
394 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
395 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
399 micro_sin(union tgsi_exec_channel
*dst
,
400 const union tgsi_exec_channel
*src
)
402 dst
->f
[0] = sinf(src
->f
[0]);
403 dst
->f
[1] = sinf(src
->f
[1]);
404 dst
->f
[2] = sinf(src
->f
[2]);
405 dst
->f
[3] = sinf(src
->f
[3]);
409 micro_sle(union tgsi_exec_channel
*dst
,
410 const union tgsi_exec_channel
*src0
,
411 const union tgsi_exec_channel
*src1
)
413 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
414 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
415 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
416 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
420 micro_slt(union tgsi_exec_channel
*dst
,
421 const union tgsi_exec_channel
*src0
,
422 const union tgsi_exec_channel
*src1
)
424 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
425 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
426 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
427 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
431 micro_sne(union tgsi_exec_channel
*dst
,
432 const union tgsi_exec_channel
*src0
,
433 const union tgsi_exec_channel
*src1
)
435 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
436 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
437 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
438 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
442 micro_sfl(union tgsi_exec_channel
*dst
)
451 micro_str(union tgsi_exec_channel
*dst
)
460 micro_trunc(union tgsi_exec_channel
*dst
,
461 const union tgsi_exec_channel
*src
)
463 dst
->f
[0] = (float)(int)src
->f
[0];
464 dst
->f
[1] = (float)(int)src
->f
[1];
465 dst
->f
[2] = (float)(int)src
->f
[2];
466 dst
->f
[3] = (float)(int)src
->f
[3];
470 enum tgsi_exec_datatype
{
471 TGSI_EXEC_DATA_FLOAT
,
477 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
479 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
480 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
481 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
482 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
483 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
484 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
487 /** The execution mask depends on the conditional mask and the loop mask */
488 #define UPDATE_EXEC_MASK(MACH) \
489 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
492 static const union tgsi_exec_channel ZeroVec
=
493 { { 0.0, 0.0, 0.0, 0.0 } };
495 static const union tgsi_exec_channel OneVec
= {
496 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
499 static const union tgsi_exec_channel P128Vec
= {
500 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
503 static const union tgsi_exec_channel M128Vec
= {
504 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
509 * Assert that none of the float values in 'chan' are infinite or NaN.
510 * NaN and Inf may occur normally during program execution and should
511 * not lead to crashes, etc. But when debugging, it's helpful to catch
515 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
517 assert(!util_is_inf_or_nan((chan
)->f
[0]));
518 assert(!util_is_inf_or_nan((chan
)->f
[1]));
519 assert(!util_is_inf_or_nan((chan
)->f
[2]));
520 assert(!util_is_inf_or_nan((chan
)->f
[3]));
526 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
528 debug_printf("%s = {%f, %f, %f, %f}\n",
529 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
536 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
538 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
540 debug_printf("Temp[%u] =\n", index
);
541 for (i
= 0; i
< 4; i
++) {
542 debug_printf(" %c: { %f, %f, %f, %f }\n",
554 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
557 const unsigned *buf_sizes
)
561 for (i
= 0; i
< num_bufs
; i
++) {
562 mach
->Consts
[i
] = bufs
[i
];
563 mach
->ConstsSize
[i
] = buf_sizes
[i
];
569 * Check if there's a potential src/dst register data dependency when
570 * using SOA execution.
573 * This would expand into:
578 * The second instruction will have the wrong value for t0 if executed as-is.
581 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
585 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
586 if (writemask
== TGSI_WRITEMASK_X
||
587 writemask
== TGSI_WRITEMASK_Y
||
588 writemask
== TGSI_WRITEMASK_Z
||
589 writemask
== TGSI_WRITEMASK_W
||
590 writemask
== TGSI_WRITEMASK_NONE
) {
591 /* no chance of data dependency */
595 /* loop over src regs */
596 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
597 if ((inst
->Src
[i
].Register
.File
==
598 inst
->Dst
[0].Register
.File
) &&
599 ((inst
->Src
[i
].Register
.Index
==
600 inst
->Dst
[0].Register
.Index
) ||
601 inst
->Src
[i
].Register
.Indirect
||
602 inst
->Dst
[0].Register
.Indirect
)) {
603 /* loop over dest channels */
604 uint channelsWritten
= 0x0;
605 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
606 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
607 /* check if we're reading a channel that's been written */
608 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
609 if (channelsWritten
& (1 << swizzle
)) {
613 channelsWritten
|= (1 << chan
);
623 * Initialize machine state by expanding tokens to full instructions,
624 * allocating temporary storage, setting up constants, etc.
625 * After this, we can call tgsi_exec_machine_run() many times.
628 tgsi_exec_machine_bind_shader(
629 struct tgsi_exec_machine
*mach
,
630 const struct tgsi_token
*tokens
,
632 struct tgsi_sampler
**samplers
)
635 struct tgsi_parse_context parse
;
636 struct tgsi_full_instruction
*instructions
;
637 struct tgsi_full_declaration
*declarations
;
638 uint maxInstructions
= 10, numInstructions
= 0;
639 uint maxDeclarations
= 10, numDeclarations
= 0;
642 tgsi_dump(tokens
, 0);
651 mach
->Tokens
= tokens
;
652 mach
->Samplers
= samplers
;
655 /* unbind and free all */
656 FREE(mach
->Declarations
);
657 mach
->Declarations
= NULL
;
658 mach
->NumDeclarations
= 0;
660 FREE(mach
->Instructions
);
661 mach
->Instructions
= NULL
;
662 mach
->NumInstructions
= 0;
667 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
668 if (k
!= TGSI_PARSE_OK
) {
669 debug_printf( "Problem parsing!\n" );
673 mach
->Processor
= parse
.FullHeader
.Processor
.Processor
;
676 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
&&
677 !mach
->UsedGeometryShader
) {
678 struct tgsi_exec_vector
*inputs
;
679 struct tgsi_exec_vector
*outputs
;
681 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
682 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
,
688 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
689 TGSI_MAX_TOTAL_VERTICES
, 16);
696 align_free(mach
->Inputs
);
697 align_free(mach
->Outputs
);
699 mach
->Inputs
= inputs
;
700 mach
->Outputs
= outputs
;
701 mach
->UsedGeometryShader
= TRUE
;
704 declarations
= (struct tgsi_full_declaration
*)
705 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
711 instructions
= (struct tgsi_full_instruction
*)
712 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
715 FREE( declarations
);
719 while( !tgsi_parse_end_of_tokens( &parse
) ) {
722 tgsi_parse_token( &parse
);
723 switch( parse
.FullToken
.Token
.Type
) {
724 case TGSI_TOKEN_TYPE_DECLARATION
:
725 /* save expanded declaration */
726 if (numDeclarations
== maxDeclarations
) {
727 declarations
= REALLOC(declarations
,
729 * sizeof(struct tgsi_full_declaration
),
730 (maxDeclarations
+ 10)
731 * sizeof(struct tgsi_full_declaration
));
732 maxDeclarations
+= 10;
734 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
736 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
737 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
742 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
==
743 TGSI_FILE_IMMEDIATE_ARRAY
) {
745 struct tgsi_full_declaration
*decl
=
746 &parse
.FullToken
.FullDeclaration
;
747 debug_assert(decl
->Range
.Last
< TGSI_EXEC_NUM_IMMEDIATES
);
748 for (reg
= decl
->Range
.First
; reg
<= decl
->Range
.Last
; ++reg
) {
749 for( i
= 0; i
< 4; i
++ ) {
750 int idx
= reg
* 4 + i
;
751 mach
->ImmArray
[reg
][i
] = decl
->ImmediateData
.u
[idx
].Float
;
755 memcpy(declarations
+ numDeclarations
,
756 &parse
.FullToken
.FullDeclaration
,
757 sizeof(declarations
[0]));
761 case TGSI_TOKEN_TYPE_IMMEDIATE
:
763 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
765 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
767 for( i
= 0; i
< size
; i
++ ) {
768 mach
->Imms
[mach
->ImmLimit
][i
] =
769 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
775 case TGSI_TOKEN_TYPE_INSTRUCTION
:
777 /* save expanded instruction */
778 if (numInstructions
== maxInstructions
) {
779 instructions
= REALLOC(instructions
,
781 * sizeof(struct tgsi_full_instruction
),
782 (maxInstructions
+ 10)
783 * sizeof(struct tgsi_full_instruction
));
784 maxInstructions
+= 10;
787 memcpy(instructions
+ numInstructions
,
788 &parse
.FullToken
.FullInstruction
,
789 sizeof(instructions
[0]));
794 case TGSI_TOKEN_TYPE_PROPERTY
:
801 tgsi_parse_free (&parse
);
803 FREE(mach
->Declarations
);
804 mach
->Declarations
= declarations
;
805 mach
->NumDeclarations
= numDeclarations
;
807 FREE(mach
->Instructions
);
808 mach
->Instructions
= instructions
;
809 mach
->NumInstructions
= numInstructions
;
813 struct tgsi_exec_machine
*
814 tgsi_exec_machine_create( void )
816 struct tgsi_exec_machine
*mach
;
819 mach
= align_malloc( sizeof *mach
, 16 );
823 memset(mach
, 0, sizeof(*mach
));
825 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
826 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
827 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
829 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_ATTRIBS
, 16);
830 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_ATTRIBS
, 16);
831 if (!mach
->Inputs
|| !mach
->Outputs
)
834 /* Setup constants needed by the SSE2 executor. */
835 for( i
= 0; i
< 4; i
++ ) {
836 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
837 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
838 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
839 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
840 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
841 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
842 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
843 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
844 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
845 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
849 /* silence warnings */
858 align_free(mach
->Inputs
);
859 align_free(mach
->Outputs
);
867 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
870 FREE(mach
->Instructions
);
871 FREE(mach
->Declarations
);
873 align_free(mach
->Inputs
);
874 align_free(mach
->Outputs
);
881 micro_add(union tgsi_exec_channel
*dst
,
882 const union tgsi_exec_channel
*src0
,
883 const union tgsi_exec_channel
*src1
)
885 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
886 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
887 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
888 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
893 union tgsi_exec_channel
*dst
,
894 const union tgsi_exec_channel
*src0
,
895 const union tgsi_exec_channel
*src1
)
897 if (src1
->f
[0] != 0) {
898 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
900 if (src1
->f
[1] != 0) {
901 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
903 if (src1
->f
[2] != 0) {
904 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
906 if (src1
->f
[3] != 0) {
907 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
912 micro_rcc(union tgsi_exec_channel
*dst
,
913 const union tgsi_exec_channel
*src
)
917 for (i
= 0; i
< 4; i
++) {
918 float recip
= 1.0f
/ src
->f
[i
];
921 if (recip
> 1.884467e+019f
) {
922 dst
->f
[i
] = 1.884467e+019f
;
924 else if (recip
< 5.42101e-020f
) {
925 dst
->f
[i
] = 5.42101e-020f
;
932 if (recip
< -1.884467e+019f
) {
933 dst
->f
[i
] = -1.884467e+019f
;
935 else if (recip
> -5.42101e-020f
) {
936 dst
->f
[i
] = -5.42101e-020f
;
947 union tgsi_exec_channel
*dst
,
948 const union tgsi_exec_channel
*src0
,
949 const union tgsi_exec_channel
*src1
,
950 const union tgsi_exec_channel
*src2
,
951 const union tgsi_exec_channel
*src3
)
953 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
954 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
955 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
956 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
960 micro_max(union tgsi_exec_channel
*dst
,
961 const union tgsi_exec_channel
*src0
,
962 const union tgsi_exec_channel
*src1
)
964 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
965 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
966 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
967 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
971 micro_min(union tgsi_exec_channel
*dst
,
972 const union tgsi_exec_channel
*src0
,
973 const union tgsi_exec_channel
*src1
)
975 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
976 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
977 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
978 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
982 micro_mul(union tgsi_exec_channel
*dst
,
983 const union tgsi_exec_channel
*src0
,
984 const union tgsi_exec_channel
*src1
)
986 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
987 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
988 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
989 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
994 union tgsi_exec_channel
*dst
,
995 const union tgsi_exec_channel
*src
)
997 dst
->f
[0] = -src
->f
[0];
998 dst
->f
[1] = -src
->f
[1];
999 dst
->f
[2] = -src
->f
[2];
1000 dst
->f
[3] = -src
->f
[3];
1005 union tgsi_exec_channel
*dst
,
1006 const union tgsi_exec_channel
*src0
,
1007 const union tgsi_exec_channel
*src1
)
1010 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1011 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1012 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1013 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1015 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1016 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1017 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1018 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1023 micro_sub(union tgsi_exec_channel
*dst
,
1024 const union tgsi_exec_channel
*src0
,
1025 const union tgsi_exec_channel
*src1
)
1027 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1028 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1029 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1030 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1034 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1035 const uint chan_index
,
1038 const union tgsi_exec_channel
*index
,
1039 const union tgsi_exec_channel
*index2D
,
1040 union tgsi_exec_channel
*chan
)
1044 assert(swizzle
< 4);
1047 case TGSI_FILE_CONSTANT
:
1048 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1049 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1050 assert(mach
->Consts
[index2D
->i
[i
]]);
1052 if (index
->i
[i
] < 0) {
1055 /* NOTE: copying the const value as a uint instead of float */
1056 const uint constbuf
= index2D
->i
[i
];
1057 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1058 const int pos
= index
->i
[i
] * 4 + swizzle
;
1059 /* const buffer bounds check */
1060 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1062 /* Debug: print warning */
1063 static int count
= 0;
1065 debug_printf("TGSI Exec: const buffer index %d"
1066 " out of bounds\n", pos
);
1071 chan
->u
[i
] = buf
[pos
];
1076 case TGSI_FILE_INPUT
:
1077 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1079 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1080 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1081 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1082 index2D->i[i], index->i[i]);
1084 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1086 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1087 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1091 case TGSI_FILE_SYSTEM_VALUE
:
1092 /* XXX no swizzling at this point. Will be needed if we put
1093 * gl_FragCoord, for example, in a sys value register.
1095 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1096 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].u
[i
];
1100 case TGSI_FILE_TEMPORARY
:
1101 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1102 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1103 assert(index2D
->i
[i
] == 0);
1105 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1109 case TGSI_FILE_TEMPORARY_ARRAY
:
1110 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1111 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1112 assert(index2D
->i
[i
] < TGSI_EXEC_NUM_TEMP_ARRAYS
);
1115 mach
->TempArray
[index2D
->i
[i
]][index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1119 case TGSI_FILE_IMMEDIATE
:
1120 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1121 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1122 assert(index2D
->i
[i
] == 0);
1124 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1128 case TGSI_FILE_IMMEDIATE_ARRAY
:
1129 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1130 assert(index2D
->i
[i
] == 0);
1132 chan
->f
[i
] = mach
->ImmArray
[index
->i
[i
]][swizzle
];
1136 case TGSI_FILE_ADDRESS
:
1137 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1138 assert(index
->i
[i
] >= 0);
1139 assert(index2D
->i
[i
] == 0);
1141 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1145 case TGSI_FILE_PREDICATE
:
1146 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1147 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1148 assert(index2D
->i
[i
] == 0);
1150 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1154 case TGSI_FILE_OUTPUT
:
1155 /* vertex/fragment output vars can be read too */
1156 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1157 assert(index
->i
[i
] >= 0);
1158 assert(index2D
->i
[i
] == 0);
1160 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1166 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1173 fetch_source(const struct tgsi_exec_machine
*mach
,
1174 union tgsi_exec_channel
*chan
,
1175 const struct tgsi_full_src_register
*reg
,
1176 const uint chan_index
,
1177 enum tgsi_exec_datatype src_datatype
)
1179 union tgsi_exec_channel index
;
1180 union tgsi_exec_channel index2D
;
1183 /* We start with a direct index into a register file.
1187 * file = Register.File
1188 * [1] = Register.Index
1193 index
.i
[3] = reg
->Register
.Index
;
1195 /* There is an extra source register that indirectly subscripts
1196 * a register file. The direct index now becomes an offset
1197 * that is being added to the indirect register.
1201 * ind = Indirect.File
1202 * [2] = Indirect.Index
1203 * .x = Indirect.SwizzleX
1205 if (reg
->Register
.Indirect
) {
1206 union tgsi_exec_channel index2
;
1207 union tgsi_exec_channel indir_index
;
1208 const uint execmask
= mach
->ExecMask
;
1211 /* which address register (always zero now) */
1215 index2
.i
[3] = reg
->Indirect
.Index
;
1216 assert(reg
->Indirect
.File
== TGSI_FILE_ADDRESS
);
1217 /* get current value of address register[swizzle] */
1218 swizzle
= tgsi_util_get_src_register_swizzle( ®
->Indirect
, TGSI_CHAN_X
);
1219 fetch_src_file_channel(mach
,
1227 /* add value of address register to the offset */
1228 index
.i
[0] += indir_index
.i
[0];
1229 index
.i
[1] += indir_index
.i
[1];
1230 index
.i
[2] += indir_index
.i
[2];
1231 index
.i
[3] += indir_index
.i
[3];
1233 /* for disabled execution channels, zero-out the index to
1234 * avoid using a potential garbage value.
1236 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1237 if ((execmask
& (1 << i
)) == 0)
1242 /* There is an extra source register that is a second
1243 * subscript to a register file. Effectively it means that
1244 * the register file is actually a 2D array of registers.
1248 * [3] = Dimension.Index
1250 if (reg
->Register
.Dimension
) {
1254 index2D
.i
[3] = reg
->Dimension
.Index
;
1256 /* Again, the second subscript index can be addressed indirectly
1257 * identically to the first one.
1258 * Nothing stops us from indirectly addressing the indirect register,
1259 * but there is no need for that, so we won't exercise it.
1261 * file[ind[4].y+3][1],
1263 * ind = DimIndirect.File
1264 * [4] = DimIndirect.Index
1265 * .y = DimIndirect.SwizzleX
1267 if (reg
->Dimension
.Indirect
) {
1268 union tgsi_exec_channel index2
;
1269 union tgsi_exec_channel indir_index
;
1270 const uint execmask
= mach
->ExecMask
;
1276 index2
.i
[3] = reg
->DimIndirect
.Index
;
1278 swizzle
= tgsi_util_get_src_register_swizzle( ®
->DimIndirect
, TGSI_CHAN_X
);
1279 fetch_src_file_channel(mach
,
1281 reg
->DimIndirect
.File
,
1287 index2D
.i
[0] += indir_index
.i
[0];
1288 index2D
.i
[1] += indir_index
.i
[1];
1289 index2D
.i
[2] += indir_index
.i
[2];
1290 index2D
.i
[3] += indir_index
.i
[3];
1292 /* for disabled execution channels, zero-out the index to
1293 * avoid using a potential garbage value.
1295 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1296 if ((execmask
& (1 << i
)) == 0) {
1302 /* If by any chance there was a need for a 3D array of register
1303 * files, we would have to check whether Dimension is followed
1304 * by a dimension register and continue the saga.
1313 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1314 fetch_src_file_channel(mach
,
1322 if (reg
->Register
.Absolute
) {
1323 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1324 micro_abs(chan
, chan
);
1326 micro_iabs(chan
, chan
);
1330 if (reg
->Register
.Negate
) {
1331 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1332 micro_neg(chan
, chan
);
1334 micro_ineg(chan
, chan
);
1340 store_dest(struct tgsi_exec_machine
*mach
,
1341 const union tgsi_exec_channel
*chan
,
1342 const struct tgsi_full_dst_register
*reg
,
1343 const struct tgsi_full_instruction
*inst
,
1345 enum tgsi_exec_datatype dst_datatype
)
1348 union tgsi_exec_channel null
;
1349 union tgsi_exec_channel
*dst
;
1350 union tgsi_exec_channel index2D
;
1351 uint execmask
= mach
->ExecMask
;
1352 int offset
= 0; /* indirection offset */
1356 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1357 check_inf_or_nan(chan
);
1360 /* There is an extra source register that indirectly subscripts
1361 * a register file. The direct index now becomes an offset
1362 * that is being added to the indirect register.
1366 * ind = Indirect.File
1367 * [2] = Indirect.Index
1368 * .x = Indirect.SwizzleX
1370 if (reg
->Register
.Indirect
) {
1371 union tgsi_exec_channel index
;
1372 union tgsi_exec_channel indir_index
;
1375 /* which address register (always zero for now) */
1379 index
.i
[3] = reg
->Indirect
.Index
;
1381 /* get current value of address register[swizzle] */
1382 swizzle
= tgsi_util_get_src_register_swizzle( ®
->Indirect
, TGSI_CHAN_X
);
1384 /* fetch values from the address/indirection register */
1385 fetch_src_file_channel(mach
,
1393 /* save indirection offset */
1394 offset
= indir_index
.i
[0];
1397 /* There is an extra source register that is a second
1398 * subscript to a register file. Effectively it means that
1399 * the register file is actually a 2D array of registers.
1403 * [3] = Dimension.Index
1405 if (reg
->Register
.Dimension
) {
1409 index2D
.i
[3] = reg
->Dimension
.Index
;
1411 /* Again, the second subscript index can be addressed indirectly
1412 * identically to the first one.
1413 * Nothing stops us from indirectly addressing the indirect register,
1414 * but there is no need for that, so we won't exercise it.
1416 * file[ind[4].y+3][1],
1418 * ind = DimIndirect.File
1419 * [4] = DimIndirect.Index
1420 * .y = DimIndirect.SwizzleX
1422 if (reg
->Dimension
.Indirect
) {
1423 union tgsi_exec_channel index2
;
1424 union tgsi_exec_channel indir_index
;
1425 const uint execmask
= mach
->ExecMask
;
1432 index2
.i
[3] = reg
->DimIndirect
.Index
;
1434 swizzle
= tgsi_util_get_src_register_swizzle( ®
->DimIndirect
, TGSI_CHAN_X
);
1435 fetch_src_file_channel(mach
,
1437 reg
->DimIndirect
.File
,
1443 index2D
.i
[0] += indir_index
.i
[0];
1444 index2D
.i
[1] += indir_index
.i
[1];
1445 index2D
.i
[2] += indir_index
.i
[2];
1446 index2D
.i
[3] += indir_index
.i
[3];
1448 /* for disabled execution channels, zero-out the index to
1449 * avoid using a potential garbage value.
1451 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1452 if ((execmask
& (1 << i
)) == 0) {
1458 /* If by any chance there was a need for a 3D array of register
1459 * files, we would have to check whether Dimension is followed
1460 * by a dimension register and continue the saga.
1469 switch (reg
->Register
.File
) {
1470 case TGSI_FILE_NULL
:
1474 case TGSI_FILE_OUTPUT
:
1475 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1476 + reg
->Register
.Index
;
1477 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1479 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1480 fprintf(stderr
, "STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1481 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1482 if (execmask
& (1 << i
))
1483 fprintf(stderr
, "%f, ", chan
->f
[i
]);
1484 fprintf(stderr
, ")\n");
1489 case TGSI_FILE_TEMPORARY
:
1490 index
= reg
->Register
.Index
;
1491 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1492 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1495 case TGSI_FILE_TEMPORARY_ARRAY
:
1496 index
= reg
->Register
.Index
;
1497 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1498 assert( index2D
.i
[0] < TGSI_EXEC_NUM_TEMP_ARRAYS
);
1499 /* XXX we use index2D.i[0] here but somehow we might
1500 * end up with someone trying to store indirectly in
1501 * different buffers */
1502 dst
= &mach
->TempArray
[index2D
.i
[0]][offset
+ index
].xyzw
[chan_index
];
1505 case TGSI_FILE_ADDRESS
:
1506 index
= reg
->Register
.Index
;
1507 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1510 case TGSI_FILE_PREDICATE
:
1511 index
= reg
->Register
.Index
;
1512 assert(index
< TGSI_EXEC_NUM_PREDS
);
1513 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1521 if (inst
->Instruction
.Predicate
) {
1523 union tgsi_exec_channel
*pred
;
1525 switch (chan_index
) {
1527 swizzle
= inst
->Predicate
.SwizzleX
;
1530 swizzle
= inst
->Predicate
.SwizzleY
;
1533 swizzle
= inst
->Predicate
.SwizzleZ
;
1536 swizzle
= inst
->Predicate
.SwizzleW
;
1543 assert(inst
->Predicate
.Index
== 0);
1545 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1547 if (inst
->Predicate
.Negate
) {
1548 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1550 execmask
&= ~(1 << i
);
1554 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1556 execmask
&= ~(1 << i
);
1562 switch (inst
->Instruction
.Saturate
) {
1564 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1565 if (execmask
& (1 << i
))
1566 dst
->i
[i
] = chan
->i
[i
];
1569 case TGSI_SAT_ZERO_ONE
:
1570 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1571 if (execmask
& (1 << i
)) {
1572 if (chan
->f
[i
] < 0.0f
)
1574 else if (chan
->f
[i
] > 1.0f
)
1577 dst
->i
[i
] = chan
->i
[i
];
1581 case TGSI_SAT_MINUS_PLUS_ONE
:
1582 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1583 if (execmask
& (1 << i
)) {
1584 if (chan
->f
[i
] < -1.0f
)
1586 else if (chan
->f
[i
] > 1.0f
)
1589 dst
->i
[i
] = chan
->i
[i
];
1598 #define FETCH(VAL,INDEX,CHAN)\
1599 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1601 #define IFETCH(VAL,INDEX,CHAN)\
1602 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1606 * Execute ARB-style KIL which is predicated by a src register.
1607 * Kill fragment if any of the four values is less than zero.
1610 exec_kil(struct tgsi_exec_machine
*mach
,
1611 const struct tgsi_full_instruction
*inst
)
1615 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1616 union tgsi_exec_channel r
[1];
1618 /* This mask stores component bits that were already tested. */
1621 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1626 /* unswizzle channel */
1627 swizzle
= tgsi_util_get_full_src_register_swizzle (
1631 /* check if the component has not been already tested */
1632 if (uniquemask
& (1 << swizzle
))
1634 uniquemask
|= 1 << swizzle
;
1636 FETCH(&r
[0], 0, chan_index
);
1637 for (i
= 0; i
< 4; i
++)
1638 if (r
[0].f
[i
] < 0.0f
)
1642 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1646 * Execute NVIDIA-style KIL which is predicated by a condition code.
1647 * Kill fragment if the condition code is TRUE.
1650 exec_kilp(struct tgsi_exec_machine
*mach
,
1651 const struct tgsi_full_instruction
*inst
)
1653 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1655 /* "unconditional" kil */
1656 kilmask
= mach
->ExecMask
;
1657 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1661 emit_vertex(struct tgsi_exec_machine
*mach
)
1663 /* FIXME: check for exec mask correctly
1665 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1666 if ((mach->ExecMask & (1 << i)))
1668 if (mach
->ExecMask
) {
1669 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1670 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1675 emit_primitive(struct tgsi_exec_machine
*mach
)
1677 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1678 /* FIXME: check for exec mask correctly
1680 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1681 if ((mach->ExecMask & (1 << i)))
1683 if (mach
->ExecMask
) {
1685 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1686 mach
->Primitives
[*prim_count
] = 0;
1691 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1693 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1695 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1696 if (emitted_verts
) {
1697 emit_primitive(mach
);
1704 * Fetch four texture samples using STR texture coordinates.
1707 fetch_texel( struct tgsi_sampler
*sampler
,
1708 const union tgsi_exec_channel
*s
,
1709 const union tgsi_exec_channel
*t
,
1710 const union tgsi_exec_channel
*p
,
1711 const union tgsi_exec_channel
*c0
,
1712 const union tgsi_exec_channel
*c1
,
1713 enum tgsi_sampler_control control
,
1714 union tgsi_exec_channel
*r
,
1715 union tgsi_exec_channel
*g
,
1716 union tgsi_exec_channel
*b
,
1717 union tgsi_exec_channel
*a
)
1720 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1722 sampler
->get_samples(sampler
, s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, control
, rgba
);
1724 for (j
= 0; j
< 4; j
++) {
1725 r
->f
[j
] = rgba
[0][j
];
1726 g
->f
[j
] = rgba
[1][j
];
1727 b
->f
[j
] = rgba
[2][j
];
1728 a
->f
[j
] = rgba
[3][j
];
1733 #define TEX_MODIFIER_NONE 0
1734 #define TEX_MODIFIER_PROJECTED 1
1735 #define TEX_MODIFIER_LOD_BIAS 2
1736 #define TEX_MODIFIER_EXPLICIT_LOD 3
1739 * execute a texture instruction.
1741 * modifier is used to control the channel routing for the\
1742 * instruction variants like proj, lod, and texture with lod bias.
1743 * sampler indicates which src register the sampler is contained in.
1746 exec_tex(struct tgsi_exec_machine
*mach
,
1747 const struct tgsi_full_instruction
*inst
,
1748 uint modifier
, uint sampler
)
1750 const uint unit
= inst
->Src
[sampler
].Register
.Index
;
1751 union tgsi_exec_channel r
[4], cubearraycomp
, cubelod
;
1752 const union tgsi_exec_channel
*lod
= &ZeroVec
;
1753 enum tgsi_sampler_control control
;
1756 if (modifier
!= TEX_MODIFIER_NONE
&& (sampler
== 1)) {
1757 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1758 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
1763 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
1764 control
= tgsi_sampler_lod_explicit
;
1766 control
= tgsi_sampler_lod_bias
;
1769 switch (inst
->Texture
.Texture
) {
1770 case TGSI_TEXTURE_1D
:
1771 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1773 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1774 micro_div(&r
[0], &r
[0], &r
[3]);
1777 fetch_texel(mach
->Samplers
[unit
],
1778 &r
[0], &ZeroVec
, &ZeroVec
, lod
, &ZeroVec
, /* S, T, P, LOD */
1780 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1782 case TGSI_TEXTURE_SHADOW1D
:
1783 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1784 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1786 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1787 micro_div(&r
[0], &r
[0], &r
[3]);
1790 fetch_texel(mach
->Samplers
[unit
],
1791 &r
[0], &ZeroVec
, &r
[2], lod
, &ZeroVec
, /* S, T, P, LOD */
1793 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1796 case TGSI_TEXTURE_2D
:
1797 case TGSI_TEXTURE_RECT
:
1798 case TGSI_TEXTURE_SHADOW2D
:
1799 case TGSI_TEXTURE_SHADOWRECT
:
1800 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1801 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1802 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1804 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1805 micro_div(&r
[0], &r
[0], &r
[3]);
1806 micro_div(&r
[1], &r
[1], &r
[3]);
1807 micro_div(&r
[2], &r
[2], &r
[3]);
1810 fetch_texel(mach
->Samplers
[unit
],
1811 &r
[0], &r
[1], &r
[2], lod
, &ZeroVec
, /* S, T, P, LOD */
1813 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1816 case TGSI_TEXTURE_1D_ARRAY
:
1817 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1818 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1820 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1821 micro_div(&r
[0], &r
[0], &r
[3]);
1824 fetch_texel(mach
->Samplers
[unit
],
1825 &r
[0], &r
[1], &ZeroVec
, lod
, &ZeroVec
, /* S, T, P, LOD */
1827 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1829 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1830 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1831 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1832 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1834 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1835 micro_div(&r
[0], &r
[0], &r
[3]);
1838 fetch_texel(mach
->Samplers
[unit
],
1839 &r
[0], &r
[1], &r
[2], lod
, &ZeroVec
, /* S, T, P, LOD */
1841 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1844 case TGSI_TEXTURE_2D_ARRAY
:
1845 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1846 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1847 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1849 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1850 micro_div(&r
[0], &r
[0], &r
[3]);
1851 micro_div(&r
[1], &r
[1], &r
[3]);
1854 fetch_texel(mach
->Samplers
[unit
],
1855 &r
[0], &r
[1], &r
[2], lod
, &ZeroVec
, /* S, T, P, LOD */
1857 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1859 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1860 case TGSI_TEXTURE_SHADOWCUBE
:
1861 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1862 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1863 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1864 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1866 fetch_texel(mach
->Samplers
[unit
],
1867 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* S, T, P, LOD */
1869 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1871 case TGSI_TEXTURE_CUBE_ARRAY
:
1872 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1873 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1874 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1875 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1877 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
||
1878 modifier
== TEX_MODIFIER_LOD_BIAS
)
1879 FETCH(&cubelod
, 1, TGSI_CHAN_X
);
1883 fetch_texel(mach
->Samplers
[unit
],
1884 &r
[0], &r
[1], &r
[2], &r
[3], &cubelod
, /* S, T, P, LOD */
1886 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1888 case TGSI_TEXTURE_3D
:
1889 case TGSI_TEXTURE_CUBE
:
1890 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1891 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1892 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1894 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1895 micro_div(&r
[0], &r
[0], &r
[3]);
1896 micro_div(&r
[1], &r
[1], &r
[3]);
1897 micro_div(&r
[2], &r
[2], &r
[3]);
1900 fetch_texel(mach
->Samplers
[unit
],
1901 &r
[0], &r
[1], &r
[2], lod
, &ZeroVec
,
1903 &r
[0], &r
[1], &r
[2], &r
[3]);
1906 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1907 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1908 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1909 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1910 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1912 FETCH(&cubearraycomp
, 1, TGSI_CHAN_X
);
1914 fetch_texel(mach
->Samplers
[unit
],
1915 &r
[0], &r
[1], &r
[2], &r
[3], &cubearraycomp
, /* S, T, P, LOD */
1917 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1924 debug_printf("fetch r: %g %g %g %g\n",
1925 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
1926 debug_printf("fetch g: %g %g %g %g\n",
1927 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
1928 debug_printf("fetch b: %g %g %g %g\n",
1929 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
1930 debug_printf("fetch a: %g %g %g %g\n",
1931 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
1934 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1935 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1936 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1942 exec_txd(struct tgsi_exec_machine
*mach
,
1943 const struct tgsi_full_instruction
*inst
)
1945 const uint unit
= inst
->Src
[3].Register
.Index
;
1946 union tgsi_exec_channel r
[4];
1950 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1953 switch (inst
->Texture
.Texture
) {
1954 case TGSI_TEXTURE_1D
:
1955 case TGSI_TEXTURE_SHADOW1D
:
1957 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1959 fetch_texel(mach
->Samplers
[unit
],
1960 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, BIAS */
1961 tgsi_sampler_lod_bias
,
1962 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1965 case TGSI_TEXTURE_1D_ARRAY
:
1966 case TGSI_TEXTURE_2D
:
1967 case TGSI_TEXTURE_RECT
:
1968 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1969 case TGSI_TEXTURE_SHADOW2D
:
1970 case TGSI_TEXTURE_SHADOWRECT
:
1972 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1973 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1974 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1976 fetch_texel(mach
->Samplers
[unit
],
1977 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
1978 tgsi_sampler_lod_bias
,
1979 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1982 case TGSI_TEXTURE_2D_ARRAY
:
1983 case TGSI_TEXTURE_3D
:
1984 case TGSI_TEXTURE_CUBE
:
1985 case TGSI_TEXTURE_CUBE_ARRAY
:
1986 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1987 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1988 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1990 fetch_texel(mach
->Samplers
[unit
],
1991 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
,
1992 tgsi_sampler_lod_bias
,
1993 &r
[0], &r
[1], &r
[2], &r
[3]);
1996 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1998 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1999 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2000 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2001 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2003 fetch_texel(mach
->Samplers
[unit
],
2004 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2005 tgsi_sampler_lod_bias
,
2006 &r
[0], &r
[1], &r
[2], &r
[3]);
2013 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2014 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2015 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2022 exec_txf(struct tgsi_exec_machine
*mach
,
2023 const struct tgsi_full_instruction
*inst
)
2025 struct tgsi_sampler
*sampler
;
2026 const uint unit
= inst
->Src
[2].Register
.Index
;
2027 union tgsi_exec_channel r
[4];
2028 union tgsi_exec_channel offset
[3];
2030 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2034 if (inst
->Texture
.NumOffsets
== 1) {
2035 union tgsi_exec_channel index
;
2036 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2037 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2038 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2039 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2040 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2041 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2042 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2043 offsets
[0] = offset
[0].i
[0];
2044 offsets
[1] = offset
[1].i
[0];
2045 offsets
[2] = offset
[2].i
[0];
2047 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2049 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2051 switch(inst
->Texture
.Texture
) {
2052 case TGSI_TEXTURE_3D
:
2053 case TGSI_TEXTURE_2D_ARRAY
:
2054 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2055 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2057 case TGSI_TEXTURE_2D
:
2058 case TGSI_TEXTURE_RECT
:
2059 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2060 case TGSI_TEXTURE_SHADOW2D
:
2061 case TGSI_TEXTURE_SHADOWRECT
:
2062 case TGSI_TEXTURE_1D_ARRAY
:
2063 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2065 case TGSI_TEXTURE_1D
:
2066 case TGSI_TEXTURE_SHADOW1D
:
2067 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2074 sampler
= mach
->Samplers
[unit
];
2075 sampler
->get_texel(sampler
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2078 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2079 r
[0].f
[j
] = rgba
[0][j
];
2080 r
[1].f
[j
] = rgba
[1][j
];
2081 r
[2].f
[j
] = rgba
[2][j
];
2082 r
[3].f
[j
] = rgba
[3][j
];
2085 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2086 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2087 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2093 exec_txq(struct tgsi_exec_machine
*mach
,
2094 const struct tgsi_full_instruction
*inst
)
2096 struct tgsi_sampler
*sampler
;
2097 const uint unit
= inst
->Src
[1].Register
.Index
;
2099 union tgsi_exec_channel r
[4], src
;
2103 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2104 sampler
= mach
->Samplers
[unit
];
2106 sampler
->get_dims(sampler
, src
.i
[0], result
);
2108 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2109 for (j
= 0; j
< 4; j
++) {
2110 r
[j
].i
[i
] = result
[j
];
2114 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2115 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2116 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2117 TGSI_EXEC_DATA_INT
);
2123 exec_sample(struct tgsi_exec_machine
*mach
,
2124 const struct tgsi_full_instruction
*inst
,
2127 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2128 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2129 union tgsi_exec_channel r
[4];
2130 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2131 enum tgsi_sampler_control control
;
2134 if (modifier
!= TEX_MODIFIER_NONE
) {
2135 if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2136 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2137 else /*TEX_MODIFIER_LOD*/
2138 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2140 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2145 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2146 control
= tgsi_sampler_lod_explicit
;
2148 control
= tgsi_sampler_lod_bias
;
2151 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2152 case TGSI_TEXTURE_1D
:
2153 case TGSI_TEXTURE_SHADOW1D
:
2154 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2156 if (modifier
== TEX_MODIFIER_PROJECTED
) {
2157 micro_div(&r
[0], &r
[0], &r
[3]);
2160 fetch_texel(mach
->Samplers
[sampler_unit
],
2161 &r
[0], &ZeroVec
, &ZeroVec
, lod
, &ZeroVec
, /* S, T, P, LOD */
2163 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2166 case TGSI_TEXTURE_1D_ARRAY
:
2167 case TGSI_TEXTURE_2D
:
2168 case TGSI_TEXTURE_RECT
:
2169 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2170 case TGSI_TEXTURE_SHADOW2D
:
2171 case TGSI_TEXTURE_SHADOWRECT
:
2172 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2173 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2174 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2176 if (modifier
== TEX_MODIFIER_PROJECTED
) {
2177 micro_div(&r
[0], &r
[0], &r
[3]);
2178 micro_div(&r
[1], &r
[1], &r
[3]);
2179 micro_div(&r
[2], &r
[2], &r
[3]);
2182 fetch_texel(mach
->Samplers
[sampler_unit
],
2183 &r
[0], &r
[1], &r
[2], lod
, &ZeroVec
, /* S, T, P, LOD */
2185 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2188 case TGSI_TEXTURE_2D_ARRAY
:
2189 case TGSI_TEXTURE_3D
:
2190 case TGSI_TEXTURE_CUBE
:
2191 case TGSI_TEXTURE_CUBE_ARRAY
:
2192 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2193 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2194 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2196 if (modifier
== TEX_MODIFIER_PROJECTED
) {
2197 micro_div(&r
[0], &r
[0], &r
[3]);
2198 micro_div(&r
[1], &r
[1], &r
[3]);
2199 micro_div(&r
[2], &r
[2], &r
[3]);
2202 fetch_texel(mach
->Samplers
[sampler_unit
],
2203 &r
[0], &r
[1], &r
[2], lod
, &ZeroVec
,
2205 &r
[0], &r
[1], &r
[2], &r
[3]);
2208 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2209 case TGSI_TEXTURE_SHADOWCUBE
:
2210 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2211 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2212 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2213 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2215 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2217 fetch_texel(mach
->Samplers
[sampler_unit
],
2218 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2220 &r
[0], &r
[1], &r
[2], &r
[3]);
2227 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2228 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2229 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2235 exec_sample_d(struct tgsi_exec_machine
*mach
,
2236 const struct tgsi_full_instruction
*inst
)
2238 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2239 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2240 union tgsi_exec_channel r
[4];
2243 * XXX: This is fake SAMPLE_D -- the derivatives are not taken into account, yet.
2246 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2247 case TGSI_TEXTURE_1D
:
2248 case TGSI_TEXTURE_SHADOW1D
:
2250 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2252 fetch_texel(mach
->Samplers
[sampler_unit
],
2253 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, BIAS */
2254 tgsi_sampler_lod_bias
,
2255 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2258 case TGSI_TEXTURE_2D
:
2259 case TGSI_TEXTURE_RECT
:
2260 case TGSI_TEXTURE_SHADOW2D
:
2261 case TGSI_TEXTURE_SHADOWRECT
:
2263 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2264 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2265 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2267 fetch_texel(mach
->Samplers
[sampler_unit
],
2268 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2269 tgsi_sampler_lod_bias
,
2270 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2273 case TGSI_TEXTURE_3D
:
2274 case TGSI_TEXTURE_CUBE
:
2275 case TGSI_TEXTURE_CUBE_ARRAY
:
2277 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2278 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2279 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2281 fetch_texel(mach
->Samplers
[sampler_unit
],
2282 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
,
2283 tgsi_sampler_lod_bias
,
2284 &r
[0], &r
[1], &r
[2], &r
[3]);
2291 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2292 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2293 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2300 * Evaluate a constant-valued coefficient at the position of the
2305 struct tgsi_exec_machine
*mach
,
2311 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2312 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2317 * Evaluate a linear-valued coefficient at the position of the
2322 struct tgsi_exec_machine
*mach
,
2326 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2327 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2328 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2329 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2330 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2331 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2332 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2333 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2334 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2338 * Evaluate a perspective-valued coefficient at the position of the
2342 eval_perspective_coef(
2343 struct tgsi_exec_machine
*mach
,
2347 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2348 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2349 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2350 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2351 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2352 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2353 /* divide by W here */
2354 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2355 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2356 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2357 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2361 typedef void (* eval_coef_func
)(
2362 struct tgsi_exec_machine
*mach
,
2367 exec_declaration(struct tgsi_exec_machine
*mach
,
2368 const struct tgsi_full_declaration
*decl
)
2370 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2371 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2375 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
2376 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2377 uint first
, last
, mask
;
2379 first
= decl
->Range
.First
;
2380 last
= decl
->Range
.Last
;
2381 mask
= decl
->Declaration
.UsageMask
;
2383 /* XXX we could remove this special-case code since
2384 * mach->InterpCoefs[first].a0 should already have the
2385 * front/back-face value. But we should first update the
2386 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2387 * Then, we could remove the tgsi_exec_machine::Face field.
2389 /* XXX make FACE a system value */
2390 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2393 assert(decl
->Semantic
.Index
== 0);
2394 assert(first
== last
);
2396 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2397 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2400 eval_coef_func eval
;
2403 switch (decl
->Interp
.Interpolate
) {
2404 case TGSI_INTERPOLATE_CONSTANT
:
2405 eval
= eval_constant_coef
;
2408 case TGSI_INTERPOLATE_LINEAR
:
2409 eval
= eval_linear_coef
;
2412 case TGSI_INTERPOLATE_PERSPECTIVE
:
2413 eval
= eval_perspective_coef
;
2416 case TGSI_INTERPOLATE_COLOR
:
2417 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2425 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2426 if (mask
& (1 << j
)) {
2427 for (i
= first
; i
<= last
; i
++) {
2436 if (decl
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
2437 mach
->SysSemanticToIndex
[decl
->Declaration
.Semantic
] = decl
->Range
.First
;
2442 typedef void (* micro_op
)(union tgsi_exec_channel
*dst
);
2445 exec_vector(struct tgsi_exec_machine
*mach
,
2446 const struct tgsi_full_instruction
*inst
,
2448 enum tgsi_exec_datatype dst_datatype
)
2452 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2453 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2454 union tgsi_exec_channel dst
;
2457 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2462 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2463 const union tgsi_exec_channel
*src
);
2466 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2467 const struct tgsi_full_instruction
*inst
,
2469 enum tgsi_exec_datatype dst_datatype
,
2470 enum tgsi_exec_datatype src_datatype
)
2473 union tgsi_exec_channel src
;
2474 union tgsi_exec_channel dst
;
2476 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2478 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2479 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2480 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2486 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2487 const struct tgsi_full_instruction
*inst
,
2489 enum tgsi_exec_datatype dst_datatype
,
2490 enum tgsi_exec_datatype src_datatype
)
2493 struct tgsi_exec_vector dst
;
2495 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2496 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2497 union tgsi_exec_channel src
;
2499 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2500 op(&dst
.xyzw
[chan
], &src
);
2503 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2504 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2505 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2510 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2511 const union tgsi_exec_channel
*src0
,
2512 const union tgsi_exec_channel
*src1
);
2515 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2516 const struct tgsi_full_instruction
*inst
,
2518 enum tgsi_exec_datatype dst_datatype
,
2519 enum tgsi_exec_datatype src_datatype
)
2522 union tgsi_exec_channel src
[2];
2523 union tgsi_exec_channel dst
;
2525 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2526 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Y
, src_datatype
);
2527 op(&dst
, &src
[0], &src
[1]);
2528 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2529 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2530 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2536 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2537 const struct tgsi_full_instruction
*inst
,
2539 enum tgsi_exec_datatype dst_datatype
,
2540 enum tgsi_exec_datatype src_datatype
)
2543 struct tgsi_exec_vector dst
;
2545 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2546 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2547 union tgsi_exec_channel src
[2];
2549 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2550 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2551 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2554 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2555 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2556 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2561 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2562 const union tgsi_exec_channel
*src0
,
2563 const union tgsi_exec_channel
*src1
,
2564 const union tgsi_exec_channel
*src2
);
2567 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2568 const struct tgsi_full_instruction
*inst
,
2569 micro_trinary_op op
,
2570 enum tgsi_exec_datatype dst_datatype
,
2571 enum tgsi_exec_datatype src_datatype
)
2574 struct tgsi_exec_vector dst
;
2576 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2577 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2578 union tgsi_exec_channel src
[3];
2580 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2581 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2582 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2583 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2586 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2587 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2588 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2594 exec_dp3(struct tgsi_exec_machine
*mach
,
2595 const struct tgsi_full_instruction
*inst
)
2598 union tgsi_exec_channel arg
[3];
2600 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2601 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2602 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2604 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2605 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2606 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2607 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2610 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2611 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2612 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2618 exec_dp4(struct tgsi_exec_machine
*mach
,
2619 const struct tgsi_full_instruction
*inst
)
2622 union tgsi_exec_channel arg
[3];
2624 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2625 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2626 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2628 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2629 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2630 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2631 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2634 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2635 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2636 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2642 exec_dp2a(struct tgsi_exec_machine
*mach
,
2643 const struct tgsi_full_instruction
*inst
)
2646 union tgsi_exec_channel arg
[3];
2648 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2649 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2650 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2652 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2653 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2654 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2656 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2657 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2659 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2660 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2661 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2667 exec_dph(struct tgsi_exec_machine
*mach
,
2668 const struct tgsi_full_instruction
*inst
)
2671 union tgsi_exec_channel arg
[3];
2673 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2674 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2675 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2677 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2678 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2679 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2681 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2682 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2683 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2685 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2686 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2688 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2689 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2690 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2696 exec_dp2(struct tgsi_exec_machine
*mach
,
2697 const struct tgsi_full_instruction
*inst
)
2700 union tgsi_exec_channel arg
[3];
2702 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2703 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2704 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2706 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2707 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2708 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2710 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2711 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2712 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2718 exec_nrm4(struct tgsi_exec_machine
*mach
,
2719 const struct tgsi_full_instruction
*inst
)
2722 union tgsi_exec_channel arg
[4];
2723 union tgsi_exec_channel scale
;
2725 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2726 micro_mul(&scale
, &arg
[0], &arg
[0]);
2728 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2729 union tgsi_exec_channel product
;
2731 fetch_source(mach
, &arg
[chan
], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2732 micro_mul(&product
, &arg
[chan
], &arg
[chan
]);
2733 micro_add(&scale
, &scale
, &product
);
2736 micro_rsq(&scale
, &scale
);
2738 for (chan
= TGSI_CHAN_X
; chan
<= TGSI_CHAN_W
; chan
++) {
2739 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2740 micro_mul(&arg
[chan
], &arg
[chan
], &scale
);
2741 store_dest(mach
, &arg
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2747 exec_nrm3(struct tgsi_exec_machine
*mach
,
2748 const struct tgsi_full_instruction
*inst
)
2750 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2752 union tgsi_exec_channel arg
[3];
2753 union tgsi_exec_channel scale
;
2755 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2756 micro_mul(&scale
, &arg
[0], &arg
[0]);
2758 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2759 union tgsi_exec_channel product
;
2761 fetch_source(mach
, &arg
[chan
], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2762 micro_mul(&product
, &arg
[chan
], &arg
[chan
]);
2763 micro_add(&scale
, &scale
, &product
);
2766 micro_rsq(&scale
, &scale
);
2768 for (chan
= TGSI_CHAN_X
; chan
<= TGSI_CHAN_Z
; chan
++) {
2769 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2770 micro_mul(&arg
[chan
], &arg
[chan
], &scale
);
2771 store_dest(mach
, &arg
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2776 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2777 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2782 exec_scs(struct tgsi_exec_machine
*mach
,
2783 const struct tgsi_full_instruction
*inst
)
2785 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
2786 union tgsi_exec_channel arg
;
2787 union tgsi_exec_channel result
;
2789 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2791 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2792 micro_cos(&result
, &arg
);
2793 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2795 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2796 micro_sin(&result
, &arg
);
2797 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2800 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2801 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2803 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2804 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2809 exec_x2d(struct tgsi_exec_machine
*mach
,
2810 const struct tgsi_full_instruction
*inst
)
2812 union tgsi_exec_channel r
[4];
2813 union tgsi_exec_channel d
[2];
2815 fetch_source(mach
, &r
[0], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2816 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2817 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XZ
) {
2818 fetch_source(mach
, &r
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2819 micro_mul(&r
[2], &r
[2], &r
[0]);
2820 fetch_source(mach
, &r
[3], &inst
->Src
[2], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2821 micro_mul(&r
[3], &r
[3], &r
[1]);
2822 micro_add(&r
[2], &r
[2], &r
[3]);
2823 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2824 micro_add(&d
[0], &r
[2], &r
[3]);
2826 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YW
) {
2827 fetch_source(mach
, &r
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2828 micro_mul(&r
[2], &r
[2], &r
[0]);
2829 fetch_source(mach
, &r
[3], &inst
->Src
[2], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2830 micro_mul(&r
[3], &r
[3], &r
[1]);
2831 micro_add(&r
[2], &r
[2], &r
[3]);
2832 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2833 micro_add(&d
[1], &r
[2], &r
[3]);
2835 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2836 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2838 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2839 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2841 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2842 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2844 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2845 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2850 exec_rfl(struct tgsi_exec_machine
*mach
,
2851 const struct tgsi_full_instruction
*inst
)
2853 union tgsi_exec_channel r
[9];
2855 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2856 /* r0 = dp3(src0, src0) */
2857 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2858 micro_mul(&r
[0], &r
[2], &r
[2]);
2859 fetch_source(mach
, &r
[4], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2860 micro_mul(&r
[8], &r
[4], &r
[4]);
2861 micro_add(&r
[0], &r
[0], &r
[8]);
2862 fetch_source(mach
, &r
[6], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2863 micro_mul(&r
[8], &r
[6], &r
[6]);
2864 micro_add(&r
[0], &r
[0], &r
[8]);
2866 /* r1 = dp3(src0, src1) */
2867 fetch_source(mach
, &r
[3], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2868 micro_mul(&r
[1], &r
[2], &r
[3]);
2869 fetch_source(mach
, &r
[5], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2870 micro_mul(&r
[8], &r
[4], &r
[5]);
2871 micro_add(&r
[1], &r
[1], &r
[8]);
2872 fetch_source(mach
, &r
[7], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2873 micro_mul(&r
[8], &r
[6], &r
[7]);
2874 micro_add(&r
[1], &r
[1], &r
[8]);
2876 /* r1 = 2 * r1 / r0 */
2877 micro_add(&r
[1], &r
[1], &r
[1]);
2878 micro_div(&r
[1], &r
[1], &r
[0]);
2880 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2881 micro_mul(&r
[2], &r
[2], &r
[1]);
2882 micro_sub(&r
[2], &r
[2], &r
[3]);
2883 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2885 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2886 micro_mul(&r
[4], &r
[4], &r
[1]);
2887 micro_sub(&r
[4], &r
[4], &r
[5]);
2888 store_dest(mach
, &r
[4], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2890 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2891 micro_mul(&r
[6], &r
[6], &r
[1]);
2892 micro_sub(&r
[6], &r
[6], &r
[7]);
2893 store_dest(mach
, &r
[6], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2896 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2897 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2902 exec_xpd(struct tgsi_exec_machine
*mach
,
2903 const struct tgsi_full_instruction
*inst
)
2905 union tgsi_exec_channel r
[6];
2906 union tgsi_exec_channel d
[3];
2908 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2909 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2911 micro_mul(&r
[2], &r
[0], &r
[1]);
2913 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2914 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2916 micro_mul(&r
[5], &r
[3], &r
[4] );
2917 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
2919 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2921 micro_mul(&r
[3], &r
[3], &r
[2]);
2923 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2925 micro_mul(&r
[1], &r
[1], &r
[5]);
2926 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
2928 micro_mul(&r
[5], &r
[5], &r
[4]);
2929 micro_mul(&r
[0], &r
[0], &r
[2]);
2930 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
2932 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2933 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2935 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2936 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2938 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2939 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2941 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2942 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2947 exec_dst(struct tgsi_exec_machine
*mach
,
2948 const struct tgsi_full_instruction
*inst
)
2950 union tgsi_exec_channel r
[2];
2951 union tgsi_exec_channel d
[4];
2953 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2954 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2955 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2956 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
2958 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2959 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2961 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2962 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2965 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2966 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2968 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2969 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2971 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2972 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2974 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2975 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2980 exec_log(struct tgsi_exec_machine
*mach
,
2981 const struct tgsi_full_instruction
*inst
)
2983 union tgsi_exec_channel r
[3];
2985 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2986 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
2987 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
2988 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
2989 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2990 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2992 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2993 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
2994 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
2995 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2997 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2998 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3000 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3001 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3006 exec_exp(struct tgsi_exec_machine
*mach
,
3007 const struct tgsi_full_instruction
*inst
)
3009 union tgsi_exec_channel r
[3];
3011 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3012 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3013 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3014 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3015 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3017 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3018 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3019 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3021 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3022 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3023 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3025 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3026 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3031 exec_lit(struct tgsi_exec_machine
*mach
,
3032 const struct tgsi_full_instruction
*inst
)
3034 union tgsi_exec_channel r
[3];
3035 union tgsi_exec_channel d
[3];
3037 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3038 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3039 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3040 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3041 micro_max(&r
[1], &r
[1], &ZeroVec
);
3043 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3044 micro_min(&r
[2], &r
[2], &P128Vec
);
3045 micro_max(&r
[2], &r
[2], &M128Vec
);
3046 micro_pow(&r
[1], &r
[1], &r
[2]);
3047 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3048 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3050 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3051 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3052 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3055 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3056 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3059 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3060 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3065 exec_break(struct tgsi_exec_machine
*mach
)
3067 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3068 /* turn off loop channels for each enabled exec channel */
3069 mach
->LoopMask
&= ~mach
->ExecMask
;
3070 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3071 UPDATE_EXEC_MASK(mach
);
3073 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3075 mach
->Switch
.mask
= 0x0;
3077 UPDATE_EXEC_MASK(mach
);
3082 exec_switch(struct tgsi_exec_machine
*mach
,
3083 const struct tgsi_full_instruction
*inst
)
3085 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3086 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3088 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3089 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3090 mach
->Switch
.mask
= 0x0;
3091 mach
->Switch
.defaultMask
= 0x0;
3093 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3094 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3096 UPDATE_EXEC_MASK(mach
);
3100 exec_case(struct tgsi_exec_machine
*mach
,
3101 const struct tgsi_full_instruction
*inst
)
3103 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3104 union tgsi_exec_channel src
;
3107 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3109 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3112 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3115 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3118 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3122 mach
->Switch
.defaultMask
|= mask
;
3124 mach
->Switch
.mask
|= mask
& prevMask
;
3126 UPDATE_EXEC_MASK(mach
);
3130 exec_default(struct tgsi_exec_machine
*mach
)
3132 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3134 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3136 UPDATE_EXEC_MASK(mach
);
3140 exec_endswitch(struct tgsi_exec_machine
*mach
)
3142 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3143 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3145 UPDATE_EXEC_MASK(mach
);
3149 micro_i2f(union tgsi_exec_channel
*dst
,
3150 const union tgsi_exec_channel
*src
)
3152 dst
->f
[0] = (float)src
->i
[0];
3153 dst
->f
[1] = (float)src
->i
[1];
3154 dst
->f
[2] = (float)src
->i
[2];
3155 dst
->f
[3] = (float)src
->i
[3];
3159 micro_not(union tgsi_exec_channel
*dst
,
3160 const union tgsi_exec_channel
*src
)
3162 dst
->u
[0] = ~src
->u
[0];
3163 dst
->u
[1] = ~src
->u
[1];
3164 dst
->u
[2] = ~src
->u
[2];
3165 dst
->u
[3] = ~src
->u
[3];
3169 micro_shl(union tgsi_exec_channel
*dst
,
3170 const union tgsi_exec_channel
*src0
,
3171 const union tgsi_exec_channel
*src1
)
3173 dst
->u
[0] = src0
->u
[0] << src1
->u
[0];
3174 dst
->u
[1] = src0
->u
[1] << src1
->u
[1];
3175 dst
->u
[2] = src0
->u
[2] << src1
->u
[2];
3176 dst
->u
[3] = src0
->u
[3] << src1
->u
[3];
3180 micro_and(union tgsi_exec_channel
*dst
,
3181 const union tgsi_exec_channel
*src0
,
3182 const union tgsi_exec_channel
*src1
)
3184 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
3185 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
3186 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
3187 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
3191 micro_or(union tgsi_exec_channel
*dst
,
3192 const union tgsi_exec_channel
*src0
,
3193 const union tgsi_exec_channel
*src1
)
3195 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
3196 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
3197 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
3198 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
3202 micro_xor(union tgsi_exec_channel
*dst
,
3203 const union tgsi_exec_channel
*src0
,
3204 const union tgsi_exec_channel
*src1
)
3206 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
3207 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
3208 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
3209 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
3213 micro_mod(union tgsi_exec_channel
*dst
,
3214 const union tgsi_exec_channel
*src0
,
3215 const union tgsi_exec_channel
*src1
)
3217 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
3218 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
3219 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
3220 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
3224 micro_f2i(union tgsi_exec_channel
*dst
,
3225 const union tgsi_exec_channel
*src
)
3227 dst
->i
[0] = (int)src
->f
[0];
3228 dst
->i
[1] = (int)src
->f
[1];
3229 dst
->i
[2] = (int)src
->f
[2];
3230 dst
->i
[3] = (int)src
->f
[3];
3234 micro_idiv(union tgsi_exec_channel
*dst
,
3235 const union tgsi_exec_channel
*src0
,
3236 const union tgsi_exec_channel
*src1
)
3238 dst
->i
[0] = src0
->i
[0] / src1
->i
[0];
3239 dst
->i
[1] = src0
->i
[1] / src1
->i
[1];
3240 dst
->i
[2] = src0
->i
[2] / src1
->i
[2];
3241 dst
->i
[3] = src0
->i
[3] / src1
->i
[3];
3245 micro_imax(union tgsi_exec_channel
*dst
,
3246 const union tgsi_exec_channel
*src0
,
3247 const union tgsi_exec_channel
*src1
)
3249 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3250 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3251 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3252 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3256 micro_imin(union tgsi_exec_channel
*dst
,
3257 const union tgsi_exec_channel
*src0
,
3258 const union tgsi_exec_channel
*src1
)
3260 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3261 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3262 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3263 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3267 micro_isge(union tgsi_exec_channel
*dst
,
3268 const union tgsi_exec_channel
*src0
,
3269 const union tgsi_exec_channel
*src1
)
3271 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
3272 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
3273 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
3274 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
3278 micro_ishr(union tgsi_exec_channel
*dst
,
3279 const union tgsi_exec_channel
*src0
,
3280 const union tgsi_exec_channel
*src1
)
3282 dst
->i
[0] = src0
->i
[0] >> src1
->i
[0];
3283 dst
->i
[1] = src0
->i
[1] >> src1
->i
[1];
3284 dst
->i
[2] = src0
->i
[2] >> src1
->i
[2];
3285 dst
->i
[3] = src0
->i
[3] >> src1
->i
[3];
3289 micro_islt(union tgsi_exec_channel
*dst
,
3290 const union tgsi_exec_channel
*src0
,
3291 const union tgsi_exec_channel
*src1
)
3293 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
3294 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
3295 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
3296 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
3300 micro_f2u(union tgsi_exec_channel
*dst
,
3301 const union tgsi_exec_channel
*src
)
3303 dst
->u
[0] = (uint
)src
->f
[0];
3304 dst
->u
[1] = (uint
)src
->f
[1];
3305 dst
->u
[2] = (uint
)src
->f
[2];
3306 dst
->u
[3] = (uint
)src
->f
[3];
3310 micro_u2f(union tgsi_exec_channel
*dst
,
3311 const union tgsi_exec_channel
*src
)
3313 dst
->f
[0] = (float)src
->u
[0];
3314 dst
->f
[1] = (float)src
->u
[1];
3315 dst
->f
[2] = (float)src
->u
[2];
3316 dst
->f
[3] = (float)src
->u
[3];
3320 micro_uadd(union tgsi_exec_channel
*dst
,
3321 const union tgsi_exec_channel
*src0
,
3322 const union tgsi_exec_channel
*src1
)
3324 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
3325 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
3326 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
3327 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
3331 micro_udiv(union tgsi_exec_channel
*dst
,
3332 const union tgsi_exec_channel
*src0
,
3333 const union tgsi_exec_channel
*src1
)
3335 dst
->u
[0] = src0
->u
[0] / src1
->u
[0];
3336 dst
->u
[1] = src0
->u
[1] / src1
->u
[1];
3337 dst
->u
[2] = src0
->u
[2] / src1
->u
[2];
3338 dst
->u
[3] = src0
->u
[3] / src1
->u
[3];
3342 micro_umad(union tgsi_exec_channel
*dst
,
3343 const union tgsi_exec_channel
*src0
,
3344 const union tgsi_exec_channel
*src1
,
3345 const union tgsi_exec_channel
*src2
)
3347 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
3348 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
3349 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
3350 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
3354 micro_umax(union tgsi_exec_channel
*dst
,
3355 const union tgsi_exec_channel
*src0
,
3356 const union tgsi_exec_channel
*src1
)
3358 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3359 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3360 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3361 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3365 micro_umin(union tgsi_exec_channel
*dst
,
3366 const union tgsi_exec_channel
*src0
,
3367 const union tgsi_exec_channel
*src1
)
3369 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3370 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3371 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3372 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3376 micro_umod(union tgsi_exec_channel
*dst
,
3377 const union tgsi_exec_channel
*src0
,
3378 const union tgsi_exec_channel
*src1
)
3380 dst
->u
[0] = src0
->u
[0] % src1
->u
[0];
3381 dst
->u
[1] = src0
->u
[1] % src1
->u
[1];
3382 dst
->u
[2] = src0
->u
[2] % src1
->u
[2];
3383 dst
->u
[3] = src0
->u
[3] % src1
->u
[3];
3387 micro_umul(union tgsi_exec_channel
*dst
,
3388 const union tgsi_exec_channel
*src0
,
3389 const union tgsi_exec_channel
*src1
)
3391 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
3392 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
3393 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
3394 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
3398 micro_useq(union tgsi_exec_channel
*dst
,
3399 const union tgsi_exec_channel
*src0
,
3400 const union tgsi_exec_channel
*src1
)
3402 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
3403 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
3404 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
3405 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
3409 micro_usge(union tgsi_exec_channel
*dst
,
3410 const union tgsi_exec_channel
*src0
,
3411 const union tgsi_exec_channel
*src1
)
3413 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
3414 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
3415 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
3416 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
3420 micro_ushr(union tgsi_exec_channel
*dst
,
3421 const union tgsi_exec_channel
*src0
,
3422 const union tgsi_exec_channel
*src1
)
3424 dst
->u
[0] = src0
->u
[0] >> src1
->u
[0];
3425 dst
->u
[1] = src0
->u
[1] >> src1
->u
[1];
3426 dst
->u
[2] = src0
->u
[2] >> src1
->u
[2];
3427 dst
->u
[3] = src0
->u
[3] >> src1
->u
[3];
3431 micro_uslt(union tgsi_exec_channel
*dst
,
3432 const union tgsi_exec_channel
*src0
,
3433 const union tgsi_exec_channel
*src1
)
3435 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
3436 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
3437 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
3438 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
3442 micro_usne(union tgsi_exec_channel
*dst
,
3443 const union tgsi_exec_channel
*src0
,
3444 const union tgsi_exec_channel
*src1
)
3446 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
3447 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
3448 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
3449 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
3453 micro_uarl(union tgsi_exec_channel
*dst
,
3454 const union tgsi_exec_channel
*src
)
3456 dst
->i
[0] = src
->u
[0];
3457 dst
->i
[1] = src
->u
[1];
3458 dst
->i
[2] = src
->u
[2];
3459 dst
->i
[3] = src
->u
[3];
3463 micro_ucmp(union tgsi_exec_channel
*dst
,
3464 const union tgsi_exec_channel
*src0
,
3465 const union tgsi_exec_channel
*src1
,
3466 const union tgsi_exec_channel
*src2
)
3468 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
3469 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
3470 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
3471 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
3476 struct tgsi_exec_machine
*mach
,
3477 const struct tgsi_full_instruction
*inst
,
3480 union tgsi_exec_channel r
[10];
3484 switch (inst
->Instruction
.Opcode
) {
3485 case TGSI_OPCODE_ARL
:
3486 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3489 case TGSI_OPCODE_MOV
:
3490 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
3493 case TGSI_OPCODE_LIT
:
3494 exec_lit(mach
, inst
);
3497 case TGSI_OPCODE_RCP
:
3498 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3501 case TGSI_OPCODE_RSQ
:
3502 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3505 case TGSI_OPCODE_EXP
:
3506 exec_exp(mach
, inst
);
3509 case TGSI_OPCODE_LOG
:
3510 exec_log(mach
, inst
);
3513 case TGSI_OPCODE_MUL
:
3514 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3517 case TGSI_OPCODE_ADD
:
3518 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3521 case TGSI_OPCODE_DP3
:
3522 exec_dp3(mach
, inst
);
3525 case TGSI_OPCODE_DP4
:
3526 exec_dp4(mach
, inst
);
3529 case TGSI_OPCODE_DST
:
3530 exec_dst(mach
, inst
);
3533 case TGSI_OPCODE_MIN
:
3534 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3537 case TGSI_OPCODE_MAX
:
3538 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3541 case TGSI_OPCODE_SLT
:
3542 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3545 case TGSI_OPCODE_SGE
:
3546 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3549 case TGSI_OPCODE_MAD
:
3550 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3553 case TGSI_OPCODE_SUB
:
3554 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3557 case TGSI_OPCODE_LRP
:
3558 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3561 case TGSI_OPCODE_CND
:
3562 exec_vector_trinary(mach
, inst
, micro_cnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3565 case TGSI_OPCODE_DP2A
:
3566 exec_dp2a(mach
, inst
);
3569 case TGSI_OPCODE_FRC
:
3570 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3573 case TGSI_OPCODE_CLAMP
:
3574 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3577 case TGSI_OPCODE_FLR
:
3578 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3581 case TGSI_OPCODE_ROUND
:
3582 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3585 case TGSI_OPCODE_EX2
:
3586 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3589 case TGSI_OPCODE_LG2
:
3590 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3593 case TGSI_OPCODE_POW
:
3594 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3597 case TGSI_OPCODE_XPD
:
3598 exec_xpd(mach
, inst
);
3601 case TGSI_OPCODE_ABS
:
3602 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3605 case TGSI_OPCODE_RCC
:
3606 exec_scalar_unary(mach
, inst
, micro_rcc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3609 case TGSI_OPCODE_DPH
:
3610 exec_dph(mach
, inst
);
3613 case TGSI_OPCODE_COS
:
3614 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3617 case TGSI_OPCODE_DDX
:
3618 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3621 case TGSI_OPCODE_DDY
:
3622 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3625 case TGSI_OPCODE_KILP
:
3626 exec_kilp (mach
, inst
);
3629 case TGSI_OPCODE_KIL
:
3630 exec_kil (mach
, inst
);
3633 case TGSI_OPCODE_PK2H
:
3637 case TGSI_OPCODE_PK2US
:
3641 case TGSI_OPCODE_PK4B
:
3645 case TGSI_OPCODE_PK4UB
:
3649 case TGSI_OPCODE_RFL
:
3650 exec_rfl(mach
, inst
);
3653 case TGSI_OPCODE_SEQ
:
3654 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3657 case TGSI_OPCODE_SFL
:
3658 exec_vector(mach
, inst
, micro_sfl
, TGSI_EXEC_DATA_FLOAT
);
3661 case TGSI_OPCODE_SGT
:
3662 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3665 case TGSI_OPCODE_SIN
:
3666 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3669 case TGSI_OPCODE_SLE
:
3670 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3673 case TGSI_OPCODE_SNE
:
3674 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3677 case TGSI_OPCODE_STR
:
3678 exec_vector(mach
, inst
, micro_str
, TGSI_EXEC_DATA_FLOAT
);
3681 case TGSI_OPCODE_TEX
:
3682 /* simple texture lookup */
3683 /* src[0] = texcoord */
3684 /* src[1] = sampler unit */
3685 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
3688 case TGSI_OPCODE_TXB
:
3689 /* Texture lookup with lod bias */
3690 /* src[0] = texcoord (src[0].w = LOD bias) */
3691 /* src[1] = sampler unit */
3692 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
3695 case TGSI_OPCODE_TXD
:
3696 /* Texture lookup with explict partial derivatives */
3697 /* src[0] = texcoord */
3698 /* src[1] = d[strq]/dx */
3699 /* src[2] = d[strq]/dy */
3700 /* src[3] = sampler unit */
3701 exec_txd(mach
, inst
);
3704 case TGSI_OPCODE_TXL
:
3705 /* Texture lookup with explit LOD */
3706 /* src[0] = texcoord (src[0].w = LOD) */
3707 /* src[1] = sampler unit */
3708 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
3711 case TGSI_OPCODE_TXP
:
3712 /* Texture lookup with projection */
3713 /* src[0] = texcoord (src[0].w = projection) */
3714 /* src[1] = sampler unit */
3715 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
3718 case TGSI_OPCODE_UP2H
:
3722 case TGSI_OPCODE_UP2US
:
3726 case TGSI_OPCODE_UP4B
:
3730 case TGSI_OPCODE_UP4UB
:
3734 case TGSI_OPCODE_X2D
:
3735 exec_x2d(mach
, inst
);
3738 case TGSI_OPCODE_ARA
:
3742 case TGSI_OPCODE_ARR
:
3743 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3746 case TGSI_OPCODE_BRA
:
3750 case TGSI_OPCODE_CAL
:
3751 /* skip the call if no execution channels are enabled */
3752 if (mach
->ExecMask
) {
3755 /* First, record the depths of the execution stacks.
3756 * This is important for deeply nested/looped return statements.
3757 * We have to unwind the stacks by the correct amount. For a
3758 * real code generator, we could determine the number of entries
3759 * to pop off each stack with simple static analysis and avoid
3760 * implementing this data structure at run time.
3762 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
3763 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
3764 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
3765 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
3766 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
3767 /* note that PC was already incremented above */
3768 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
3770 mach
->CallStackTop
++;
3772 /* Second, push the Cond, Loop, Cont, Func stacks */
3773 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3774 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3775 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3776 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3777 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3778 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
3780 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3781 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
3782 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
3783 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3784 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3785 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
3787 /* Finally, jump to the subroutine */
3788 *pc
= inst
->Label
.Label
;
3792 case TGSI_OPCODE_RET
:
3793 mach
->FuncMask
&= ~mach
->ExecMask
;
3794 UPDATE_EXEC_MASK(mach
);
3796 if (mach
->FuncMask
== 0x0) {
3797 /* really return now (otherwise, keep executing */
3799 if (mach
->CallStackTop
== 0) {
3800 /* returning from main() */
3801 mach
->CondStackTop
= 0;
3802 mach
->LoopStackTop
= 0;
3807 assert(mach
->CallStackTop
> 0);
3808 mach
->CallStackTop
--;
3810 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
3811 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
3813 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
3814 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
3816 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
3817 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
3819 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
3820 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
3822 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
3823 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
3825 assert(mach
->FuncStackTop
> 0);
3826 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
3828 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
3830 UPDATE_EXEC_MASK(mach
);
3834 case TGSI_OPCODE_SSG
:
3835 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3838 case TGSI_OPCODE_CMP
:
3839 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3842 case TGSI_OPCODE_SCS
:
3843 exec_scs(mach
, inst
);
3846 case TGSI_OPCODE_NRM
:
3847 exec_nrm3(mach
, inst
);
3850 case TGSI_OPCODE_NRM4
:
3851 exec_nrm4(mach
, inst
);
3854 case TGSI_OPCODE_DIV
:
3855 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3858 case TGSI_OPCODE_DP2
:
3859 exec_dp2(mach
, inst
);
3862 case TGSI_OPCODE_IF
:
3864 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3865 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3866 FETCH( &r
[0], 0, TGSI_CHAN_X
);
3867 /* update CondMask */
3869 mach
->CondMask
&= ~0x1;
3872 mach
->CondMask
&= ~0x2;
3875 mach
->CondMask
&= ~0x4;
3878 mach
->CondMask
&= ~0x8;
3880 UPDATE_EXEC_MASK(mach
);
3881 /* Todo: If CondMask==0, jump to ELSE */
3884 case TGSI_OPCODE_ELSE
:
3885 /* invert CondMask wrt previous mask */
3888 assert(mach
->CondStackTop
> 0);
3889 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
3890 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
3891 UPDATE_EXEC_MASK(mach
);
3892 /* Todo: If CondMask==0, jump to ENDIF */
3896 case TGSI_OPCODE_ENDIF
:
3898 assert(mach
->CondStackTop
> 0);
3899 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
3900 UPDATE_EXEC_MASK(mach
);
3903 case TGSI_OPCODE_END
:
3904 /* make sure we end primitives which haven't
3905 * been explicitly emitted */
3906 conditional_emit_primitive(mach
);
3907 /* halt execution */
3911 case TGSI_OPCODE_PUSHA
:
3915 case TGSI_OPCODE_POPA
:
3919 case TGSI_OPCODE_CEIL
:
3920 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3923 case TGSI_OPCODE_I2F
:
3924 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
3927 case TGSI_OPCODE_NOT
:
3928 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3931 case TGSI_OPCODE_TRUNC
:
3932 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3935 case TGSI_OPCODE_SHL
:
3936 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3939 case TGSI_OPCODE_AND
:
3940 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3943 case TGSI_OPCODE_OR
:
3944 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3947 case TGSI_OPCODE_MOD
:
3948 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
3951 case TGSI_OPCODE_XOR
:
3952 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3955 case TGSI_OPCODE_SAD
:
3959 case TGSI_OPCODE_TXF
:
3960 exec_txf(mach
, inst
);
3963 case TGSI_OPCODE_TXQ
:
3964 exec_txq(mach
, inst
);
3967 case TGSI_OPCODE_EMIT
:
3971 case TGSI_OPCODE_ENDPRIM
:
3972 emit_primitive(mach
);
3975 case TGSI_OPCODE_BGNLOOP
:
3976 /* push LoopMask and ContMasks */
3977 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3978 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3979 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3980 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3982 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
3983 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
3984 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
3985 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3986 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
3989 case TGSI_OPCODE_ENDLOOP
:
3990 /* Restore ContMask, but don't pop */
3991 assert(mach
->ContStackTop
> 0);
3992 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
3993 UPDATE_EXEC_MASK(mach
);
3994 if (mach
->ExecMask
) {
3995 /* repeat loop: jump to instruction just past BGNLOOP */
3996 assert(mach
->LoopLabelStackTop
> 0);
3997 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
4000 /* exit loop: pop LoopMask */
4001 assert(mach
->LoopStackTop
> 0);
4002 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
4004 assert(mach
->ContStackTop
> 0);
4005 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
4006 assert(mach
->LoopLabelStackTop
> 0);
4007 --mach
->LoopLabelStackTop
;
4009 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
4011 UPDATE_EXEC_MASK(mach
);
4014 case TGSI_OPCODE_BRK
:
4018 case TGSI_OPCODE_CONT
:
4019 /* turn off cont channels for each enabled exec channel */
4020 mach
->ContMask
&= ~mach
->ExecMask
;
4021 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4022 UPDATE_EXEC_MASK(mach
);
4025 case TGSI_OPCODE_BGNSUB
:
4029 case TGSI_OPCODE_ENDSUB
:
4031 * XXX: This really should be a no-op. We should never reach this opcode.
4034 assert(mach
->CallStackTop
> 0);
4035 mach
->CallStackTop
--;
4037 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
4038 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
4040 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
4041 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
4043 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
4044 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
4046 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
4047 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
4049 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
4050 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
4052 assert(mach
->FuncStackTop
> 0);
4053 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4055 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4057 UPDATE_EXEC_MASK(mach
);
4060 case TGSI_OPCODE_NOP
:
4063 case TGSI_OPCODE_BREAKC
:
4064 FETCH(&r
[0], 0, TGSI_CHAN_X
);
4065 /* update CondMask */
4066 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
4067 mach
->LoopMask
&= ~0x1;
4069 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
4070 mach
->LoopMask
&= ~0x2;
4072 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
4073 mach
->LoopMask
&= ~0x4;
4075 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
4076 mach
->LoopMask
&= ~0x8;
4078 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4079 UPDATE_EXEC_MASK(mach
);
4082 case TGSI_OPCODE_F2I
:
4083 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4086 case TGSI_OPCODE_IDIV
:
4087 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4090 case TGSI_OPCODE_IMAX
:
4091 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4094 case TGSI_OPCODE_IMIN
:
4095 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4098 case TGSI_OPCODE_INEG
:
4099 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4102 case TGSI_OPCODE_ISGE
:
4103 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4106 case TGSI_OPCODE_ISHR
:
4107 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4110 case TGSI_OPCODE_ISLT
:
4111 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4114 case TGSI_OPCODE_F2U
:
4115 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4118 case TGSI_OPCODE_U2F
:
4119 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
4122 case TGSI_OPCODE_UADD
:
4123 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4126 case TGSI_OPCODE_UDIV
:
4127 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4130 case TGSI_OPCODE_UMAD
:
4131 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4134 case TGSI_OPCODE_UMAX
:
4135 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4138 case TGSI_OPCODE_UMIN
:
4139 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4142 case TGSI_OPCODE_UMOD
:
4143 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4146 case TGSI_OPCODE_UMUL
:
4147 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4150 case TGSI_OPCODE_USEQ
:
4151 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4154 case TGSI_OPCODE_USGE
:
4155 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4158 case TGSI_OPCODE_USHR
:
4159 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4162 case TGSI_OPCODE_USLT
:
4163 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4166 case TGSI_OPCODE_USNE
:
4167 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4170 case TGSI_OPCODE_SWITCH
:
4171 exec_switch(mach
, inst
);
4174 case TGSI_OPCODE_CASE
:
4175 exec_case(mach
, inst
);
4178 case TGSI_OPCODE_DEFAULT
:
4182 case TGSI_OPCODE_ENDSWITCH
:
4183 exec_endswitch(mach
);
4186 case TGSI_OPCODE_SAMPLE_I
:
4190 case TGSI_OPCODE_SAMPLE_I_MS
:
4194 case TGSI_OPCODE_SAMPLE
:
4195 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
);
4198 case TGSI_OPCODE_SAMPLE_B
:
4199 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
);
4202 case TGSI_OPCODE_SAMPLE_C
:
4203 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
);
4206 case TGSI_OPCODE_SAMPLE_C_LZ
:
4207 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
);
4210 case TGSI_OPCODE_SAMPLE_D
:
4211 exec_sample_d(mach
, inst
);
4214 case TGSI_OPCODE_SAMPLE_L
:
4215 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
);
4218 case TGSI_OPCODE_GATHER4
:
4222 case TGSI_OPCODE_SVIEWINFO
:
4226 case TGSI_OPCODE_SAMPLE_POS
:
4230 case TGSI_OPCODE_SAMPLE_INFO
:
4234 case TGSI_OPCODE_UARL
:
4235 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
4238 case TGSI_OPCODE_UCMP
:
4239 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4242 case TGSI_OPCODE_IABS
:
4243 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4246 case TGSI_OPCODE_ISSG
:
4247 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4250 case TGSI_OPCODE_TEX2
:
4251 /* simple texture lookup */
4252 /* src[0] = texcoord */
4253 /* src[1] = compare */
4254 /* src[2] = sampler unit */
4255 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
4257 case TGSI_OPCODE_TXB2
:
4258 /* simple texture lookup */
4259 /* src[0] = texcoord */
4261 /* src[2] = sampler unit */
4262 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
4264 case TGSI_OPCODE_TXL2
:
4265 /* simple texture lookup */
4266 /* src[0] = texcoord */
4268 /* src[2] = sampler unit */
4269 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
4277 #define DEBUG_EXECUTION 0
4281 * Run TGSI interpreter.
4282 * \return bitmask of "alive" quad components
4285 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
)
4290 mach
->CondMask
= 0xf;
4291 mach
->LoopMask
= 0xf;
4292 mach
->ContMask
= 0xf;
4293 mach
->FuncMask
= 0xf;
4294 mach
->ExecMask
= 0xf;
4296 mach
->Switch
.mask
= 0xf;
4298 assert(mach
->CondStackTop
== 0);
4299 assert(mach
->LoopStackTop
== 0);
4300 assert(mach
->ContStackTop
== 0);
4301 assert(mach
->SwitchStackTop
== 0);
4302 assert(mach
->BreakStackTop
== 0);
4303 assert(mach
->CallStackTop
== 0);
4305 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
4306 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
4308 if( mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
4309 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
4310 mach
->Primitives
[0] = 0;
4313 /* execute declarations (interpolants) */
4314 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
4315 exec_declaration( mach
, mach
->Declarations
+i
);
4320 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
4321 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
4324 memcpy(temps
, mach
->Temps
, sizeof(temps
));
4325 memcpy(outputs
, mach
->Outputs
, sizeof(outputs
));
4328 /* execute instructions, until pc is set to -1 */
4334 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
4337 assert(pc
< (int) mach
->NumInstructions
);
4338 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
4341 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
4342 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
4345 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
4346 debug_printf("TEMP[%2u] = ", i
);
4347 for (j
= 0; j
< 4; j
++) {
4351 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4352 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
4353 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
4354 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
4355 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
4359 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
4360 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
4363 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
4364 debug_printf("OUT[%2u] = ", i
);
4365 for (j
= 0; j
< 4; j
++) {
4369 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4370 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
4371 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
4372 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
4373 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
4382 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4383 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
4385 * Scale back depth component.
4387 for (i
= 0; i
< 4; i
++)
4388 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
4392 /* Strictly speaking, these assertions aren't really needed but they
4393 * can potentially catch some bugs in the control flow code.
4395 assert(mach
->CondStackTop
== 0);
4396 assert(mach
->LoopStackTop
== 0);
4397 assert(mach
->ContStackTop
== 0);
4398 assert(mach
->SwitchStackTop
== 0);
4399 assert(mach
->BreakStackTop
== 0);
4400 assert(mach
->CallStackTop
== 0);
4402 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];