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gallium: add TGSI opcodes UARL and UCMP
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
381 {
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
386 }
387
388 static void
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
391 {
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
396 }
397
398 static void
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
402 {
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
407 }
408
409 static void
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_sfl(union tgsi_exec_channel *dst)
433 {
434 dst->f[0] = 0.0f;
435 dst->f[1] = 0.0f;
436 dst->f[2] = 0.0f;
437 dst->f[3] = 0.0f;
438 }
439
440 static void
441 micro_str(union tgsi_exec_channel *dst)
442 {
443 dst->f[0] = 1.0f;
444 dst->f[1] = 1.0f;
445 dst->f[2] = 1.0f;
446 dst->f[3] = 1.0f;
447 }
448
449 static void
450 micro_trunc(union tgsi_exec_channel *dst,
451 const union tgsi_exec_channel *src)
452 {
453 dst->f[0] = (float)(int)src->f[0];
454 dst->f[1] = (float)(int)src->f[1];
455 dst->f[2] = (float)(int)src->f[2];
456 dst->f[3] = (float)(int)src->f[3];
457 }
458
459
460 #define CHAN_X 0
461 #define CHAN_Y 1
462 #define CHAN_Z 2
463 #define CHAN_W 3
464
465 enum tgsi_exec_datatype {
466 TGSI_EXEC_DATA_FLOAT,
467 TGSI_EXEC_DATA_INT,
468 TGSI_EXEC_DATA_UINT
469 };
470
471 /*
472 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
473 */
474 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
475 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
476 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
477 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
478 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
479 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
480
481
482 /** The execution mask depends on the conditional mask and the loop mask */
483 #define UPDATE_EXEC_MASK(MACH) \
484 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
485
486
487 static const union tgsi_exec_channel ZeroVec =
488 { { 0.0, 0.0, 0.0, 0.0 } };
489
490 static const union tgsi_exec_channel OneVec = {
491 {1.0f, 1.0f, 1.0f, 1.0f}
492 };
493
494 static const union tgsi_exec_channel P128Vec = {
495 {128.0f, 128.0f, 128.0f, 128.0f}
496 };
497
498 static const union tgsi_exec_channel M128Vec = {
499 {-128.0f, -128.0f, -128.0f, -128.0f}
500 };
501
502
503 /**
504 * Assert that none of the float values in 'chan' are infinite or NaN.
505 * NaN and Inf may occur normally during program execution and should
506 * not lead to crashes, etc. But when debugging, it's helpful to catch
507 * them.
508 */
509 static INLINE void
510 check_inf_or_nan(const union tgsi_exec_channel *chan)
511 {
512 assert(!util_is_inf_or_nan((chan)->f[0]));
513 assert(!util_is_inf_or_nan((chan)->f[1]));
514 assert(!util_is_inf_or_nan((chan)->f[2]));
515 assert(!util_is_inf_or_nan((chan)->f[3]));
516 }
517
518
519 #ifdef DEBUG
520 static void
521 print_chan(const char *msg, const union tgsi_exec_channel *chan)
522 {
523 debug_printf("%s = {%f, %f, %f, %f}\n",
524 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
525 }
526 #endif
527
528
529 #ifdef DEBUG
530 static void
531 print_temp(const struct tgsi_exec_machine *mach, uint index)
532 {
533 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
534 int i;
535 debug_printf("Temp[%u] =\n", index);
536 for (i = 0; i < 4; i++) {
537 debug_printf(" %c: { %f, %f, %f, %f }\n",
538 "XYZW"[i],
539 tmp->xyzw[i].f[0],
540 tmp->xyzw[i].f[1],
541 tmp->xyzw[i].f[2],
542 tmp->xyzw[i].f[3]);
543 }
544 }
545 #endif
546
547
548 void
549 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
550 unsigned num_bufs,
551 const void **bufs,
552 const unsigned *buf_sizes)
553 {
554 unsigned i;
555
556 for (i = 0; i < num_bufs; i++) {
557 mach->Consts[i] = bufs[i];
558 mach->ConstsSize[i] = buf_sizes[i];
559 }
560 }
561
562
563 /**
564 * Check if there's a potential src/dst register data dependency when
565 * using SOA execution.
566 * Example:
567 * MOV T, T.yxwz;
568 * This would expand into:
569 * MOV t0, t1;
570 * MOV t1, t0;
571 * MOV t2, t3;
572 * MOV t3, t2;
573 * The second instruction will have the wrong value for t0 if executed as-is.
574 */
575 boolean
576 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
577 {
578 uint i, chan;
579
580 uint writemask = inst->Dst[0].Register.WriteMask;
581 if (writemask == TGSI_WRITEMASK_X ||
582 writemask == TGSI_WRITEMASK_Y ||
583 writemask == TGSI_WRITEMASK_Z ||
584 writemask == TGSI_WRITEMASK_W ||
585 writemask == TGSI_WRITEMASK_NONE) {
586 /* no chance of data dependency */
587 return FALSE;
588 }
589
590 /* loop over src regs */
591 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
592 if ((inst->Src[i].Register.File ==
593 inst->Dst[0].Register.File) &&
594 ((inst->Src[i].Register.Index ==
595 inst->Dst[0].Register.Index) ||
596 inst->Src[i].Register.Indirect ||
597 inst->Dst[0].Register.Indirect)) {
598 /* loop over dest channels */
599 uint channelsWritten = 0x0;
600 for (chan = 0; chan < NUM_CHANNELS; chan++) {
601 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
602 /* check if we're reading a channel that's been written */
603 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
604 if (channelsWritten & (1 << swizzle)) {
605 return TRUE;
606 }
607
608 channelsWritten |= (1 << chan);
609 }
610 }
611 }
612 }
613 return FALSE;
614 }
615
616
617 /**
618 * Initialize machine state by expanding tokens to full instructions,
619 * allocating temporary storage, setting up constants, etc.
620 * After this, we can call tgsi_exec_machine_run() many times.
621 */
622 void
623 tgsi_exec_machine_bind_shader(
624 struct tgsi_exec_machine *mach,
625 const struct tgsi_token *tokens,
626 uint numSamplers,
627 struct tgsi_sampler **samplers)
628 {
629 uint k;
630 struct tgsi_parse_context parse;
631 struct tgsi_full_instruction *instructions;
632 struct tgsi_full_declaration *declarations;
633 uint maxInstructions = 10, numInstructions = 0;
634 uint maxDeclarations = 10, numDeclarations = 0;
635
636 #if 0
637 tgsi_dump(tokens, 0);
638 #endif
639
640 util_init_math();
641
642 if (numSamplers) {
643 assert(samplers);
644 }
645
646 mach->Tokens = tokens;
647 mach->Samplers = samplers;
648
649 if (!tokens) {
650 /* unbind and free all */
651 if (mach->Declarations) {
652 FREE( mach->Declarations );
653 }
654 mach->Declarations = NULL;
655 mach->NumDeclarations = 0;
656
657 if (mach->Instructions) {
658 FREE( mach->Instructions );
659 }
660 mach->Instructions = NULL;
661 mach->NumInstructions = 0;
662
663 return;
664 }
665
666 k = tgsi_parse_init (&parse, mach->Tokens);
667 if (k != TGSI_PARSE_OK) {
668 debug_printf( "Problem parsing!\n" );
669 return;
670 }
671
672 mach->Processor = parse.FullHeader.Processor.Processor;
673 mach->ImmLimit = 0;
674
675 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
676 !mach->UsedGeometryShader) {
677 struct tgsi_exec_vector *inputs =
678 align_malloc(sizeof(struct tgsi_exec_vector) *
679 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
680 16);
681 struct tgsi_exec_vector *outputs =
682 align_malloc(sizeof(struct tgsi_exec_vector) *
683 TGSI_MAX_TOTAL_VERTICES, 16);
684
685 if (!inputs)
686 return;
687 if (!outputs) {
688 align_free(inputs);
689 return;
690 }
691
692 align_free(mach->Inputs);
693 align_free(mach->Outputs);
694
695 mach->Inputs = inputs;
696 mach->Outputs = outputs;
697 mach->UsedGeometryShader = TRUE;
698 }
699
700 declarations = (struct tgsi_full_declaration *)
701 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
702
703 if (!declarations) {
704 return;
705 }
706
707 instructions = (struct tgsi_full_instruction *)
708 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
709
710 if (!instructions) {
711 FREE( declarations );
712 return;
713 }
714
715 while( !tgsi_parse_end_of_tokens( &parse ) ) {
716 uint i;
717
718 tgsi_parse_token( &parse );
719 switch( parse.FullToken.Token.Type ) {
720 case TGSI_TOKEN_TYPE_DECLARATION:
721 /* save expanded declaration */
722 if (numDeclarations == maxDeclarations) {
723 declarations = REALLOC(declarations,
724 maxDeclarations
725 * sizeof(struct tgsi_full_declaration),
726 (maxDeclarations + 10)
727 * sizeof(struct tgsi_full_declaration));
728 maxDeclarations += 10;
729 }
730 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
731 unsigned reg;
732 for (reg = parse.FullToken.FullDeclaration.Range.First;
733 reg <= parse.FullToken.FullDeclaration.Range.Last;
734 ++reg) {
735 ++mach->NumOutputs;
736 }
737 }
738 if (parse.FullToken.FullDeclaration.Declaration.File ==
739 TGSI_FILE_IMMEDIATE_ARRAY) {
740 unsigned reg;
741 struct tgsi_full_declaration *decl =
742 &parse.FullToken.FullDeclaration;
743 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
744 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
745 for( i = 0; i < 4; i++ ) {
746 int idx = reg * 4 + i;
747 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
748 }
749 }
750 }
751 memcpy(declarations + numDeclarations,
752 &parse.FullToken.FullDeclaration,
753 sizeof(declarations[0]));
754 numDeclarations++;
755 break;
756
757 case TGSI_TOKEN_TYPE_IMMEDIATE:
758 {
759 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
760 assert( size <= 4 );
761 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
762
763 for( i = 0; i < size; i++ ) {
764 mach->Imms[mach->ImmLimit][i] =
765 parse.FullToken.FullImmediate.u[i].Float;
766 }
767 mach->ImmLimit += 1;
768 }
769 break;
770
771 case TGSI_TOKEN_TYPE_INSTRUCTION:
772
773 /* save expanded instruction */
774 if (numInstructions == maxInstructions) {
775 instructions = REALLOC(instructions,
776 maxInstructions
777 * sizeof(struct tgsi_full_instruction),
778 (maxInstructions + 10)
779 * sizeof(struct tgsi_full_instruction));
780 maxInstructions += 10;
781 }
782
783 memcpy(instructions + numInstructions,
784 &parse.FullToken.FullInstruction,
785 sizeof(instructions[0]));
786
787 numInstructions++;
788 break;
789
790 case TGSI_TOKEN_TYPE_PROPERTY:
791 break;
792
793 default:
794 assert( 0 );
795 }
796 }
797 tgsi_parse_free (&parse);
798
799 if (mach->Declarations) {
800 FREE( mach->Declarations );
801 }
802 mach->Declarations = declarations;
803 mach->NumDeclarations = numDeclarations;
804
805 if (mach->Instructions) {
806 FREE( mach->Instructions );
807 }
808 mach->Instructions = instructions;
809 mach->NumInstructions = numInstructions;
810 }
811
812
813 struct tgsi_exec_machine *
814 tgsi_exec_machine_create( void )
815 {
816 struct tgsi_exec_machine *mach;
817 uint i;
818
819 mach = align_malloc( sizeof *mach, 16 );
820 if (!mach)
821 goto fail;
822
823 memset(mach, 0, sizeof(*mach));
824
825 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
826 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
827 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
828
829 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
830 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
831 if (!mach->Inputs || !mach->Outputs)
832 goto fail;
833
834 /* Setup constants needed by the SSE2 executor. */
835 for( i = 0; i < 4; i++ ) {
836 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
837 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
838 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
839 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
840 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
841 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
842 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
843 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
844 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
845 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
846 }
847
848 #ifdef DEBUG
849 /* silence warnings */
850 (void) print_chan;
851 (void) print_temp;
852 #endif
853
854 return mach;
855
856 fail:
857 if (mach) {
858 align_free(mach->Inputs);
859 align_free(mach->Outputs);
860 align_free(mach);
861 }
862 return NULL;
863 }
864
865
866 void
867 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
868 {
869 if (mach) {
870 if (mach->Instructions)
871 FREE(mach->Instructions);
872 if (mach->Declarations)
873 FREE(mach->Declarations);
874
875 align_free(mach->Inputs);
876 align_free(mach->Outputs);
877
878 align_free(mach);
879 }
880 }
881
882 static void
883 micro_add(union tgsi_exec_channel *dst,
884 const union tgsi_exec_channel *src0,
885 const union tgsi_exec_channel *src1)
886 {
887 dst->f[0] = src0->f[0] + src1->f[0];
888 dst->f[1] = src0->f[1] + src1->f[1];
889 dst->f[2] = src0->f[2] + src1->f[2];
890 dst->f[3] = src0->f[3] + src1->f[3];
891 }
892
893 static void
894 micro_div(
895 union tgsi_exec_channel *dst,
896 const union tgsi_exec_channel *src0,
897 const union tgsi_exec_channel *src1 )
898 {
899 if (src1->f[0] != 0) {
900 dst->f[0] = src0->f[0] / src1->f[0];
901 }
902 if (src1->f[1] != 0) {
903 dst->f[1] = src0->f[1] / src1->f[1];
904 }
905 if (src1->f[2] != 0) {
906 dst->f[2] = src0->f[2] / src1->f[2];
907 }
908 if (src1->f[3] != 0) {
909 dst->f[3] = src0->f[3] / src1->f[3];
910 }
911 }
912
913 static void
914 micro_rcc(union tgsi_exec_channel *dst,
915 const union tgsi_exec_channel *src)
916 {
917 uint i;
918
919 for (i = 0; i < 4; i++) {
920 float recip = 1.0f / src->f[i];
921
922 if (recip > 0.0f) {
923 if (recip > 1.884467e+019f) {
924 dst->f[i] = 1.884467e+019f;
925 }
926 else if (recip < 5.42101e-020f) {
927 dst->f[i] = 5.42101e-020f;
928 }
929 else {
930 dst->f[i] = recip;
931 }
932 }
933 else {
934 if (recip < -1.884467e+019f) {
935 dst->f[i] = -1.884467e+019f;
936 }
937 else if (recip > -5.42101e-020f) {
938 dst->f[i] = -5.42101e-020f;
939 }
940 else {
941 dst->f[i] = recip;
942 }
943 }
944 }
945 }
946
947 static void
948 micro_lt(
949 union tgsi_exec_channel *dst,
950 const union tgsi_exec_channel *src0,
951 const union tgsi_exec_channel *src1,
952 const union tgsi_exec_channel *src2,
953 const union tgsi_exec_channel *src3 )
954 {
955 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
956 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
957 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
958 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
959 }
960
961 static void
962 micro_max(union tgsi_exec_channel *dst,
963 const union tgsi_exec_channel *src0,
964 const union tgsi_exec_channel *src1)
965 {
966 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
967 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
968 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
969 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
970 }
971
972 static void
973 micro_min(union tgsi_exec_channel *dst,
974 const union tgsi_exec_channel *src0,
975 const union tgsi_exec_channel *src1)
976 {
977 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
978 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
979 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
980 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
981 }
982
983 static void
984 micro_mul(union tgsi_exec_channel *dst,
985 const union tgsi_exec_channel *src0,
986 const union tgsi_exec_channel *src1)
987 {
988 dst->f[0] = src0->f[0] * src1->f[0];
989 dst->f[1] = src0->f[1] * src1->f[1];
990 dst->f[2] = src0->f[2] * src1->f[2];
991 dst->f[3] = src0->f[3] * src1->f[3];
992 }
993
994 static void
995 micro_neg(
996 union tgsi_exec_channel *dst,
997 const union tgsi_exec_channel *src )
998 {
999 dst->f[0] = -src->f[0];
1000 dst->f[1] = -src->f[1];
1001 dst->f[2] = -src->f[2];
1002 dst->f[3] = -src->f[3];
1003 }
1004
1005 static void
1006 micro_pow(
1007 union tgsi_exec_channel *dst,
1008 const union tgsi_exec_channel *src0,
1009 const union tgsi_exec_channel *src1 )
1010 {
1011 #if FAST_MATH
1012 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1013 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1014 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1015 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1016 #else
1017 dst->f[0] = powf( src0->f[0], src1->f[0] );
1018 dst->f[1] = powf( src0->f[1], src1->f[1] );
1019 dst->f[2] = powf( src0->f[2], src1->f[2] );
1020 dst->f[3] = powf( src0->f[3], src1->f[3] );
1021 #endif
1022 }
1023
1024 static void
1025 micro_sub(union tgsi_exec_channel *dst,
1026 const union tgsi_exec_channel *src0,
1027 const union tgsi_exec_channel *src1)
1028 {
1029 dst->f[0] = src0->f[0] - src1->f[0];
1030 dst->f[1] = src0->f[1] - src1->f[1];
1031 dst->f[2] = src0->f[2] - src1->f[2];
1032 dst->f[3] = src0->f[3] - src1->f[3];
1033 }
1034
1035 static void
1036 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1037 const uint file,
1038 const uint swizzle,
1039 const union tgsi_exec_channel *index,
1040 const union tgsi_exec_channel *index2D,
1041 union tgsi_exec_channel *chan)
1042 {
1043 uint i;
1044
1045 assert(swizzle < 4);
1046
1047 switch (file) {
1048 case TGSI_FILE_CONSTANT:
1049 for (i = 0; i < QUAD_SIZE; i++) {
1050 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1051 assert(mach->Consts[index2D->i[i]]);
1052
1053 if (index->i[i] < 0) {
1054 chan->u[i] = 0;
1055 } else {
1056 /* NOTE: copying the const value as a uint instead of float */
1057 const uint constbuf = index2D->i[i];
1058 const uint *buf = (const uint *)mach->Consts[constbuf];
1059 const int pos = index->i[i] * 4 + swizzle;
1060 /* const buffer bounds check */
1061 if (pos < 0 || pos >= mach->ConstsSize[constbuf]) {
1062 if (0) {
1063 /* Debug: print warning */
1064 static int count = 0;
1065 if (count++ < 100)
1066 debug_printf("TGSI Exec: const buffer index %d"
1067 " out of bounds\n", pos);
1068 }
1069 chan->u[i] = 0;
1070 }
1071 else
1072 chan->u[i] = buf[pos];
1073 }
1074 }
1075 break;
1076
1077 case TGSI_FILE_INPUT:
1078 for (i = 0; i < QUAD_SIZE; i++) {
1079 /*
1080 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1081 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1082 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1083 index2D->i[i], index->i[i]);
1084 }*/
1085 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1086 assert(pos >= 0);
1087 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1088 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1089 }
1090 break;
1091
1092 case TGSI_FILE_SYSTEM_VALUE:
1093 /* XXX no swizzling at this point. Will be needed if we put
1094 * gl_FragCoord, for example, in a sys value register.
1095 */
1096 for (i = 0; i < QUAD_SIZE; i++) {
1097 chan->f[i] = mach->SystemValue[index->i[i]][0];
1098 }
1099 break;
1100
1101 case TGSI_FILE_TEMPORARY:
1102 for (i = 0; i < QUAD_SIZE; i++) {
1103 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1104 assert(index2D->i[i] == 0);
1105
1106 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1107 }
1108 break;
1109
1110 case TGSI_FILE_TEMPORARY_ARRAY:
1111 for (i = 0; i < QUAD_SIZE; i++) {
1112 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1113 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1114
1115 chan->u[i] =
1116 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1117 }
1118 break;
1119
1120 case TGSI_FILE_IMMEDIATE:
1121 for (i = 0; i < QUAD_SIZE; i++) {
1122 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1123 assert(index2D->i[i] == 0);
1124
1125 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1126 }
1127 break;
1128
1129 case TGSI_FILE_IMMEDIATE_ARRAY:
1130 for (i = 0; i < QUAD_SIZE; i++) {
1131 assert(index2D->i[i] == 0);
1132
1133 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1134 }
1135 break;
1136
1137 case TGSI_FILE_ADDRESS:
1138 for (i = 0; i < QUAD_SIZE; i++) {
1139 assert(index->i[i] >= 0);
1140 assert(index2D->i[i] == 0);
1141
1142 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1143 }
1144 break;
1145
1146 case TGSI_FILE_PREDICATE:
1147 for (i = 0; i < QUAD_SIZE; i++) {
1148 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1149 assert(index2D->i[i] == 0);
1150
1151 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1152 }
1153 break;
1154
1155 case TGSI_FILE_OUTPUT:
1156 /* vertex/fragment output vars can be read too */
1157 for (i = 0; i < QUAD_SIZE; i++) {
1158 assert(index->i[i] >= 0);
1159 assert(index2D->i[i] == 0);
1160
1161 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1162 }
1163 break;
1164
1165 default:
1166 assert(0);
1167 for (i = 0; i < QUAD_SIZE; i++) {
1168 chan->u[i] = 0;
1169 }
1170 }
1171 }
1172
1173 static void
1174 fetch_source(const struct tgsi_exec_machine *mach,
1175 union tgsi_exec_channel *chan,
1176 const struct tgsi_full_src_register *reg,
1177 const uint chan_index,
1178 enum tgsi_exec_datatype src_datatype)
1179 {
1180 union tgsi_exec_channel index;
1181 union tgsi_exec_channel index2D;
1182 uint swizzle;
1183
1184 /* We start with a direct index into a register file.
1185 *
1186 * file[1],
1187 * where:
1188 * file = Register.File
1189 * [1] = Register.Index
1190 */
1191 index.i[0] =
1192 index.i[1] =
1193 index.i[2] =
1194 index.i[3] = reg->Register.Index;
1195
1196 /* There is an extra source register that indirectly subscripts
1197 * a register file. The direct index now becomes an offset
1198 * that is being added to the indirect register.
1199 *
1200 * file[ind[2].x+1],
1201 * where:
1202 * ind = Indirect.File
1203 * [2] = Indirect.Index
1204 * .x = Indirect.SwizzleX
1205 */
1206 if (reg->Register.Indirect) {
1207 union tgsi_exec_channel index2;
1208 union tgsi_exec_channel indir_index;
1209 const uint execmask = mach->ExecMask;
1210 uint i;
1211
1212 /* which address register (always zero now) */
1213 index2.i[0] =
1214 index2.i[1] =
1215 index2.i[2] =
1216 index2.i[3] = reg->Indirect.Index;
1217 assert(reg->Indirect.File == TGSI_FILE_ADDRESS);
1218 /* get current value of address register[swizzle] */
1219 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1220 fetch_src_file_channel(mach,
1221 reg->Indirect.File,
1222 swizzle,
1223 &index2,
1224 &ZeroVec,
1225 &indir_index);
1226
1227 /* add value of address register to the offset */
1228 index.i[0] += indir_index.i[0];
1229 index.i[1] += indir_index.i[1];
1230 index.i[2] += indir_index.i[2];
1231 index.i[3] += indir_index.i[3];
1232
1233 /* for disabled execution channels, zero-out the index to
1234 * avoid using a potential garbage value.
1235 */
1236 for (i = 0; i < QUAD_SIZE; i++) {
1237 if ((execmask & (1 << i)) == 0)
1238 index.i[i] = 0;
1239 }
1240 }
1241
1242 /* There is an extra source register that is a second
1243 * subscript to a register file. Effectively it means that
1244 * the register file is actually a 2D array of registers.
1245 *
1246 * file[3][1],
1247 * where:
1248 * [3] = Dimension.Index
1249 */
1250 if (reg->Register.Dimension) {
1251 index2D.i[0] =
1252 index2D.i[1] =
1253 index2D.i[2] =
1254 index2D.i[3] = reg->Dimension.Index;
1255
1256 /* Again, the second subscript index can be addressed indirectly
1257 * identically to the first one.
1258 * Nothing stops us from indirectly addressing the indirect register,
1259 * but there is no need for that, so we won't exercise it.
1260 *
1261 * file[ind[4].y+3][1],
1262 * where:
1263 * ind = DimIndirect.File
1264 * [4] = DimIndirect.Index
1265 * .y = DimIndirect.SwizzleX
1266 */
1267 if (reg->Dimension.Indirect) {
1268 union tgsi_exec_channel index2;
1269 union tgsi_exec_channel indir_index;
1270 const uint execmask = mach->ExecMask;
1271 uint i;
1272
1273 index2.i[0] =
1274 index2.i[1] =
1275 index2.i[2] =
1276 index2.i[3] = reg->DimIndirect.Index;
1277
1278 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1279 fetch_src_file_channel(mach,
1280 reg->DimIndirect.File,
1281 swizzle,
1282 &index2,
1283 &ZeroVec,
1284 &indir_index);
1285
1286 index2D.i[0] += indir_index.i[0];
1287 index2D.i[1] += indir_index.i[1];
1288 index2D.i[2] += indir_index.i[2];
1289 index2D.i[3] += indir_index.i[3];
1290
1291 /* for disabled execution channels, zero-out the index to
1292 * avoid using a potential garbage value.
1293 */
1294 for (i = 0; i < QUAD_SIZE; i++) {
1295 if ((execmask & (1 << i)) == 0) {
1296 index2D.i[i] = 0;
1297 }
1298 }
1299 }
1300
1301 /* If by any chance there was a need for a 3D array of register
1302 * files, we would have to check whether Dimension is followed
1303 * by a dimension register and continue the saga.
1304 */
1305 } else {
1306 index2D.i[0] =
1307 index2D.i[1] =
1308 index2D.i[2] =
1309 index2D.i[3] = 0;
1310 }
1311
1312 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1313 fetch_src_file_channel(mach,
1314 reg->Register.File,
1315 swizzle,
1316 &index,
1317 &index2D,
1318 chan);
1319
1320 if (reg->Register.Absolute) {
1321 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1322 micro_abs(chan, chan);
1323 } else {
1324 micro_iabs(chan, chan);
1325 }
1326 }
1327
1328 if (reg->Register.Negate) {
1329 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1330 micro_neg(chan, chan);
1331 } else {
1332 micro_ineg(chan, chan);
1333 }
1334 }
1335 }
1336
1337 static void
1338 store_dest(struct tgsi_exec_machine *mach,
1339 const union tgsi_exec_channel *chan,
1340 const struct tgsi_full_dst_register *reg,
1341 const struct tgsi_full_instruction *inst,
1342 uint chan_index,
1343 enum tgsi_exec_datatype dst_datatype)
1344 {
1345 uint i;
1346 union tgsi_exec_channel null;
1347 union tgsi_exec_channel *dst;
1348 union tgsi_exec_channel index2D;
1349 uint execmask = mach->ExecMask;
1350 int offset = 0; /* indirection offset */
1351 int index;
1352
1353 /* for debugging */
1354 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1355 check_inf_or_nan(chan);
1356 }
1357
1358 /* There is an extra source register that indirectly subscripts
1359 * a register file. The direct index now becomes an offset
1360 * that is being added to the indirect register.
1361 *
1362 * file[ind[2].x+1],
1363 * where:
1364 * ind = Indirect.File
1365 * [2] = Indirect.Index
1366 * .x = Indirect.SwizzleX
1367 */
1368 if (reg->Register.Indirect) {
1369 union tgsi_exec_channel index;
1370 union tgsi_exec_channel indir_index;
1371 uint swizzle;
1372
1373 /* which address register (always zero for now) */
1374 index.i[0] =
1375 index.i[1] =
1376 index.i[2] =
1377 index.i[3] = reg->Indirect.Index;
1378
1379 /* get current value of address register[swizzle] */
1380 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1381
1382 /* fetch values from the address/indirection register */
1383 fetch_src_file_channel(mach,
1384 reg->Indirect.File,
1385 swizzle,
1386 &index,
1387 &ZeroVec,
1388 &indir_index);
1389
1390 /* save indirection offset */
1391 offset = indir_index.i[0];
1392 }
1393
1394 /* There is an extra source register that is a second
1395 * subscript to a register file. Effectively it means that
1396 * the register file is actually a 2D array of registers.
1397 *
1398 * file[3][1],
1399 * where:
1400 * [3] = Dimension.Index
1401 */
1402 if (reg->Register.Dimension) {
1403 index2D.i[0] =
1404 index2D.i[1] =
1405 index2D.i[2] =
1406 index2D.i[3] = reg->Dimension.Index;
1407
1408 /* Again, the second subscript index can be addressed indirectly
1409 * identically to the first one.
1410 * Nothing stops us from indirectly addressing the indirect register,
1411 * but there is no need for that, so we won't exercise it.
1412 *
1413 * file[ind[4].y+3][1],
1414 * where:
1415 * ind = DimIndirect.File
1416 * [4] = DimIndirect.Index
1417 * .y = DimIndirect.SwizzleX
1418 */
1419 if (reg->Dimension.Indirect) {
1420 union tgsi_exec_channel index2;
1421 union tgsi_exec_channel indir_index;
1422 const uint execmask = mach->ExecMask;
1423 unsigned swizzle;
1424 uint i;
1425
1426 index2.i[0] =
1427 index2.i[1] =
1428 index2.i[2] =
1429 index2.i[3] = reg->DimIndirect.Index;
1430
1431 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1432 fetch_src_file_channel(mach,
1433 reg->DimIndirect.File,
1434 swizzle,
1435 &index2,
1436 &ZeroVec,
1437 &indir_index);
1438
1439 index2D.i[0] += indir_index.i[0];
1440 index2D.i[1] += indir_index.i[1];
1441 index2D.i[2] += indir_index.i[2];
1442 index2D.i[3] += indir_index.i[3];
1443
1444 /* for disabled execution channels, zero-out the index to
1445 * avoid using a potential garbage value.
1446 */
1447 for (i = 0; i < QUAD_SIZE; i++) {
1448 if ((execmask & (1 << i)) == 0) {
1449 index2D.i[i] = 0;
1450 }
1451 }
1452 }
1453
1454 /* If by any chance there was a need for a 3D array of register
1455 * files, we would have to check whether Dimension is followed
1456 * by a dimension register and continue the saga.
1457 */
1458 } else {
1459 index2D.i[0] =
1460 index2D.i[1] =
1461 index2D.i[2] =
1462 index2D.i[3] = 0;
1463 }
1464
1465 switch (reg->Register.File) {
1466 case TGSI_FILE_NULL:
1467 dst = &null;
1468 break;
1469
1470 case TGSI_FILE_OUTPUT:
1471 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1472 + reg->Register.Index;
1473 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1474 #if 0
1475 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1476 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1477 for (i = 0; i < QUAD_SIZE; i++)
1478 if (execmask & (1 << i))
1479 fprintf(stderr, "%f, ", chan->f[i]);
1480 fprintf(stderr, ")\n");
1481 }
1482 #endif
1483 break;
1484
1485 case TGSI_FILE_TEMPORARY:
1486 index = reg->Register.Index;
1487 assert( index < TGSI_EXEC_NUM_TEMPS );
1488 dst = &mach->Temps[offset + index].xyzw[chan_index];
1489 break;
1490
1491 case TGSI_FILE_TEMPORARY_ARRAY:
1492 index = reg->Register.Index;
1493 assert( index < TGSI_EXEC_NUM_TEMPS );
1494 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1495 /* XXX we use index2D.i[0] here but somehow we might
1496 * end up with someone trying to store indirectly in
1497 * different buffers */
1498 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1499 break;
1500
1501 case TGSI_FILE_ADDRESS:
1502 index = reg->Register.Index;
1503 dst = &mach->Addrs[index].xyzw[chan_index];
1504 break;
1505
1506 case TGSI_FILE_PREDICATE:
1507 index = reg->Register.Index;
1508 assert(index < TGSI_EXEC_NUM_PREDS);
1509 dst = &mach->Predicates[index].xyzw[chan_index];
1510 break;
1511
1512 default:
1513 assert( 0 );
1514 return;
1515 }
1516
1517 if (inst->Instruction.Predicate) {
1518 uint swizzle;
1519 union tgsi_exec_channel *pred;
1520
1521 switch (chan_index) {
1522 case CHAN_X:
1523 swizzle = inst->Predicate.SwizzleX;
1524 break;
1525 case CHAN_Y:
1526 swizzle = inst->Predicate.SwizzleY;
1527 break;
1528 case CHAN_Z:
1529 swizzle = inst->Predicate.SwizzleZ;
1530 break;
1531 case CHAN_W:
1532 swizzle = inst->Predicate.SwizzleW;
1533 break;
1534 default:
1535 assert(0);
1536 return;
1537 }
1538
1539 assert(inst->Predicate.Index == 0);
1540
1541 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1542
1543 if (inst->Predicate.Negate) {
1544 for (i = 0; i < QUAD_SIZE; i++) {
1545 if (pred->u[i]) {
1546 execmask &= ~(1 << i);
1547 }
1548 }
1549 } else {
1550 for (i = 0; i < QUAD_SIZE; i++) {
1551 if (!pred->u[i]) {
1552 execmask &= ~(1 << i);
1553 }
1554 }
1555 }
1556 }
1557
1558 switch (inst->Instruction.Saturate) {
1559 case TGSI_SAT_NONE:
1560 for (i = 0; i < QUAD_SIZE; i++)
1561 if (execmask & (1 << i))
1562 dst->i[i] = chan->i[i];
1563 break;
1564
1565 case TGSI_SAT_ZERO_ONE:
1566 for (i = 0; i < QUAD_SIZE; i++)
1567 if (execmask & (1 << i)) {
1568 if (chan->f[i] < 0.0f)
1569 dst->f[i] = 0.0f;
1570 else if (chan->f[i] > 1.0f)
1571 dst->f[i] = 1.0f;
1572 else
1573 dst->i[i] = chan->i[i];
1574 }
1575 break;
1576
1577 case TGSI_SAT_MINUS_PLUS_ONE:
1578 for (i = 0; i < QUAD_SIZE; i++)
1579 if (execmask & (1 << i)) {
1580 if (chan->f[i] < -1.0f)
1581 dst->f[i] = -1.0f;
1582 else if (chan->f[i] > 1.0f)
1583 dst->f[i] = 1.0f;
1584 else
1585 dst->i[i] = chan->i[i];
1586 }
1587 break;
1588
1589 default:
1590 assert( 0 );
1591 }
1592 }
1593
1594 #define FETCH(VAL,INDEX,CHAN)\
1595 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1596
1597 #define IFETCH(VAL,INDEX,CHAN)\
1598 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1599
1600
1601 /**
1602 * Execute ARB-style KIL which is predicated by a src register.
1603 * Kill fragment if any of the four values is less than zero.
1604 */
1605 static void
1606 exec_kil(struct tgsi_exec_machine *mach,
1607 const struct tgsi_full_instruction *inst)
1608 {
1609 uint uniquemask;
1610 uint chan_index;
1611 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1612 union tgsi_exec_channel r[1];
1613
1614 /* This mask stores component bits that were already tested. */
1615 uniquemask = 0;
1616
1617 for (chan_index = 0; chan_index < 4; chan_index++)
1618 {
1619 uint swizzle;
1620 uint i;
1621
1622 /* unswizzle channel */
1623 swizzle = tgsi_util_get_full_src_register_swizzle (
1624 &inst->Src[0],
1625 chan_index);
1626
1627 /* check if the component has not been already tested */
1628 if (uniquemask & (1 << swizzle))
1629 continue;
1630 uniquemask |= 1 << swizzle;
1631
1632 FETCH(&r[0], 0, chan_index);
1633 for (i = 0; i < 4; i++)
1634 if (r[0].f[i] < 0.0f)
1635 kilmask |= 1 << i;
1636 }
1637
1638 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1639 }
1640
1641 /**
1642 * Execute NVIDIA-style KIL which is predicated by a condition code.
1643 * Kill fragment if the condition code is TRUE.
1644 */
1645 static void
1646 exec_kilp(struct tgsi_exec_machine *mach,
1647 const struct tgsi_full_instruction *inst)
1648 {
1649 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1650
1651 /* "unconditional" kil */
1652 kilmask = mach->ExecMask;
1653 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1654 }
1655
1656 static void
1657 emit_vertex(struct tgsi_exec_machine *mach)
1658 {
1659 /* FIXME: check for exec mask correctly
1660 unsigned i;
1661 for (i = 0; i < QUAD_SIZE; ++i) {
1662 if ((mach->ExecMask & (1 << i)))
1663 */
1664 if (mach->ExecMask) {
1665 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1666 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1667 }
1668 }
1669
1670 static void
1671 emit_primitive(struct tgsi_exec_machine *mach)
1672 {
1673 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1674 /* FIXME: check for exec mask correctly
1675 unsigned i;
1676 for (i = 0; i < QUAD_SIZE; ++i) {
1677 if ((mach->ExecMask & (1 << i)))
1678 */
1679 if (mach->ExecMask) {
1680 ++(*prim_count);
1681 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1682 mach->Primitives[*prim_count] = 0;
1683 }
1684 }
1685
1686 static void
1687 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1688 {
1689 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1690 int emitted_verts =
1691 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1692 if (emitted_verts) {
1693 emit_primitive(mach);
1694 }
1695 }
1696 }
1697
1698
1699 /*
1700 * Fetch four texture samples using STR texture coordinates.
1701 */
1702 static void
1703 fetch_texel( struct tgsi_sampler *sampler,
1704 const union tgsi_exec_channel *s,
1705 const union tgsi_exec_channel *t,
1706 const union tgsi_exec_channel *p,
1707 const union tgsi_exec_channel *c0,
1708 enum tgsi_sampler_control control,
1709 union tgsi_exec_channel *r,
1710 union tgsi_exec_channel *g,
1711 union tgsi_exec_channel *b,
1712 union tgsi_exec_channel *a )
1713 {
1714 uint j;
1715 float rgba[NUM_CHANNELS][QUAD_SIZE];
1716
1717 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1718
1719 for (j = 0; j < 4; j++) {
1720 r->f[j] = rgba[0][j];
1721 g->f[j] = rgba[1][j];
1722 b->f[j] = rgba[2][j];
1723 a->f[j] = rgba[3][j];
1724 }
1725 }
1726
1727
1728 #define TEX_MODIFIER_NONE 0
1729 #define TEX_MODIFIER_PROJECTED 1
1730 #define TEX_MODIFIER_LOD_BIAS 2
1731 #define TEX_MODIFIER_EXPLICIT_LOD 3
1732
1733
1734 static void
1735 exec_tex(struct tgsi_exec_machine *mach,
1736 const struct tgsi_full_instruction *inst,
1737 uint modifier)
1738 {
1739 const uint unit = inst->Src[1].Register.Index;
1740 union tgsi_exec_channel r[4];
1741 const union tgsi_exec_channel *lod = &ZeroVec;
1742 enum tgsi_sampler_control control;
1743 uint chan;
1744
1745 if (modifier != TEX_MODIFIER_NONE) {
1746 FETCH(&r[3], 0, CHAN_W);
1747 if (modifier != TEX_MODIFIER_PROJECTED) {
1748 lod = &r[3];
1749 }
1750 }
1751
1752 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1753 control = tgsi_sampler_lod_explicit;
1754 } else {
1755 control = tgsi_sampler_lod_bias;
1756 }
1757
1758 switch (inst->Texture.Texture) {
1759 case TGSI_TEXTURE_1D:
1760 case TGSI_TEXTURE_SHADOW1D:
1761 FETCH(&r[0], 0, CHAN_X);
1762
1763 if (modifier == TEX_MODIFIER_PROJECTED) {
1764 micro_div(&r[0], &r[0], &r[3]);
1765 }
1766
1767 fetch_texel(mach->Samplers[unit],
1768 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1769 control,
1770 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1771 break;
1772
1773 case TGSI_TEXTURE_2D:
1774 case TGSI_TEXTURE_RECT:
1775 case TGSI_TEXTURE_SHADOW2D:
1776 case TGSI_TEXTURE_SHADOWRECT:
1777 FETCH(&r[0], 0, CHAN_X);
1778 FETCH(&r[1], 0, CHAN_Y);
1779 FETCH(&r[2], 0, CHAN_Z);
1780
1781 if (modifier == TEX_MODIFIER_PROJECTED) {
1782 micro_div(&r[0], &r[0], &r[3]);
1783 micro_div(&r[1], &r[1], &r[3]);
1784 micro_div(&r[2], &r[2], &r[3]);
1785 }
1786
1787 fetch_texel(mach->Samplers[unit],
1788 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1789 control,
1790 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1791 break;
1792
1793 case TGSI_TEXTURE_1D_ARRAY:
1794 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1795 FETCH(&r[0], 0, CHAN_X);
1796 FETCH(&r[1], 0, CHAN_Y);
1797
1798 if (modifier == TEX_MODIFIER_PROJECTED) {
1799 micro_div(&r[0], &r[0], &r[3]);
1800 }
1801
1802 fetch_texel(mach->Samplers[unit],
1803 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1804 control,
1805 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1806 break;
1807
1808 case TGSI_TEXTURE_2D_ARRAY:
1809 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1810 FETCH(&r[0], 0, CHAN_X);
1811 FETCH(&r[1], 0, CHAN_Y);
1812 FETCH(&r[2], 0, CHAN_Z);
1813
1814 if (modifier == TEX_MODIFIER_PROJECTED) {
1815 micro_div(&r[0], &r[0], &r[3]);
1816 micro_div(&r[1], &r[1], &r[3]);
1817 }
1818
1819 fetch_texel(mach->Samplers[unit],
1820 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1821 control,
1822 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1823 break;
1824
1825 case TGSI_TEXTURE_3D:
1826 case TGSI_TEXTURE_CUBE:
1827 FETCH(&r[0], 0, CHAN_X);
1828 FETCH(&r[1], 0, CHAN_Y);
1829 FETCH(&r[2], 0, CHAN_Z);
1830
1831 if (modifier == TEX_MODIFIER_PROJECTED) {
1832 micro_div(&r[0], &r[0], &r[3]);
1833 micro_div(&r[1], &r[1], &r[3]);
1834 micro_div(&r[2], &r[2], &r[3]);
1835 }
1836
1837 fetch_texel(mach->Samplers[unit],
1838 &r[0], &r[1], &r[2], lod,
1839 control,
1840 &r[0], &r[1], &r[2], &r[3]);
1841 break;
1842
1843 default:
1844 assert(0);
1845 }
1846
1847 #if 0
1848 debug_printf("fetch r: %g %g %g %g\n",
1849 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1850 debug_printf("fetch g: %g %g %g %g\n",
1851 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1852 debug_printf("fetch b: %g %g %g %g\n",
1853 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1854 debug_printf("fetch a: %g %g %g %g\n",
1855 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1856 #endif
1857
1858 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1859 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1860 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1861 }
1862 }
1863 }
1864
1865 static void
1866 exec_txd(struct tgsi_exec_machine *mach,
1867 const struct tgsi_full_instruction *inst)
1868 {
1869 const uint unit = inst->Src[3].Register.Index;
1870 union tgsi_exec_channel r[4];
1871 uint chan;
1872
1873 /*
1874 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1875 */
1876
1877 switch (inst->Texture.Texture) {
1878 case TGSI_TEXTURE_1D:
1879 case TGSI_TEXTURE_SHADOW1D:
1880
1881 FETCH(&r[0], 0, CHAN_X);
1882
1883 fetch_texel(mach->Samplers[unit],
1884 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1885 tgsi_sampler_lod_bias,
1886 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1887 break;
1888
1889 case TGSI_TEXTURE_1D_ARRAY:
1890 case TGSI_TEXTURE_2D:
1891 case TGSI_TEXTURE_RECT:
1892 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1893 case TGSI_TEXTURE_SHADOW2D:
1894 case TGSI_TEXTURE_SHADOWRECT:
1895
1896 FETCH(&r[0], 0, CHAN_X);
1897 FETCH(&r[1], 0, CHAN_Y);
1898 FETCH(&r[2], 0, CHAN_Z);
1899
1900 fetch_texel(mach->Samplers[unit],
1901 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1902 tgsi_sampler_lod_bias,
1903 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1904 break;
1905
1906 case TGSI_TEXTURE_2D_ARRAY:
1907 case TGSI_TEXTURE_3D:
1908 case TGSI_TEXTURE_CUBE:
1909
1910 FETCH(&r[0], 0, CHAN_X);
1911 FETCH(&r[1], 0, CHAN_Y);
1912 FETCH(&r[2], 0, CHAN_Z);
1913
1914 fetch_texel(mach->Samplers[unit],
1915 &r[0], &r[1], &r[2], &ZeroVec,
1916 tgsi_sampler_lod_bias,
1917 &r[0], &r[1], &r[2], &r[3]);
1918 break;
1919
1920 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1921
1922 FETCH(&r[0], 0, CHAN_X);
1923 FETCH(&r[1], 0, CHAN_Y);
1924 FETCH(&r[2], 0, CHAN_Z);
1925 FETCH(&r[3], 0, CHAN_W);
1926
1927 fetch_texel(mach->Samplers[unit],
1928 &r[0], &r[1], &r[2], &r[3],
1929 tgsi_sampler_lod_bias,
1930 &r[0], &r[1], &r[2], &r[3]);
1931 break;
1932
1933 default:
1934 assert(0);
1935 }
1936
1937 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1938 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1939 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1940 }
1941 }
1942 }
1943
1944
1945 static void
1946 exec_txf(struct tgsi_exec_machine *mach,
1947 const struct tgsi_full_instruction *inst)
1948 {
1949 struct tgsi_sampler *sampler;
1950 const uint unit = inst->Src[2].Register.Index;
1951 union tgsi_exec_channel r[4];
1952 union tgsi_exec_channel offset[3];
1953 uint chan;
1954 float rgba[NUM_CHANNELS][QUAD_SIZE];
1955 int j;
1956 int8_t offsets[3];
1957
1958 if (inst->Texture.NumOffsets == 1) {
1959 union tgsi_exec_channel index;
1960 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1961 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1962 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1963 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1964 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1965 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1966 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1967 offsets[0] = offset[0].i[0];
1968 offsets[1] = offset[1].i[0];
1969 offsets[2] = offset[2].i[0];
1970 } else
1971 offsets[0] = offsets[1] = offsets[2] = 0;
1972
1973 IFETCH(&r[3], 0, CHAN_W);
1974
1975 switch(inst->Texture.Texture) {
1976 case TGSI_TEXTURE_3D:
1977 case TGSI_TEXTURE_2D_ARRAY:
1978 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1979 IFETCH(&r[2], 0, CHAN_Z);
1980 /* fallthrough */
1981 case TGSI_TEXTURE_2D:
1982 case TGSI_TEXTURE_RECT:
1983 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1984 case TGSI_TEXTURE_SHADOW2D:
1985 case TGSI_TEXTURE_SHADOWRECT:
1986 case TGSI_TEXTURE_1D_ARRAY:
1987 IFETCH(&r[1], 0, CHAN_Y);
1988 /* fallthrough */
1989 case TGSI_TEXTURE_1D:
1990 case TGSI_TEXTURE_SHADOW1D:
1991 IFETCH(&r[0], 0, CHAN_X);
1992 break;
1993 default:
1994 assert(0);
1995 break;
1996 }
1997
1998 sampler = mach->Samplers[unit];
1999 sampler->get_texel(sampler, r[0].i, r[1].i, r[2].i, r[3].i,
2000 offsets, rgba);
2001
2002 for (j = 0; j < QUAD_SIZE; j++) {
2003 r[0].f[j] = rgba[0][j];
2004 r[1].f[j] = rgba[1][j];
2005 r[2].f[j] = rgba[2][j];
2006 r[3].f[j] = rgba[3][j];
2007 }
2008
2009 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2010 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2011 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2012 }
2013 }
2014 }
2015
2016 static void
2017 exec_txq(struct tgsi_exec_machine *mach,
2018 const struct tgsi_full_instruction *inst)
2019 {
2020 struct tgsi_sampler *sampler;
2021 const uint unit = inst->Src[1].Register.Index;
2022 int result[4];
2023 union tgsi_exec_channel r[4], src;
2024 uint chan;
2025 int i,j;
2026
2027 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_INT);
2028 sampler = mach->Samplers[unit];
2029
2030 sampler->get_dims(sampler, src.i[0], result);
2031
2032 for (i = 0; i < QUAD_SIZE; i++) {
2033 for (j = 0; j < 4; j++) {
2034 r[j].i[i] = result[j];
2035 }
2036 }
2037
2038 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2039 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2040 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2041 TGSI_EXEC_DATA_INT);
2042 }
2043 }
2044 }
2045
2046 static void
2047 exec_sample(struct tgsi_exec_machine *mach,
2048 const struct tgsi_full_instruction *inst,
2049 uint modifier)
2050 {
2051 const uint resource_unit = inst->Src[1].Register.Index;
2052 const uint sampler_unit = inst->Src[2].Register.Index;
2053 union tgsi_exec_channel r[4];
2054 const union tgsi_exec_channel *lod = &ZeroVec;
2055 enum tgsi_sampler_control control;
2056 uint chan;
2057
2058 if (modifier != TEX_MODIFIER_NONE) {
2059 if (modifier == TEX_MODIFIER_LOD_BIAS)
2060 FETCH(&r[3], 3, CHAN_X);
2061 else /*TEX_MODIFIER_LOD*/
2062 FETCH(&r[3], 0, CHAN_W);
2063
2064 if (modifier != TEX_MODIFIER_PROJECTED) {
2065 lod = &r[3];
2066 }
2067 }
2068
2069 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2070 control = tgsi_sampler_lod_explicit;
2071 } else {
2072 control = tgsi_sampler_lod_bias;
2073 }
2074
2075 switch (mach->Resources[resource_unit].Resource) {
2076 case TGSI_TEXTURE_1D:
2077 case TGSI_TEXTURE_SHADOW1D:
2078 FETCH(&r[0], 0, CHAN_X);
2079
2080 if (modifier == TEX_MODIFIER_PROJECTED) {
2081 micro_div(&r[0], &r[0], &r[3]);
2082 }
2083
2084 fetch_texel(mach->Samplers[sampler_unit],
2085 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
2086 control,
2087 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2088 break;
2089
2090 case TGSI_TEXTURE_1D_ARRAY:
2091 case TGSI_TEXTURE_2D:
2092 case TGSI_TEXTURE_RECT:
2093 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2094 case TGSI_TEXTURE_SHADOW2D:
2095 case TGSI_TEXTURE_SHADOWRECT:
2096 FETCH(&r[0], 0, CHAN_X);
2097 FETCH(&r[1], 0, CHAN_Y);
2098 FETCH(&r[2], 0, CHAN_Z);
2099
2100 if (modifier == TEX_MODIFIER_PROJECTED) {
2101 micro_div(&r[0], &r[0], &r[3]);
2102 micro_div(&r[1], &r[1], &r[3]);
2103 micro_div(&r[2], &r[2], &r[3]);
2104 }
2105
2106 fetch_texel(mach->Samplers[sampler_unit],
2107 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
2108 control,
2109 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2110 break;
2111
2112 case TGSI_TEXTURE_2D_ARRAY:
2113 case TGSI_TEXTURE_3D:
2114 case TGSI_TEXTURE_CUBE:
2115 FETCH(&r[0], 0, CHAN_X);
2116 FETCH(&r[1], 0, CHAN_Y);
2117 FETCH(&r[2], 0, CHAN_Z);
2118
2119 if (modifier == TEX_MODIFIER_PROJECTED) {
2120 micro_div(&r[0], &r[0], &r[3]);
2121 micro_div(&r[1], &r[1], &r[3]);
2122 micro_div(&r[2], &r[2], &r[3]);
2123 }
2124
2125 fetch_texel(mach->Samplers[sampler_unit],
2126 &r[0], &r[1], &r[2], lod,
2127 control,
2128 &r[0], &r[1], &r[2], &r[3]);
2129 break;
2130
2131 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2132 FETCH(&r[0], 0, CHAN_X);
2133 FETCH(&r[1], 0, CHAN_Y);
2134 FETCH(&r[2], 0, CHAN_Z);
2135 FETCH(&r[3], 0, CHAN_W);
2136
2137 assert(modifier != TEX_MODIFIER_PROJECTED);
2138
2139 fetch_texel(mach->Samplers[sampler_unit],
2140 &r[0], &r[1], &r[2], &r[3],
2141 control,
2142 &r[0], &r[1], &r[2], &r[3]);
2143 break;
2144
2145 default:
2146 assert(0);
2147 }
2148
2149 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2150 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2151 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2152 }
2153 }
2154 }
2155
2156 static void
2157 exec_sample_d(struct tgsi_exec_machine *mach,
2158 const struct tgsi_full_instruction *inst)
2159 {
2160 const uint resource_unit = inst->Src[1].Register.Index;
2161 const uint sampler_unit = inst->Src[2].Register.Index;
2162 union tgsi_exec_channel r[4];
2163 uint chan;
2164 /*
2165 * XXX: This is fake SAMPLE_D -- the derivatives are not taken into account, yet.
2166 */
2167
2168 switch (mach->Resources[resource_unit].Resource) {
2169 case TGSI_TEXTURE_1D:
2170 case TGSI_TEXTURE_SHADOW1D:
2171
2172 FETCH(&r[0], 0, CHAN_X);
2173
2174 fetch_texel(mach->Samplers[sampler_unit],
2175 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
2176 tgsi_sampler_lod_bias,
2177 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2178 break;
2179
2180 case TGSI_TEXTURE_2D:
2181 case TGSI_TEXTURE_RECT:
2182 case TGSI_TEXTURE_SHADOW2D:
2183 case TGSI_TEXTURE_SHADOWRECT:
2184
2185 FETCH(&r[0], 0, CHAN_X);
2186 FETCH(&r[1], 0, CHAN_Y);
2187 FETCH(&r[2], 0, CHAN_Z);
2188
2189 fetch_texel(mach->Samplers[sampler_unit],
2190 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
2191 tgsi_sampler_lod_bias,
2192 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2193 break;
2194
2195 case TGSI_TEXTURE_3D:
2196 case TGSI_TEXTURE_CUBE:
2197
2198 FETCH(&r[0], 0, CHAN_X);
2199 FETCH(&r[1], 0, CHAN_Y);
2200 FETCH(&r[2], 0, CHAN_Z);
2201
2202 fetch_texel(mach->Samplers[sampler_unit],
2203 &r[0], &r[1], &r[2], &ZeroVec,
2204 tgsi_sampler_lod_bias,
2205 &r[0], &r[1], &r[2], &r[3]);
2206 break;
2207
2208 default:
2209 assert(0);
2210 }
2211
2212 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2213 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2214 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2215 }
2216 }
2217 }
2218
2219
2220 /**
2221 * Evaluate a constant-valued coefficient at the position of the
2222 * current quad.
2223 */
2224 static void
2225 eval_constant_coef(
2226 struct tgsi_exec_machine *mach,
2227 unsigned attrib,
2228 unsigned chan )
2229 {
2230 unsigned i;
2231
2232 for( i = 0; i < QUAD_SIZE; i++ ) {
2233 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2234 }
2235 }
2236
2237 /**
2238 * Evaluate a linear-valued coefficient at the position of the
2239 * current quad.
2240 */
2241 static void
2242 eval_linear_coef(
2243 struct tgsi_exec_machine *mach,
2244 unsigned attrib,
2245 unsigned chan )
2246 {
2247 const float x = mach->QuadPos.xyzw[0].f[0];
2248 const float y = mach->QuadPos.xyzw[1].f[0];
2249 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2250 const float dady = mach->InterpCoefs[attrib].dady[chan];
2251 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2252 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2253 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2254 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2255 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2256 }
2257
2258 /**
2259 * Evaluate a perspective-valued coefficient at the position of the
2260 * current quad.
2261 */
2262 static void
2263 eval_perspective_coef(
2264 struct tgsi_exec_machine *mach,
2265 unsigned attrib,
2266 unsigned chan )
2267 {
2268 const float x = mach->QuadPos.xyzw[0].f[0];
2269 const float y = mach->QuadPos.xyzw[1].f[0];
2270 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2271 const float dady = mach->InterpCoefs[attrib].dady[chan];
2272 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2273 const float *w = mach->QuadPos.xyzw[3].f;
2274 /* divide by W here */
2275 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2276 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2277 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2278 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2279 }
2280
2281
2282 typedef void (* eval_coef_func)(
2283 struct tgsi_exec_machine *mach,
2284 unsigned attrib,
2285 unsigned chan );
2286
2287 static void
2288 exec_declaration(struct tgsi_exec_machine *mach,
2289 const struct tgsi_full_declaration *decl)
2290 {
2291 if (decl->Declaration.File == TGSI_FILE_RESOURCE) {
2292 mach->Resources[decl->Range.First] = decl->Resource;
2293 return;
2294 }
2295
2296 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2297 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2298 uint first, last, mask;
2299
2300 first = decl->Range.First;
2301 last = decl->Range.Last;
2302 mask = decl->Declaration.UsageMask;
2303
2304 /* XXX we could remove this special-case code since
2305 * mach->InterpCoefs[first].a0 should already have the
2306 * front/back-face value. But we should first update the
2307 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2308 * Then, we could remove the tgsi_exec_machine::Face field.
2309 */
2310 /* XXX make FACE a system value */
2311 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2312 uint i;
2313
2314 assert(decl->Semantic.Index == 0);
2315 assert(first == last);
2316
2317 for (i = 0; i < QUAD_SIZE; i++) {
2318 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2319 }
2320 } else {
2321 eval_coef_func eval;
2322 uint i, j;
2323
2324 switch (decl->Declaration.Interpolate) {
2325 case TGSI_INTERPOLATE_CONSTANT:
2326 eval = eval_constant_coef;
2327 break;
2328
2329 case TGSI_INTERPOLATE_LINEAR:
2330 eval = eval_linear_coef;
2331 break;
2332
2333 case TGSI_INTERPOLATE_PERSPECTIVE:
2334 eval = eval_perspective_coef;
2335 break;
2336
2337 default:
2338 assert(0);
2339 return;
2340 }
2341
2342 for (j = 0; j < NUM_CHANNELS; j++) {
2343 if (mask & (1 << j)) {
2344 for (i = first; i <= last; i++) {
2345 eval(mach, i, j);
2346 }
2347 }
2348 }
2349 }
2350 }
2351 }
2352
2353 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2354 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2355 }
2356 }
2357
2358
2359 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2360
2361 static void
2362 exec_vector(struct tgsi_exec_machine *mach,
2363 const struct tgsi_full_instruction *inst,
2364 micro_op op,
2365 enum tgsi_exec_datatype dst_datatype)
2366 {
2367 unsigned int chan;
2368
2369 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2370 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2371 union tgsi_exec_channel dst;
2372
2373 op(&dst);
2374 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2375 }
2376 }
2377 }
2378
2379 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2380 const union tgsi_exec_channel *src);
2381
2382 static void
2383 exec_scalar_unary(struct tgsi_exec_machine *mach,
2384 const struct tgsi_full_instruction *inst,
2385 micro_unary_op op,
2386 enum tgsi_exec_datatype dst_datatype,
2387 enum tgsi_exec_datatype src_datatype)
2388 {
2389 unsigned int chan;
2390 union tgsi_exec_channel src;
2391 union tgsi_exec_channel dst;
2392
2393 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
2394 op(&dst, &src);
2395 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2396 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2397 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2398 }
2399 }
2400 }
2401
2402 static void
2403 exec_vector_unary(struct tgsi_exec_machine *mach,
2404 const struct tgsi_full_instruction *inst,
2405 micro_unary_op op,
2406 enum tgsi_exec_datatype dst_datatype,
2407 enum tgsi_exec_datatype src_datatype)
2408 {
2409 unsigned int chan;
2410 struct tgsi_exec_vector dst;
2411
2412 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2413 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2414 union tgsi_exec_channel src;
2415
2416 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2417 op(&dst.xyzw[chan], &src);
2418 }
2419 }
2420 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2421 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2422 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2423 }
2424 }
2425 }
2426
2427 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2428 const union tgsi_exec_channel *src0,
2429 const union tgsi_exec_channel *src1);
2430
2431 static void
2432 exec_scalar_binary(struct tgsi_exec_machine *mach,
2433 const struct tgsi_full_instruction *inst,
2434 micro_binary_op op,
2435 enum tgsi_exec_datatype dst_datatype,
2436 enum tgsi_exec_datatype src_datatype)
2437 {
2438 unsigned int chan;
2439 union tgsi_exec_channel src[2];
2440 union tgsi_exec_channel dst;
2441
2442 fetch_source(mach, &src[0], &inst->Src[0], CHAN_X, src_datatype);
2443 fetch_source(mach, &src[1], &inst->Src[1], CHAN_Y, src_datatype);
2444 op(&dst, &src[0], &src[1]);
2445 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2446 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2447 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2448 }
2449 }
2450 }
2451
2452 static void
2453 exec_vector_binary(struct tgsi_exec_machine *mach,
2454 const struct tgsi_full_instruction *inst,
2455 micro_binary_op op,
2456 enum tgsi_exec_datatype dst_datatype,
2457 enum tgsi_exec_datatype src_datatype)
2458 {
2459 unsigned int chan;
2460 struct tgsi_exec_vector dst;
2461
2462 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2463 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2464 union tgsi_exec_channel src[2];
2465
2466 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2467 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2468 op(&dst.xyzw[chan], &src[0], &src[1]);
2469 }
2470 }
2471 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2472 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2473 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2474 }
2475 }
2476 }
2477
2478 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2479 const union tgsi_exec_channel *src0,
2480 const union tgsi_exec_channel *src1,
2481 const union tgsi_exec_channel *src2);
2482
2483 static void
2484 exec_vector_trinary(struct tgsi_exec_machine *mach,
2485 const struct tgsi_full_instruction *inst,
2486 micro_trinary_op op,
2487 enum tgsi_exec_datatype dst_datatype,
2488 enum tgsi_exec_datatype src_datatype)
2489 {
2490 unsigned int chan;
2491 struct tgsi_exec_vector dst;
2492
2493 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2494 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2495 union tgsi_exec_channel src[3];
2496
2497 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2498 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2499 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2500 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2501 }
2502 }
2503 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2504 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2505 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2506 }
2507 }
2508 }
2509
2510 static void
2511 exec_dp3(struct tgsi_exec_machine *mach,
2512 const struct tgsi_full_instruction *inst)
2513 {
2514 unsigned int chan;
2515 union tgsi_exec_channel arg[3];
2516
2517 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2518 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2519 micro_mul(&arg[2], &arg[0], &arg[1]);
2520
2521 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2522 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2523 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2524 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2525 }
2526
2527 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2528 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2529 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2530 }
2531 }
2532 }
2533
2534 static void
2535 exec_dp4(struct tgsi_exec_machine *mach,
2536 const struct tgsi_full_instruction *inst)
2537 {
2538 unsigned int chan;
2539 union tgsi_exec_channel arg[3];
2540
2541 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2542 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2543 micro_mul(&arg[2], &arg[0], &arg[1]);
2544
2545 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2546 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2547 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2548 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2549 }
2550
2551 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2552 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2553 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2554 }
2555 }
2556 }
2557
2558 static void
2559 exec_dp2a(struct tgsi_exec_machine *mach,
2560 const struct tgsi_full_instruction *inst)
2561 {
2562 unsigned int chan;
2563 union tgsi_exec_channel arg[3];
2564
2565 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2566 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2567 micro_mul(&arg[2], &arg[0], &arg[1]);
2568
2569 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2570 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2571 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2572
2573 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2574 micro_add(&arg[0], &arg[0], &arg[1]);
2575
2576 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2577 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2578 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2579 }
2580 }
2581 }
2582
2583 static void
2584 exec_dph(struct tgsi_exec_machine *mach,
2585 const struct tgsi_full_instruction *inst)
2586 {
2587 unsigned int chan;
2588 union tgsi_exec_channel arg[3];
2589
2590 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2591 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2592 micro_mul(&arg[2], &arg[0], &arg[1]);
2593
2594 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2595 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2596 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2597
2598 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2599 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2600 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2601
2602 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2603 micro_add(&arg[0], &arg[0], &arg[1]);
2604
2605 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2607 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2608 }
2609 }
2610 }
2611
2612 static void
2613 exec_dp2(struct tgsi_exec_machine *mach,
2614 const struct tgsi_full_instruction *inst)
2615 {
2616 unsigned int chan;
2617 union tgsi_exec_channel arg[3];
2618
2619 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2620 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2621 micro_mul(&arg[2], &arg[0], &arg[1]);
2622
2623 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2624 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2625 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2626
2627 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2628 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2629 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2630 }
2631 }
2632 }
2633
2634 static void
2635 exec_nrm4(struct tgsi_exec_machine *mach,
2636 const struct tgsi_full_instruction *inst)
2637 {
2638 unsigned int chan;
2639 union tgsi_exec_channel arg[4];
2640 union tgsi_exec_channel scale;
2641
2642 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2643 micro_mul(&scale, &arg[0], &arg[0]);
2644
2645 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2646 union tgsi_exec_channel product;
2647
2648 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2649 micro_mul(&product, &arg[chan], &arg[chan]);
2650 micro_add(&scale, &scale, &product);
2651 }
2652
2653 micro_rsq(&scale, &scale);
2654
2655 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2656 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2657 micro_mul(&arg[chan], &arg[chan], &scale);
2658 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2659 }
2660 }
2661 }
2662
2663 static void
2664 exec_nrm3(struct tgsi_exec_machine *mach,
2665 const struct tgsi_full_instruction *inst)
2666 {
2667 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2668 unsigned int chan;
2669 union tgsi_exec_channel arg[3];
2670 union tgsi_exec_channel scale;
2671
2672 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2673 micro_mul(&scale, &arg[0], &arg[0]);
2674
2675 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2676 union tgsi_exec_channel product;
2677
2678 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2679 micro_mul(&product, &arg[chan], &arg[chan]);
2680 micro_add(&scale, &scale, &product);
2681 }
2682
2683 micro_rsq(&scale, &scale);
2684
2685 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2686 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2687 micro_mul(&arg[chan], &arg[chan], &scale);
2688 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2689 }
2690 }
2691 }
2692
2693 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2694 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2695 }
2696 }
2697
2698 static void
2699 exec_scs(struct tgsi_exec_machine *mach,
2700 const struct tgsi_full_instruction *inst)
2701 {
2702 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2703 union tgsi_exec_channel arg;
2704 union tgsi_exec_channel result;
2705
2706 fetch_source(mach, &arg, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2707
2708 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2709 micro_cos(&result, &arg);
2710 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2711 }
2712 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2713 micro_sin(&result, &arg);
2714 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2715 }
2716 }
2717 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2718 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2719 }
2720 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2721 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2722 }
2723 }
2724
2725 static void
2726 exec_x2d(struct tgsi_exec_machine *mach,
2727 const struct tgsi_full_instruction *inst)
2728 {
2729 union tgsi_exec_channel r[4];
2730 union tgsi_exec_channel d[2];
2731
2732 fetch_source(mach, &r[0], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2733 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2734 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2735 fetch_source(mach, &r[2], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2736 micro_mul(&r[2], &r[2], &r[0]);
2737 fetch_source(mach, &r[3], &inst->Src[2], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2738 micro_mul(&r[3], &r[3], &r[1]);
2739 micro_add(&r[2], &r[2], &r[3]);
2740 fetch_source(mach, &r[3], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2741 micro_add(&d[0], &r[2], &r[3]);
2742 }
2743 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2744 fetch_source(mach, &r[2], &inst->Src[2], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2745 micro_mul(&r[2], &r[2], &r[0]);
2746 fetch_source(mach, &r[3], &inst->Src[2], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2747 micro_mul(&r[3], &r[3], &r[1]);
2748 micro_add(&r[2], &r[2], &r[3]);
2749 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2750 micro_add(&d[1], &r[2], &r[3]);
2751 }
2752 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2753 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2754 }
2755 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2756 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2757 }
2758 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2759 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2760 }
2761 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2762 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2763 }
2764 }
2765
2766 static void
2767 exec_rfl(struct tgsi_exec_machine *mach,
2768 const struct tgsi_full_instruction *inst)
2769 {
2770 union tgsi_exec_channel r[9];
2771
2772 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2773 /* r0 = dp3(src0, src0) */
2774 fetch_source(mach, &r[2], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2775 micro_mul(&r[0], &r[2], &r[2]);
2776 fetch_source(mach, &r[4], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2777 micro_mul(&r[8], &r[4], &r[4]);
2778 micro_add(&r[0], &r[0], &r[8]);
2779 fetch_source(mach, &r[6], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2780 micro_mul(&r[8], &r[6], &r[6]);
2781 micro_add(&r[0], &r[0], &r[8]);
2782
2783 /* r1 = dp3(src0, src1) */
2784 fetch_source(mach, &r[3], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2785 micro_mul(&r[1], &r[2], &r[3]);
2786 fetch_source(mach, &r[5], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2787 micro_mul(&r[8], &r[4], &r[5]);
2788 micro_add(&r[1], &r[1], &r[8]);
2789 fetch_source(mach, &r[7], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2790 micro_mul(&r[8], &r[6], &r[7]);
2791 micro_add(&r[1], &r[1], &r[8]);
2792
2793 /* r1 = 2 * r1 / r0 */
2794 micro_add(&r[1], &r[1], &r[1]);
2795 micro_div(&r[1], &r[1], &r[0]);
2796
2797 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2798 micro_mul(&r[2], &r[2], &r[1]);
2799 micro_sub(&r[2], &r[2], &r[3]);
2800 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2801 }
2802 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2803 micro_mul(&r[4], &r[4], &r[1]);
2804 micro_sub(&r[4], &r[4], &r[5]);
2805 store_dest(mach, &r[4], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2806 }
2807 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2808 micro_mul(&r[6], &r[6], &r[1]);
2809 micro_sub(&r[6], &r[6], &r[7]);
2810 store_dest(mach, &r[6], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2811 }
2812 }
2813 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2814 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2815 }
2816 }
2817
2818 static void
2819 exec_xpd(struct tgsi_exec_machine *mach,
2820 const struct tgsi_full_instruction *inst)
2821 {
2822 union tgsi_exec_channel r[6];
2823 union tgsi_exec_channel d[3];
2824
2825 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2826 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2827
2828 micro_mul(&r[2], &r[0], &r[1]);
2829
2830 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2831 fetch_source(mach, &r[4], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2832
2833 micro_mul(&r[5], &r[3], &r[4] );
2834 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2835
2836 fetch_source(mach, &r[2], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2837
2838 micro_mul(&r[3], &r[3], &r[2]);
2839
2840 fetch_source(mach, &r[5], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2841
2842 micro_mul(&r[1], &r[1], &r[5]);
2843 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2844
2845 micro_mul(&r[5], &r[5], &r[4]);
2846 micro_mul(&r[0], &r[0], &r[2]);
2847 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2848
2849 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2850 store_dest(mach, &d[CHAN_X], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2851 }
2852 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2853 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2854 }
2855 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2856 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2857 }
2858 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2859 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2860 }
2861 }
2862
2863 static void
2864 exec_dst(struct tgsi_exec_machine *mach,
2865 const struct tgsi_full_instruction *inst)
2866 {
2867 union tgsi_exec_channel r[2];
2868 union tgsi_exec_channel d[4];
2869
2870 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2871 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2872 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2873 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2874 }
2875 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2876 fetch_source(mach, &d[CHAN_Z], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2877 }
2878 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2879 fetch_source(mach, &d[CHAN_W], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2880 }
2881
2882 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2883 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2884 }
2885 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2886 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2887 }
2888 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2889 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2890 }
2891 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2892 store_dest(mach, &d[CHAN_W], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2893 }
2894 }
2895
2896 static void
2897 exec_log(struct tgsi_exec_machine *mach,
2898 const struct tgsi_full_instruction *inst)
2899 {
2900 union tgsi_exec_channel r[3];
2901
2902 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2903 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2904 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2905 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2906 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2907 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2908 }
2909 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2910 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2911 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2912 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2913 }
2914 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2915 store_dest(mach, &r[1], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2916 }
2917 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2918 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2919 }
2920 }
2921
2922 static void
2923 exec_exp(struct tgsi_exec_machine *mach,
2924 const struct tgsi_full_instruction *inst)
2925 {
2926 union tgsi_exec_channel r[3];
2927
2928 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2929 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2930 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2931 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2932 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2933 }
2934 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2935 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2936 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2937 }
2938 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2939 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2940 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2941 }
2942 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2943 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2944 }
2945 }
2946
2947 static void
2948 exec_lit(struct tgsi_exec_machine *mach,
2949 const struct tgsi_full_instruction *inst)
2950 {
2951 union tgsi_exec_channel r[3];
2952 union tgsi_exec_channel d[3];
2953
2954 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2955 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2956 }
2957 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2958 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2959 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2960 micro_max(&d[CHAN_Y], &r[0], &ZeroVec);
2961 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2962 }
2963
2964 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2965 fetch_source(mach, &r[1], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2966 micro_max(&r[1], &r[1], &ZeroVec);
2967
2968 fetch_source(mach, &r[2], &inst->Src[0], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2969 micro_min(&r[2], &r[2], &P128Vec);
2970 micro_max(&r[2], &r[2], &M128Vec);
2971 micro_pow(&r[1], &r[1], &r[2]);
2972 micro_lt(&d[CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
2973 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2974 }
2975 }
2976 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2977 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2978 }
2979 }
2980
2981 static void
2982 exec_break(struct tgsi_exec_machine *mach)
2983 {
2984 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2985 /* turn off loop channels for each enabled exec channel */
2986 mach->LoopMask &= ~mach->ExecMask;
2987 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2988 UPDATE_EXEC_MASK(mach);
2989 } else {
2990 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2991
2992 mach->Switch.mask = 0x0;
2993
2994 UPDATE_EXEC_MASK(mach);
2995 }
2996 }
2997
2998 static void
2999 exec_switch(struct tgsi_exec_machine *mach,
3000 const struct tgsi_full_instruction *inst)
3001 {
3002 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3003 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3004
3005 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3006 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
3007 mach->Switch.mask = 0x0;
3008 mach->Switch.defaultMask = 0x0;
3009
3010 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3011 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3012
3013 UPDATE_EXEC_MASK(mach);
3014 }
3015
3016 static void
3017 exec_case(struct tgsi_exec_machine *mach,
3018 const struct tgsi_full_instruction *inst)
3019 {
3020 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3021 union tgsi_exec_channel src;
3022 uint mask = 0;
3023
3024 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
3025
3026 if (mach->Switch.selector.u[0] == src.u[0]) {
3027 mask |= 0x1;
3028 }
3029 if (mach->Switch.selector.u[1] == src.u[1]) {
3030 mask |= 0x2;
3031 }
3032 if (mach->Switch.selector.u[2] == src.u[2]) {
3033 mask |= 0x4;
3034 }
3035 if (mach->Switch.selector.u[3] == src.u[3]) {
3036 mask |= 0x8;
3037 }
3038
3039 mach->Switch.defaultMask |= mask;
3040
3041 mach->Switch.mask |= mask & prevMask;
3042
3043 UPDATE_EXEC_MASK(mach);
3044 }
3045
3046 static void
3047 exec_default(struct tgsi_exec_machine *mach)
3048 {
3049 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3050
3051 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3052
3053 UPDATE_EXEC_MASK(mach);
3054 }
3055
3056 static void
3057 exec_endswitch(struct tgsi_exec_machine *mach)
3058 {
3059 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3060 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3061
3062 UPDATE_EXEC_MASK(mach);
3063 }
3064
3065 static void
3066 micro_i2f(union tgsi_exec_channel *dst,
3067 const union tgsi_exec_channel *src)
3068 {
3069 dst->f[0] = (float)src->i[0];
3070 dst->f[1] = (float)src->i[1];
3071 dst->f[2] = (float)src->i[2];
3072 dst->f[3] = (float)src->i[3];
3073 }
3074
3075 static void
3076 micro_not(union tgsi_exec_channel *dst,
3077 const union tgsi_exec_channel *src)
3078 {
3079 dst->u[0] = ~src->u[0];
3080 dst->u[1] = ~src->u[1];
3081 dst->u[2] = ~src->u[2];
3082 dst->u[3] = ~src->u[3];
3083 }
3084
3085 static void
3086 micro_shl(union tgsi_exec_channel *dst,
3087 const union tgsi_exec_channel *src0,
3088 const union tgsi_exec_channel *src1)
3089 {
3090 dst->u[0] = src0->u[0] << src1->u[0];
3091 dst->u[1] = src0->u[1] << src1->u[1];
3092 dst->u[2] = src0->u[2] << src1->u[2];
3093 dst->u[3] = src0->u[3] << src1->u[3];
3094 }
3095
3096 static void
3097 micro_and(union tgsi_exec_channel *dst,
3098 const union tgsi_exec_channel *src0,
3099 const union tgsi_exec_channel *src1)
3100 {
3101 dst->u[0] = src0->u[0] & src1->u[0];
3102 dst->u[1] = src0->u[1] & src1->u[1];
3103 dst->u[2] = src0->u[2] & src1->u[2];
3104 dst->u[3] = src0->u[3] & src1->u[3];
3105 }
3106
3107 static void
3108 micro_or(union tgsi_exec_channel *dst,
3109 const union tgsi_exec_channel *src0,
3110 const union tgsi_exec_channel *src1)
3111 {
3112 dst->u[0] = src0->u[0] | src1->u[0];
3113 dst->u[1] = src0->u[1] | src1->u[1];
3114 dst->u[2] = src0->u[2] | src1->u[2];
3115 dst->u[3] = src0->u[3] | src1->u[3];
3116 }
3117
3118 static void
3119 micro_xor(union tgsi_exec_channel *dst,
3120 const union tgsi_exec_channel *src0,
3121 const union tgsi_exec_channel *src1)
3122 {
3123 dst->u[0] = src0->u[0] ^ src1->u[0];
3124 dst->u[1] = src0->u[1] ^ src1->u[1];
3125 dst->u[2] = src0->u[2] ^ src1->u[2];
3126 dst->u[3] = src0->u[3] ^ src1->u[3];
3127 }
3128
3129 static void
3130 micro_mod(union tgsi_exec_channel *dst,
3131 const union tgsi_exec_channel *src0,
3132 const union tgsi_exec_channel *src1)
3133 {
3134 dst->i[0] = src0->i[0] % src1->i[0];
3135 dst->i[1] = src0->i[1] % src1->i[1];
3136 dst->i[2] = src0->i[2] % src1->i[2];
3137 dst->i[3] = src0->i[3] % src1->i[3];
3138 }
3139
3140 static void
3141 micro_f2i(union tgsi_exec_channel *dst,
3142 const union tgsi_exec_channel *src)
3143 {
3144 dst->i[0] = (int)src->f[0];
3145 dst->i[1] = (int)src->f[1];
3146 dst->i[2] = (int)src->f[2];
3147 dst->i[3] = (int)src->f[3];
3148 }
3149
3150 static void
3151 micro_idiv(union tgsi_exec_channel *dst,
3152 const union tgsi_exec_channel *src0,
3153 const union tgsi_exec_channel *src1)
3154 {
3155 dst->i[0] = src0->i[0] / src1->i[0];
3156 dst->i[1] = src0->i[1] / src1->i[1];
3157 dst->i[2] = src0->i[2] / src1->i[2];
3158 dst->i[3] = src0->i[3] / src1->i[3];
3159 }
3160
3161 static void
3162 micro_imax(union tgsi_exec_channel *dst,
3163 const union tgsi_exec_channel *src0,
3164 const union tgsi_exec_channel *src1)
3165 {
3166 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3167 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3168 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3169 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3170 }
3171
3172 static void
3173 micro_imin(union tgsi_exec_channel *dst,
3174 const union tgsi_exec_channel *src0,
3175 const union tgsi_exec_channel *src1)
3176 {
3177 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3178 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3179 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3180 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3181 }
3182
3183 static void
3184 micro_isge(union tgsi_exec_channel *dst,
3185 const union tgsi_exec_channel *src0,
3186 const union tgsi_exec_channel *src1)
3187 {
3188 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3189 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3190 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3191 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3192 }
3193
3194 static void
3195 micro_ishr(union tgsi_exec_channel *dst,
3196 const union tgsi_exec_channel *src0,
3197 const union tgsi_exec_channel *src1)
3198 {
3199 dst->i[0] = src0->i[0] >> src1->i[0];
3200 dst->i[1] = src0->i[1] >> src1->i[1];
3201 dst->i[2] = src0->i[2] >> src1->i[2];
3202 dst->i[3] = src0->i[3] >> src1->i[3];
3203 }
3204
3205 static void
3206 micro_islt(union tgsi_exec_channel *dst,
3207 const union tgsi_exec_channel *src0,
3208 const union tgsi_exec_channel *src1)
3209 {
3210 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3211 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3212 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3213 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3214 }
3215
3216 static void
3217 micro_f2u(union tgsi_exec_channel *dst,
3218 const union tgsi_exec_channel *src)
3219 {
3220 dst->u[0] = (uint)src->f[0];
3221 dst->u[1] = (uint)src->f[1];
3222 dst->u[2] = (uint)src->f[2];
3223 dst->u[3] = (uint)src->f[3];
3224 }
3225
3226 static void
3227 micro_u2f(union tgsi_exec_channel *dst,
3228 const union tgsi_exec_channel *src)
3229 {
3230 dst->f[0] = (float)src->u[0];
3231 dst->f[1] = (float)src->u[1];
3232 dst->f[2] = (float)src->u[2];
3233 dst->f[3] = (float)src->u[3];
3234 }
3235
3236 static void
3237 micro_uadd(union tgsi_exec_channel *dst,
3238 const union tgsi_exec_channel *src0,
3239 const union tgsi_exec_channel *src1)
3240 {
3241 dst->u[0] = src0->u[0] + src1->u[0];
3242 dst->u[1] = src0->u[1] + src1->u[1];
3243 dst->u[2] = src0->u[2] + src1->u[2];
3244 dst->u[3] = src0->u[3] + src1->u[3];
3245 }
3246
3247 static void
3248 micro_udiv(union tgsi_exec_channel *dst,
3249 const union tgsi_exec_channel *src0,
3250 const union tgsi_exec_channel *src1)
3251 {
3252 dst->u[0] = src0->u[0] / src1->u[0];
3253 dst->u[1] = src0->u[1] / src1->u[1];
3254 dst->u[2] = src0->u[2] / src1->u[2];
3255 dst->u[3] = src0->u[3] / src1->u[3];
3256 }
3257
3258 static void
3259 micro_umad(union tgsi_exec_channel *dst,
3260 const union tgsi_exec_channel *src0,
3261 const union tgsi_exec_channel *src1,
3262 const union tgsi_exec_channel *src2)
3263 {
3264 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3265 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3266 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3267 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3268 }
3269
3270 static void
3271 micro_umax(union tgsi_exec_channel *dst,
3272 const union tgsi_exec_channel *src0,
3273 const union tgsi_exec_channel *src1)
3274 {
3275 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3276 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3277 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3278 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3279 }
3280
3281 static void
3282 micro_umin(union tgsi_exec_channel *dst,
3283 const union tgsi_exec_channel *src0,
3284 const union tgsi_exec_channel *src1)
3285 {
3286 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3287 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3288 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3289 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3290 }
3291
3292 static void
3293 micro_umod(union tgsi_exec_channel *dst,
3294 const union tgsi_exec_channel *src0,
3295 const union tgsi_exec_channel *src1)
3296 {
3297 dst->u[0] = src0->u[0] % src1->u[0];
3298 dst->u[1] = src0->u[1] % src1->u[1];
3299 dst->u[2] = src0->u[2] % src1->u[2];
3300 dst->u[3] = src0->u[3] % src1->u[3];
3301 }
3302
3303 static void
3304 micro_umul(union tgsi_exec_channel *dst,
3305 const union tgsi_exec_channel *src0,
3306 const union tgsi_exec_channel *src1)
3307 {
3308 dst->u[0] = src0->u[0] * src1->u[0];
3309 dst->u[1] = src0->u[1] * src1->u[1];
3310 dst->u[2] = src0->u[2] * src1->u[2];
3311 dst->u[3] = src0->u[3] * src1->u[3];
3312 }
3313
3314 static void
3315 micro_useq(union tgsi_exec_channel *dst,
3316 const union tgsi_exec_channel *src0,
3317 const union tgsi_exec_channel *src1)
3318 {
3319 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3320 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3321 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3322 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3323 }
3324
3325 static void
3326 micro_usge(union tgsi_exec_channel *dst,
3327 const union tgsi_exec_channel *src0,
3328 const union tgsi_exec_channel *src1)
3329 {
3330 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3331 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3332 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3333 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3334 }
3335
3336 static void
3337 micro_ushr(union tgsi_exec_channel *dst,
3338 const union tgsi_exec_channel *src0,
3339 const union tgsi_exec_channel *src1)
3340 {
3341 dst->u[0] = src0->u[0] >> src1->u[0];
3342 dst->u[1] = src0->u[1] >> src1->u[1];
3343 dst->u[2] = src0->u[2] >> src1->u[2];
3344 dst->u[3] = src0->u[3] >> src1->u[3];
3345 }
3346
3347 static void
3348 micro_uslt(union tgsi_exec_channel *dst,
3349 const union tgsi_exec_channel *src0,
3350 const union tgsi_exec_channel *src1)
3351 {
3352 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3353 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3354 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3355 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3356 }
3357
3358 static void
3359 micro_usne(union tgsi_exec_channel *dst,
3360 const union tgsi_exec_channel *src0,
3361 const union tgsi_exec_channel *src1)
3362 {
3363 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3364 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3365 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3366 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3367 }
3368
3369 static void
3370 micro_uarl(union tgsi_exec_channel *dst,
3371 const union tgsi_exec_channel *src)
3372 {
3373 dst->i[0] = src->u[0];
3374 dst->i[1] = src->u[1];
3375 dst->i[2] = src->u[2];
3376 dst->i[3] = src->u[3];
3377 }
3378
3379 static void
3380 micro_ucmp(union tgsi_exec_channel *dst,
3381 const union tgsi_exec_channel *src0,
3382 const union tgsi_exec_channel *src1,
3383 const union tgsi_exec_channel *src2)
3384 {
3385 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3386 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3387 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3388 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3389 }
3390
3391 static void
3392 exec_instruction(
3393 struct tgsi_exec_machine *mach,
3394 const struct tgsi_full_instruction *inst,
3395 int *pc )
3396 {
3397 union tgsi_exec_channel r[10];
3398
3399 (*pc)++;
3400
3401 switch (inst->Instruction.Opcode) {
3402 case TGSI_OPCODE_ARL:
3403 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3404 break;
3405
3406 case TGSI_OPCODE_MOV:
3407 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3408 break;
3409
3410 case TGSI_OPCODE_LIT:
3411 exec_lit(mach, inst);
3412 break;
3413
3414 case TGSI_OPCODE_RCP:
3415 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3416 break;
3417
3418 case TGSI_OPCODE_RSQ:
3419 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3420 break;
3421
3422 case TGSI_OPCODE_EXP:
3423 exec_exp(mach, inst);
3424 break;
3425
3426 case TGSI_OPCODE_LOG:
3427 exec_log(mach, inst);
3428 break;
3429
3430 case TGSI_OPCODE_MUL:
3431 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3432 break;
3433
3434 case TGSI_OPCODE_ADD:
3435 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3436 break;
3437
3438 case TGSI_OPCODE_DP3:
3439 exec_dp3(mach, inst);
3440 break;
3441
3442 case TGSI_OPCODE_DP4:
3443 exec_dp4(mach, inst);
3444 break;
3445
3446 case TGSI_OPCODE_DST:
3447 exec_dst(mach, inst);
3448 break;
3449
3450 case TGSI_OPCODE_MIN:
3451 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3452 break;
3453
3454 case TGSI_OPCODE_MAX:
3455 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3456 break;
3457
3458 case TGSI_OPCODE_SLT:
3459 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3460 break;
3461
3462 case TGSI_OPCODE_SGE:
3463 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3464 break;
3465
3466 case TGSI_OPCODE_MAD:
3467 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3468 break;
3469
3470 case TGSI_OPCODE_SUB:
3471 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3472 break;
3473
3474 case TGSI_OPCODE_LRP:
3475 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3476 break;
3477
3478 case TGSI_OPCODE_CND:
3479 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3480 break;
3481
3482 case TGSI_OPCODE_DP2A:
3483 exec_dp2a(mach, inst);
3484 break;
3485
3486 case TGSI_OPCODE_FRC:
3487 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3488 break;
3489
3490 case TGSI_OPCODE_CLAMP:
3491 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3492 break;
3493
3494 case TGSI_OPCODE_FLR:
3495 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3496 break;
3497
3498 case TGSI_OPCODE_ROUND:
3499 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3500 break;
3501
3502 case TGSI_OPCODE_EX2:
3503 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3504 break;
3505
3506 case TGSI_OPCODE_LG2:
3507 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3508 break;
3509
3510 case TGSI_OPCODE_POW:
3511 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3512 break;
3513
3514 case TGSI_OPCODE_XPD:
3515 exec_xpd(mach, inst);
3516 break;
3517
3518 case TGSI_OPCODE_ABS:
3519 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3520 break;
3521
3522 case TGSI_OPCODE_RCC:
3523 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3524 break;
3525
3526 case TGSI_OPCODE_DPH:
3527 exec_dph(mach, inst);
3528 break;
3529
3530 case TGSI_OPCODE_COS:
3531 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3532 break;
3533
3534 case TGSI_OPCODE_DDX:
3535 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3536 break;
3537
3538 case TGSI_OPCODE_DDY:
3539 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3540 break;
3541
3542 case TGSI_OPCODE_KILP:
3543 exec_kilp (mach, inst);
3544 break;
3545
3546 case TGSI_OPCODE_KIL:
3547 exec_kil (mach, inst);
3548 break;
3549
3550 case TGSI_OPCODE_PK2H:
3551 assert (0);
3552 break;
3553
3554 case TGSI_OPCODE_PK2US:
3555 assert (0);
3556 break;
3557
3558 case TGSI_OPCODE_PK4B:
3559 assert (0);
3560 break;
3561
3562 case TGSI_OPCODE_PK4UB:
3563 assert (0);
3564 break;
3565
3566 case TGSI_OPCODE_RFL:
3567 exec_rfl(mach, inst);
3568 break;
3569
3570 case TGSI_OPCODE_SEQ:
3571 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3572 break;
3573
3574 case TGSI_OPCODE_SFL:
3575 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3576 break;
3577
3578 case TGSI_OPCODE_SGT:
3579 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3580 break;
3581
3582 case TGSI_OPCODE_SIN:
3583 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3584 break;
3585
3586 case TGSI_OPCODE_SLE:
3587 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3588 break;
3589
3590 case TGSI_OPCODE_SNE:
3591 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3592 break;
3593
3594 case TGSI_OPCODE_STR:
3595 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3596 break;
3597
3598 case TGSI_OPCODE_TEX:
3599 /* simple texture lookup */
3600 /* src[0] = texcoord */
3601 /* src[1] = sampler unit */
3602 exec_tex(mach, inst, TEX_MODIFIER_NONE);
3603 break;
3604
3605 case TGSI_OPCODE_TXB:
3606 /* Texture lookup with lod bias */
3607 /* src[0] = texcoord (src[0].w = LOD bias) */
3608 /* src[1] = sampler unit */
3609 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
3610 break;
3611
3612 case TGSI_OPCODE_TXD:
3613 /* Texture lookup with explict partial derivatives */
3614 /* src[0] = texcoord */
3615 /* src[1] = d[strq]/dx */
3616 /* src[2] = d[strq]/dy */
3617 /* src[3] = sampler unit */
3618 exec_txd(mach, inst);
3619 break;
3620
3621 case TGSI_OPCODE_TXL:
3622 /* Texture lookup with explit LOD */
3623 /* src[0] = texcoord (src[0].w = LOD) */
3624 /* src[1] = sampler unit */
3625 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3626 break;
3627
3628 case TGSI_OPCODE_TXP:
3629 /* Texture lookup with projection */
3630 /* src[0] = texcoord (src[0].w = projection) */
3631 /* src[1] = sampler unit */
3632 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
3633 break;
3634
3635 case TGSI_OPCODE_UP2H:
3636 assert (0);
3637 break;
3638
3639 case TGSI_OPCODE_UP2US:
3640 assert (0);
3641 break;
3642
3643 case TGSI_OPCODE_UP4B:
3644 assert (0);
3645 break;
3646
3647 case TGSI_OPCODE_UP4UB:
3648 assert (0);
3649 break;
3650
3651 case TGSI_OPCODE_X2D:
3652 exec_x2d(mach, inst);
3653 break;
3654
3655 case TGSI_OPCODE_ARA:
3656 assert (0);
3657 break;
3658
3659 case TGSI_OPCODE_ARR:
3660 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3661 break;
3662
3663 case TGSI_OPCODE_BRA:
3664 assert (0);
3665 break;
3666
3667 case TGSI_OPCODE_CAL:
3668 /* skip the call if no execution channels are enabled */
3669 if (mach->ExecMask) {
3670 /* do the call */
3671
3672 /* First, record the depths of the execution stacks.
3673 * This is important for deeply nested/looped return statements.
3674 * We have to unwind the stacks by the correct amount. For a
3675 * real code generator, we could determine the number of entries
3676 * to pop off each stack with simple static analysis and avoid
3677 * implementing this data structure at run time.
3678 */
3679 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3680 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3681 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3682 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3683 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3684 /* note that PC was already incremented above */
3685 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3686
3687 mach->CallStackTop++;
3688
3689 /* Second, push the Cond, Loop, Cont, Func stacks */
3690 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3691 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3692 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3693 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3694 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3695 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3696
3697 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3698 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3699 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3700 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3701 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3702 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3703
3704 /* Finally, jump to the subroutine */
3705 *pc = inst->Label.Label;
3706 }
3707 break;
3708
3709 case TGSI_OPCODE_RET:
3710 mach->FuncMask &= ~mach->ExecMask;
3711 UPDATE_EXEC_MASK(mach);
3712
3713 if (mach->FuncMask == 0x0) {
3714 /* really return now (otherwise, keep executing */
3715
3716 if (mach->CallStackTop == 0) {
3717 /* returning from main() */
3718 mach->CondStackTop = 0;
3719 mach->LoopStackTop = 0;
3720 *pc = -1;
3721 return;
3722 }
3723
3724 assert(mach->CallStackTop > 0);
3725 mach->CallStackTop--;
3726
3727 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3728 mach->CondMask = mach->CondStack[mach->CondStackTop];
3729
3730 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3731 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3732
3733 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3734 mach->ContMask = mach->ContStack[mach->ContStackTop];
3735
3736 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3737 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3738
3739 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3740 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3741
3742 assert(mach->FuncStackTop > 0);
3743 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3744
3745 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3746
3747 UPDATE_EXEC_MASK(mach);
3748 }
3749 break;
3750
3751 case TGSI_OPCODE_SSG:
3752 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3753 break;
3754
3755 case TGSI_OPCODE_CMP:
3756 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3757 break;
3758
3759 case TGSI_OPCODE_SCS:
3760 exec_scs(mach, inst);
3761 break;
3762
3763 case TGSI_OPCODE_NRM:
3764 exec_nrm3(mach, inst);
3765 break;
3766
3767 case TGSI_OPCODE_NRM4:
3768 exec_nrm4(mach, inst);
3769 break;
3770
3771 case TGSI_OPCODE_DIV:
3772 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3773 break;
3774
3775 case TGSI_OPCODE_DP2:
3776 exec_dp2(mach, inst);
3777 break;
3778
3779 case TGSI_OPCODE_IF:
3780 /* push CondMask */
3781 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3782 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3783 FETCH( &r[0], 0, CHAN_X );
3784 /* update CondMask */
3785 if( ! r[0].u[0] ) {
3786 mach->CondMask &= ~0x1;
3787 }
3788 if( ! r[0].u[1] ) {
3789 mach->CondMask &= ~0x2;
3790 }
3791 if( ! r[0].u[2] ) {
3792 mach->CondMask &= ~0x4;
3793 }
3794 if( ! r[0].u[3] ) {
3795 mach->CondMask &= ~0x8;
3796 }
3797 UPDATE_EXEC_MASK(mach);
3798 /* Todo: If CondMask==0, jump to ELSE */
3799 break;
3800
3801 case TGSI_OPCODE_ELSE:
3802 /* invert CondMask wrt previous mask */
3803 {
3804 uint prevMask;
3805 assert(mach->CondStackTop > 0);
3806 prevMask = mach->CondStack[mach->CondStackTop - 1];
3807 mach->CondMask = ~mach->CondMask & prevMask;
3808 UPDATE_EXEC_MASK(mach);
3809 /* Todo: If CondMask==0, jump to ENDIF */
3810 }
3811 break;
3812
3813 case TGSI_OPCODE_ENDIF:
3814 /* pop CondMask */
3815 assert(mach->CondStackTop > 0);
3816 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3817 UPDATE_EXEC_MASK(mach);
3818 break;
3819
3820 case TGSI_OPCODE_END:
3821 /* make sure we end primitives which haven't
3822 * been explicitly emitted */
3823 conditional_emit_primitive(mach);
3824 /* halt execution */
3825 *pc = -1;
3826 break;
3827
3828 case TGSI_OPCODE_PUSHA:
3829 assert (0);
3830 break;
3831
3832 case TGSI_OPCODE_POPA:
3833 assert (0);
3834 break;
3835
3836 case TGSI_OPCODE_CEIL:
3837 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3838 break;
3839
3840 case TGSI_OPCODE_I2F:
3841 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3842 break;
3843
3844 case TGSI_OPCODE_NOT:
3845 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3846 break;
3847
3848 case TGSI_OPCODE_TRUNC:
3849 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3850 break;
3851
3852 case TGSI_OPCODE_SHL:
3853 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3854 break;
3855
3856 case TGSI_OPCODE_AND:
3857 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3858 break;
3859
3860 case TGSI_OPCODE_OR:
3861 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3862 break;
3863
3864 case TGSI_OPCODE_MOD:
3865 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3866 break;
3867
3868 case TGSI_OPCODE_XOR:
3869 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3870 break;
3871
3872 case TGSI_OPCODE_SAD:
3873 assert (0);
3874 break;
3875
3876 case TGSI_OPCODE_TXF:
3877 exec_txf(mach, inst);
3878 break;
3879
3880 case TGSI_OPCODE_TXQ:
3881 exec_txq(mach, inst);
3882 break;
3883
3884 case TGSI_OPCODE_EMIT:
3885 emit_vertex(mach);
3886 break;
3887
3888 case TGSI_OPCODE_ENDPRIM:
3889 emit_primitive(mach);
3890 break;
3891
3892 case TGSI_OPCODE_BGNLOOP:
3893 /* push LoopMask and ContMasks */
3894 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3895 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3896 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3897 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3898
3899 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3900 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3901 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3902 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3903 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3904 break;
3905
3906 case TGSI_OPCODE_ENDLOOP:
3907 /* Restore ContMask, but don't pop */
3908 assert(mach->ContStackTop > 0);
3909 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3910 UPDATE_EXEC_MASK(mach);
3911 if (mach->ExecMask) {
3912 /* repeat loop: jump to instruction just past BGNLOOP */
3913 assert(mach->LoopLabelStackTop > 0);
3914 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3915 }
3916 else {
3917 /* exit loop: pop LoopMask */
3918 assert(mach->LoopStackTop > 0);
3919 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3920 /* pop ContMask */
3921 assert(mach->ContStackTop > 0);
3922 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3923 assert(mach->LoopLabelStackTop > 0);
3924 --mach->LoopLabelStackTop;
3925
3926 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3927 }
3928 UPDATE_EXEC_MASK(mach);
3929 break;
3930
3931 case TGSI_OPCODE_BRK:
3932 exec_break(mach);
3933 break;
3934
3935 case TGSI_OPCODE_CONT:
3936 /* turn off cont channels for each enabled exec channel */
3937 mach->ContMask &= ~mach->ExecMask;
3938 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3939 UPDATE_EXEC_MASK(mach);
3940 break;
3941
3942 case TGSI_OPCODE_BGNSUB:
3943 /* no-op */
3944 break;
3945
3946 case TGSI_OPCODE_ENDSUB:
3947 /*
3948 * XXX: This really should be a no-op. We should never reach this opcode.
3949 */
3950
3951 assert(mach->CallStackTop > 0);
3952 mach->CallStackTop--;
3953
3954 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3955 mach->CondMask = mach->CondStack[mach->CondStackTop];
3956
3957 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3958 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3959
3960 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3961 mach->ContMask = mach->ContStack[mach->ContStackTop];
3962
3963 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3964 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3965
3966 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3967 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3968
3969 assert(mach->FuncStackTop > 0);
3970 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3971
3972 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3973
3974 UPDATE_EXEC_MASK(mach);
3975 break;
3976
3977 case TGSI_OPCODE_NOP:
3978 break;
3979
3980 case TGSI_OPCODE_BREAKC:
3981 FETCH(&r[0], 0, CHAN_X);
3982 /* update CondMask */
3983 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3984 mach->LoopMask &= ~0x1;
3985 }
3986 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3987 mach->LoopMask &= ~0x2;
3988 }
3989 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3990 mach->LoopMask &= ~0x4;
3991 }
3992 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3993 mach->LoopMask &= ~0x8;
3994 }
3995 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3996 UPDATE_EXEC_MASK(mach);
3997 break;
3998
3999 case TGSI_OPCODE_F2I:
4000 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4001 break;
4002
4003 case TGSI_OPCODE_IDIV:
4004 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4005 break;
4006
4007 case TGSI_OPCODE_IMAX:
4008 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4009 break;
4010
4011 case TGSI_OPCODE_IMIN:
4012 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4013 break;
4014
4015 case TGSI_OPCODE_INEG:
4016 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4017 break;
4018
4019 case TGSI_OPCODE_ISGE:
4020 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4021 break;
4022
4023 case TGSI_OPCODE_ISHR:
4024 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4025 break;
4026
4027 case TGSI_OPCODE_ISLT:
4028 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4029 break;
4030
4031 case TGSI_OPCODE_F2U:
4032 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4033 break;
4034
4035 case TGSI_OPCODE_U2F:
4036 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4037 break;
4038
4039 case TGSI_OPCODE_UADD:
4040 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4041 break;
4042
4043 case TGSI_OPCODE_UDIV:
4044 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4045 break;
4046
4047 case TGSI_OPCODE_UMAD:
4048 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4049 break;
4050
4051 case TGSI_OPCODE_UMAX:
4052 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4053 break;
4054
4055 case TGSI_OPCODE_UMIN:
4056 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4057 break;
4058
4059 case TGSI_OPCODE_UMOD:
4060 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4061 break;
4062
4063 case TGSI_OPCODE_UMUL:
4064 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4065 break;
4066
4067 case TGSI_OPCODE_USEQ:
4068 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4069 break;
4070
4071 case TGSI_OPCODE_USGE:
4072 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4073 break;
4074
4075 case TGSI_OPCODE_USHR:
4076 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4077 break;
4078
4079 case TGSI_OPCODE_USLT:
4080 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4081 break;
4082
4083 case TGSI_OPCODE_USNE:
4084 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4085 break;
4086
4087 case TGSI_OPCODE_SWITCH:
4088 exec_switch(mach, inst);
4089 break;
4090
4091 case TGSI_OPCODE_CASE:
4092 exec_case(mach, inst);
4093 break;
4094
4095 case TGSI_OPCODE_DEFAULT:
4096 exec_default(mach);
4097 break;
4098
4099 case TGSI_OPCODE_ENDSWITCH:
4100 exec_endswitch(mach);
4101 break;
4102
4103 case TGSI_OPCODE_LOAD:
4104 assert(0);
4105 break;
4106
4107 case TGSI_OPCODE_LOAD_MS:
4108 assert(0);
4109 break;
4110
4111 case TGSI_OPCODE_SAMPLE:
4112 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4113 break;
4114
4115 case TGSI_OPCODE_SAMPLE_B:
4116 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4117 break;
4118
4119 case TGSI_OPCODE_SAMPLE_C:
4120 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4121 break;
4122
4123 case TGSI_OPCODE_SAMPLE_C_LZ:
4124 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4125 break;
4126
4127 case TGSI_OPCODE_SAMPLE_D:
4128 exec_sample_d(mach, inst);
4129 break;
4130
4131 case TGSI_OPCODE_SAMPLE_L:
4132 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
4133 break;
4134
4135 case TGSI_OPCODE_GATHER4:
4136 assert(0);
4137 break;
4138
4139 case TGSI_OPCODE_RESINFO:
4140 assert(0);
4141 break;
4142
4143 case TGSI_OPCODE_SAMPLE_POS:
4144 assert(0);
4145 break;
4146
4147 case TGSI_OPCODE_SAMPLE_INFO:
4148 assert(0);
4149 break;
4150
4151 case TGSI_OPCODE_UARL:
4152 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4153 break;
4154
4155 case TGSI_OPCODE_UCMP:
4156 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4157 break;
4158
4159 default:
4160 assert( 0 );
4161 }
4162 }
4163
4164
4165 #define DEBUG_EXECUTION 0
4166
4167
4168 /**
4169 * Run TGSI interpreter.
4170 * \return bitmask of "alive" quad components
4171 */
4172 uint
4173 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4174 {
4175 uint i;
4176 int pc = 0;
4177
4178 mach->CondMask = 0xf;
4179 mach->LoopMask = 0xf;
4180 mach->ContMask = 0xf;
4181 mach->FuncMask = 0xf;
4182 mach->ExecMask = 0xf;
4183
4184 mach->Switch.mask = 0xf;
4185
4186 assert(mach->CondStackTop == 0);
4187 assert(mach->LoopStackTop == 0);
4188 assert(mach->ContStackTop == 0);
4189 assert(mach->SwitchStackTop == 0);
4190 assert(mach->BreakStackTop == 0);
4191 assert(mach->CallStackTop == 0);
4192
4193 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4194 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4195
4196 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4197 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4198 mach->Primitives[0] = 0;
4199 }
4200
4201 /* execute declarations (interpolants) */
4202 for (i = 0; i < mach->NumDeclarations; i++) {
4203 exec_declaration( mach, mach->Declarations+i );
4204 }
4205
4206 {
4207 #if DEBUG_EXECUTION
4208 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4209 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4210 uint inst = 1;
4211
4212 memcpy(temps, mach->Temps, sizeof(temps));
4213 memcpy(outputs, mach->Outputs, sizeof(outputs));
4214 #endif
4215
4216 /* execute instructions, until pc is set to -1 */
4217 while (pc != -1) {
4218
4219 #if DEBUG_EXECUTION
4220 uint i;
4221
4222 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4223 #endif
4224
4225 assert(pc < (int) mach->NumInstructions);
4226 exec_instruction(mach, mach->Instructions + pc, &pc);
4227
4228 #if DEBUG_EXECUTION
4229 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4230 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4231 uint j;
4232
4233 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4234 debug_printf("TEMP[%2u] = ", i);
4235 for (j = 0; j < 4; j++) {
4236 if (j > 0) {
4237 debug_printf(" ");
4238 }
4239 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4240 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4241 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4242 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4243 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4244 }
4245 }
4246 }
4247 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4248 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4249 uint j;
4250
4251 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4252 debug_printf("OUT[%2u] = ", i);
4253 for (j = 0; j < 4; j++) {
4254 if (j > 0) {
4255 debug_printf(" ");
4256 }
4257 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4258 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4259 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4260 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4261 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4262 }
4263 }
4264 }
4265 #endif
4266 }
4267 }
4268
4269 #if 0
4270 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4271 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4272 /*
4273 * Scale back depth component.
4274 */
4275 for (i = 0; i < 4; i++)
4276 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4277 }
4278 #endif
4279
4280 /* Strictly speaking, these assertions aren't really needed but they
4281 * can potentially catch some bugs in the control flow code.
4282 */
4283 assert(mach->CondStackTop == 0);
4284 assert(mach->LoopStackTop == 0);
4285 assert(mach->ContStackTop == 0);
4286 assert(mach->SwitchStackTop == 0);
4287 assert(mach->BreakStackTop == 0);
4288 assert(mach->CallStackTop == 0);
4289
4290 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4291 }