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Merge remote branch 'origin/master' into nv50-compiler
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
381 {
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
386 }
387
388 static void
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
391 {
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
396 }
397
398 static void
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
402 {
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
407 }
408
409 static void
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_trunc(union tgsi_exec_channel *dst,
433 const union tgsi_exec_channel *src)
434 {
435 dst->f[0] = (float)(int)src->f[0];
436 dst->f[1] = (float)(int)src->f[1];
437 dst->f[2] = (float)(int)src->f[2];
438 dst->f[3] = (float)(int)src->f[3];
439 }
440
441
442 #define CHAN_X 0
443 #define CHAN_Y 1
444 #define CHAN_Z 2
445 #define CHAN_W 3
446
447 enum tgsi_exec_datatype {
448 TGSI_EXEC_DATA_FLOAT,
449 TGSI_EXEC_DATA_INT,
450 TGSI_EXEC_DATA_UINT
451 };
452
453 /*
454 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
455 */
456 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
457 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
458 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
459 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
460 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
461 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
462 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
463 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
464 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
465 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
466 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
467 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
468 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
469 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
470 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
471 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
472 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
473 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
474 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
475 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
476 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
477 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
478 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
479 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
480 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
481 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
482 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
483 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
484 #define TEMP_R0 TGSI_EXEC_TEMP_R0
485 #define TEMP_P0 TGSI_EXEC_TEMP_P0
486
487 #define IS_CHANNEL_ENABLED(INST, CHAN)\
488 ((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
489
490 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
491 ((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
492
493 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
494 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
495 if (IS_CHANNEL_ENABLED( INST, CHAN ))
496
497 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
498 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
499 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
500
501
502 /** The execution mask depends on the conditional mask and the loop mask */
503 #define UPDATE_EXEC_MASK(MACH) \
504 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
505
506
507 static const union tgsi_exec_channel ZeroVec =
508 { { 0.0, 0.0, 0.0, 0.0 } };
509
510 static const union tgsi_exec_channel OneVec = {
511 {1.0f, 1.0f, 1.0f, 1.0f}
512 };
513
514
515 /**
516 * Assert that none of the float values in 'chan' are infinite or NaN.
517 * NaN and Inf may occur normally during program execution and should
518 * not lead to crashes, etc. But when debugging, it's helpful to catch
519 * them.
520 */
521 static INLINE void
522 check_inf_or_nan(const union tgsi_exec_channel *chan)
523 {
524 assert(!util_is_inf_or_nan((chan)->f[0]));
525 assert(!util_is_inf_or_nan((chan)->f[1]));
526 assert(!util_is_inf_or_nan((chan)->f[2]));
527 assert(!util_is_inf_or_nan((chan)->f[3]));
528 }
529
530
531 #ifdef DEBUG
532 static void
533 print_chan(const char *msg, const union tgsi_exec_channel *chan)
534 {
535 debug_printf("%s = {%f, %f, %f, %f}\n",
536 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
537 }
538 #endif
539
540
541 #ifdef DEBUG
542 static void
543 print_temp(const struct tgsi_exec_machine *mach, uint index)
544 {
545 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
546 int i;
547 debug_printf("Temp[%u] =\n", index);
548 for (i = 0; i < 4; i++) {
549 debug_printf(" %c: { %f, %f, %f, %f }\n",
550 "XYZW"[i],
551 tmp->xyzw[i].f[0],
552 tmp->xyzw[i].f[1],
553 tmp->xyzw[i].f[2],
554 tmp->xyzw[i].f[3]);
555 }
556 }
557 #endif
558
559
560 void
561 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
562 unsigned num_bufs,
563 const void **bufs,
564 const unsigned *buf_sizes)
565 {
566 unsigned i;
567
568 for (i = 0; i < num_bufs; i++) {
569 mach->Consts[i] = bufs[i];
570 mach->ConstsSize[i] = buf_sizes[i];
571 }
572 }
573
574
575
576
577 /**
578 * Check if there's a potential src/dst register data dependency when
579 * using SOA execution.
580 * Example:
581 * MOV T, T.yxwz;
582 * This would expand into:
583 * MOV t0, t1;
584 * MOV t1, t0;
585 * MOV t2, t3;
586 * MOV t3, t2;
587 * The second instruction will have the wrong value for t0 if executed as-is.
588 */
589 boolean
590 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
591 {
592 uint i, chan;
593
594 uint writemask = inst->Dst[0].Register.WriteMask;
595 if (writemask == TGSI_WRITEMASK_X ||
596 writemask == TGSI_WRITEMASK_Y ||
597 writemask == TGSI_WRITEMASK_Z ||
598 writemask == TGSI_WRITEMASK_W ||
599 writemask == TGSI_WRITEMASK_NONE) {
600 /* no chance of data dependency */
601 return FALSE;
602 }
603
604 /* loop over src regs */
605 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
606 if ((inst->Src[i].Register.File ==
607 inst->Dst[0].Register.File) &&
608 (inst->Src[i].Register.Index ==
609 inst->Dst[0].Register.Index)) {
610 /* loop over dest channels */
611 uint channelsWritten = 0x0;
612 FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
613 /* check if we're reading a channel that's been written */
614 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
615 if (channelsWritten & (1 << swizzle)) {
616 return TRUE;
617 }
618
619 channelsWritten |= (1 << chan);
620 }
621 }
622 }
623 return FALSE;
624 }
625
626
627 /**
628 * Initialize machine state by expanding tokens to full instructions,
629 * allocating temporary storage, setting up constants, etc.
630 * After this, we can call tgsi_exec_machine_run() many times.
631 */
632 void
633 tgsi_exec_machine_bind_shader(
634 struct tgsi_exec_machine *mach,
635 const struct tgsi_token *tokens,
636 uint numSamplers,
637 struct tgsi_sampler **samplers)
638 {
639 uint k;
640 struct tgsi_parse_context parse;
641 struct tgsi_full_instruction *instructions;
642 struct tgsi_full_declaration *declarations;
643 uint maxInstructions = 10, numInstructions = 0;
644 uint maxDeclarations = 10, numDeclarations = 0;
645
646 #if 0
647 tgsi_dump(tokens, 0);
648 #endif
649
650 util_init_math();
651
652 if (numSamplers) {
653 assert(samplers);
654 }
655
656 mach->Tokens = tokens;
657 mach->Samplers = samplers;
658
659 if (!tokens) {
660 /* unbind and free all */
661 if (mach->Declarations) {
662 FREE( mach->Declarations );
663 }
664 mach->Declarations = NULL;
665 mach->NumDeclarations = 0;
666
667 if (mach->Instructions) {
668 FREE( mach->Instructions );
669 }
670 mach->Instructions = NULL;
671 mach->NumInstructions = 0;
672
673 return;
674 }
675
676 k = tgsi_parse_init (&parse, mach->Tokens);
677 if (k != TGSI_PARSE_OK) {
678 debug_printf( "Problem parsing!\n" );
679 return;
680 }
681
682 mach->Processor = parse.FullHeader.Processor.Processor;
683 mach->ImmLimit = 0;
684
685 declarations = (struct tgsi_full_declaration *)
686 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
687
688 if (!declarations) {
689 return;
690 }
691
692 instructions = (struct tgsi_full_instruction *)
693 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
694
695 if (!instructions) {
696 FREE( declarations );
697 return;
698 }
699
700 while( !tgsi_parse_end_of_tokens( &parse ) ) {
701 uint i;
702
703 tgsi_parse_token( &parse );
704 switch( parse.FullToken.Token.Type ) {
705 case TGSI_TOKEN_TYPE_DECLARATION:
706 /* save expanded declaration */
707 if (numDeclarations == maxDeclarations) {
708 declarations = REALLOC(declarations,
709 maxDeclarations
710 * sizeof(struct tgsi_full_declaration),
711 (maxDeclarations + 10)
712 * sizeof(struct tgsi_full_declaration));
713 maxDeclarations += 10;
714 }
715 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
716 unsigned reg;
717 for (reg = parse.FullToken.FullDeclaration.Range.First;
718 reg <= parse.FullToken.FullDeclaration.Range.Last;
719 ++reg) {
720 ++mach->NumOutputs;
721 }
722 }
723 if (parse.FullToken.FullDeclaration.Declaration.File ==
724 TGSI_FILE_IMMEDIATE_ARRAY) {
725 unsigned reg;
726 struct tgsi_full_declaration *decl =
727 &parse.FullToken.FullDeclaration;
728 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
729 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
730 for( i = 0; i < 4; i++ ) {
731 int idx = reg * 4 + i;
732 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
733 }
734 }
735 }
736 memcpy(declarations + numDeclarations,
737 &parse.FullToken.FullDeclaration,
738 sizeof(declarations[0]));
739 numDeclarations++;
740 break;
741
742 case TGSI_TOKEN_TYPE_IMMEDIATE:
743 {
744 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
745 assert( size <= 4 );
746 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
747
748 for( i = 0; i < size; i++ ) {
749 mach->Imms[mach->ImmLimit][i] =
750 parse.FullToken.FullImmediate.u[i].Float;
751 }
752 mach->ImmLimit += 1;
753 }
754 break;
755
756 case TGSI_TOKEN_TYPE_INSTRUCTION:
757
758 /* save expanded instruction */
759 if (numInstructions == maxInstructions) {
760 instructions = REALLOC(instructions,
761 maxInstructions
762 * sizeof(struct tgsi_full_instruction),
763 (maxInstructions + 10)
764 * sizeof(struct tgsi_full_instruction));
765 maxInstructions += 10;
766 }
767
768 memcpy(instructions + numInstructions,
769 &parse.FullToken.FullInstruction,
770 sizeof(instructions[0]));
771
772 numInstructions++;
773 break;
774
775 case TGSI_TOKEN_TYPE_PROPERTY:
776 break;
777
778 default:
779 assert( 0 );
780 }
781 }
782 tgsi_parse_free (&parse);
783
784 if (mach->Declarations) {
785 FREE( mach->Declarations );
786 }
787 mach->Declarations = declarations;
788 mach->NumDeclarations = numDeclarations;
789
790 if (mach->Instructions) {
791 FREE( mach->Instructions );
792 }
793 mach->Instructions = instructions;
794 mach->NumInstructions = numInstructions;
795 }
796
797
798 struct tgsi_exec_machine *
799 tgsi_exec_machine_create( void )
800 {
801 struct tgsi_exec_machine *mach;
802 uint i;
803
804 mach = align_malloc( sizeof *mach, 16 );
805 if (!mach)
806 goto fail;
807
808 memset(mach, 0, sizeof(*mach));
809
810 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
811 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
812 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
813
814 /* Setup constants. */
815 for( i = 0; i < 4; i++ ) {
816 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
817 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
818 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
819 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
820 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
821 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
822 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
823 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
824 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
825 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
826 }
827
828 #ifdef DEBUG
829 /* silence warnings */
830 (void) print_chan;
831 (void) print_temp;
832 #endif
833
834 return mach;
835
836 fail:
837 align_free(mach);
838 return NULL;
839 }
840
841
842 void
843 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
844 {
845 if (mach) {
846 if (mach->Instructions)
847 FREE(mach->Instructions);
848 if (mach->Declarations)
849 FREE(mach->Declarations);
850 }
851
852 align_free(mach);
853 }
854
855 static void
856 micro_add(union tgsi_exec_channel *dst,
857 const union tgsi_exec_channel *src0,
858 const union tgsi_exec_channel *src1)
859 {
860 dst->f[0] = src0->f[0] + src1->f[0];
861 dst->f[1] = src0->f[1] + src1->f[1];
862 dst->f[2] = src0->f[2] + src1->f[2];
863 dst->f[3] = src0->f[3] + src1->f[3];
864 }
865
866 static void
867 micro_div(
868 union tgsi_exec_channel *dst,
869 const union tgsi_exec_channel *src0,
870 const union tgsi_exec_channel *src1 )
871 {
872 if (src1->f[0] != 0) {
873 dst->f[0] = src0->f[0] / src1->f[0];
874 }
875 if (src1->f[1] != 0) {
876 dst->f[1] = src0->f[1] / src1->f[1];
877 }
878 if (src1->f[2] != 0) {
879 dst->f[2] = src0->f[2] / src1->f[2];
880 }
881 if (src1->f[3] != 0) {
882 dst->f[3] = src0->f[3] / src1->f[3];
883 }
884 }
885
886 static void
887 micro_float_clamp(union tgsi_exec_channel *dst,
888 const union tgsi_exec_channel *src)
889 {
890 uint i;
891
892 for (i = 0; i < 4; i++) {
893 if (src->f[i] > 0.0f) {
894 if (src->f[i] > 1.884467e+019f)
895 dst->f[i] = 1.884467e+019f;
896 else if (src->f[i] < 5.42101e-020f)
897 dst->f[i] = 5.42101e-020f;
898 else
899 dst->f[i] = src->f[i];
900 }
901 else {
902 if (src->f[i] < -1.884467e+019f)
903 dst->f[i] = -1.884467e+019f;
904 else if (src->f[i] > -5.42101e-020f)
905 dst->f[i] = -5.42101e-020f;
906 else
907 dst->f[i] = src->f[i];
908 }
909 }
910 }
911
912 static void
913 micro_lt(
914 union tgsi_exec_channel *dst,
915 const union tgsi_exec_channel *src0,
916 const union tgsi_exec_channel *src1,
917 const union tgsi_exec_channel *src2,
918 const union tgsi_exec_channel *src3 )
919 {
920 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
921 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
922 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
923 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
924 }
925
926 static void
927 micro_max(union tgsi_exec_channel *dst,
928 const union tgsi_exec_channel *src0,
929 const union tgsi_exec_channel *src1)
930 {
931 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
932 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
933 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
934 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
935 }
936
937 static void
938 micro_min(union tgsi_exec_channel *dst,
939 const union tgsi_exec_channel *src0,
940 const union tgsi_exec_channel *src1)
941 {
942 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
943 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
944 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
945 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
946 }
947
948 static void
949 micro_mul(union tgsi_exec_channel *dst,
950 const union tgsi_exec_channel *src0,
951 const union tgsi_exec_channel *src1)
952 {
953 dst->f[0] = src0->f[0] * src1->f[0];
954 dst->f[1] = src0->f[1] * src1->f[1];
955 dst->f[2] = src0->f[2] * src1->f[2];
956 dst->f[3] = src0->f[3] * src1->f[3];
957 }
958
959 #if 0
960 static void
961 micro_imul64(
962 union tgsi_exec_channel *dst0,
963 union tgsi_exec_channel *dst1,
964 const union tgsi_exec_channel *src0,
965 const union tgsi_exec_channel *src1 )
966 {
967 dst1->i[0] = src0->i[0] * src1->i[0];
968 dst1->i[1] = src0->i[1] * src1->i[1];
969 dst1->i[2] = src0->i[2] * src1->i[2];
970 dst1->i[3] = src0->i[3] * src1->i[3];
971 dst0->i[0] = 0;
972 dst0->i[1] = 0;
973 dst0->i[2] = 0;
974 dst0->i[3] = 0;
975 }
976 #endif
977
978 #if 0
979 static void
980 micro_umul64(
981 union tgsi_exec_channel *dst0,
982 union tgsi_exec_channel *dst1,
983 const union tgsi_exec_channel *src0,
984 const union tgsi_exec_channel *src1 )
985 {
986 dst1->u[0] = src0->u[0] * src1->u[0];
987 dst1->u[1] = src0->u[1] * src1->u[1];
988 dst1->u[2] = src0->u[2] * src1->u[2];
989 dst1->u[3] = src0->u[3] * src1->u[3];
990 dst0->u[0] = 0;
991 dst0->u[1] = 0;
992 dst0->u[2] = 0;
993 dst0->u[3] = 0;
994 }
995 #endif
996
997
998 #if 0
999 static void
1000 micro_movc(
1001 union tgsi_exec_channel *dst,
1002 const union tgsi_exec_channel *src0,
1003 const union tgsi_exec_channel *src1,
1004 const union tgsi_exec_channel *src2 )
1005 {
1006 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
1007 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
1008 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
1009 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
1010 }
1011 #endif
1012
1013 static void
1014 micro_neg(
1015 union tgsi_exec_channel *dst,
1016 const union tgsi_exec_channel *src )
1017 {
1018 dst->f[0] = -src->f[0];
1019 dst->f[1] = -src->f[1];
1020 dst->f[2] = -src->f[2];
1021 dst->f[3] = -src->f[3];
1022 }
1023
1024 static void
1025 micro_pow(
1026 union tgsi_exec_channel *dst,
1027 const union tgsi_exec_channel *src0,
1028 const union tgsi_exec_channel *src1 )
1029 {
1030 #if FAST_MATH
1031 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1032 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1033 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1034 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1035 #else
1036 dst->f[0] = powf( src0->f[0], src1->f[0] );
1037 dst->f[1] = powf( src0->f[1], src1->f[1] );
1038 dst->f[2] = powf( src0->f[2], src1->f[2] );
1039 dst->f[3] = powf( src0->f[3], src1->f[3] );
1040 #endif
1041 }
1042
1043 static void
1044 micro_sub(union tgsi_exec_channel *dst,
1045 const union tgsi_exec_channel *src0,
1046 const union tgsi_exec_channel *src1)
1047 {
1048 dst->f[0] = src0->f[0] - src1->f[0];
1049 dst->f[1] = src0->f[1] - src1->f[1];
1050 dst->f[2] = src0->f[2] - src1->f[2];
1051 dst->f[3] = src0->f[3] - src1->f[3];
1052 }
1053
1054 static void
1055 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1056 const uint file,
1057 const uint swizzle,
1058 const union tgsi_exec_channel *index,
1059 const union tgsi_exec_channel *index2D,
1060 union tgsi_exec_channel *chan)
1061 {
1062 uint i;
1063
1064 assert(swizzle < 4);
1065
1066 switch (file) {
1067 case TGSI_FILE_CONSTANT:
1068 for (i = 0; i < QUAD_SIZE; i++) {
1069 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1070 assert(mach->Consts[index2D->i[i]]);
1071
1072 if (index->i[i] < 0) {
1073 chan->u[i] = 0;
1074 } else {
1075 /* NOTE: copying the const value as a uint instead of float */
1076 const uint constbuf = index2D->i[i];
1077 const uint *buf = (const uint *)mach->Consts[constbuf];
1078 const int pos = index->i[i] * 4 + swizzle;
1079 /* const buffer bounds check */
1080 if (pos < 0 || pos >= mach->ConstsSize[constbuf]) {
1081 if (0) {
1082 /* Debug: print warning */
1083 static int count = 0;
1084 if (count++ < 100)
1085 debug_printf("TGSI Exec: const buffer index %d"
1086 " out of bounds\n", pos);
1087 }
1088 chan->u[i] = 0;
1089 }
1090 else
1091 chan->u[i] = buf[pos];
1092 }
1093 }
1094 break;
1095
1096 case TGSI_FILE_INPUT:
1097 case TGSI_FILE_SYSTEM_VALUE:
1098 for (i = 0; i < QUAD_SIZE; i++) {
1099 /*
1100 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1101 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1102 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1103 index2D->i[i], index->i[i]);
1104 }*/
1105 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1106 assert(pos >= 0);
1107 assert(pos < Elements(mach->Inputs));
1108 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1109 }
1110 break;
1111
1112 case TGSI_FILE_TEMPORARY:
1113 for (i = 0; i < QUAD_SIZE; i++) {
1114 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1115 assert(index2D->i[i] == 0);
1116
1117 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1118 }
1119 break;
1120
1121 case TGSI_FILE_TEMPORARY_ARRAY:
1122 for (i = 0; i < QUAD_SIZE; i++) {
1123 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1124 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1125
1126 chan->u[i] =
1127 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1128 }
1129 break;
1130
1131 case TGSI_FILE_IMMEDIATE:
1132 for (i = 0; i < QUAD_SIZE; i++) {
1133 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1134 assert(index2D->i[i] == 0);
1135
1136 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1137 }
1138 break;
1139
1140 case TGSI_FILE_IMMEDIATE_ARRAY:
1141 for (i = 0; i < QUAD_SIZE; i++) {
1142 assert(index2D->i[i] == 0);
1143
1144 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1145 }
1146 break;
1147
1148 case TGSI_FILE_ADDRESS:
1149 for (i = 0; i < QUAD_SIZE; i++) {
1150 assert(index->i[i] >= 0);
1151 assert(index2D->i[i] == 0);
1152
1153 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1154 }
1155 break;
1156
1157 case TGSI_FILE_PREDICATE:
1158 for (i = 0; i < QUAD_SIZE; i++) {
1159 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1160 assert(index2D->i[i] == 0);
1161
1162 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1163 }
1164 break;
1165
1166 case TGSI_FILE_OUTPUT:
1167 /* vertex/fragment output vars can be read too */
1168 for (i = 0; i < QUAD_SIZE; i++) {
1169 assert(index->i[i] >= 0);
1170 assert(index2D->i[i] == 0);
1171
1172 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1173 }
1174 break;
1175
1176 default:
1177 assert(0);
1178 for (i = 0; i < QUAD_SIZE; i++) {
1179 chan->u[i] = 0;
1180 }
1181 }
1182 }
1183
1184 static void
1185 fetch_source(const struct tgsi_exec_machine *mach,
1186 union tgsi_exec_channel *chan,
1187 const struct tgsi_full_src_register *reg,
1188 const uint chan_index,
1189 enum tgsi_exec_datatype src_datatype)
1190 {
1191 union tgsi_exec_channel index;
1192 union tgsi_exec_channel index2D;
1193 uint swizzle;
1194
1195 /* We start with a direct index into a register file.
1196 *
1197 * file[1],
1198 * where:
1199 * file = Register.File
1200 * [1] = Register.Index
1201 */
1202 index.i[0] =
1203 index.i[1] =
1204 index.i[2] =
1205 index.i[3] = reg->Register.Index;
1206
1207 /* There is an extra source register that indirectly subscripts
1208 * a register file. The direct index now becomes an offset
1209 * that is being added to the indirect register.
1210 *
1211 * file[ind[2].x+1],
1212 * where:
1213 * ind = Indirect.File
1214 * [2] = Indirect.Index
1215 * .x = Indirect.SwizzleX
1216 */
1217 if (reg->Register.Indirect) {
1218 union tgsi_exec_channel index2;
1219 union tgsi_exec_channel indir_index;
1220 const uint execmask = mach->ExecMask;
1221 uint i;
1222
1223 /* which address register (always zero now) */
1224 index2.i[0] =
1225 index2.i[1] =
1226 index2.i[2] =
1227 index2.i[3] = reg->Indirect.Index;
1228 assert(reg->Indirect.File == TGSI_FILE_ADDRESS);
1229 /* get current value of address register[swizzle] */
1230 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1231 fetch_src_file_channel(mach,
1232 reg->Indirect.File,
1233 swizzle,
1234 &index2,
1235 &ZeroVec,
1236 &indir_index);
1237
1238 /* add value of address register to the offset */
1239 index.i[0] += indir_index.i[0];
1240 index.i[1] += indir_index.i[1];
1241 index.i[2] += indir_index.i[2];
1242 index.i[3] += indir_index.i[3];
1243
1244 /* for disabled execution channels, zero-out the index to
1245 * avoid using a potential garbage value.
1246 */
1247 for (i = 0; i < QUAD_SIZE; i++) {
1248 if ((execmask & (1 << i)) == 0)
1249 index.i[i] = 0;
1250 }
1251 }
1252
1253 /* There is an extra source register that is a second
1254 * subscript to a register file. Effectively it means that
1255 * the register file is actually a 2D array of registers.
1256 *
1257 * file[3][1],
1258 * where:
1259 * [3] = Dimension.Index
1260 */
1261 if (reg->Register.Dimension) {
1262 index2D.i[0] =
1263 index2D.i[1] =
1264 index2D.i[2] =
1265 index2D.i[3] = reg->Dimension.Index;
1266
1267 /* Again, the second subscript index can be addressed indirectly
1268 * identically to the first one.
1269 * Nothing stops us from indirectly addressing the indirect register,
1270 * but there is no need for that, so we won't exercise it.
1271 *
1272 * file[ind[4].y+3][1],
1273 * where:
1274 * ind = DimIndirect.File
1275 * [4] = DimIndirect.Index
1276 * .y = DimIndirect.SwizzleX
1277 */
1278 if (reg->Dimension.Indirect) {
1279 union tgsi_exec_channel index2;
1280 union tgsi_exec_channel indir_index;
1281 const uint execmask = mach->ExecMask;
1282 uint i;
1283
1284 index2.i[0] =
1285 index2.i[1] =
1286 index2.i[2] =
1287 index2.i[3] = reg->DimIndirect.Index;
1288
1289 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1290 fetch_src_file_channel(mach,
1291 reg->DimIndirect.File,
1292 swizzle,
1293 &index2,
1294 &ZeroVec,
1295 &indir_index);
1296
1297 index2D.i[0] += indir_index.i[0];
1298 index2D.i[1] += indir_index.i[1];
1299 index2D.i[2] += indir_index.i[2];
1300 index2D.i[3] += indir_index.i[3];
1301
1302 /* for disabled execution channels, zero-out the index to
1303 * avoid using a potential garbage value.
1304 */
1305 for (i = 0; i < QUAD_SIZE; i++) {
1306 if ((execmask & (1 << i)) == 0) {
1307 index2D.i[i] = 0;
1308 }
1309 }
1310 }
1311
1312 /* If by any chance there was a need for a 3D array of register
1313 * files, we would have to check whether Dimension is followed
1314 * by a dimension register and continue the saga.
1315 */
1316 } else {
1317 index2D.i[0] =
1318 index2D.i[1] =
1319 index2D.i[2] =
1320 index2D.i[3] = 0;
1321 }
1322
1323 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1324 fetch_src_file_channel(mach,
1325 reg->Register.File,
1326 swizzle,
1327 &index,
1328 &index2D,
1329 chan);
1330
1331 if (reg->Register.Absolute) {
1332 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1333 micro_abs(chan, chan);
1334 } else {
1335 micro_iabs(chan, chan);
1336 }
1337 }
1338
1339 if (reg->Register.Negate) {
1340 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1341 micro_neg(chan, chan);
1342 } else {
1343 micro_ineg(chan, chan);
1344 }
1345 }
1346 }
1347
1348 static void
1349 store_dest(struct tgsi_exec_machine *mach,
1350 const union tgsi_exec_channel *chan,
1351 const struct tgsi_full_dst_register *reg,
1352 const struct tgsi_full_instruction *inst,
1353 uint chan_index,
1354 enum tgsi_exec_datatype dst_datatype)
1355 {
1356 uint i;
1357 union tgsi_exec_channel null;
1358 union tgsi_exec_channel *dst;
1359 union tgsi_exec_channel index2D;
1360 uint execmask = mach->ExecMask;
1361 int offset = 0; /* indirection offset */
1362 int index;
1363
1364 /* for debugging */
1365 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1366 check_inf_or_nan(chan);
1367 }
1368
1369 /* There is an extra source register that indirectly subscripts
1370 * a register file. The direct index now becomes an offset
1371 * that is being added to the indirect register.
1372 *
1373 * file[ind[2].x+1],
1374 * where:
1375 * ind = Indirect.File
1376 * [2] = Indirect.Index
1377 * .x = Indirect.SwizzleX
1378 */
1379 if (reg->Register.Indirect) {
1380 union tgsi_exec_channel index;
1381 union tgsi_exec_channel indir_index;
1382 uint swizzle;
1383
1384 /* which address register (always zero for now) */
1385 index.i[0] =
1386 index.i[1] =
1387 index.i[2] =
1388 index.i[3] = reg->Indirect.Index;
1389
1390 /* get current value of address register[swizzle] */
1391 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1392
1393 /* fetch values from the address/indirection register */
1394 fetch_src_file_channel(mach,
1395 reg->Indirect.File,
1396 swizzle,
1397 &index,
1398 &ZeroVec,
1399 &indir_index);
1400
1401 /* save indirection offset */
1402 offset = indir_index.i[0];
1403 }
1404
1405 /* There is an extra source register that is a second
1406 * subscript to a register file. Effectively it means that
1407 * the register file is actually a 2D array of registers.
1408 *
1409 * file[3][1],
1410 * where:
1411 * [3] = Dimension.Index
1412 */
1413 if (reg->Register.Dimension) {
1414 index2D.i[0] =
1415 index2D.i[1] =
1416 index2D.i[2] =
1417 index2D.i[3] = reg->Dimension.Index;
1418
1419 /* Again, the second subscript index can be addressed indirectly
1420 * identically to the first one.
1421 * Nothing stops us from indirectly addressing the indirect register,
1422 * but there is no need for that, so we won't exercise it.
1423 *
1424 * file[ind[4].y+3][1],
1425 * where:
1426 * ind = DimIndirect.File
1427 * [4] = DimIndirect.Index
1428 * .y = DimIndirect.SwizzleX
1429 */
1430 if (reg->Dimension.Indirect) {
1431 union tgsi_exec_channel index2;
1432 union tgsi_exec_channel indir_index;
1433 const uint execmask = mach->ExecMask;
1434 unsigned swizzle;
1435 uint i;
1436
1437 index2.i[0] =
1438 index2.i[1] =
1439 index2.i[2] =
1440 index2.i[3] = reg->DimIndirect.Index;
1441
1442 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1443 fetch_src_file_channel(mach,
1444 reg->DimIndirect.File,
1445 swizzle,
1446 &index2,
1447 &ZeroVec,
1448 &indir_index);
1449
1450 index2D.i[0] += indir_index.i[0];
1451 index2D.i[1] += indir_index.i[1];
1452 index2D.i[2] += indir_index.i[2];
1453 index2D.i[3] += indir_index.i[3];
1454
1455 /* for disabled execution channels, zero-out the index to
1456 * avoid using a potential garbage value.
1457 */
1458 for (i = 0; i < QUAD_SIZE; i++) {
1459 if ((execmask & (1 << i)) == 0) {
1460 index2D.i[i] = 0;
1461 }
1462 }
1463 }
1464
1465 /* If by any chance there was a need for a 3D array of register
1466 * files, we would have to check whether Dimension is followed
1467 * by a dimension register and continue the saga.
1468 */
1469 } else {
1470 index2D.i[0] =
1471 index2D.i[1] =
1472 index2D.i[2] =
1473 index2D.i[3] = 0;
1474 }
1475
1476 switch (reg->Register.File) {
1477 case TGSI_FILE_NULL:
1478 dst = &null;
1479 break;
1480
1481 case TGSI_FILE_OUTPUT:
1482 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1483 + reg->Register.Index;
1484 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1485 #if 0
1486 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1487 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1488 for (i = 0; i < QUAD_SIZE; i++)
1489 if (execmask & (1 << i))
1490 fprintf(stderr, "%f, ", chan->f[i]);
1491 fprintf(stderr, ")\n");
1492 }
1493 #endif
1494 break;
1495
1496 case TGSI_FILE_TEMPORARY:
1497 index = reg->Register.Index;
1498 assert( index < TGSI_EXEC_NUM_TEMPS );
1499 dst = &mach->Temps[offset + index].xyzw[chan_index];
1500 break;
1501
1502 case TGSI_FILE_TEMPORARY_ARRAY:
1503 index = reg->Register.Index;
1504 assert( index < TGSI_EXEC_NUM_TEMPS );
1505 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1506 /* XXX we use index2D.i[0] here but somehow we might
1507 * end up with someone trying to store indirectly in
1508 * different buffers */
1509 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1510 break;
1511
1512 case TGSI_FILE_ADDRESS:
1513 index = reg->Register.Index;
1514 dst = &mach->Addrs[index].xyzw[chan_index];
1515 break;
1516
1517 case TGSI_FILE_PREDICATE:
1518 index = reg->Register.Index;
1519 assert(index < TGSI_EXEC_NUM_PREDS);
1520 dst = &mach->Predicates[index].xyzw[chan_index];
1521 break;
1522
1523 default:
1524 assert( 0 );
1525 return;
1526 }
1527
1528 if (inst->Instruction.Predicate) {
1529 uint swizzle;
1530 union tgsi_exec_channel *pred;
1531
1532 switch (chan_index) {
1533 case CHAN_X:
1534 swizzle = inst->Predicate.SwizzleX;
1535 break;
1536 case CHAN_Y:
1537 swizzle = inst->Predicate.SwizzleY;
1538 break;
1539 case CHAN_Z:
1540 swizzle = inst->Predicate.SwizzleZ;
1541 break;
1542 case CHAN_W:
1543 swizzle = inst->Predicate.SwizzleW;
1544 break;
1545 default:
1546 assert(0);
1547 return;
1548 }
1549
1550 assert(inst->Predicate.Index == 0);
1551
1552 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1553
1554 if (inst->Predicate.Negate) {
1555 for (i = 0; i < QUAD_SIZE; i++) {
1556 if (pred->u[i]) {
1557 execmask &= ~(1 << i);
1558 }
1559 }
1560 } else {
1561 for (i = 0; i < QUAD_SIZE; i++) {
1562 if (!pred->u[i]) {
1563 execmask &= ~(1 << i);
1564 }
1565 }
1566 }
1567 }
1568
1569 switch (inst->Instruction.Saturate) {
1570 case TGSI_SAT_NONE:
1571 for (i = 0; i < QUAD_SIZE; i++)
1572 if (execmask & (1 << i))
1573 dst->i[i] = chan->i[i];
1574 break;
1575
1576 case TGSI_SAT_ZERO_ONE:
1577 for (i = 0; i < QUAD_SIZE; i++)
1578 if (execmask & (1 << i)) {
1579 if (chan->f[i] < 0.0f)
1580 dst->f[i] = 0.0f;
1581 else if (chan->f[i] > 1.0f)
1582 dst->f[i] = 1.0f;
1583 else
1584 dst->i[i] = chan->i[i];
1585 }
1586 break;
1587
1588 case TGSI_SAT_MINUS_PLUS_ONE:
1589 for (i = 0; i < QUAD_SIZE; i++)
1590 if (execmask & (1 << i)) {
1591 if (chan->f[i] < -1.0f)
1592 dst->f[i] = -1.0f;
1593 else if (chan->f[i] > 1.0f)
1594 dst->f[i] = 1.0f;
1595 else
1596 dst->i[i] = chan->i[i];
1597 }
1598 break;
1599
1600 default:
1601 assert( 0 );
1602 }
1603 }
1604
1605 #define FETCH(VAL,INDEX,CHAN)\
1606 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1607
1608 #define STORE(VAL,INDEX,CHAN)\
1609 store_dest(mach, VAL, &inst->Dst[INDEX], inst, CHAN, TGSI_EXEC_DATA_FLOAT)
1610
1611
1612 /**
1613 * Execute ARB-style KIL which is predicated by a src register.
1614 * Kill fragment if any of the four values is less than zero.
1615 */
1616 static void
1617 exec_kil(struct tgsi_exec_machine *mach,
1618 const struct tgsi_full_instruction *inst)
1619 {
1620 uint uniquemask;
1621 uint chan_index;
1622 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1623 union tgsi_exec_channel r[1];
1624
1625 /* This mask stores component bits that were already tested. */
1626 uniquemask = 0;
1627
1628 for (chan_index = 0; chan_index < 4; chan_index++)
1629 {
1630 uint swizzle;
1631 uint i;
1632
1633 /* unswizzle channel */
1634 swizzle = tgsi_util_get_full_src_register_swizzle (
1635 &inst->Src[0],
1636 chan_index);
1637
1638 /* check if the component has not been already tested */
1639 if (uniquemask & (1 << swizzle))
1640 continue;
1641 uniquemask |= 1 << swizzle;
1642
1643 FETCH(&r[0], 0, chan_index);
1644 for (i = 0; i < 4; i++)
1645 if (r[0].f[i] < 0.0f)
1646 kilmask |= 1 << i;
1647 }
1648
1649 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1650 }
1651
1652 /**
1653 * Execute NVIDIA-style KIL which is predicated by a condition code.
1654 * Kill fragment if the condition code is TRUE.
1655 */
1656 static void
1657 exec_kilp(struct tgsi_exec_machine *mach,
1658 const struct tgsi_full_instruction *inst)
1659 {
1660 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1661
1662 /* "unconditional" kil */
1663 kilmask = mach->ExecMask;
1664 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1665 }
1666
1667 static void
1668 emit_vertex(struct tgsi_exec_machine *mach)
1669 {
1670 /* FIXME: check for exec mask correctly
1671 unsigned i;
1672 for (i = 0; i < QUAD_SIZE; ++i) {
1673 if ((mach->ExecMask & (1 << i)))
1674 */
1675 if (mach->ExecMask) {
1676 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1677 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1678 }
1679 }
1680
1681 static void
1682 emit_primitive(struct tgsi_exec_machine *mach)
1683 {
1684 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1685 /* FIXME: check for exec mask correctly
1686 unsigned i;
1687 for (i = 0; i < QUAD_SIZE; ++i) {
1688 if ((mach->ExecMask & (1 << i)))
1689 */
1690 if (mach->ExecMask) {
1691 ++(*prim_count);
1692 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1693 mach->Primitives[*prim_count] = 0;
1694 }
1695 }
1696
1697 static void
1698 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1699 {
1700 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1701 int emitted_verts =
1702 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1703 if (emitted_verts) {
1704 emit_primitive(mach);
1705 }
1706 }
1707 }
1708
1709
1710 /*
1711 * Fetch four texture samples using STR texture coordinates.
1712 */
1713 static void
1714 fetch_texel( struct tgsi_sampler *sampler,
1715 const union tgsi_exec_channel *s,
1716 const union tgsi_exec_channel *t,
1717 const union tgsi_exec_channel *p,
1718 const union tgsi_exec_channel *c0,
1719 enum tgsi_sampler_control control,
1720 union tgsi_exec_channel *r,
1721 union tgsi_exec_channel *g,
1722 union tgsi_exec_channel *b,
1723 union tgsi_exec_channel *a )
1724 {
1725 uint j;
1726 float rgba[NUM_CHANNELS][QUAD_SIZE];
1727
1728 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1729
1730 for (j = 0; j < 4; j++) {
1731 r->f[j] = rgba[0][j];
1732 g->f[j] = rgba[1][j];
1733 b->f[j] = rgba[2][j];
1734 a->f[j] = rgba[3][j];
1735 }
1736 }
1737
1738
1739 #define TEX_MODIFIER_NONE 0
1740 #define TEX_MODIFIER_PROJECTED 1
1741 #define TEX_MODIFIER_LOD_BIAS 2
1742 #define TEX_MODIFIER_EXPLICIT_LOD 3
1743
1744
1745 static void
1746 exec_tex(struct tgsi_exec_machine *mach,
1747 const struct tgsi_full_instruction *inst,
1748 uint modifier)
1749 {
1750 const uint unit = inst->Src[1].Register.Index;
1751 union tgsi_exec_channel r[4];
1752 const union tgsi_exec_channel *lod = &ZeroVec;
1753 enum tgsi_sampler_control control;
1754 uint chan_index;
1755
1756 if (modifier != TEX_MODIFIER_NONE) {
1757 FETCH(&r[3], 0, CHAN_W);
1758 if (modifier != TEX_MODIFIER_PROJECTED) {
1759 lod = &r[3];
1760 }
1761 }
1762
1763 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1764 control = tgsi_sampler_lod_explicit;
1765 } else {
1766 control = tgsi_sampler_lod_bias;
1767 }
1768
1769 switch (inst->Texture.Texture) {
1770 case TGSI_TEXTURE_1D:
1771 case TGSI_TEXTURE_SHADOW1D:
1772 FETCH(&r[0], 0, CHAN_X);
1773
1774 if (modifier == TEX_MODIFIER_PROJECTED) {
1775 micro_div(&r[0], &r[0], &r[3]);
1776 }
1777
1778 fetch_texel(mach->Samplers[unit],
1779 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1780 control,
1781 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1782 break;
1783
1784 case TGSI_TEXTURE_2D:
1785 case TGSI_TEXTURE_RECT:
1786 case TGSI_TEXTURE_SHADOW2D:
1787 case TGSI_TEXTURE_SHADOWRECT:
1788 FETCH(&r[0], 0, CHAN_X);
1789 FETCH(&r[1], 0, CHAN_Y);
1790 FETCH(&r[2], 0, CHAN_Z);
1791
1792 if (modifier == TEX_MODIFIER_PROJECTED) {
1793 micro_div(&r[0], &r[0], &r[3]);
1794 micro_div(&r[1], &r[1], &r[3]);
1795 micro_div(&r[2], &r[2], &r[3]);
1796 }
1797
1798 fetch_texel(mach->Samplers[unit],
1799 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1800 control,
1801 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1802 break;
1803
1804 case TGSI_TEXTURE_3D:
1805 case TGSI_TEXTURE_CUBE:
1806 FETCH(&r[0], 0, CHAN_X);
1807 FETCH(&r[1], 0, CHAN_Y);
1808 FETCH(&r[2], 0, CHAN_Z);
1809
1810 if (modifier == TEX_MODIFIER_PROJECTED) {
1811 micro_div(&r[0], &r[0], &r[3]);
1812 micro_div(&r[1], &r[1], &r[3]);
1813 micro_div(&r[2], &r[2], &r[3]);
1814 }
1815
1816 fetch_texel(mach->Samplers[unit],
1817 &r[0], &r[1], &r[2], lod,
1818 control,
1819 &r[0], &r[1], &r[2], &r[3]);
1820 break;
1821
1822 default:
1823 assert(0);
1824 }
1825
1826 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1827 STORE(&r[chan_index], 0, chan_index);
1828 }
1829 }
1830
1831 static void
1832 exec_txd(struct tgsi_exec_machine *mach,
1833 const struct tgsi_full_instruction *inst)
1834 {
1835 const uint unit = inst->Src[3].Register.Index;
1836 union tgsi_exec_channel r[4];
1837 uint chan_index;
1838
1839 /*
1840 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1841 */
1842
1843 switch (inst->Texture.Texture) {
1844 case TGSI_TEXTURE_1D:
1845 case TGSI_TEXTURE_SHADOW1D:
1846
1847 FETCH(&r[0], 0, CHAN_X);
1848
1849 fetch_texel(mach->Samplers[unit],
1850 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1851 tgsi_sampler_lod_bias,
1852 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1853 break;
1854
1855 case TGSI_TEXTURE_2D:
1856 case TGSI_TEXTURE_RECT:
1857 case TGSI_TEXTURE_SHADOW2D:
1858 case TGSI_TEXTURE_SHADOWRECT:
1859
1860 FETCH(&r[0], 0, CHAN_X);
1861 FETCH(&r[1], 0, CHAN_Y);
1862 FETCH(&r[2], 0, CHAN_Z);
1863
1864 fetch_texel(mach->Samplers[unit],
1865 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1866 tgsi_sampler_lod_bias,
1867 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1868 break;
1869
1870 case TGSI_TEXTURE_3D:
1871 case TGSI_TEXTURE_CUBE:
1872
1873 FETCH(&r[0], 0, CHAN_X);
1874 FETCH(&r[1], 0, CHAN_Y);
1875 FETCH(&r[2], 0, CHAN_Z);
1876
1877 fetch_texel(mach->Samplers[unit],
1878 &r[0], &r[1], &r[2], &ZeroVec,
1879 tgsi_sampler_lod_bias,
1880 &r[0], &r[1], &r[2], &r[3]);
1881 break;
1882
1883 default:
1884 assert(0);
1885 }
1886
1887 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1888 STORE(&r[chan_index], 0, chan_index);
1889 }
1890 }
1891
1892
1893 /**
1894 * Evaluate a constant-valued coefficient at the position of the
1895 * current quad.
1896 */
1897 static void
1898 eval_constant_coef(
1899 struct tgsi_exec_machine *mach,
1900 unsigned attrib,
1901 unsigned chan )
1902 {
1903 unsigned i;
1904
1905 for( i = 0; i < QUAD_SIZE; i++ ) {
1906 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1907 }
1908 }
1909
1910 /**
1911 * Evaluate a linear-valued coefficient at the position of the
1912 * current quad.
1913 */
1914 static void
1915 eval_linear_coef(
1916 struct tgsi_exec_machine *mach,
1917 unsigned attrib,
1918 unsigned chan )
1919 {
1920 const float x = mach->QuadPos.xyzw[0].f[0];
1921 const float y = mach->QuadPos.xyzw[1].f[0];
1922 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1923 const float dady = mach->InterpCoefs[attrib].dady[chan];
1924 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1925 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1926 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1927 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1928 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1929 }
1930
1931 /**
1932 * Evaluate a perspective-valued coefficient at the position of the
1933 * current quad.
1934 */
1935 static void
1936 eval_perspective_coef(
1937 struct tgsi_exec_machine *mach,
1938 unsigned attrib,
1939 unsigned chan )
1940 {
1941 const float x = mach->QuadPos.xyzw[0].f[0];
1942 const float y = mach->QuadPos.xyzw[1].f[0];
1943 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1944 const float dady = mach->InterpCoefs[attrib].dady[chan];
1945 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1946 const float *w = mach->QuadPos.xyzw[3].f;
1947 /* divide by W here */
1948 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1949 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1950 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1951 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1952 }
1953
1954
1955 typedef void (* eval_coef_func)(
1956 struct tgsi_exec_machine *mach,
1957 unsigned attrib,
1958 unsigned chan );
1959
1960 static void
1961 exec_declaration(struct tgsi_exec_machine *mach,
1962 const struct tgsi_full_declaration *decl)
1963 {
1964 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
1965 if (decl->Declaration.File == TGSI_FILE_INPUT ||
1966 decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1967 uint first, last, mask;
1968
1969 first = decl->Range.First;
1970 last = decl->Range.Last;
1971 mask = decl->Declaration.UsageMask;
1972
1973 /* XXX we could remove this special-case code since
1974 * mach->InterpCoefs[first].a0 should already have the
1975 * front/back-face value. But we should first update the
1976 * ureg code to emit the right UsageMask value (WRITEMASK_X).
1977 * Then, we could remove the tgsi_exec_machine::Face field.
1978 */
1979 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1980 uint i;
1981
1982 assert(decl->Semantic.Index == 0);
1983 assert(first == last);
1984
1985 for (i = 0; i < QUAD_SIZE; i++) {
1986 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
1987 }
1988 } else {
1989 eval_coef_func eval;
1990 uint i, j;
1991
1992 switch (decl->Declaration.Interpolate) {
1993 case TGSI_INTERPOLATE_CONSTANT:
1994 eval = eval_constant_coef;
1995 break;
1996
1997 case TGSI_INTERPOLATE_LINEAR:
1998 eval = eval_linear_coef;
1999 break;
2000
2001 case TGSI_INTERPOLATE_PERSPECTIVE:
2002 eval = eval_perspective_coef;
2003 break;
2004
2005 default:
2006 assert(0);
2007 return;
2008 }
2009
2010 for (j = 0; j < NUM_CHANNELS; j++) {
2011 if (mask & (1 << j)) {
2012 for (i = first; i <= last; i++) {
2013 eval(mach, i, j);
2014 }
2015 }
2016 }
2017 }
2018 }
2019 }
2020 }
2021
2022 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2023 const union tgsi_exec_channel *src);
2024
2025 static void
2026 exec_scalar_unary(struct tgsi_exec_machine *mach,
2027 const struct tgsi_full_instruction *inst,
2028 micro_unary_op op,
2029 enum tgsi_exec_datatype dst_datatype,
2030 enum tgsi_exec_datatype src_datatype)
2031 {
2032 unsigned int chan;
2033 union tgsi_exec_channel src;
2034 union tgsi_exec_channel dst;
2035
2036 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
2037 op(&dst, &src);
2038 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2039 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2040 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2041 }
2042 }
2043 }
2044
2045 static void
2046 exec_vector_unary(struct tgsi_exec_machine *mach,
2047 const struct tgsi_full_instruction *inst,
2048 micro_unary_op op,
2049 enum tgsi_exec_datatype dst_datatype,
2050 enum tgsi_exec_datatype src_datatype)
2051 {
2052 unsigned int chan;
2053 struct tgsi_exec_vector dst;
2054
2055 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2056 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2057 union tgsi_exec_channel src;
2058
2059 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2060 op(&dst.xyzw[chan], &src);
2061 }
2062 }
2063 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2064 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2065 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2066 }
2067 }
2068 }
2069
2070 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2071 const union tgsi_exec_channel *src0,
2072 const union tgsi_exec_channel *src1);
2073
2074 static void
2075 exec_vector_binary(struct tgsi_exec_machine *mach,
2076 const struct tgsi_full_instruction *inst,
2077 micro_binary_op op,
2078 enum tgsi_exec_datatype dst_datatype,
2079 enum tgsi_exec_datatype src_datatype)
2080 {
2081 unsigned int chan;
2082 struct tgsi_exec_vector dst;
2083
2084 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2085 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2086 union tgsi_exec_channel src[2];
2087
2088 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2089 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2090 op(&dst.xyzw[chan], &src[0], &src[1]);
2091 }
2092 }
2093 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2094 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2095 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2096 }
2097 }
2098 }
2099
2100 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2101 const union tgsi_exec_channel *src0,
2102 const union tgsi_exec_channel *src1,
2103 const union tgsi_exec_channel *src2);
2104
2105 static void
2106 exec_vector_trinary(struct tgsi_exec_machine *mach,
2107 const struct tgsi_full_instruction *inst,
2108 micro_trinary_op op,
2109 enum tgsi_exec_datatype dst_datatype,
2110 enum tgsi_exec_datatype src_datatype)
2111 {
2112 unsigned int chan;
2113 struct tgsi_exec_vector dst;
2114
2115 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2116 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2117 union tgsi_exec_channel src[3];
2118
2119 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2120 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2121 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2122 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2123 }
2124 }
2125 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2126 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2127 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2128 }
2129 }
2130 }
2131
2132 static void
2133 exec_dp3(struct tgsi_exec_machine *mach,
2134 const struct tgsi_full_instruction *inst)
2135 {
2136 unsigned int chan;
2137 union tgsi_exec_channel arg[3];
2138
2139 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2140 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2141 micro_mul(&arg[2], &arg[0], &arg[1]);
2142
2143 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2144 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2145 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2146 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2147 }
2148
2149 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2150 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2151 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2152 }
2153 }
2154 }
2155
2156 static void
2157 exec_dp4(struct tgsi_exec_machine *mach,
2158 const struct tgsi_full_instruction *inst)
2159 {
2160 unsigned int chan;
2161 union tgsi_exec_channel arg[3];
2162
2163 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2164 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2165 micro_mul(&arg[2], &arg[0], &arg[1]);
2166
2167 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2168 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2169 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2170 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2171 }
2172
2173 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2174 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2175 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2176 }
2177 }
2178 }
2179
2180 static void
2181 exec_dp2a(struct tgsi_exec_machine *mach,
2182 const struct tgsi_full_instruction *inst)
2183 {
2184 unsigned int chan;
2185 union tgsi_exec_channel arg[3];
2186
2187 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2188 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2189 micro_mul(&arg[2], &arg[0], &arg[1]);
2190
2191 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2192 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2193 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2194
2195 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2196 micro_add(&arg[0], &arg[0], &arg[1]);
2197
2198 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2199 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2200 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2201 }
2202 }
2203 }
2204
2205 static void
2206 exec_dph(struct tgsi_exec_machine *mach,
2207 const struct tgsi_full_instruction *inst)
2208 {
2209 unsigned int chan;
2210 union tgsi_exec_channel arg[3];
2211
2212 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2213 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2214 micro_mul(&arg[2], &arg[0], &arg[1]);
2215
2216 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2217 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2218 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2219
2220 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2221 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2222 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2223
2224 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2225 micro_add(&arg[0], &arg[0], &arg[1]);
2226
2227 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2228 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2229 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2230 }
2231 }
2232 }
2233
2234 static void
2235 exec_dp2(struct tgsi_exec_machine *mach,
2236 const struct tgsi_full_instruction *inst)
2237 {
2238 unsigned int chan;
2239 union tgsi_exec_channel arg[3];
2240
2241 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2242 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2243 micro_mul(&arg[2], &arg[0], &arg[1]);
2244
2245 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2246 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2247 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2248
2249 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2250 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2251 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2252 }
2253 }
2254 }
2255
2256 static void
2257 exec_nrm4(struct tgsi_exec_machine *mach,
2258 const struct tgsi_full_instruction *inst)
2259 {
2260 unsigned int chan;
2261 union tgsi_exec_channel arg[4];
2262 union tgsi_exec_channel scale;
2263
2264 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2265 micro_mul(&scale, &arg[0], &arg[0]);
2266
2267 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2268 union tgsi_exec_channel product;
2269
2270 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2271 micro_mul(&product, &arg[chan], &arg[chan]);
2272 micro_add(&scale, &scale, &product);
2273 }
2274
2275 micro_rsq(&scale, &scale);
2276
2277 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2278 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2279 micro_mul(&arg[chan], &arg[chan], &scale);
2280 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2281 }
2282 }
2283 }
2284
2285 static void
2286 exec_nrm3(struct tgsi_exec_machine *mach,
2287 const struct tgsi_full_instruction *inst)
2288 {
2289 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2290 unsigned int chan;
2291 union tgsi_exec_channel arg[3];
2292 union tgsi_exec_channel scale;
2293
2294 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2295 micro_mul(&scale, &arg[0], &arg[0]);
2296
2297 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2298 union tgsi_exec_channel product;
2299
2300 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2301 micro_mul(&product, &arg[chan], &arg[chan]);
2302 micro_add(&scale, &scale, &product);
2303 }
2304
2305 micro_rsq(&scale, &scale);
2306
2307 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2308 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2309 micro_mul(&arg[chan], &arg[chan], &scale);
2310 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2311 }
2312 }
2313 }
2314
2315 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2316 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2317 }
2318 }
2319
2320 static void
2321 exec_break(struct tgsi_exec_machine *mach)
2322 {
2323 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2324 /* turn off loop channels for each enabled exec channel */
2325 mach->LoopMask &= ~mach->ExecMask;
2326 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2327 UPDATE_EXEC_MASK(mach);
2328 } else {
2329 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2330
2331 mach->Switch.mask = 0x0;
2332
2333 UPDATE_EXEC_MASK(mach);
2334 }
2335 }
2336
2337 static void
2338 exec_switch(struct tgsi_exec_machine *mach,
2339 const struct tgsi_full_instruction *inst)
2340 {
2341 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2342 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2343
2344 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2345 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2346 mach->Switch.mask = 0x0;
2347 mach->Switch.defaultMask = 0x0;
2348
2349 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2350 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2351
2352 UPDATE_EXEC_MASK(mach);
2353 }
2354
2355 static void
2356 exec_case(struct tgsi_exec_machine *mach,
2357 const struct tgsi_full_instruction *inst)
2358 {
2359 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2360 union tgsi_exec_channel src;
2361 uint mask = 0;
2362
2363 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2364
2365 if (mach->Switch.selector.u[0] == src.u[0]) {
2366 mask |= 0x1;
2367 }
2368 if (mach->Switch.selector.u[1] == src.u[1]) {
2369 mask |= 0x2;
2370 }
2371 if (mach->Switch.selector.u[2] == src.u[2]) {
2372 mask |= 0x4;
2373 }
2374 if (mach->Switch.selector.u[3] == src.u[3]) {
2375 mask |= 0x8;
2376 }
2377
2378 mach->Switch.defaultMask |= mask;
2379
2380 mach->Switch.mask |= mask & prevMask;
2381
2382 UPDATE_EXEC_MASK(mach);
2383 }
2384
2385 static void
2386 exec_default(struct tgsi_exec_machine *mach)
2387 {
2388 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2389
2390 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2391
2392 UPDATE_EXEC_MASK(mach);
2393 }
2394
2395 static void
2396 exec_endswitch(struct tgsi_exec_machine *mach)
2397 {
2398 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2399 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2400
2401 UPDATE_EXEC_MASK(mach);
2402 }
2403
2404 static void
2405 micro_i2f(union tgsi_exec_channel *dst,
2406 const union tgsi_exec_channel *src)
2407 {
2408 dst->f[0] = (float)src->i[0];
2409 dst->f[1] = (float)src->i[1];
2410 dst->f[2] = (float)src->i[2];
2411 dst->f[3] = (float)src->i[3];
2412 }
2413
2414 static void
2415 micro_not(union tgsi_exec_channel *dst,
2416 const union tgsi_exec_channel *src)
2417 {
2418 dst->u[0] = ~src->u[0];
2419 dst->u[1] = ~src->u[1];
2420 dst->u[2] = ~src->u[2];
2421 dst->u[3] = ~src->u[3];
2422 }
2423
2424 static void
2425 micro_shl(union tgsi_exec_channel *dst,
2426 const union tgsi_exec_channel *src0,
2427 const union tgsi_exec_channel *src1)
2428 {
2429 dst->u[0] = src0->u[0] << src1->u[0];
2430 dst->u[1] = src0->u[1] << src1->u[1];
2431 dst->u[2] = src0->u[2] << src1->u[2];
2432 dst->u[3] = src0->u[3] << src1->u[3];
2433 }
2434
2435 static void
2436 micro_and(union tgsi_exec_channel *dst,
2437 const union tgsi_exec_channel *src0,
2438 const union tgsi_exec_channel *src1)
2439 {
2440 dst->u[0] = src0->u[0] & src1->u[0];
2441 dst->u[1] = src0->u[1] & src1->u[1];
2442 dst->u[2] = src0->u[2] & src1->u[2];
2443 dst->u[3] = src0->u[3] & src1->u[3];
2444 }
2445
2446 static void
2447 micro_or(union tgsi_exec_channel *dst,
2448 const union tgsi_exec_channel *src0,
2449 const union tgsi_exec_channel *src1)
2450 {
2451 dst->u[0] = src0->u[0] | src1->u[0];
2452 dst->u[1] = src0->u[1] | src1->u[1];
2453 dst->u[2] = src0->u[2] | src1->u[2];
2454 dst->u[3] = src0->u[3] | src1->u[3];
2455 }
2456
2457 static void
2458 micro_xor(union tgsi_exec_channel *dst,
2459 const union tgsi_exec_channel *src0,
2460 const union tgsi_exec_channel *src1)
2461 {
2462 dst->u[0] = src0->u[0] ^ src1->u[0];
2463 dst->u[1] = src0->u[1] ^ src1->u[1];
2464 dst->u[2] = src0->u[2] ^ src1->u[2];
2465 dst->u[3] = src0->u[3] ^ src1->u[3];
2466 }
2467
2468 static void
2469 micro_f2i(union tgsi_exec_channel *dst,
2470 const union tgsi_exec_channel *src)
2471 {
2472 dst->i[0] = (int)src->f[0];
2473 dst->i[1] = (int)src->f[1];
2474 dst->i[2] = (int)src->f[2];
2475 dst->i[3] = (int)src->f[3];
2476 }
2477
2478 static void
2479 micro_idiv(union tgsi_exec_channel *dst,
2480 const union tgsi_exec_channel *src0,
2481 const union tgsi_exec_channel *src1)
2482 {
2483 dst->i[0] = src0->i[0] / src1->i[0];
2484 dst->i[1] = src0->i[1] / src1->i[1];
2485 dst->i[2] = src0->i[2] / src1->i[2];
2486 dst->i[3] = src0->i[3] / src1->i[3];
2487 }
2488
2489 static void
2490 micro_imax(union tgsi_exec_channel *dst,
2491 const union tgsi_exec_channel *src0,
2492 const union tgsi_exec_channel *src1)
2493 {
2494 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
2495 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
2496 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
2497 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
2498 }
2499
2500 static void
2501 micro_imin(union tgsi_exec_channel *dst,
2502 const union tgsi_exec_channel *src0,
2503 const union tgsi_exec_channel *src1)
2504 {
2505 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
2506 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
2507 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
2508 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
2509 }
2510
2511 static void
2512 micro_isge(union tgsi_exec_channel *dst,
2513 const union tgsi_exec_channel *src0,
2514 const union tgsi_exec_channel *src1)
2515 {
2516 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
2517 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
2518 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
2519 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
2520 }
2521
2522 static void
2523 micro_ishr(union tgsi_exec_channel *dst,
2524 const union tgsi_exec_channel *src0,
2525 const union tgsi_exec_channel *src1)
2526 {
2527 dst->i[0] = src0->i[0] >> src1->i[0];
2528 dst->i[1] = src0->i[1] >> src1->i[1];
2529 dst->i[2] = src0->i[2] >> src1->i[2];
2530 dst->i[3] = src0->i[3] >> src1->i[3];
2531 }
2532
2533 static void
2534 micro_islt(union tgsi_exec_channel *dst,
2535 const union tgsi_exec_channel *src0,
2536 const union tgsi_exec_channel *src1)
2537 {
2538 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
2539 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
2540 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
2541 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
2542 }
2543
2544 static void
2545 micro_f2u(union tgsi_exec_channel *dst,
2546 const union tgsi_exec_channel *src)
2547 {
2548 dst->u[0] = (uint)src->f[0];
2549 dst->u[1] = (uint)src->f[1];
2550 dst->u[2] = (uint)src->f[2];
2551 dst->u[3] = (uint)src->f[3];
2552 }
2553
2554 static void
2555 micro_u2f(union tgsi_exec_channel *dst,
2556 const union tgsi_exec_channel *src)
2557 {
2558 dst->f[0] = (float)src->u[0];
2559 dst->f[1] = (float)src->u[1];
2560 dst->f[2] = (float)src->u[2];
2561 dst->f[3] = (float)src->u[3];
2562 }
2563
2564 static void
2565 micro_uadd(union tgsi_exec_channel *dst,
2566 const union tgsi_exec_channel *src0,
2567 const union tgsi_exec_channel *src1)
2568 {
2569 dst->u[0] = src0->u[0] + src1->u[0];
2570 dst->u[1] = src0->u[1] + src1->u[1];
2571 dst->u[2] = src0->u[2] + src1->u[2];
2572 dst->u[3] = src0->u[3] + src1->u[3];
2573 }
2574
2575 static void
2576 micro_udiv(union tgsi_exec_channel *dst,
2577 const union tgsi_exec_channel *src0,
2578 const union tgsi_exec_channel *src1)
2579 {
2580 dst->u[0] = src0->u[0] / src1->u[0];
2581 dst->u[1] = src0->u[1] / src1->u[1];
2582 dst->u[2] = src0->u[2] / src1->u[2];
2583 dst->u[3] = src0->u[3] / src1->u[3];
2584 }
2585
2586 static void
2587 micro_umad(union tgsi_exec_channel *dst,
2588 const union tgsi_exec_channel *src0,
2589 const union tgsi_exec_channel *src1,
2590 const union tgsi_exec_channel *src2)
2591 {
2592 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
2593 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
2594 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
2595 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
2596 }
2597
2598 static void
2599 micro_umax(union tgsi_exec_channel *dst,
2600 const union tgsi_exec_channel *src0,
2601 const union tgsi_exec_channel *src1)
2602 {
2603 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
2604 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
2605 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
2606 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
2607 }
2608
2609 static void
2610 micro_umin(union tgsi_exec_channel *dst,
2611 const union tgsi_exec_channel *src0,
2612 const union tgsi_exec_channel *src1)
2613 {
2614 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
2615 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
2616 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
2617 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
2618 }
2619
2620 static void
2621 micro_umod(union tgsi_exec_channel *dst,
2622 const union tgsi_exec_channel *src0,
2623 const union tgsi_exec_channel *src1)
2624 {
2625 dst->u[0] = src0->u[0] % src1->u[0];
2626 dst->u[1] = src0->u[1] % src1->u[1];
2627 dst->u[2] = src0->u[2] % src1->u[2];
2628 dst->u[3] = src0->u[3] % src1->u[3];
2629 }
2630
2631 static void
2632 micro_umul(union tgsi_exec_channel *dst,
2633 const union tgsi_exec_channel *src0,
2634 const union tgsi_exec_channel *src1)
2635 {
2636 dst->u[0] = src0->u[0] * src1->u[0];
2637 dst->u[1] = src0->u[1] * src1->u[1];
2638 dst->u[2] = src0->u[2] * src1->u[2];
2639 dst->u[3] = src0->u[3] * src1->u[3];
2640 }
2641
2642 static void
2643 micro_useq(union tgsi_exec_channel *dst,
2644 const union tgsi_exec_channel *src0,
2645 const union tgsi_exec_channel *src1)
2646 {
2647 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
2648 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
2649 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
2650 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
2651 }
2652
2653 static void
2654 micro_usge(union tgsi_exec_channel *dst,
2655 const union tgsi_exec_channel *src0,
2656 const union tgsi_exec_channel *src1)
2657 {
2658 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
2659 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
2660 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
2661 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
2662 }
2663
2664 static void
2665 micro_ushr(union tgsi_exec_channel *dst,
2666 const union tgsi_exec_channel *src0,
2667 const union tgsi_exec_channel *src1)
2668 {
2669 dst->u[0] = src0->u[0] >> src1->u[0];
2670 dst->u[1] = src0->u[1] >> src1->u[1];
2671 dst->u[2] = src0->u[2] >> src1->u[2];
2672 dst->u[3] = src0->u[3] >> src1->u[3];
2673 }
2674
2675 static void
2676 micro_uslt(union tgsi_exec_channel *dst,
2677 const union tgsi_exec_channel *src0,
2678 const union tgsi_exec_channel *src1)
2679 {
2680 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
2681 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
2682 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
2683 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
2684 }
2685
2686 static void
2687 micro_usne(union tgsi_exec_channel *dst,
2688 const union tgsi_exec_channel *src0,
2689 const union tgsi_exec_channel *src1)
2690 {
2691 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
2692 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
2693 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
2694 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
2695 }
2696
2697 static void
2698 exec_instruction(
2699 struct tgsi_exec_machine *mach,
2700 const struct tgsi_full_instruction *inst,
2701 int *pc )
2702 {
2703 uint chan_index;
2704 union tgsi_exec_channel r[10];
2705 union tgsi_exec_channel d[8];
2706
2707 (*pc)++;
2708
2709 switch (inst->Instruction.Opcode) {
2710 case TGSI_OPCODE_ARL:
2711 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2712 break;
2713
2714 case TGSI_OPCODE_MOV:
2715 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
2716 break;
2717
2718 case TGSI_OPCODE_LIT:
2719 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2720 FETCH( &r[0], 0, CHAN_X );
2721 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2722 micro_max(&d[CHAN_Y], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2723 }
2724
2725 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2726 FETCH( &r[1], 0, CHAN_Y );
2727 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2728
2729 FETCH( &r[2], 0, CHAN_W );
2730 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
2731 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
2732 micro_pow( &r[1], &r[1], &r[2] );
2733 micro_lt(&d[CHAN_Z], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2734 }
2735
2736 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2737 STORE(&d[CHAN_Y], 0, CHAN_Y);
2738 }
2739 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2740 STORE(&d[CHAN_Z], 0, CHAN_Z);
2741 }
2742 }
2743 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2744 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
2745 }
2746 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2747 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2748 }
2749 break;
2750
2751 case TGSI_OPCODE_RCP:
2752 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2753 break;
2754
2755 case TGSI_OPCODE_RSQ:
2756 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2757 break;
2758
2759 case TGSI_OPCODE_EXP:
2760 FETCH( &r[0], 0, CHAN_X );
2761 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
2762 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2763 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
2764 STORE( &r[2], 0, CHAN_X ); /* store r2 */
2765 }
2766 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2767 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
2768 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
2769 }
2770 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2771 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
2772 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
2773 }
2774 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2775 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2776 }
2777 break;
2778
2779 case TGSI_OPCODE_LOG:
2780 FETCH( &r[0], 0, CHAN_X );
2781 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
2782 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
2783 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
2784 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2785 STORE( &r[0], 0, CHAN_X );
2786 }
2787 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2788 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
2789 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
2790 STORE( &r[0], 0, CHAN_Y );
2791 }
2792 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2793 STORE( &r[1], 0, CHAN_Z );
2794 }
2795 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2796 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2797 }
2798 break;
2799
2800 case TGSI_OPCODE_MUL:
2801 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2802 break;
2803
2804 case TGSI_OPCODE_ADD:
2805 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2806 break;
2807
2808 case TGSI_OPCODE_DP3:
2809 exec_dp3(mach, inst);
2810 break;
2811
2812 case TGSI_OPCODE_DP4:
2813 exec_dp4(mach, inst);
2814 break;
2815
2816 case TGSI_OPCODE_DST:
2817 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2818 FETCH( &r[0], 0, CHAN_Y );
2819 FETCH( &r[1], 1, CHAN_Y);
2820 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2821 }
2822 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2823 FETCH(&d[CHAN_Z], 0, CHAN_Z);
2824 }
2825 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2826 FETCH(&d[CHAN_W], 1, CHAN_W);
2827 }
2828
2829 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2830 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X);
2831 }
2832 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2833 STORE(&d[CHAN_Y], 0, CHAN_Y);
2834 }
2835 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2836 STORE(&d[CHAN_Z], 0, CHAN_Z);
2837 }
2838 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2839 STORE(&d[CHAN_W], 0, CHAN_W);
2840 }
2841 break;
2842
2843 case TGSI_OPCODE_MIN:
2844 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2845 break;
2846
2847 case TGSI_OPCODE_MAX:
2848 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2849 break;
2850
2851 case TGSI_OPCODE_SLT:
2852 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2853 break;
2854
2855 case TGSI_OPCODE_SGE:
2856 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2857 break;
2858
2859 case TGSI_OPCODE_MAD:
2860 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2861 break;
2862
2863 case TGSI_OPCODE_SUB:
2864 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2865 break;
2866
2867 case TGSI_OPCODE_LRP:
2868 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2869 break;
2870
2871 case TGSI_OPCODE_CND:
2872 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2873 break;
2874
2875 case TGSI_OPCODE_DP2A:
2876 exec_dp2a(mach, inst);
2877 break;
2878
2879 case TGSI_OPCODE_FRC:
2880 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2881 break;
2882
2883 case TGSI_OPCODE_CLAMP:
2884 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2885 break;
2886
2887 case TGSI_OPCODE_FLR:
2888 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2889 break;
2890
2891 case TGSI_OPCODE_ROUND:
2892 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2893 break;
2894
2895 case TGSI_OPCODE_EX2:
2896 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2897 break;
2898
2899 case TGSI_OPCODE_LG2:
2900 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2901 break;
2902
2903 case TGSI_OPCODE_POW:
2904 FETCH(&r[0], 0, CHAN_X);
2905 FETCH(&r[1], 1, CHAN_X);
2906
2907 micro_pow( &r[0], &r[0], &r[1] );
2908
2909 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2910 STORE( &r[0], 0, chan_index );
2911 }
2912 break;
2913
2914 case TGSI_OPCODE_XPD:
2915 FETCH(&r[0], 0, CHAN_Y);
2916 FETCH(&r[1], 1, CHAN_Z);
2917
2918 micro_mul( &r[2], &r[0], &r[1] );
2919
2920 FETCH(&r[3], 0, CHAN_Z);
2921 FETCH(&r[4], 1, CHAN_Y);
2922
2923 micro_mul( &r[5], &r[3], &r[4] );
2924 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2925
2926 FETCH(&r[2], 1, CHAN_X);
2927
2928 micro_mul( &r[3], &r[3], &r[2] );
2929
2930 FETCH(&r[5], 0, CHAN_X);
2931
2932 micro_mul( &r[1], &r[1], &r[5] );
2933 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2934
2935 micro_mul( &r[5], &r[5], &r[4] );
2936 micro_mul( &r[0], &r[0], &r[2] );
2937 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2938
2939 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2940 STORE(&d[CHAN_X], 0, CHAN_X);
2941 }
2942 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2943 STORE(&d[CHAN_Y], 0, CHAN_Y);
2944 }
2945 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2946 STORE(&d[CHAN_Z], 0, CHAN_Z);
2947 }
2948 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2949 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2950 }
2951 break;
2952
2953 case TGSI_OPCODE_ABS:
2954 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2955 break;
2956
2957 case TGSI_OPCODE_RCC:
2958 FETCH(&r[0], 0, CHAN_X);
2959 micro_div(&r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0]);
2960 micro_float_clamp(&r[0], &r[0]);
2961 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2962 STORE(&r[0], 0, chan_index);
2963 }
2964 break;
2965
2966 case TGSI_OPCODE_DPH:
2967 exec_dph(mach, inst);
2968 break;
2969
2970 case TGSI_OPCODE_COS:
2971 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2972 break;
2973
2974 case TGSI_OPCODE_DDX:
2975 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2976 break;
2977
2978 case TGSI_OPCODE_DDY:
2979 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2980 break;
2981
2982 case TGSI_OPCODE_KILP:
2983 exec_kilp (mach, inst);
2984 break;
2985
2986 case TGSI_OPCODE_KIL:
2987 exec_kil (mach, inst);
2988 break;
2989
2990 case TGSI_OPCODE_PK2H:
2991 assert (0);
2992 break;
2993
2994 case TGSI_OPCODE_PK2US:
2995 assert (0);
2996 break;
2997
2998 case TGSI_OPCODE_PK4B:
2999 assert (0);
3000 break;
3001
3002 case TGSI_OPCODE_PK4UB:
3003 assert (0);
3004 break;
3005
3006 case TGSI_OPCODE_RFL:
3007 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
3008 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
3009 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3010 /* r0 = dp3(src0, src0) */
3011 FETCH(&r[2], 0, CHAN_X);
3012 micro_mul(&r[0], &r[2], &r[2]);
3013 FETCH(&r[4], 0, CHAN_Y);
3014 micro_mul(&r[8], &r[4], &r[4]);
3015 micro_add(&r[0], &r[0], &r[8]);
3016 FETCH(&r[6], 0, CHAN_Z);
3017 micro_mul(&r[8], &r[6], &r[6]);
3018 micro_add(&r[0], &r[0], &r[8]);
3019
3020 /* r1 = dp3(src0, src1) */
3021 FETCH(&r[3], 1, CHAN_X);
3022 micro_mul(&r[1], &r[2], &r[3]);
3023 FETCH(&r[5], 1, CHAN_Y);
3024 micro_mul(&r[8], &r[4], &r[5]);
3025 micro_add(&r[1], &r[1], &r[8]);
3026 FETCH(&r[7], 1, CHAN_Z);
3027 micro_mul(&r[8], &r[6], &r[7]);
3028 micro_add(&r[1], &r[1], &r[8]);
3029
3030 /* r1 = 2 * r1 / r0 */
3031 micro_add(&r[1], &r[1], &r[1]);
3032 micro_div(&r[1], &r[1], &r[0]);
3033
3034 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3035 micro_mul(&r[2], &r[2], &r[1]);
3036 micro_sub(&r[2], &r[2], &r[3]);
3037 STORE(&r[2], 0, CHAN_X);
3038 }
3039 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3040 micro_mul(&r[4], &r[4], &r[1]);
3041 micro_sub(&r[4], &r[4], &r[5]);
3042 STORE(&r[4], 0, CHAN_Y);
3043 }
3044 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3045 micro_mul(&r[6], &r[6], &r[1]);
3046 micro_sub(&r[6], &r[6], &r[7]);
3047 STORE(&r[6], 0, CHAN_Z);
3048 }
3049 }
3050 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
3051 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
3052 }
3053 break;
3054
3055 case TGSI_OPCODE_SEQ:
3056 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3057 break;
3058
3059 case TGSI_OPCODE_SFL:
3060 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3061 STORE(&mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, chan_index);
3062 }
3063 break;
3064
3065 case TGSI_OPCODE_SGT:
3066 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3067 break;
3068
3069 case TGSI_OPCODE_SIN:
3070 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3071 break;
3072
3073 case TGSI_OPCODE_SLE:
3074 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3075 break;
3076
3077 case TGSI_OPCODE_SNE:
3078 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3079 break;
3080
3081 case TGSI_OPCODE_STR:
3082 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3083 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, chan_index);
3084 }
3085 break;
3086
3087 case TGSI_OPCODE_TEX:
3088 /* simple texture lookup */
3089 /* src[0] = texcoord */
3090 /* src[1] = sampler unit */
3091 exec_tex(mach, inst, TEX_MODIFIER_NONE);
3092 break;
3093
3094 case TGSI_OPCODE_TXB:
3095 /* Texture lookup with lod bias */
3096 /* src[0] = texcoord (src[0].w = LOD bias) */
3097 /* src[1] = sampler unit */
3098 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
3099 break;
3100
3101 case TGSI_OPCODE_TXD:
3102 /* Texture lookup with explict partial derivatives */
3103 /* src[0] = texcoord */
3104 /* src[1] = d[strq]/dx */
3105 /* src[2] = d[strq]/dy */
3106 /* src[3] = sampler unit */
3107 exec_txd(mach, inst);
3108 break;
3109
3110 case TGSI_OPCODE_TXL:
3111 /* Texture lookup with explit LOD */
3112 /* src[0] = texcoord (src[0].w = LOD) */
3113 /* src[1] = sampler unit */
3114 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3115 break;
3116
3117 case TGSI_OPCODE_TXP:
3118 /* Texture lookup with projection */
3119 /* src[0] = texcoord (src[0].w = projection) */
3120 /* src[1] = sampler unit */
3121 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
3122 break;
3123
3124 case TGSI_OPCODE_UP2H:
3125 assert (0);
3126 break;
3127
3128 case TGSI_OPCODE_UP2US:
3129 assert (0);
3130 break;
3131
3132 case TGSI_OPCODE_UP4B:
3133 assert (0);
3134 break;
3135
3136 case TGSI_OPCODE_UP4UB:
3137 assert (0);
3138 break;
3139
3140 case TGSI_OPCODE_X2D:
3141 FETCH(&r[0], 1, CHAN_X);
3142 FETCH(&r[1], 1, CHAN_Y);
3143 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
3144 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3145 FETCH(&r[2], 2, CHAN_X);
3146 micro_mul(&r[2], &r[2], &r[0]);
3147 FETCH(&r[3], 2, CHAN_Y);
3148 micro_mul(&r[3], &r[3], &r[1]);
3149 micro_add(&r[2], &r[2], &r[3]);
3150 FETCH(&r[3], 0, CHAN_X);
3151 micro_add(&d[CHAN_X], &r[2], &r[3]);
3152
3153 }
3154 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
3155 IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
3156 FETCH(&r[2], 2, CHAN_Z);
3157 micro_mul(&r[2], &r[2], &r[0]);
3158 FETCH(&r[3], 2, CHAN_W);
3159 micro_mul(&r[3], &r[3], &r[1]);
3160 micro_add(&r[2], &r[2], &r[3]);
3161 FETCH(&r[3], 0, CHAN_Y);
3162 micro_add(&d[CHAN_Y], &r[2], &r[3]);
3163
3164 }
3165 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3166 STORE(&d[CHAN_X], 0, CHAN_X);
3167 }
3168 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3169 STORE(&d[CHAN_Y], 0, CHAN_Y);
3170 }
3171 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3172 STORE(&d[CHAN_X], 0, CHAN_Z);
3173 }
3174 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
3175 STORE(&d[CHAN_Y], 0, CHAN_W);
3176 }
3177 break;
3178
3179 case TGSI_OPCODE_ARA:
3180 assert (0);
3181 break;
3182
3183 case TGSI_OPCODE_ARR:
3184 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3185 break;
3186
3187 case TGSI_OPCODE_BRA:
3188 assert (0);
3189 break;
3190
3191 case TGSI_OPCODE_CAL:
3192 /* skip the call if no execution channels are enabled */
3193 if (mach->ExecMask) {
3194 /* do the call */
3195
3196 /* First, record the depths of the execution stacks.
3197 * This is important for deeply nested/looped return statements.
3198 * We have to unwind the stacks by the correct amount. For a
3199 * real code generator, we could determine the number of entries
3200 * to pop off each stack with simple static analysis and avoid
3201 * implementing this data structure at run time.
3202 */
3203 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3204 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3205 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3206 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3207 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3208 /* note that PC was already incremented above */
3209 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3210
3211 mach->CallStackTop++;
3212
3213 /* Second, push the Cond, Loop, Cont, Func stacks */
3214 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3215 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3216 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3217 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3218 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3219 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3220
3221 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3222 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3223 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3224 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3225 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3226 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3227
3228 /* Finally, jump to the subroutine */
3229 *pc = inst->Label.Label;
3230 }
3231 break;
3232
3233 case TGSI_OPCODE_RET:
3234 mach->FuncMask &= ~mach->ExecMask;
3235 UPDATE_EXEC_MASK(mach);
3236
3237 if (mach->FuncMask == 0x0) {
3238 /* really return now (otherwise, keep executing */
3239
3240 if (mach->CallStackTop == 0) {
3241 /* returning from main() */
3242 *pc = -1;
3243 return;
3244 }
3245
3246 assert(mach->CallStackTop > 0);
3247 mach->CallStackTop--;
3248
3249 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3250 mach->CondMask = mach->CondStack[mach->CondStackTop];
3251
3252 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3253 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3254
3255 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3256 mach->ContMask = mach->ContStack[mach->ContStackTop];
3257
3258 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3259 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3260
3261 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3262 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3263
3264 assert(mach->FuncStackTop > 0);
3265 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3266
3267 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3268
3269 UPDATE_EXEC_MASK(mach);
3270 }
3271 break;
3272
3273 case TGSI_OPCODE_SSG:
3274 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3275 break;
3276
3277 case TGSI_OPCODE_CMP:
3278 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3279 break;
3280
3281 case TGSI_OPCODE_SCS:
3282 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
3283 FETCH( &r[0], 0, CHAN_X );
3284 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3285 micro_cos(&r[1], &r[0]);
3286 STORE(&r[1], 0, CHAN_X);
3287 }
3288 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3289 micro_sin(&r[1], &r[0]);
3290 STORE(&r[1], 0, CHAN_Y);
3291 }
3292 }
3293 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
3294 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
3295 }
3296 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
3297 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
3298 }
3299 break;
3300
3301 case TGSI_OPCODE_NRM:
3302 exec_nrm3(mach, inst);
3303 break;
3304
3305 case TGSI_OPCODE_NRM4:
3306 exec_nrm4(mach, inst);
3307 break;
3308
3309 case TGSI_OPCODE_DIV:
3310 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3311 break;
3312
3313 case TGSI_OPCODE_DP2:
3314 exec_dp2(mach, inst);
3315 break;
3316
3317 case TGSI_OPCODE_IF:
3318 /* push CondMask */
3319 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3320 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3321 FETCH( &r[0], 0, CHAN_X );
3322 /* update CondMask */
3323 if( ! r[0].u[0] ) {
3324 mach->CondMask &= ~0x1;
3325 }
3326 if( ! r[0].u[1] ) {
3327 mach->CondMask &= ~0x2;
3328 }
3329 if( ! r[0].u[2] ) {
3330 mach->CondMask &= ~0x4;
3331 }
3332 if( ! r[0].u[3] ) {
3333 mach->CondMask &= ~0x8;
3334 }
3335 UPDATE_EXEC_MASK(mach);
3336 /* Todo: If CondMask==0, jump to ELSE */
3337 break;
3338
3339 case TGSI_OPCODE_ELSE:
3340 /* invert CondMask wrt previous mask */
3341 {
3342 uint prevMask;
3343 assert(mach->CondStackTop > 0);
3344 prevMask = mach->CondStack[mach->CondStackTop - 1];
3345 mach->CondMask = ~mach->CondMask & prevMask;
3346 UPDATE_EXEC_MASK(mach);
3347 /* Todo: If CondMask==0, jump to ENDIF */
3348 }
3349 break;
3350
3351 case TGSI_OPCODE_ENDIF:
3352 /* pop CondMask */
3353 assert(mach->CondStackTop > 0);
3354 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3355 UPDATE_EXEC_MASK(mach);
3356 break;
3357
3358 case TGSI_OPCODE_END:
3359 /* make sure we end primitives which haven't
3360 * been explicitly emitted */
3361 conditional_emit_primitive(mach);
3362 /* halt execution */
3363 *pc = -1;
3364 break;
3365
3366 case TGSI_OPCODE_PUSHA:
3367 assert (0);
3368 break;
3369
3370 case TGSI_OPCODE_POPA:
3371 assert (0);
3372 break;
3373
3374 case TGSI_OPCODE_CEIL:
3375 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3376 break;
3377
3378 case TGSI_OPCODE_I2F:
3379 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3380 break;
3381
3382 case TGSI_OPCODE_NOT:
3383 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3384 break;
3385
3386 case TGSI_OPCODE_TRUNC:
3387 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3388 break;
3389
3390 case TGSI_OPCODE_SHL:
3391 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3392 break;
3393
3394 case TGSI_OPCODE_AND:
3395 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3396 break;
3397
3398 case TGSI_OPCODE_OR:
3399 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3400 break;
3401
3402 case TGSI_OPCODE_MOD:
3403 assert (0);
3404 break;
3405
3406 case TGSI_OPCODE_XOR:
3407 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3408 break;
3409
3410 case TGSI_OPCODE_SAD:
3411 assert (0);
3412 break;
3413
3414 case TGSI_OPCODE_TXF:
3415 assert (0);
3416 break;
3417
3418 case TGSI_OPCODE_TXQ:
3419 assert (0);
3420 break;
3421
3422 case TGSI_OPCODE_EMIT:
3423 emit_vertex(mach);
3424 break;
3425
3426 case TGSI_OPCODE_ENDPRIM:
3427 emit_primitive(mach);
3428 break;
3429
3430 case TGSI_OPCODE_BGNLOOP:
3431 /* push LoopMask and ContMasks */
3432 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3433 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3434 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3435 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3436
3437 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3438 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3439 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3440 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3441 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3442 break;
3443
3444 case TGSI_OPCODE_ENDLOOP:
3445 /* Restore ContMask, but don't pop */
3446 assert(mach->ContStackTop > 0);
3447 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3448 UPDATE_EXEC_MASK(mach);
3449 if (mach->ExecMask) {
3450 /* repeat loop: jump to instruction just past BGNLOOP */
3451 assert(mach->LoopLabelStackTop > 0);
3452 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3453 }
3454 else {
3455 /* exit loop: pop LoopMask */
3456 assert(mach->LoopStackTop > 0);
3457 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3458 /* pop ContMask */
3459 assert(mach->ContStackTop > 0);
3460 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3461 assert(mach->LoopLabelStackTop > 0);
3462 --mach->LoopLabelStackTop;
3463
3464 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3465 }
3466 UPDATE_EXEC_MASK(mach);
3467 break;
3468
3469 case TGSI_OPCODE_BRK:
3470 exec_break(mach);
3471 break;
3472
3473 case TGSI_OPCODE_CONT:
3474 /* turn off cont channels for each enabled exec channel */
3475 mach->ContMask &= ~mach->ExecMask;
3476 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3477 UPDATE_EXEC_MASK(mach);
3478 break;
3479
3480 case TGSI_OPCODE_BGNSUB:
3481 /* no-op */
3482 break;
3483
3484 case TGSI_OPCODE_ENDSUB:
3485 /*
3486 * XXX: This really should be a no-op. We should never reach this opcode.
3487 */
3488
3489 assert(mach->CallStackTop > 0);
3490 mach->CallStackTop--;
3491
3492 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3493 mach->CondMask = mach->CondStack[mach->CondStackTop];
3494
3495 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3496 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3497
3498 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3499 mach->ContMask = mach->ContStack[mach->ContStackTop];
3500
3501 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3502 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3503
3504 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3505 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3506
3507 assert(mach->FuncStackTop > 0);
3508 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3509
3510 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3511
3512 UPDATE_EXEC_MASK(mach);
3513 break;
3514
3515 case TGSI_OPCODE_NOP:
3516 break;
3517
3518 case TGSI_OPCODE_BREAKC:
3519 FETCH(&r[0], 0, CHAN_X);
3520 /* update CondMask */
3521 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3522 mach->LoopMask &= ~0x1;
3523 }
3524 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3525 mach->LoopMask &= ~0x2;
3526 }
3527 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3528 mach->LoopMask &= ~0x4;
3529 }
3530 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3531 mach->LoopMask &= ~0x8;
3532 }
3533 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3534 UPDATE_EXEC_MASK(mach);
3535 break;
3536
3537 case TGSI_OPCODE_F2I:
3538 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3539 break;
3540
3541 case TGSI_OPCODE_IDIV:
3542 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3543 break;
3544
3545 case TGSI_OPCODE_IMAX:
3546 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3547 break;
3548
3549 case TGSI_OPCODE_IMIN:
3550 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3551 break;
3552
3553 case TGSI_OPCODE_INEG:
3554 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3555 break;
3556
3557 case TGSI_OPCODE_ISGE:
3558 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3559 break;
3560
3561 case TGSI_OPCODE_ISHR:
3562 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3563 break;
3564
3565 case TGSI_OPCODE_ISLT:
3566 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3567 break;
3568
3569 case TGSI_OPCODE_F2U:
3570 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3571 break;
3572
3573 case TGSI_OPCODE_U2F:
3574 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
3575 break;
3576
3577 case TGSI_OPCODE_UADD:
3578 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3579 break;
3580
3581 case TGSI_OPCODE_UDIV:
3582 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3583 break;
3584
3585 case TGSI_OPCODE_UMAD:
3586 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3587 break;
3588
3589 case TGSI_OPCODE_UMAX:
3590 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3591 break;
3592
3593 case TGSI_OPCODE_UMIN:
3594 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3595 break;
3596
3597 case TGSI_OPCODE_UMOD:
3598 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3599 break;
3600
3601 case TGSI_OPCODE_UMUL:
3602 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3603 break;
3604
3605 case TGSI_OPCODE_USEQ:
3606 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3607 break;
3608
3609 case TGSI_OPCODE_USGE:
3610 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3611 break;
3612
3613 case TGSI_OPCODE_USHR:
3614 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3615 break;
3616
3617 case TGSI_OPCODE_USLT:
3618 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3619 break;
3620
3621 case TGSI_OPCODE_USNE:
3622 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3623 break;
3624
3625 case TGSI_OPCODE_SWITCH:
3626 exec_switch(mach, inst);
3627 break;
3628
3629 case TGSI_OPCODE_CASE:
3630 exec_case(mach, inst);
3631 break;
3632
3633 case TGSI_OPCODE_DEFAULT:
3634 exec_default(mach);
3635 break;
3636
3637 case TGSI_OPCODE_ENDSWITCH:
3638 exec_endswitch(mach);
3639 break;
3640
3641 default:
3642 assert( 0 );
3643 }
3644 }
3645
3646
3647 #define DEBUG_EXECUTION 0
3648
3649
3650 /**
3651 * Run TGSI interpreter.
3652 * \return bitmask of "alive" quad components
3653 */
3654 uint
3655 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3656 {
3657 uint i;
3658 int pc = 0;
3659
3660 mach->CondMask = 0xf;
3661 mach->LoopMask = 0xf;
3662 mach->ContMask = 0xf;
3663 mach->FuncMask = 0xf;
3664 mach->ExecMask = 0xf;
3665
3666 mach->Switch.mask = 0xf;
3667
3668 assert(mach->CondStackTop == 0);
3669 assert(mach->LoopStackTop == 0);
3670 assert(mach->ContStackTop == 0);
3671 assert(mach->SwitchStackTop == 0);
3672 assert(mach->BreakStackTop == 0);
3673 assert(mach->CallStackTop == 0);
3674
3675 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3676 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3677
3678 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3679 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3680 mach->Primitives[0] = 0;
3681 }
3682
3683 for (i = 0; i < QUAD_SIZE; i++) {
3684 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
3685 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
3686 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
3687 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
3688 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
3689 }
3690
3691 /* execute declarations (interpolants) */
3692 for (i = 0; i < mach->NumDeclarations; i++) {
3693 exec_declaration( mach, mach->Declarations+i );
3694 }
3695
3696 {
3697 #if DEBUG_EXECUTION
3698 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
3699 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
3700 uint inst = 1;
3701
3702 memcpy(temps, mach->Temps, sizeof(temps));
3703 memcpy(outputs, mach->Outputs, sizeof(outputs));
3704 #endif
3705
3706 /* execute instructions, until pc is set to -1 */
3707 while (pc != -1) {
3708
3709 #if DEBUG_EXECUTION
3710 uint i;
3711
3712 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
3713 #endif
3714
3715 assert(pc < (int) mach->NumInstructions);
3716 exec_instruction(mach, mach->Instructions + pc, &pc);
3717
3718 #if DEBUG_EXECUTION
3719 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
3720 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
3721 uint j;
3722
3723 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
3724 debug_printf("TEMP[%2u] = ", i);
3725 for (j = 0; j < 4; j++) {
3726 if (j > 0) {
3727 debug_printf(" ");
3728 }
3729 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3730 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
3731 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
3732 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
3733 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
3734 }
3735 }
3736 }
3737 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
3738 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
3739 uint j;
3740
3741 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
3742 debug_printf("OUT[%2u] = ", i);
3743 for (j = 0; j < 4; j++) {
3744 if (j > 0) {
3745 debug_printf(" ");
3746 }
3747 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3748 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
3749 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
3750 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
3751 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
3752 }
3753 }
3754 }
3755 #endif
3756 }
3757 }
3758
3759 #if 0
3760 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3761 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3762 /*
3763 * Scale back depth component.
3764 */
3765 for (i = 0; i < 4; i++)
3766 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3767 }
3768 #endif
3769
3770 assert(mach->CondStackTop == 0);
3771 assert(mach->LoopStackTop == 0);
3772 assert(mach->ContStackTop == 0);
3773 assert(mach->SwitchStackTop == 0);
3774 assert(mach->BreakStackTop == 0);
3775 assert(mach->CallStackTop == 0);
3776
3777 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3778 }