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gallium: implement TGSI_OPCODE_DP2A, add sqrt to NRM3/NRM4
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /**
29 * TGSI interpreter/executor.
30 *
31 * Flow control information:
32 *
33 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
34 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
35 * care since a condition may be true for some quad components but false
36 * for other components.
37 *
38 * We basically execute all statements (even if they're in the part of
39 * an IF/ELSE clause that's "not taken") and use a special mask to
40 * control writing to destination registers. This is the ExecMask.
41 * See store_dest().
42 *
43 * The ExecMask is computed from three other masks (CondMask, LoopMask and
44 * ContMask) which are controlled by the flow control instructions (namely:
45 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
46 *
47 *
48 * Authors:
49 * Michal Krol
50 * Brian Paul
51 */
52
53 #include "pipe/p_compiler.h"
54 #include "pipe/p_state.h"
55 #include "pipe/p_shader_tokens.h"
56 #include "tgsi/tgsi_parse.h"
57 #include "tgsi/tgsi_util.h"
58 #include "tgsi_exec.h"
59 #include "util/u_memory.h"
60 #include "util/u_math.h"
61
62 #define FAST_MATH 1
63
64 #define TILE_TOP_LEFT 0
65 #define TILE_TOP_RIGHT 1
66 #define TILE_BOTTOM_LEFT 2
67 #define TILE_BOTTOM_RIGHT 3
68
69 #define CHAN_X 0
70 #define CHAN_Y 1
71 #define CHAN_Z 2
72 #define CHAN_W 3
73
74 /*
75 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
76 */
77 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
78 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
79 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
80 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
81 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
82 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
83 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
84 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
85 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
86 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
87 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
88 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
89 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
90 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
91 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
92 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
93 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
94 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
95 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
96 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
97 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
98 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
99 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
100 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
101 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
102 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
103 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
104 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
105 #define TEMP_R0 TGSI_EXEC_TEMP_R0
106
107 #define IS_CHANNEL_ENABLED(INST, CHAN)\
108 ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
109
110 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
111 ((INST).FullDstRegisters[1].DstRegister.WriteMask & (1 << (CHAN)))
112
113 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
114 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
115 if (IS_CHANNEL_ENABLED( INST, CHAN ))
116
117 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
118 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
119 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
120
121
122 /** The execution mask depends on the conditional mask and the loop mask */
123 #define UPDATE_EXEC_MASK(MACH) \
124 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->FuncMask
125
126 /**
127 * Initialize machine state by expanding tokens to full instructions,
128 * allocating temporary storage, setting up constants, etc.
129 * After this, we can call tgsi_exec_machine_run() many times.
130 */
131 void
132 tgsi_exec_machine_bind_shader(
133 struct tgsi_exec_machine *mach,
134 const struct tgsi_token *tokens,
135 uint numSamplers,
136 struct tgsi_sampler *samplers)
137 {
138 uint k;
139 struct tgsi_parse_context parse;
140 struct tgsi_exec_labels *labels = &mach->Labels;
141 struct tgsi_full_instruction *instructions;
142 struct tgsi_full_declaration *declarations;
143 uint maxInstructions = 10, numInstructions = 0;
144 uint maxDeclarations = 10, numDeclarations = 0;
145 uint instno = 0;
146
147 #if 0
148 tgsi_dump(tokens, 0);
149 #endif
150
151 util_init_math();
152
153 mach->Tokens = tokens;
154 mach->Samplers = samplers;
155
156 k = tgsi_parse_init (&parse, mach->Tokens);
157 if (k != TGSI_PARSE_OK) {
158 debug_printf( "Problem parsing!\n" );
159 return;
160 }
161
162 mach->Processor = parse.FullHeader.Processor.Processor;
163 mach->ImmLimit = 0;
164 labels->count = 0;
165
166 declarations = (struct tgsi_full_declaration *)
167 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
168
169 if (!declarations) {
170 return;
171 }
172
173 instructions = (struct tgsi_full_instruction *)
174 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
175
176 if (!instructions) {
177 FREE( declarations );
178 return;
179 }
180
181 while( !tgsi_parse_end_of_tokens( &parse ) ) {
182 uint pointer = parse.Position;
183 uint i;
184
185 tgsi_parse_token( &parse );
186 switch( parse.FullToken.Token.Type ) {
187 case TGSI_TOKEN_TYPE_DECLARATION:
188 /* save expanded declaration */
189 if (numDeclarations == maxDeclarations) {
190 declarations = REALLOC(declarations,
191 maxDeclarations
192 * sizeof(struct tgsi_full_declaration),
193 (maxDeclarations + 10)
194 * sizeof(struct tgsi_full_declaration));
195 maxDeclarations += 10;
196 }
197 memcpy(declarations + numDeclarations,
198 &parse.FullToken.FullDeclaration,
199 sizeof(declarations[0]));
200 numDeclarations++;
201 break;
202
203 case TGSI_TOKEN_TYPE_IMMEDIATE:
204 {
205 uint size = parse.FullToken.FullImmediate.Immediate.Size - 1;
206 assert( size % 4 == 0 );
207 assert( mach->ImmLimit + size / 4 <= TGSI_EXEC_NUM_IMMEDIATES );
208
209 for( i = 0; i < size; i++ ) {
210 mach->Imms[mach->ImmLimit + i / 4][i % 4] =
211 parse.FullToken.FullImmediate.u.ImmediateFloat32[i].Float;
212 }
213 mach->ImmLimit += size / 4;
214 }
215 break;
216
217 case TGSI_TOKEN_TYPE_INSTRUCTION:
218 assert( labels->count < MAX_LABELS );
219
220 labels->labels[labels->count][0] = instno;
221 labels->labels[labels->count][1] = pointer;
222 labels->count++;
223
224 /* save expanded instruction */
225 if (numInstructions == maxInstructions) {
226 instructions = REALLOC(instructions,
227 maxInstructions
228 * sizeof(struct tgsi_full_instruction),
229 (maxInstructions + 10)
230 * sizeof(struct tgsi_full_instruction));
231 maxInstructions += 10;
232 }
233 memcpy(instructions + numInstructions,
234 &parse.FullToken.FullInstruction,
235 sizeof(instructions[0]));
236 numInstructions++;
237 break;
238
239 default:
240 assert( 0 );
241 }
242 }
243 tgsi_parse_free (&parse);
244
245 if (mach->Declarations) {
246 FREE( mach->Declarations );
247 }
248 mach->Declarations = declarations;
249 mach->NumDeclarations = numDeclarations;
250
251 if (mach->Instructions) {
252 FREE( mach->Instructions );
253 }
254 mach->Instructions = instructions;
255 mach->NumInstructions = numInstructions;
256 }
257
258
259 void
260 tgsi_exec_machine_init(
261 struct tgsi_exec_machine *mach )
262 {
263 uint i;
264
265 mach->Temps = (struct tgsi_exec_vector *) tgsi_align_128bit( mach->_Temps);
266 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
267
268 /* Setup constants. */
269 for( i = 0; i < 4; i++ ) {
270 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
271 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
272 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
273 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
274 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
275 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
276 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
277 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
278 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
279 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
280 }
281 }
282
283
284 void
285 tgsi_exec_machine_free_data(struct tgsi_exec_machine *mach)
286 {
287 if (mach->Instructions) {
288 FREE(mach->Instructions);
289 mach->Instructions = NULL;
290 mach->NumInstructions = 0;
291 }
292 if (mach->Declarations) {
293 FREE(mach->Declarations);
294 mach->Declarations = NULL;
295 mach->NumDeclarations = 0;
296 }
297 }
298
299
300 static void
301 micro_abs(
302 union tgsi_exec_channel *dst,
303 const union tgsi_exec_channel *src )
304 {
305 dst->f[0] = fabsf( src->f[0] );
306 dst->f[1] = fabsf( src->f[1] );
307 dst->f[2] = fabsf( src->f[2] );
308 dst->f[3] = fabsf( src->f[3] );
309 }
310
311 static void
312 micro_add(
313 union tgsi_exec_channel *dst,
314 const union tgsi_exec_channel *src0,
315 const union tgsi_exec_channel *src1 )
316 {
317 dst->f[0] = src0->f[0] + src1->f[0];
318 dst->f[1] = src0->f[1] + src1->f[1];
319 dst->f[2] = src0->f[2] + src1->f[2];
320 dst->f[3] = src0->f[3] + src1->f[3];
321 }
322
323 static void
324 micro_iadd(
325 union tgsi_exec_channel *dst,
326 const union tgsi_exec_channel *src0,
327 const union tgsi_exec_channel *src1 )
328 {
329 dst->i[0] = src0->i[0] + src1->i[0];
330 dst->i[1] = src0->i[1] + src1->i[1];
331 dst->i[2] = src0->i[2] + src1->i[2];
332 dst->i[3] = src0->i[3] + src1->i[3];
333 }
334
335 static void
336 micro_and(
337 union tgsi_exec_channel *dst,
338 const union tgsi_exec_channel *src0,
339 const union tgsi_exec_channel *src1 )
340 {
341 dst->u[0] = src0->u[0] & src1->u[0];
342 dst->u[1] = src0->u[1] & src1->u[1];
343 dst->u[2] = src0->u[2] & src1->u[2];
344 dst->u[3] = src0->u[3] & src1->u[3];
345 }
346
347 static void
348 micro_ceil(
349 union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src )
351 {
352 dst->f[0] = ceilf( src->f[0] );
353 dst->f[1] = ceilf( src->f[1] );
354 dst->f[2] = ceilf( src->f[2] );
355 dst->f[3] = ceilf( src->f[3] );
356 }
357
358 static void
359 micro_cos(
360 union tgsi_exec_channel *dst,
361 const union tgsi_exec_channel *src )
362 {
363 dst->f[0] = cosf( src->f[0] );
364 dst->f[1] = cosf( src->f[1] );
365 dst->f[2] = cosf( src->f[2] );
366 dst->f[3] = cosf( src->f[3] );
367 }
368
369 static void
370 micro_ddx(
371 union tgsi_exec_channel *dst,
372 const union tgsi_exec_channel *src )
373 {
374 dst->f[0] =
375 dst->f[1] =
376 dst->f[2] =
377 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
378 }
379
380 static void
381 micro_ddy(
382 union tgsi_exec_channel *dst,
383 const union tgsi_exec_channel *src )
384 {
385 dst->f[0] =
386 dst->f[1] =
387 dst->f[2] =
388 dst->f[3] = src->f[TILE_TOP_LEFT] - src->f[TILE_BOTTOM_LEFT];
389 }
390
391 static void
392 micro_div(
393 union tgsi_exec_channel *dst,
394 const union tgsi_exec_channel *src0,
395 const union tgsi_exec_channel *src1 )
396 {
397 if (src1->f[0] != 0) {
398 dst->f[0] = src0->f[0] / src1->f[0];
399 }
400 if (src1->f[1] != 0) {
401 dst->f[1] = src0->f[1] / src1->f[1];
402 }
403 if (src1->f[2] != 0) {
404 dst->f[2] = src0->f[2] / src1->f[2];
405 }
406 if (src1->f[3] != 0) {
407 dst->f[3] = src0->f[3] / src1->f[3];
408 }
409 }
410
411 static void
412 micro_udiv(
413 union tgsi_exec_channel *dst,
414 const union tgsi_exec_channel *src0,
415 const union tgsi_exec_channel *src1 )
416 {
417 dst->u[0] = src0->u[0] / src1->u[0];
418 dst->u[1] = src0->u[1] / src1->u[1];
419 dst->u[2] = src0->u[2] / src1->u[2];
420 dst->u[3] = src0->u[3] / src1->u[3];
421 }
422
423 static void
424 micro_eq(
425 union tgsi_exec_channel *dst,
426 const union tgsi_exec_channel *src0,
427 const union tgsi_exec_channel *src1,
428 const union tgsi_exec_channel *src2,
429 const union tgsi_exec_channel *src3 )
430 {
431 dst->f[0] = src0->f[0] == src1->f[0] ? src2->f[0] : src3->f[0];
432 dst->f[1] = src0->f[1] == src1->f[1] ? src2->f[1] : src3->f[1];
433 dst->f[2] = src0->f[2] == src1->f[2] ? src2->f[2] : src3->f[2];
434 dst->f[3] = src0->f[3] == src1->f[3] ? src2->f[3] : src3->f[3];
435 }
436
437 static void
438 micro_ieq(
439 union tgsi_exec_channel *dst,
440 const union tgsi_exec_channel *src0,
441 const union tgsi_exec_channel *src1,
442 const union tgsi_exec_channel *src2,
443 const union tgsi_exec_channel *src3 )
444 {
445 dst->i[0] = src0->i[0] == src1->i[0] ? src2->i[0] : src3->i[0];
446 dst->i[1] = src0->i[1] == src1->i[1] ? src2->i[1] : src3->i[1];
447 dst->i[2] = src0->i[2] == src1->i[2] ? src2->i[2] : src3->i[2];
448 dst->i[3] = src0->i[3] == src1->i[3] ? src2->i[3] : src3->i[3];
449 }
450
451 static void
452 micro_exp2(
453 union tgsi_exec_channel *dst,
454 const union tgsi_exec_channel *src)
455 {
456 #if FAST_MATH
457 dst->f[0] = util_fast_exp2( src->f[0] );
458 dst->f[1] = util_fast_exp2( src->f[1] );
459 dst->f[2] = util_fast_exp2( src->f[2] );
460 dst->f[3] = util_fast_exp2( src->f[3] );
461 #else
462 dst->f[0] = powf( 2.0f, src->f[0] );
463 dst->f[1] = powf( 2.0f, src->f[1] );
464 dst->f[2] = powf( 2.0f, src->f[2] );
465 dst->f[3] = powf( 2.0f, src->f[3] );
466 #endif
467 }
468
469 static void
470 micro_f2ut(
471 union tgsi_exec_channel *dst,
472 const union tgsi_exec_channel *src )
473 {
474 dst->u[0] = (uint) src->f[0];
475 dst->u[1] = (uint) src->f[1];
476 dst->u[2] = (uint) src->f[2];
477 dst->u[3] = (uint) src->f[3];
478 }
479
480 static void
481 micro_flr(
482 union tgsi_exec_channel *dst,
483 const union tgsi_exec_channel *src )
484 {
485 dst->f[0] = floorf( src->f[0] );
486 dst->f[1] = floorf( src->f[1] );
487 dst->f[2] = floorf( src->f[2] );
488 dst->f[3] = floorf( src->f[3] );
489 }
490
491 static void
492 micro_frc(
493 union tgsi_exec_channel *dst,
494 const union tgsi_exec_channel *src )
495 {
496 dst->f[0] = src->f[0] - floorf( src->f[0] );
497 dst->f[1] = src->f[1] - floorf( src->f[1] );
498 dst->f[2] = src->f[2] - floorf( src->f[2] );
499 dst->f[3] = src->f[3] - floorf( src->f[3] );
500 }
501
502 static void
503 micro_ge(
504 union tgsi_exec_channel *dst,
505 const union tgsi_exec_channel *src0,
506 const union tgsi_exec_channel *src1,
507 const union tgsi_exec_channel *src2,
508 const union tgsi_exec_channel *src3 )
509 {
510 dst->f[0] = src0->f[0] >= src1->f[0] ? src2->f[0] : src3->f[0];
511 dst->f[1] = src0->f[1] >= src1->f[1] ? src2->f[1] : src3->f[1];
512 dst->f[2] = src0->f[2] >= src1->f[2] ? src2->f[2] : src3->f[2];
513 dst->f[3] = src0->f[3] >= src1->f[3] ? src2->f[3] : src3->f[3];
514 }
515
516 static void
517 micro_i2f(
518 union tgsi_exec_channel *dst,
519 const union tgsi_exec_channel *src )
520 {
521 dst->f[0] = (float) src->i[0];
522 dst->f[1] = (float) src->i[1];
523 dst->f[2] = (float) src->i[2];
524 dst->f[3] = (float) src->i[3];
525 }
526
527 static void
528 micro_lg2(
529 union tgsi_exec_channel *dst,
530 const union tgsi_exec_channel *src )
531 {
532 #if FAST_MATH
533 dst->f[0] = util_fast_log2( src->f[0] );
534 dst->f[1] = util_fast_log2( src->f[1] );
535 dst->f[2] = util_fast_log2( src->f[2] );
536 dst->f[3] = util_fast_log2( src->f[3] );
537 #else
538 dst->f[0] = logf( src->f[0] ) * 1.442695f;
539 dst->f[1] = logf( src->f[1] ) * 1.442695f;
540 dst->f[2] = logf( src->f[2] ) * 1.442695f;
541 dst->f[3] = logf( src->f[3] ) * 1.442695f;
542 #endif
543 }
544
545 static void
546 micro_le(
547 union tgsi_exec_channel *dst,
548 const union tgsi_exec_channel *src0,
549 const union tgsi_exec_channel *src1,
550 const union tgsi_exec_channel *src2,
551 const union tgsi_exec_channel *src3 )
552 {
553 dst->f[0] = src0->f[0] <= src1->f[0] ? src2->f[0] : src3->f[0];
554 dst->f[1] = src0->f[1] <= src1->f[1] ? src2->f[1] : src3->f[1];
555 dst->f[2] = src0->f[2] <= src1->f[2] ? src2->f[2] : src3->f[2];
556 dst->f[3] = src0->f[3] <= src1->f[3] ? src2->f[3] : src3->f[3];
557 }
558
559 static void
560 micro_lt(
561 union tgsi_exec_channel *dst,
562 const union tgsi_exec_channel *src0,
563 const union tgsi_exec_channel *src1,
564 const union tgsi_exec_channel *src2,
565 const union tgsi_exec_channel *src3 )
566 {
567 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
568 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
569 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
570 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
571 }
572
573 static void
574 micro_ilt(
575 union tgsi_exec_channel *dst,
576 const union tgsi_exec_channel *src0,
577 const union tgsi_exec_channel *src1,
578 const union tgsi_exec_channel *src2,
579 const union tgsi_exec_channel *src3 )
580 {
581 dst->i[0] = src0->i[0] < src1->i[0] ? src2->i[0] : src3->i[0];
582 dst->i[1] = src0->i[1] < src1->i[1] ? src2->i[1] : src3->i[1];
583 dst->i[2] = src0->i[2] < src1->i[2] ? src2->i[2] : src3->i[2];
584 dst->i[3] = src0->i[3] < src1->i[3] ? src2->i[3] : src3->i[3];
585 }
586
587 static void
588 micro_ult(
589 union tgsi_exec_channel *dst,
590 const union tgsi_exec_channel *src0,
591 const union tgsi_exec_channel *src1,
592 const union tgsi_exec_channel *src2,
593 const union tgsi_exec_channel *src3 )
594 {
595 dst->u[0] = src0->u[0] < src1->u[0] ? src2->u[0] : src3->u[0];
596 dst->u[1] = src0->u[1] < src1->u[1] ? src2->u[1] : src3->u[1];
597 dst->u[2] = src0->u[2] < src1->u[2] ? src2->u[2] : src3->u[2];
598 dst->u[3] = src0->u[3] < src1->u[3] ? src2->u[3] : src3->u[3];
599 }
600
601 static void
602 micro_max(
603 union tgsi_exec_channel *dst,
604 const union tgsi_exec_channel *src0,
605 const union tgsi_exec_channel *src1 )
606 {
607 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
608 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
609 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
610 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
611 }
612
613 static void
614 micro_imax(
615 union tgsi_exec_channel *dst,
616 const union tgsi_exec_channel *src0,
617 const union tgsi_exec_channel *src1 )
618 {
619 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
620 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
621 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
622 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
623 }
624
625 static void
626 micro_umax(
627 union tgsi_exec_channel *dst,
628 const union tgsi_exec_channel *src0,
629 const union tgsi_exec_channel *src1 )
630 {
631 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
632 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
633 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
634 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
635 }
636
637 static void
638 micro_min(
639 union tgsi_exec_channel *dst,
640 const union tgsi_exec_channel *src0,
641 const union tgsi_exec_channel *src1 )
642 {
643 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
644 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
645 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
646 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
647 }
648
649 static void
650 micro_imin(
651 union tgsi_exec_channel *dst,
652 const union tgsi_exec_channel *src0,
653 const union tgsi_exec_channel *src1 )
654 {
655 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
656 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
657 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
658 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
659 }
660
661 static void
662 micro_umin(
663 union tgsi_exec_channel *dst,
664 const union tgsi_exec_channel *src0,
665 const union tgsi_exec_channel *src1 )
666 {
667 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
668 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
669 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
670 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
671 }
672
673 static void
674 micro_umod(
675 union tgsi_exec_channel *dst,
676 const union tgsi_exec_channel *src0,
677 const union tgsi_exec_channel *src1 )
678 {
679 dst->u[0] = src0->u[0] % src1->u[0];
680 dst->u[1] = src0->u[1] % src1->u[1];
681 dst->u[2] = src0->u[2] % src1->u[2];
682 dst->u[3] = src0->u[3] % src1->u[3];
683 }
684
685 static void
686 micro_mul(
687 union tgsi_exec_channel *dst,
688 const union tgsi_exec_channel *src0,
689 const union tgsi_exec_channel *src1 )
690 {
691 dst->f[0] = src0->f[0] * src1->f[0];
692 dst->f[1] = src0->f[1] * src1->f[1];
693 dst->f[2] = src0->f[2] * src1->f[2];
694 dst->f[3] = src0->f[3] * src1->f[3];
695 }
696
697 static void
698 micro_imul(
699 union tgsi_exec_channel *dst,
700 const union tgsi_exec_channel *src0,
701 const union tgsi_exec_channel *src1 )
702 {
703 dst->i[0] = src0->i[0] * src1->i[0];
704 dst->i[1] = src0->i[1] * src1->i[1];
705 dst->i[2] = src0->i[2] * src1->i[2];
706 dst->i[3] = src0->i[3] * src1->i[3];
707 }
708
709 static void
710 micro_imul64(
711 union tgsi_exec_channel *dst0,
712 union tgsi_exec_channel *dst1,
713 const union tgsi_exec_channel *src0,
714 const union tgsi_exec_channel *src1 )
715 {
716 dst1->i[0] = src0->i[0] * src1->i[0];
717 dst1->i[1] = src0->i[1] * src1->i[1];
718 dst1->i[2] = src0->i[2] * src1->i[2];
719 dst1->i[3] = src0->i[3] * src1->i[3];
720 dst0->i[0] = 0;
721 dst0->i[1] = 0;
722 dst0->i[2] = 0;
723 dst0->i[3] = 0;
724 }
725
726 static void
727 micro_umul64(
728 union tgsi_exec_channel *dst0,
729 union tgsi_exec_channel *dst1,
730 const union tgsi_exec_channel *src0,
731 const union tgsi_exec_channel *src1 )
732 {
733 dst1->u[0] = src0->u[0] * src1->u[0];
734 dst1->u[1] = src0->u[1] * src1->u[1];
735 dst1->u[2] = src0->u[2] * src1->u[2];
736 dst1->u[3] = src0->u[3] * src1->u[3];
737 dst0->u[0] = 0;
738 dst0->u[1] = 0;
739 dst0->u[2] = 0;
740 dst0->u[3] = 0;
741 }
742
743 static void
744 micro_movc(
745 union tgsi_exec_channel *dst,
746 const union tgsi_exec_channel *src0,
747 const union tgsi_exec_channel *src1,
748 const union tgsi_exec_channel *src2 )
749 {
750 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
751 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
752 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
753 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
754 }
755
756 static void
757 micro_neg(
758 union tgsi_exec_channel *dst,
759 const union tgsi_exec_channel *src )
760 {
761 dst->f[0] = -src->f[0];
762 dst->f[1] = -src->f[1];
763 dst->f[2] = -src->f[2];
764 dst->f[3] = -src->f[3];
765 }
766
767 static void
768 micro_ineg(
769 union tgsi_exec_channel *dst,
770 const union tgsi_exec_channel *src )
771 {
772 dst->i[0] = -src->i[0];
773 dst->i[1] = -src->i[1];
774 dst->i[2] = -src->i[2];
775 dst->i[3] = -src->i[3];
776 }
777
778 static void
779 micro_not(
780 union tgsi_exec_channel *dst,
781 const union tgsi_exec_channel *src )
782 {
783 dst->u[0] = ~src->u[0];
784 dst->u[1] = ~src->u[1];
785 dst->u[2] = ~src->u[2];
786 dst->u[3] = ~src->u[3];
787 }
788
789 static void
790 micro_or(
791 union tgsi_exec_channel *dst,
792 const union tgsi_exec_channel *src0,
793 const union tgsi_exec_channel *src1 )
794 {
795 dst->u[0] = src0->u[0] | src1->u[0];
796 dst->u[1] = src0->u[1] | src1->u[1];
797 dst->u[2] = src0->u[2] | src1->u[2];
798 dst->u[3] = src0->u[3] | src1->u[3];
799 }
800
801 static void
802 micro_pow(
803 union tgsi_exec_channel *dst,
804 const union tgsi_exec_channel *src0,
805 const union tgsi_exec_channel *src1 )
806 {
807 #if FAST_MATH
808 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
809 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
810 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
811 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
812 #else
813 dst->f[0] = powf( src0->f[0], src1->f[0] );
814 dst->f[1] = powf( src0->f[1], src1->f[1] );
815 dst->f[2] = powf( src0->f[2], src1->f[2] );
816 dst->f[3] = powf( src0->f[3], src1->f[3] );
817 #endif
818 }
819
820 static void
821 micro_rnd(
822 union tgsi_exec_channel *dst,
823 const union tgsi_exec_channel *src )
824 {
825 dst->f[0] = floorf( src->f[0] + 0.5f );
826 dst->f[1] = floorf( src->f[1] + 0.5f );
827 dst->f[2] = floorf( src->f[2] + 0.5f );
828 dst->f[3] = floorf( src->f[3] + 0.5f );
829 }
830
831 static void
832 micro_sgn(
833 union tgsi_exec_channel *dst,
834 const union tgsi_exec_channel *src )
835 {
836 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
837 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
838 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
839 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
840 }
841
842 static void
843 micro_shl(
844 union tgsi_exec_channel *dst,
845 const union tgsi_exec_channel *src0,
846 const union tgsi_exec_channel *src1 )
847 {
848 dst->i[0] = src0->i[0] << src1->i[0];
849 dst->i[1] = src0->i[1] << src1->i[1];
850 dst->i[2] = src0->i[2] << src1->i[2];
851 dst->i[3] = src0->i[3] << src1->i[3];
852 }
853
854 static void
855 micro_ishr(
856 union tgsi_exec_channel *dst,
857 const union tgsi_exec_channel *src0,
858 const union tgsi_exec_channel *src1 )
859 {
860 dst->i[0] = src0->i[0] >> src1->i[0];
861 dst->i[1] = src0->i[1] >> src1->i[1];
862 dst->i[2] = src0->i[2] >> src1->i[2];
863 dst->i[3] = src0->i[3] >> src1->i[3];
864 }
865
866 static void
867 micro_trunc(
868 union tgsi_exec_channel *dst,
869 const union tgsi_exec_channel *src0 )
870 {
871 dst->f[0] = (float) (int) src0->f[0];
872 dst->f[1] = (float) (int) src0->f[1];
873 dst->f[2] = (float) (int) src0->f[2];
874 dst->f[3] = (float) (int) src0->f[3];
875 }
876
877 static void
878 micro_ushr(
879 union tgsi_exec_channel *dst,
880 const union tgsi_exec_channel *src0,
881 const union tgsi_exec_channel *src1 )
882 {
883 dst->u[0] = src0->u[0] >> src1->u[0];
884 dst->u[1] = src0->u[1] >> src1->u[1];
885 dst->u[2] = src0->u[2] >> src1->u[2];
886 dst->u[3] = src0->u[3] >> src1->u[3];
887 }
888
889 static void
890 micro_sin(
891 union tgsi_exec_channel *dst,
892 const union tgsi_exec_channel *src )
893 {
894 dst->f[0] = sinf( src->f[0] );
895 dst->f[1] = sinf( src->f[1] );
896 dst->f[2] = sinf( src->f[2] );
897 dst->f[3] = sinf( src->f[3] );
898 }
899
900 static void
901 micro_sqrt( union tgsi_exec_channel *dst,
902 const union tgsi_exec_channel *src )
903 {
904 dst->f[0] = sqrtf( src->f[0] );
905 dst->f[1] = sqrtf( src->f[1] );
906 dst->f[2] = sqrtf( src->f[2] );
907 dst->f[3] = sqrtf( src->f[3] );
908 }
909
910 static void
911 micro_sub(
912 union tgsi_exec_channel *dst,
913 const union tgsi_exec_channel *src0,
914 const union tgsi_exec_channel *src1 )
915 {
916 dst->f[0] = src0->f[0] - src1->f[0];
917 dst->f[1] = src0->f[1] - src1->f[1];
918 dst->f[2] = src0->f[2] - src1->f[2];
919 dst->f[3] = src0->f[3] - src1->f[3];
920 }
921
922 static void
923 micro_u2f(
924 union tgsi_exec_channel *dst,
925 const union tgsi_exec_channel *src )
926 {
927 dst->f[0] = (float) src->u[0];
928 dst->f[1] = (float) src->u[1];
929 dst->f[2] = (float) src->u[2];
930 dst->f[3] = (float) src->u[3];
931 }
932
933 static void
934 micro_xor(
935 union tgsi_exec_channel *dst,
936 const union tgsi_exec_channel *src0,
937 const union tgsi_exec_channel *src1 )
938 {
939 dst->u[0] = src0->u[0] ^ src1->u[0];
940 dst->u[1] = src0->u[1] ^ src1->u[1];
941 dst->u[2] = src0->u[2] ^ src1->u[2];
942 dst->u[3] = src0->u[3] ^ src1->u[3];
943 }
944
945 static void
946 fetch_src_file_channel(
947 const struct tgsi_exec_machine *mach,
948 const uint file,
949 const uint swizzle,
950 const union tgsi_exec_channel *index,
951 union tgsi_exec_channel *chan )
952 {
953 switch( swizzle ) {
954 case TGSI_EXTSWIZZLE_X:
955 case TGSI_EXTSWIZZLE_Y:
956 case TGSI_EXTSWIZZLE_Z:
957 case TGSI_EXTSWIZZLE_W:
958 switch( file ) {
959 case TGSI_FILE_CONSTANT:
960 assert(mach->Consts);
961 if (index->i[0] < 0)
962 chan->f[0] = 0.0f;
963 else
964 chan->f[0] = mach->Consts[index->i[0]][swizzle];
965 if (index->i[1] < 0)
966 chan->f[1] = 0.0f;
967 else
968 chan->f[1] = mach->Consts[index->i[1]][swizzle];
969 if (index->i[2] < 0)
970 chan->f[2] = 0.0f;
971 else
972 chan->f[2] = mach->Consts[index->i[2]][swizzle];
973 if (index->i[3] < 0)
974 chan->f[3] = 0.0f;
975 else
976 chan->f[3] = mach->Consts[index->i[3]][swizzle];
977 break;
978
979 case TGSI_FILE_INPUT:
980 chan->u[0] = mach->Inputs[index->i[0]].xyzw[swizzle].u[0];
981 chan->u[1] = mach->Inputs[index->i[1]].xyzw[swizzle].u[1];
982 chan->u[2] = mach->Inputs[index->i[2]].xyzw[swizzle].u[2];
983 chan->u[3] = mach->Inputs[index->i[3]].xyzw[swizzle].u[3];
984 break;
985
986 case TGSI_FILE_TEMPORARY:
987 assert(index->i[0] < TGSI_EXEC_NUM_TEMPS);
988 chan->u[0] = mach->Temps[index->i[0]].xyzw[swizzle].u[0];
989 chan->u[1] = mach->Temps[index->i[1]].xyzw[swizzle].u[1];
990 chan->u[2] = mach->Temps[index->i[2]].xyzw[swizzle].u[2];
991 chan->u[3] = mach->Temps[index->i[3]].xyzw[swizzle].u[3];
992 break;
993
994 case TGSI_FILE_IMMEDIATE:
995 assert( index->i[0] < (int) mach->ImmLimit );
996 chan->f[0] = mach->Imms[index->i[0]][swizzle];
997 assert( index->i[1] < (int) mach->ImmLimit );
998 chan->f[1] = mach->Imms[index->i[1]][swizzle];
999 assert( index->i[2] < (int) mach->ImmLimit );
1000 chan->f[2] = mach->Imms[index->i[2]][swizzle];
1001 assert( index->i[3] < (int) mach->ImmLimit );
1002 chan->f[3] = mach->Imms[index->i[3]][swizzle];
1003 break;
1004
1005 case TGSI_FILE_ADDRESS:
1006 chan->u[0] = mach->Addrs[index->i[0]].xyzw[swizzle].u[0];
1007 chan->u[1] = mach->Addrs[index->i[1]].xyzw[swizzle].u[1];
1008 chan->u[2] = mach->Addrs[index->i[2]].xyzw[swizzle].u[2];
1009 chan->u[3] = mach->Addrs[index->i[3]].xyzw[swizzle].u[3];
1010 break;
1011
1012 case TGSI_FILE_OUTPUT:
1013 /* vertex/fragment output vars can be read too */
1014 chan->u[0] = mach->Outputs[index->i[0]].xyzw[swizzle].u[0];
1015 chan->u[1] = mach->Outputs[index->i[1]].xyzw[swizzle].u[1];
1016 chan->u[2] = mach->Outputs[index->i[2]].xyzw[swizzle].u[2];
1017 chan->u[3] = mach->Outputs[index->i[3]].xyzw[swizzle].u[3];
1018 break;
1019
1020 default:
1021 assert( 0 );
1022 }
1023 break;
1024
1025 case TGSI_EXTSWIZZLE_ZERO:
1026 *chan = mach->Temps[TEMP_0_I].xyzw[TEMP_0_C];
1027 break;
1028
1029 case TGSI_EXTSWIZZLE_ONE:
1030 *chan = mach->Temps[TEMP_1_I].xyzw[TEMP_1_C];
1031 break;
1032
1033 default:
1034 assert( 0 );
1035 }
1036 }
1037
1038 static void
1039 fetch_source(
1040 const struct tgsi_exec_machine *mach,
1041 union tgsi_exec_channel *chan,
1042 const struct tgsi_full_src_register *reg,
1043 const uint chan_index )
1044 {
1045 union tgsi_exec_channel index;
1046 uint swizzle;
1047
1048 index.i[0] =
1049 index.i[1] =
1050 index.i[2] =
1051 index.i[3] = reg->SrcRegister.Index;
1052
1053 if (reg->SrcRegister.Indirect) {
1054 union tgsi_exec_channel index2;
1055 union tgsi_exec_channel indir_index;
1056 const uint execmask = mach->ExecMask;
1057 uint i;
1058
1059 /* which address register (always zero now) */
1060 index2.i[0] =
1061 index2.i[1] =
1062 index2.i[2] =
1063 index2.i[3] = reg->SrcRegisterInd.Index;
1064
1065 /* get current value of address register[swizzle] */
1066 swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterInd, CHAN_X );
1067 fetch_src_file_channel(
1068 mach,
1069 reg->SrcRegisterInd.File,
1070 swizzle,
1071 &index2,
1072 &indir_index );
1073
1074 /* add value of address register to the offset */
1075 index.i[0] += (int) indir_index.f[0];
1076 index.i[1] += (int) indir_index.f[1];
1077 index.i[2] += (int) indir_index.f[2];
1078 index.i[3] += (int) indir_index.f[3];
1079
1080 /* for disabled execution channels, zero-out the index to
1081 * avoid using a potential garbage value.
1082 */
1083 for (i = 0; i < QUAD_SIZE; i++) {
1084 if ((execmask & (1 << i)) == 0)
1085 index.i[i] = 0;
1086 }
1087 }
1088
1089 if( reg->SrcRegister.Dimension ) {
1090 switch( reg->SrcRegister.File ) {
1091 case TGSI_FILE_INPUT:
1092 index.i[0] *= 17;
1093 index.i[1] *= 17;
1094 index.i[2] *= 17;
1095 index.i[3] *= 17;
1096 break;
1097 case TGSI_FILE_CONSTANT:
1098 index.i[0] *= 4096;
1099 index.i[1] *= 4096;
1100 index.i[2] *= 4096;
1101 index.i[3] *= 4096;
1102 break;
1103 default:
1104 assert( 0 );
1105 }
1106
1107 index.i[0] += reg->SrcRegisterDim.Index;
1108 index.i[1] += reg->SrcRegisterDim.Index;
1109 index.i[2] += reg->SrcRegisterDim.Index;
1110 index.i[3] += reg->SrcRegisterDim.Index;
1111
1112 if (reg->SrcRegisterDim.Indirect) {
1113 union tgsi_exec_channel index2;
1114 union tgsi_exec_channel indir_index;
1115 const uint execmask = mach->ExecMask;
1116 uint i;
1117
1118 index2.i[0] =
1119 index2.i[1] =
1120 index2.i[2] =
1121 index2.i[3] = reg->SrcRegisterDimInd.Index;
1122
1123 swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterDimInd, CHAN_X );
1124 fetch_src_file_channel(
1125 mach,
1126 reg->SrcRegisterDimInd.File,
1127 swizzle,
1128 &index2,
1129 &indir_index );
1130
1131 index.i[0] += (int) indir_index.f[0];
1132 index.i[1] += (int) indir_index.f[1];
1133 index.i[2] += (int) indir_index.f[2];
1134 index.i[3] += (int) indir_index.f[3];
1135
1136 /* for disabled execution channels, zero-out the index to
1137 * avoid using a potential garbage value.
1138 */
1139 for (i = 0; i < QUAD_SIZE; i++) {
1140 if ((execmask & (1 << i)) == 0)
1141 index.i[i] = 0;
1142 }
1143 }
1144 }
1145
1146 swizzle = tgsi_util_get_full_src_register_extswizzle( reg, chan_index );
1147 fetch_src_file_channel(
1148 mach,
1149 reg->SrcRegister.File,
1150 swizzle,
1151 &index,
1152 chan );
1153
1154 switch (tgsi_util_get_full_src_register_sign_mode( reg, chan_index )) {
1155 case TGSI_UTIL_SIGN_CLEAR:
1156 micro_abs( chan, chan );
1157 break;
1158
1159 case TGSI_UTIL_SIGN_SET:
1160 micro_abs( chan, chan );
1161 micro_neg( chan, chan );
1162 break;
1163
1164 case TGSI_UTIL_SIGN_TOGGLE:
1165 micro_neg( chan, chan );
1166 break;
1167
1168 case TGSI_UTIL_SIGN_KEEP:
1169 break;
1170 }
1171
1172 if (reg->SrcRegisterExtMod.Complement) {
1173 micro_sub( chan, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], chan );
1174 }
1175 }
1176
1177 static void
1178 store_dest(
1179 struct tgsi_exec_machine *mach,
1180 const union tgsi_exec_channel *chan,
1181 const struct tgsi_full_dst_register *reg,
1182 const struct tgsi_full_instruction *inst,
1183 uint chan_index )
1184 {
1185 uint i;
1186 union tgsi_exec_channel null;
1187 union tgsi_exec_channel *dst;
1188 uint execmask = mach->ExecMask;
1189
1190 switch (reg->DstRegister.File) {
1191 case TGSI_FILE_NULL:
1192 dst = &null;
1193 break;
1194
1195 case TGSI_FILE_OUTPUT:
1196 dst = &mach->Outputs[mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1197 + reg->DstRegister.Index].xyzw[chan_index];
1198 break;
1199
1200 case TGSI_FILE_TEMPORARY:
1201 assert( reg->DstRegister.Index < TGSI_EXEC_NUM_TEMPS );
1202 dst = &mach->Temps[reg->DstRegister.Index].xyzw[chan_index];
1203 break;
1204
1205 case TGSI_FILE_ADDRESS:
1206 dst = &mach->Addrs[reg->DstRegister.Index].xyzw[chan_index];
1207 break;
1208
1209 default:
1210 assert( 0 );
1211 return;
1212 }
1213
1214 if (inst->InstructionExtNv.CondFlowEnable) {
1215 union tgsi_exec_channel *cc = &mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C];
1216 uint swizzle;
1217 uint shift;
1218 uint mask;
1219 uint test;
1220
1221 /* Only CC0 supported.
1222 */
1223 assert( inst->InstructionExtNv.CondFlowIndex < 1 );
1224
1225 switch (chan_index) {
1226 case CHAN_X:
1227 swizzle = inst->InstructionExtNv.CondSwizzleX;
1228 break;
1229 case CHAN_Y:
1230 swizzle = inst->InstructionExtNv.CondSwizzleY;
1231 break;
1232 case CHAN_Z:
1233 swizzle = inst->InstructionExtNv.CondSwizzleZ;
1234 break;
1235 case CHAN_W:
1236 swizzle = inst->InstructionExtNv.CondSwizzleW;
1237 break;
1238 default:
1239 assert( 0 );
1240 return;
1241 }
1242
1243 switch (swizzle) {
1244 case TGSI_SWIZZLE_X:
1245 shift = TGSI_EXEC_CC_X_SHIFT;
1246 mask = TGSI_EXEC_CC_X_MASK;
1247 break;
1248 case TGSI_SWIZZLE_Y:
1249 shift = TGSI_EXEC_CC_Y_SHIFT;
1250 mask = TGSI_EXEC_CC_Y_MASK;
1251 break;
1252 case TGSI_SWIZZLE_Z:
1253 shift = TGSI_EXEC_CC_Z_SHIFT;
1254 mask = TGSI_EXEC_CC_Z_MASK;
1255 break;
1256 case TGSI_SWIZZLE_W:
1257 shift = TGSI_EXEC_CC_W_SHIFT;
1258 mask = TGSI_EXEC_CC_W_MASK;
1259 break;
1260 default:
1261 assert( 0 );
1262 return;
1263 }
1264
1265 switch (inst->InstructionExtNv.CondMask) {
1266 case TGSI_CC_GT:
1267 test = ~(TGSI_EXEC_CC_GT << shift) & mask;
1268 for (i = 0; i < QUAD_SIZE; i++)
1269 if (cc->u[i] & test)
1270 execmask &= ~(1 << i);
1271 break;
1272
1273 case TGSI_CC_EQ:
1274 test = ~(TGSI_EXEC_CC_EQ << shift) & mask;
1275 for (i = 0; i < QUAD_SIZE; i++)
1276 if (cc->u[i] & test)
1277 execmask &= ~(1 << i);
1278 break;
1279
1280 case TGSI_CC_LT:
1281 test = ~(TGSI_EXEC_CC_LT << shift) & mask;
1282 for (i = 0; i < QUAD_SIZE; i++)
1283 if (cc->u[i] & test)
1284 execmask &= ~(1 << i);
1285 break;
1286
1287 case TGSI_CC_GE:
1288 test = ~((TGSI_EXEC_CC_GT | TGSI_EXEC_CC_EQ) << shift) & mask;
1289 for (i = 0; i < QUAD_SIZE; i++)
1290 if (cc->u[i] & test)
1291 execmask &= ~(1 << i);
1292 break;
1293
1294 case TGSI_CC_LE:
1295 test = ~((TGSI_EXEC_CC_LT | TGSI_EXEC_CC_EQ) << shift) & mask;
1296 for (i = 0; i < QUAD_SIZE; i++)
1297 if (cc->u[i] & test)
1298 execmask &= ~(1 << i);
1299 break;
1300
1301 case TGSI_CC_NE:
1302 test = ~((TGSI_EXEC_CC_GT | TGSI_EXEC_CC_LT | TGSI_EXEC_CC_UN) << shift) & mask;
1303 for (i = 0; i < QUAD_SIZE; i++)
1304 if (cc->u[i] & test)
1305 execmask &= ~(1 << i);
1306 break;
1307
1308 case TGSI_CC_TR:
1309 break;
1310
1311 case TGSI_CC_FL:
1312 for (i = 0; i < QUAD_SIZE; i++)
1313 execmask &= ~(1 << i);
1314 break;
1315
1316 default:
1317 assert( 0 );
1318 return;
1319 }
1320 }
1321
1322 switch (inst->Instruction.Saturate) {
1323 case TGSI_SAT_NONE:
1324 for (i = 0; i < QUAD_SIZE; i++)
1325 if (execmask & (1 << i))
1326 dst->i[i] = chan->i[i];
1327 break;
1328
1329 case TGSI_SAT_ZERO_ONE:
1330 for (i = 0; i < QUAD_SIZE; i++)
1331 if (execmask & (1 << i)) {
1332 if (chan->f[i] < 0.0f)
1333 dst->f[i] = 0.0f;
1334 else if (chan->f[i] > 1.0f)
1335 dst->f[i] = 1.0f;
1336 else
1337 dst->i[i] = chan->i[i];
1338 }
1339 break;
1340
1341 case TGSI_SAT_MINUS_PLUS_ONE:
1342 for (i = 0; i < QUAD_SIZE; i++)
1343 if (execmask & (1 << i)) {
1344 if (chan->f[i] < -1.0f)
1345 dst->f[i] = -1.0f;
1346 else if (chan->f[i] > 1.0f)
1347 dst->f[i] = 1.0f;
1348 else
1349 dst->i[i] = chan->i[i];
1350 }
1351 break;
1352
1353 default:
1354 assert( 0 );
1355 }
1356
1357 if (inst->InstructionExtNv.CondDstUpdate) {
1358 union tgsi_exec_channel *cc = &mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C];
1359 uint shift;
1360 uint mask;
1361
1362 /* Only CC0 supported.
1363 */
1364 assert( inst->InstructionExtNv.CondDstIndex < 1 );
1365
1366 switch (chan_index) {
1367 case CHAN_X:
1368 shift = TGSI_EXEC_CC_X_SHIFT;
1369 mask = ~TGSI_EXEC_CC_X_MASK;
1370 break;
1371 case CHAN_Y:
1372 shift = TGSI_EXEC_CC_Y_SHIFT;
1373 mask = ~TGSI_EXEC_CC_Y_MASK;
1374 break;
1375 case CHAN_Z:
1376 shift = TGSI_EXEC_CC_Z_SHIFT;
1377 mask = ~TGSI_EXEC_CC_Z_MASK;
1378 break;
1379 case CHAN_W:
1380 shift = TGSI_EXEC_CC_W_SHIFT;
1381 mask = ~TGSI_EXEC_CC_W_MASK;
1382 break;
1383 default:
1384 assert( 0 );
1385 return;
1386 }
1387
1388 for (i = 0; i < QUAD_SIZE; i++)
1389 if (execmask & (1 << i)) {
1390 cc->u[i] &= mask;
1391 if (dst->f[i] < 0.0f)
1392 cc->u[i] |= TGSI_EXEC_CC_LT << shift;
1393 else if (dst->f[i] > 0.0f)
1394 cc->u[i] |= TGSI_EXEC_CC_GT << shift;
1395 else if (dst->f[i] == 0.0f)
1396 cc->u[i] |= TGSI_EXEC_CC_EQ << shift;
1397 else
1398 cc->u[i] |= TGSI_EXEC_CC_UN << shift;
1399 }
1400 }
1401 }
1402
1403 #define FETCH(VAL,INDEX,CHAN)\
1404 fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
1405
1406 #define STORE(VAL,INDEX,CHAN)\
1407 store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
1408
1409
1410 /**
1411 * Execute ARB-style KIL which is predicated by a src register.
1412 * Kill fragment if any of the four values is less than zero.
1413 */
1414 static void
1415 exec_kil(struct tgsi_exec_machine *mach,
1416 const struct tgsi_full_instruction *inst)
1417 {
1418 uint uniquemask;
1419 uint chan_index;
1420 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1421 union tgsi_exec_channel r[1];
1422
1423 /* This mask stores component bits that were already tested. Note that
1424 * we test if the value is less than zero, so 1.0 and 0.0 need not to be
1425 * tested. */
1426 uniquemask = (1 << TGSI_EXTSWIZZLE_ZERO) | (1 << TGSI_EXTSWIZZLE_ONE);
1427
1428 for (chan_index = 0; chan_index < 4; chan_index++)
1429 {
1430 uint swizzle;
1431 uint i;
1432
1433 /* unswizzle channel */
1434 swizzle = tgsi_util_get_full_src_register_extswizzle (
1435 &inst->FullSrcRegisters[0],
1436 chan_index);
1437
1438 /* check if the component has not been already tested */
1439 if (uniquemask & (1 << swizzle))
1440 continue;
1441 uniquemask |= 1 << swizzle;
1442
1443 FETCH(&r[0], 0, chan_index);
1444 for (i = 0; i < 4; i++)
1445 if (r[0].f[i] < 0.0f)
1446 kilmask |= 1 << i;
1447 }
1448
1449 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1450 }
1451
1452 /**
1453 * Execute NVIDIA-style KIL which is predicated by a condition code.
1454 * Kill fragment if the condition code is TRUE.
1455 */
1456 static void
1457 exec_kilp(struct tgsi_exec_machine *mach,
1458 const struct tgsi_full_instruction *inst)
1459 {
1460 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1461
1462 if (inst->InstructionExtNv.CondFlowEnable) {
1463 uint swizzle[4];
1464 uint chan_index;
1465
1466 kilmask = 0x0;
1467
1468 swizzle[0] = inst->InstructionExtNv.CondSwizzleX;
1469 swizzle[1] = inst->InstructionExtNv.CondSwizzleY;
1470 swizzle[2] = inst->InstructionExtNv.CondSwizzleZ;
1471 swizzle[3] = inst->InstructionExtNv.CondSwizzleW;
1472
1473 for (chan_index = 0; chan_index < 4; chan_index++)
1474 {
1475 uint i;
1476
1477 for (i = 0; i < 4; i++) {
1478 /* TODO: evaluate the condition code */
1479 if (0)
1480 kilmask |= 1 << i;
1481 }
1482 }
1483 }
1484 else {
1485 /* "unconditional" kil */
1486 kilmask = mach->ExecMask;
1487 }
1488 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1489 }
1490
1491
1492 /*
1493 * Fetch a texel using STR texture coordinates.
1494 */
1495 static void
1496 fetch_texel( struct tgsi_sampler *sampler,
1497 const union tgsi_exec_channel *s,
1498 const union tgsi_exec_channel *t,
1499 const union tgsi_exec_channel *p,
1500 float lodbias, /* XXX should be float[4] */
1501 union tgsi_exec_channel *r,
1502 union tgsi_exec_channel *g,
1503 union tgsi_exec_channel *b,
1504 union tgsi_exec_channel *a )
1505 {
1506 uint j;
1507 float rgba[NUM_CHANNELS][QUAD_SIZE];
1508
1509 sampler->get_samples(sampler, s->f, t->f, p->f, lodbias, rgba);
1510
1511 for (j = 0; j < 4; j++) {
1512 r->f[j] = rgba[0][j];
1513 g->f[j] = rgba[1][j];
1514 b->f[j] = rgba[2][j];
1515 a->f[j] = rgba[3][j];
1516 }
1517 }
1518
1519
1520 static void
1521 exec_tex(struct tgsi_exec_machine *mach,
1522 const struct tgsi_full_instruction *inst,
1523 boolean biasLod,
1524 boolean projected)
1525 {
1526 const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
1527 union tgsi_exec_channel r[8];
1528 uint chan_index;
1529 float lodBias;
1530
1531 /* debug_printf("Sampler %u unit %u\n", sampler, unit); */
1532
1533 switch (inst->InstructionExtTexture.Texture) {
1534 case TGSI_TEXTURE_1D:
1535
1536 FETCH(&r[0], 0, CHAN_X);
1537
1538 if (projected) {
1539 FETCH(&r[1], 0, CHAN_W);
1540 micro_div( &r[0], &r[0], &r[1] );
1541 }
1542
1543 if (biasLod) {
1544 FETCH(&r[1], 0, CHAN_W);
1545 lodBias = r[2].f[0];
1546 }
1547 else
1548 lodBias = 0.0;
1549
1550 fetch_texel(&mach->Samplers[unit],
1551 &r[0], NULL, NULL, lodBias, /* S, T, P, BIAS */
1552 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1553 break;
1554
1555 case TGSI_TEXTURE_2D:
1556 case TGSI_TEXTURE_RECT:
1557
1558 FETCH(&r[0], 0, CHAN_X);
1559 FETCH(&r[1], 0, CHAN_Y);
1560 FETCH(&r[2], 0, CHAN_Z);
1561
1562 if (projected) {
1563 FETCH(&r[3], 0, CHAN_W);
1564 micro_div( &r[0], &r[0], &r[3] );
1565 micro_div( &r[1], &r[1], &r[3] );
1566 micro_div( &r[2], &r[2], &r[3] );
1567 }
1568
1569 if (biasLod) {
1570 FETCH(&r[3], 0, CHAN_W);
1571 lodBias = r[3].f[0];
1572 }
1573 else
1574 lodBias = 0.0;
1575
1576 fetch_texel(&mach->Samplers[unit],
1577 &r[0], &r[1], &r[2], lodBias, /* inputs */
1578 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1579 break;
1580
1581 case TGSI_TEXTURE_3D:
1582 case TGSI_TEXTURE_CUBE:
1583
1584 FETCH(&r[0], 0, CHAN_X);
1585 FETCH(&r[1], 0, CHAN_Y);
1586 FETCH(&r[2], 0, CHAN_Z);
1587
1588 if (projected) {
1589 FETCH(&r[3], 0, CHAN_W);
1590 micro_div( &r[0], &r[0], &r[3] );
1591 micro_div( &r[1], &r[1], &r[3] );
1592 micro_div( &r[2], &r[2], &r[3] );
1593 }
1594
1595 if (biasLod) {
1596 FETCH(&r[3], 0, CHAN_W);
1597 lodBias = r[3].f[0];
1598 }
1599 else
1600 lodBias = 0.0;
1601
1602 fetch_texel(&mach->Samplers[unit],
1603 &r[0], &r[1], &r[2], lodBias,
1604 &r[0], &r[1], &r[2], &r[3]);
1605 break;
1606
1607 default:
1608 assert (0);
1609 }
1610
1611 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1612 STORE( &r[chan_index], 0, chan_index );
1613 }
1614 }
1615
1616
1617 /**
1618 * Evaluate a constant-valued coefficient at the position of the
1619 * current quad.
1620 */
1621 static void
1622 eval_constant_coef(
1623 struct tgsi_exec_machine *mach,
1624 unsigned attrib,
1625 unsigned chan )
1626 {
1627 unsigned i;
1628
1629 for( i = 0; i < QUAD_SIZE; i++ ) {
1630 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1631 }
1632 }
1633
1634 /**
1635 * Evaluate a linear-valued coefficient at the position of the
1636 * current quad.
1637 */
1638 static void
1639 eval_linear_coef(
1640 struct tgsi_exec_machine *mach,
1641 unsigned attrib,
1642 unsigned chan )
1643 {
1644 const float x = mach->QuadPos.xyzw[0].f[0];
1645 const float y = mach->QuadPos.xyzw[1].f[0];
1646 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1647 const float dady = mach->InterpCoefs[attrib].dady[chan];
1648 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1649 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1650 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1651 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1652 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1653 }
1654
1655 /**
1656 * Evaluate a perspective-valued coefficient at the position of the
1657 * current quad.
1658 */
1659 static void
1660 eval_perspective_coef(
1661 struct tgsi_exec_machine *mach,
1662 unsigned attrib,
1663 unsigned chan )
1664 {
1665 const float x = mach->QuadPos.xyzw[0].f[0];
1666 const float y = mach->QuadPos.xyzw[1].f[0];
1667 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1668 const float dady = mach->InterpCoefs[attrib].dady[chan];
1669 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1670 const float *w = mach->QuadPos.xyzw[3].f;
1671 /* divide by W here */
1672 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1673 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1674 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1675 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1676 }
1677
1678
1679 typedef void (* eval_coef_func)(
1680 struct tgsi_exec_machine *mach,
1681 unsigned attrib,
1682 unsigned chan );
1683
1684 static void
1685 exec_declaration(
1686 struct tgsi_exec_machine *mach,
1687 const struct tgsi_full_declaration *decl )
1688 {
1689 if( mach->Processor == TGSI_PROCESSOR_FRAGMENT ) {
1690 if( decl->Declaration.File == TGSI_FILE_INPUT ) {
1691 unsigned first, last, mask;
1692 eval_coef_func eval;
1693
1694 first = decl->DeclarationRange.First;
1695 last = decl->DeclarationRange.Last;
1696 mask = decl->Declaration.UsageMask;
1697
1698 switch( decl->Declaration.Interpolate ) {
1699 case TGSI_INTERPOLATE_CONSTANT:
1700 eval = eval_constant_coef;
1701 break;
1702
1703 case TGSI_INTERPOLATE_LINEAR:
1704 eval = eval_linear_coef;
1705 break;
1706
1707 case TGSI_INTERPOLATE_PERSPECTIVE:
1708 eval = eval_perspective_coef;
1709 break;
1710
1711 default:
1712 assert( 0 );
1713 }
1714
1715 if( mask == TGSI_WRITEMASK_XYZW ) {
1716 unsigned i, j;
1717
1718 for( i = first; i <= last; i++ ) {
1719 for( j = 0; j < NUM_CHANNELS; j++ ) {
1720 eval( mach, i, j );
1721 }
1722 }
1723 }
1724 else {
1725 unsigned i, j;
1726
1727 for( j = 0; j < NUM_CHANNELS; j++ ) {
1728 if( mask & (1 << j) ) {
1729 for( i = first; i <= last; i++ ) {
1730 eval( mach, i, j );
1731 }
1732 }
1733 }
1734 }
1735 }
1736 }
1737 }
1738
1739 static void
1740 exec_instruction(
1741 struct tgsi_exec_machine *mach,
1742 const struct tgsi_full_instruction *inst,
1743 int *pc )
1744 {
1745 uint chan_index;
1746 union tgsi_exec_channel r[8];
1747
1748 (*pc)++;
1749
1750 switch (inst->Instruction.Opcode) {
1751 case TGSI_OPCODE_ARL:
1752 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1753 FETCH( &r[0], 0, chan_index );
1754 micro_trunc( &r[0], &r[0] );
1755 STORE( &r[0], 0, chan_index );
1756 }
1757 break;
1758
1759 case TGSI_OPCODE_MOV:
1760 case TGSI_OPCODE_SWZ:
1761 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1762 FETCH( &r[0], 0, chan_index );
1763 STORE( &r[0], 0, chan_index );
1764 }
1765 break;
1766
1767 case TGSI_OPCODE_LIT:
1768 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1769 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
1770 }
1771
1772 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1773 FETCH( &r[0], 0, CHAN_X );
1774 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1775 micro_max( &r[0], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1776 STORE( &r[0], 0, CHAN_Y );
1777 }
1778
1779 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1780 FETCH( &r[1], 0, CHAN_Y );
1781 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1782
1783 FETCH( &r[2], 0, CHAN_W );
1784 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
1785 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
1786 micro_pow( &r[1], &r[1], &r[2] );
1787 micro_lt( &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1788 STORE( &r[0], 0, CHAN_Z );
1789 }
1790 }
1791
1792 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1793 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1794 }
1795 break;
1796
1797 case TGSI_OPCODE_RCP:
1798 /* TGSI_OPCODE_RECIP */
1799 FETCH( &r[0], 0, CHAN_X );
1800 micro_div( &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0] );
1801 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1802 STORE( &r[0], 0, chan_index );
1803 }
1804 break;
1805
1806 case TGSI_OPCODE_RSQ:
1807 /* TGSI_OPCODE_RECIPSQRT */
1808 FETCH( &r[0], 0, CHAN_X );
1809 micro_sqrt( &r[0], &r[0] );
1810 micro_div( &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0] );
1811 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1812 STORE( &r[0], 0, chan_index );
1813 }
1814 break;
1815
1816 case TGSI_OPCODE_EXP:
1817 FETCH( &r[0], 0, CHAN_X );
1818 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
1819 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1820 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
1821 STORE( &r[2], 0, CHAN_X ); /* store r2 */
1822 }
1823 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1824 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
1825 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
1826 }
1827 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1828 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
1829 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
1830 }
1831 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1832 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1833 }
1834 break;
1835
1836 case TGSI_OPCODE_LOG:
1837 FETCH( &r[0], 0, CHAN_X );
1838 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
1839 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
1840 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
1841 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1842 STORE( &r[0], 0, CHAN_X );
1843 }
1844 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1845 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
1846 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
1847 STORE( &r[0], 0, CHAN_Y );
1848 }
1849 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1850 STORE( &r[1], 0, CHAN_Z );
1851 }
1852 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1853 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1854 }
1855 break;
1856
1857 case TGSI_OPCODE_MUL:
1858 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index )
1859 {
1860 FETCH(&r[0], 0, chan_index);
1861 FETCH(&r[1], 1, chan_index);
1862
1863 micro_mul( &r[0], &r[0], &r[1] );
1864
1865 STORE(&r[0], 0, chan_index);
1866 }
1867 break;
1868
1869 case TGSI_OPCODE_ADD:
1870 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1871 FETCH( &r[0], 0, chan_index );
1872 FETCH( &r[1], 1, chan_index );
1873 micro_add( &r[0], &r[0], &r[1] );
1874 STORE( &r[0], 0, chan_index );
1875 }
1876 break;
1877
1878 case TGSI_OPCODE_DP3:
1879 /* TGSI_OPCODE_DOT3 */
1880 FETCH( &r[0], 0, CHAN_X );
1881 FETCH( &r[1], 1, CHAN_X );
1882 micro_mul( &r[0], &r[0], &r[1] );
1883
1884 FETCH( &r[1], 0, CHAN_Y );
1885 FETCH( &r[2], 1, CHAN_Y );
1886 micro_mul( &r[1], &r[1], &r[2] );
1887 micro_add( &r[0], &r[0], &r[1] );
1888
1889 FETCH( &r[1], 0, CHAN_Z );
1890 FETCH( &r[2], 1, CHAN_Z );
1891 micro_mul( &r[1], &r[1], &r[2] );
1892 micro_add( &r[0], &r[0], &r[1] );
1893
1894 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1895 STORE( &r[0], 0, chan_index );
1896 }
1897 break;
1898
1899 case TGSI_OPCODE_DP4:
1900 /* TGSI_OPCODE_DOT4 */
1901 FETCH(&r[0], 0, CHAN_X);
1902 FETCH(&r[1], 1, CHAN_X);
1903
1904 micro_mul( &r[0], &r[0], &r[1] );
1905
1906 FETCH(&r[1], 0, CHAN_Y);
1907 FETCH(&r[2], 1, CHAN_Y);
1908
1909 micro_mul( &r[1], &r[1], &r[2] );
1910 micro_add( &r[0], &r[0], &r[1] );
1911
1912 FETCH(&r[1], 0, CHAN_Z);
1913 FETCH(&r[2], 1, CHAN_Z);
1914
1915 micro_mul( &r[1], &r[1], &r[2] );
1916 micro_add( &r[0], &r[0], &r[1] );
1917
1918 FETCH(&r[1], 0, CHAN_W);
1919 FETCH(&r[2], 1, CHAN_W);
1920
1921 micro_mul( &r[1], &r[1], &r[2] );
1922 micro_add( &r[0], &r[0], &r[1] );
1923
1924 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1925 STORE( &r[0], 0, chan_index );
1926 }
1927 break;
1928
1929 case TGSI_OPCODE_DST:
1930 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1931 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
1932 }
1933
1934 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1935 FETCH( &r[0], 0, CHAN_Y );
1936 FETCH( &r[1], 1, CHAN_Y);
1937 micro_mul( &r[0], &r[0], &r[1] );
1938 STORE( &r[0], 0, CHAN_Y );
1939 }
1940
1941 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1942 FETCH( &r[0], 0, CHAN_Z );
1943 STORE( &r[0], 0, CHAN_Z );
1944 }
1945
1946 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1947 FETCH( &r[0], 1, CHAN_W );
1948 STORE( &r[0], 0, CHAN_W );
1949 }
1950 break;
1951
1952 case TGSI_OPCODE_MIN:
1953 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1954 FETCH(&r[0], 0, chan_index);
1955 FETCH(&r[1], 1, chan_index);
1956
1957 /* XXX use micro_min()?? */
1958 micro_lt( &r[0], &r[0], &r[1], &r[0], &r[1] );
1959
1960 STORE(&r[0], 0, chan_index);
1961 }
1962 break;
1963
1964 case TGSI_OPCODE_MAX:
1965 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1966 FETCH(&r[0], 0, chan_index);
1967 FETCH(&r[1], 1, chan_index);
1968
1969 /* XXX use micro_max()?? */
1970 micro_lt( &r[0], &r[0], &r[1], &r[1], &r[0] );
1971
1972 STORE(&r[0], 0, chan_index );
1973 }
1974 break;
1975
1976 case TGSI_OPCODE_SLT:
1977 /* TGSI_OPCODE_SETLT */
1978 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1979 FETCH( &r[0], 0, chan_index );
1980 FETCH( &r[1], 1, chan_index );
1981 micro_lt( &r[0], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1982 STORE( &r[0], 0, chan_index );
1983 }
1984 break;
1985
1986 case TGSI_OPCODE_SGE:
1987 /* TGSI_OPCODE_SETGE */
1988 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1989 FETCH( &r[0], 0, chan_index );
1990 FETCH( &r[1], 1, chan_index );
1991 micro_ge( &r[0], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1992 STORE( &r[0], 0, chan_index );
1993 }
1994 break;
1995
1996 case TGSI_OPCODE_MAD:
1997 /* TGSI_OPCODE_MADD */
1998 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1999 FETCH( &r[0], 0, chan_index );
2000 FETCH( &r[1], 1, chan_index );
2001 micro_mul( &r[0], &r[0], &r[1] );
2002 FETCH( &r[1], 2, chan_index );
2003 micro_add( &r[0], &r[0], &r[1] );
2004 STORE( &r[0], 0, chan_index );
2005 }
2006 break;
2007
2008 case TGSI_OPCODE_SUB:
2009 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2010 FETCH(&r[0], 0, chan_index);
2011 FETCH(&r[1], 1, chan_index);
2012
2013 micro_sub( &r[0], &r[0], &r[1] );
2014
2015 STORE(&r[0], 0, chan_index);
2016 }
2017 break;
2018
2019 case TGSI_OPCODE_LERP:
2020 /* TGSI_OPCODE_LRP */
2021 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2022 FETCH(&r[0], 0, chan_index);
2023 FETCH(&r[1], 1, chan_index);
2024 FETCH(&r[2], 2, chan_index);
2025
2026 micro_sub( &r[1], &r[1], &r[2] );
2027 micro_mul( &r[0], &r[0], &r[1] );
2028 micro_add( &r[0], &r[0], &r[2] );
2029
2030 STORE(&r[0], 0, chan_index);
2031 }
2032 break;
2033
2034 case TGSI_OPCODE_CND:
2035 assert (0);
2036 break;
2037
2038 case TGSI_OPCODE_CND0:
2039 assert (0);
2040 break;
2041
2042 case TGSI_OPCODE_DOT2ADD:
2043 /* TGSI_OPCODE_DP2A */
2044 FETCH( &r[0], 0, CHAN_X );
2045 FETCH( &r[1], 1, CHAN_X );
2046 micro_mul( &r[0], &r[0], &r[1] );
2047
2048 FETCH( &r[1], 0, CHAN_Y );
2049 FETCH( &r[2], 1, CHAN_Y );
2050 micro_mul( &r[1], &r[1], &r[2] );
2051 micro_add( &r[0], &r[0], &r[1] );
2052
2053 FETCH( &r[2], 2, CHAN_X );
2054 micro_add( &r[0], &r[0], &r[2] );
2055
2056 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2057 STORE( &r[0], 0, chan_index );
2058 }
2059 break;
2060
2061 case TGSI_OPCODE_INDEX:
2062 assert (0);
2063 break;
2064
2065 case TGSI_OPCODE_NEGATE:
2066 assert (0);
2067 break;
2068
2069 case TGSI_OPCODE_FRAC:
2070 /* TGSI_OPCODE_FRC */
2071 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2072 FETCH( &r[0], 0, chan_index );
2073 micro_frc( &r[0], &r[0] );
2074 STORE( &r[0], 0, chan_index );
2075 }
2076 break;
2077
2078 case TGSI_OPCODE_CLAMP:
2079 assert (0);
2080 break;
2081
2082 case TGSI_OPCODE_FLOOR:
2083 /* TGSI_OPCODE_FLR */
2084 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2085 FETCH( &r[0], 0, chan_index );
2086 micro_flr( &r[0], &r[0] );
2087 STORE( &r[0], 0, chan_index );
2088 }
2089 break;
2090
2091 case TGSI_OPCODE_ROUND:
2092 case TGSI_OPCODE_ARR:
2093 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2094 FETCH( &r[0], 0, chan_index );
2095 micro_rnd( &r[0], &r[0] );
2096 STORE( &r[0], 0, chan_index );
2097 }
2098 break;
2099
2100 case TGSI_OPCODE_EXPBASE2:
2101 /* TGSI_OPCODE_EX2 */
2102 FETCH(&r[0], 0, CHAN_X);
2103
2104 #if FAST_MATH
2105 micro_exp2( &r[0], &r[0] );
2106 #else
2107 micro_pow( &r[0], &mach->Temps[TEMP_2_I].xyzw[TEMP_2_C], &r[0] );
2108 #endif
2109
2110 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2111 STORE( &r[0], 0, chan_index );
2112 }
2113 break;
2114
2115 case TGSI_OPCODE_LOGBASE2:
2116 /* TGSI_OPCODE_LG2 */
2117 FETCH( &r[0], 0, CHAN_X );
2118 micro_lg2( &r[0], &r[0] );
2119 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2120 STORE( &r[0], 0, chan_index );
2121 }
2122 break;
2123
2124 case TGSI_OPCODE_POWER:
2125 /* TGSI_OPCODE_POW */
2126 FETCH(&r[0], 0, CHAN_X);
2127 FETCH(&r[1], 1, CHAN_X);
2128
2129 micro_pow( &r[0], &r[0], &r[1] );
2130
2131 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2132 STORE( &r[0], 0, chan_index );
2133 }
2134 break;
2135
2136 case TGSI_OPCODE_CROSSPRODUCT:
2137 /* TGSI_OPCODE_XPD */
2138 FETCH(&r[0], 0, CHAN_Y);
2139 FETCH(&r[1], 1, CHAN_Z);
2140
2141 micro_mul( &r[2], &r[0], &r[1] );
2142
2143 FETCH(&r[3], 0, CHAN_Z);
2144 FETCH(&r[4], 1, CHAN_Y);
2145
2146 micro_mul( &r[5], &r[3], &r[4] );
2147 micro_sub( &r[2], &r[2], &r[5] );
2148
2149 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2150 STORE( &r[2], 0, CHAN_X );
2151 }
2152
2153 FETCH(&r[2], 1, CHAN_X);
2154
2155 micro_mul( &r[3], &r[3], &r[2] );
2156
2157 FETCH(&r[5], 0, CHAN_X);
2158
2159 micro_mul( &r[1], &r[1], &r[5] );
2160 micro_sub( &r[3], &r[3], &r[1] );
2161
2162 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2163 STORE( &r[3], 0, CHAN_Y );
2164 }
2165
2166 micro_mul( &r[5], &r[5], &r[4] );
2167 micro_mul( &r[0], &r[0], &r[2] );
2168 micro_sub( &r[5], &r[5], &r[0] );
2169
2170 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2171 STORE( &r[5], 0, CHAN_Z );
2172 }
2173
2174 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2175 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2176 }
2177 break;
2178
2179 case TGSI_OPCODE_MULTIPLYMATRIX:
2180 assert (0);
2181 break;
2182
2183 case TGSI_OPCODE_ABS:
2184 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2185 FETCH(&r[0], 0, chan_index);
2186
2187 micro_abs( &r[0], &r[0] );
2188
2189 STORE(&r[0], 0, chan_index);
2190 }
2191 break;
2192
2193 case TGSI_OPCODE_RCC:
2194 assert (0);
2195 break;
2196
2197 case TGSI_OPCODE_DPH:
2198 FETCH(&r[0], 0, CHAN_X);
2199 FETCH(&r[1], 1, CHAN_X);
2200
2201 micro_mul( &r[0], &r[0], &r[1] );
2202
2203 FETCH(&r[1], 0, CHAN_Y);
2204 FETCH(&r[2], 1, CHAN_Y);
2205
2206 micro_mul( &r[1], &r[1], &r[2] );
2207 micro_add( &r[0], &r[0], &r[1] );
2208
2209 FETCH(&r[1], 0, CHAN_Z);
2210 FETCH(&r[2], 1, CHAN_Z);
2211
2212 micro_mul( &r[1], &r[1], &r[2] );
2213 micro_add( &r[0], &r[0], &r[1] );
2214
2215 FETCH(&r[1], 1, CHAN_W);
2216
2217 micro_add( &r[0], &r[0], &r[1] );
2218
2219 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2220 STORE( &r[0], 0, chan_index );
2221 }
2222 break;
2223
2224 case TGSI_OPCODE_COS:
2225 FETCH(&r[0], 0, CHAN_X);
2226
2227 micro_cos( &r[0], &r[0] );
2228
2229 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2230 STORE( &r[0], 0, chan_index );
2231 }
2232 break;
2233
2234 case TGSI_OPCODE_DDX:
2235 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2236 FETCH( &r[0], 0, chan_index );
2237 micro_ddx( &r[0], &r[0] );
2238 STORE( &r[0], 0, chan_index );
2239 }
2240 break;
2241
2242 case TGSI_OPCODE_DDY:
2243 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2244 FETCH( &r[0], 0, chan_index );
2245 micro_ddy( &r[0], &r[0] );
2246 STORE( &r[0], 0, chan_index );
2247 }
2248 break;
2249
2250 case TGSI_OPCODE_KILP:
2251 exec_kilp (mach, inst);
2252 break;
2253
2254 case TGSI_OPCODE_KIL:
2255 exec_kil (mach, inst);
2256 break;
2257
2258 case TGSI_OPCODE_PK2H:
2259 assert (0);
2260 break;
2261
2262 case TGSI_OPCODE_PK2US:
2263 assert (0);
2264 break;
2265
2266 case TGSI_OPCODE_PK4B:
2267 assert (0);
2268 break;
2269
2270 case TGSI_OPCODE_PK4UB:
2271 assert (0);
2272 break;
2273
2274 case TGSI_OPCODE_RFL:
2275 assert (0);
2276 break;
2277
2278 case TGSI_OPCODE_SEQ:
2279 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2280 FETCH( &r[0], 0, chan_index );
2281 FETCH( &r[1], 1, chan_index );
2282 micro_eq( &r[0], &r[0], &r[1],
2283 &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C],
2284 &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2285 STORE( &r[0], 0, chan_index );
2286 }
2287 break;
2288
2289 case TGSI_OPCODE_SFL:
2290 assert (0);
2291 break;
2292
2293 case TGSI_OPCODE_SGT:
2294 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2295 FETCH( &r[0], 0, chan_index );
2296 FETCH( &r[1], 1, chan_index );
2297 micro_le( &r[0], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C] );
2298 STORE( &r[0], 0, chan_index );
2299 }
2300 break;
2301
2302 case TGSI_OPCODE_SIN:
2303 FETCH( &r[0], 0, CHAN_X );
2304 micro_sin( &r[0], &r[0] );
2305 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2306 STORE( &r[0], 0, chan_index );
2307 }
2308 break;
2309
2310 case TGSI_OPCODE_SLE:
2311 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2312 FETCH( &r[0], 0, chan_index );
2313 FETCH( &r[1], 1, chan_index );
2314 micro_le( &r[0], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2315 STORE( &r[0], 0, chan_index );
2316 }
2317 break;
2318
2319 case TGSI_OPCODE_SNE:
2320 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2321 FETCH( &r[0], 0, chan_index );
2322 FETCH( &r[1], 1, chan_index );
2323 micro_eq( &r[0], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C] );
2324 STORE( &r[0], 0, chan_index );
2325 }
2326 break;
2327
2328 case TGSI_OPCODE_STR:
2329 assert (0);
2330 break;
2331
2332 case TGSI_OPCODE_TEX:
2333 /* simple texture lookup */
2334 /* src[0] = texcoord */
2335 /* src[1] = sampler unit */
2336 exec_tex(mach, inst, FALSE, FALSE);
2337 break;
2338
2339 case TGSI_OPCODE_TXB:
2340 /* Texture lookup with lod bias */
2341 /* src[0] = texcoord (src[0].w = LOD bias) */
2342 /* src[1] = sampler unit */
2343 exec_tex(mach, inst, TRUE, FALSE);
2344 break;
2345
2346 case TGSI_OPCODE_TXD:
2347 /* Texture lookup with explict partial derivatives */
2348 /* src[0] = texcoord */
2349 /* src[1] = d[strq]/dx */
2350 /* src[2] = d[strq]/dy */
2351 /* src[3] = sampler unit */
2352 assert (0);
2353 break;
2354
2355 case TGSI_OPCODE_TXL:
2356 /* Texture lookup with explit LOD */
2357 /* src[0] = texcoord (src[0].w = LOD) */
2358 /* src[1] = sampler unit */
2359 exec_tex(mach, inst, TRUE, FALSE);
2360 break;
2361
2362 case TGSI_OPCODE_TXP:
2363 /* Texture lookup with projection */
2364 /* src[0] = texcoord (src[0].w = projection) */
2365 /* src[1] = sampler unit */
2366 exec_tex(mach, inst, FALSE, TRUE);
2367 break;
2368
2369 case TGSI_OPCODE_UP2H:
2370 assert (0);
2371 break;
2372
2373 case TGSI_OPCODE_UP2US:
2374 assert (0);
2375 break;
2376
2377 case TGSI_OPCODE_UP4B:
2378 assert (0);
2379 break;
2380
2381 case TGSI_OPCODE_UP4UB:
2382 assert (0);
2383 break;
2384
2385 case TGSI_OPCODE_X2D:
2386 assert (0);
2387 break;
2388
2389 case TGSI_OPCODE_ARA:
2390 assert (0);
2391 break;
2392
2393 case TGSI_OPCODE_BRA:
2394 assert (0);
2395 break;
2396
2397 case TGSI_OPCODE_CAL:
2398 /* skip the call if no execution channels are enabled */
2399 if (mach->ExecMask) {
2400 /* do the call */
2401
2402 /* push the Cond, Loop, Cont stacks */
2403 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
2404 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
2405 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2406 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
2407 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2408 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
2409
2410 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
2411 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
2412
2413 /* note that PC was already incremented above */
2414 mach->CallStack[mach->CallStackTop++] = *pc;
2415 *pc = inst->InstructionExtLabel.Label;
2416 }
2417 break;
2418
2419 case TGSI_OPCODE_RET:
2420 mach->FuncMask &= ~mach->ExecMask;
2421 UPDATE_EXEC_MASK(mach);
2422
2423 if (mach->FuncMask == 0x0) {
2424 /* really return now (otherwise, keep executing */
2425
2426 if (mach->CallStackTop == 0) {
2427 /* returning from main() */
2428 *pc = -1;
2429 return;
2430 }
2431 *pc = mach->CallStack[--mach->CallStackTop];
2432
2433 /* pop the Cond, Loop, Cont stacks */
2434 assert(mach->CondStackTop > 0);
2435 mach->CondMask = mach->CondStack[--mach->CondStackTop];
2436 assert(mach->LoopStackTop > 0);
2437 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
2438 assert(mach->ContStackTop > 0);
2439 mach->ContMask = mach->ContStack[--mach->ContStackTop];
2440 assert(mach->FuncStackTop > 0);
2441 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
2442
2443 UPDATE_EXEC_MASK(mach);
2444 }
2445 break;
2446
2447 case TGSI_OPCODE_SSG:
2448 /* TGSI_OPCODE_SGN */
2449 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2450 FETCH( &r[0], 0, chan_index );
2451 micro_sgn( &r[0], &r[0] );
2452 STORE( &r[0], 0, chan_index );
2453 }
2454 break;
2455
2456 case TGSI_OPCODE_CMP:
2457 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2458 FETCH(&r[0], 0, chan_index);
2459 FETCH(&r[1], 1, chan_index);
2460 FETCH(&r[2], 2, chan_index);
2461
2462 micro_lt( &r[0], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[1], &r[2] );
2463
2464 STORE(&r[0], 0, chan_index);
2465 }
2466 break;
2467
2468 case TGSI_OPCODE_SCS:
2469 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
2470 FETCH( &r[0], 0, CHAN_X );
2471 }
2472 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) ) {
2473 micro_cos( &r[1], &r[0] );
2474 STORE( &r[1], 0, CHAN_X );
2475 }
2476 if( IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
2477 micro_sin( &r[1], &r[0] );
2478 STORE( &r[1], 0, CHAN_Y );
2479 }
2480 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
2481 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
2482 }
2483 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
2484 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2485 }
2486 break;
2487
2488 case TGSI_OPCODE_NRM:
2489 /* 3-component vector normalize */
2490 {
2491 union tgsi_exec_channel tmp, dot;
2492
2493 /* tmp = dp3(src0, src0): */
2494 FETCH( &r[0], 0, CHAN_X );
2495 micro_mul( &tmp, &r[0], &r[0] );
2496
2497 FETCH( &r[1], 0, CHAN_Y );
2498 micro_mul( &dot, &r[1], &r[1] );
2499 micro_add( &tmp, &tmp, &dot );
2500
2501 FETCH( &r[2], 0, CHAN_Z );
2502 micro_mul( &dot, &r[2], &r[2] );
2503 micro_add( &tmp, &tmp, &dot );
2504
2505 /* tmp = 1 / sqrt(tmp) */
2506 micro_sqrt( &tmp, &tmp );
2507 micro_div( &tmp, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &tmp );
2508
2509 /* note: w channel is undefined */
2510 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2511 /* chan = chan * tmp */
2512 micro_mul( &r[chan_index], &tmp, &r[chan_index] );
2513 STORE( &r[chan_index], 0, chan_index );
2514 }
2515 }
2516 break;
2517
2518 case TGSI_OPCODE_NRM4:
2519 /* 4-component vector normalize */
2520 {
2521 union tgsi_exec_channel tmp, dot;
2522
2523 /* tmp = dp4(src0, src0): */
2524 FETCH( &r[0], 0, CHAN_X );
2525 micro_mul( &tmp, &r[0], &r[0] );
2526
2527 FETCH( &r[1], 0, CHAN_Y );
2528 micro_mul( &dot, &r[1], &r[1] );
2529 micro_add( &tmp, &tmp, &dot );
2530
2531 FETCH( &r[2], 0, CHAN_Z );
2532 micro_mul( &dot, &r[2], &r[2] );
2533 micro_add( &tmp, &tmp, &dot );
2534
2535 FETCH( &r[3], 0, CHAN_W );
2536 micro_mul( &dot, &r[3], &r[3] );
2537 micro_add( &tmp, &tmp, &dot );
2538
2539 /* tmp = 1 / sqrt(tmp) */
2540 micro_sqrt( &tmp, &tmp );
2541 micro_div( &tmp, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &tmp );
2542
2543 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2544 /* chan = chan * tmp */
2545 micro_mul( &r[chan_index], &tmp, &r[chan_index] );
2546 STORE( &r[chan_index], 0, chan_index );
2547 }
2548 }
2549 break;
2550
2551 case TGSI_OPCODE_DIV:
2552 assert( 0 );
2553 break;
2554
2555 case TGSI_OPCODE_DP2:
2556 FETCH( &r[0], 0, CHAN_X );
2557 FETCH( &r[1], 1, CHAN_X );
2558 micro_mul( &r[0], &r[0], &r[1] );
2559
2560 FETCH( &r[1], 0, CHAN_Y );
2561 FETCH( &r[2], 1, CHAN_Y );
2562 micro_mul( &r[1], &r[1], &r[2] );
2563 micro_add( &r[0], &r[0], &r[1] );
2564
2565 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2566 STORE( &r[0], 0, chan_index );
2567 }
2568 break;
2569
2570 case TGSI_OPCODE_IF:
2571 /* push CondMask */
2572 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
2573 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
2574 FETCH( &r[0], 0, CHAN_X );
2575 /* update CondMask */
2576 if( ! r[0].u[0] ) {
2577 mach->CondMask &= ~0x1;
2578 }
2579 if( ! r[0].u[1] ) {
2580 mach->CondMask &= ~0x2;
2581 }
2582 if( ! r[0].u[2] ) {
2583 mach->CondMask &= ~0x4;
2584 }
2585 if( ! r[0].u[3] ) {
2586 mach->CondMask &= ~0x8;
2587 }
2588 UPDATE_EXEC_MASK(mach);
2589 /* Todo: If CondMask==0, jump to ELSE */
2590 break;
2591
2592 case TGSI_OPCODE_ELSE:
2593 /* invert CondMask wrt previous mask */
2594 {
2595 uint prevMask;
2596 assert(mach->CondStackTop > 0);
2597 prevMask = mach->CondStack[mach->CondStackTop - 1];
2598 mach->CondMask = ~mach->CondMask & prevMask;
2599 UPDATE_EXEC_MASK(mach);
2600 /* Todo: If CondMask==0, jump to ENDIF */
2601 }
2602 break;
2603
2604 case TGSI_OPCODE_ENDIF:
2605 /* pop CondMask */
2606 assert(mach->CondStackTop > 0);
2607 mach->CondMask = mach->CondStack[--mach->CondStackTop];
2608 UPDATE_EXEC_MASK(mach);
2609 break;
2610
2611 case TGSI_OPCODE_END:
2612 /* halt execution */
2613 *pc = -1;
2614 break;
2615
2616 case TGSI_OPCODE_REP:
2617 assert (0);
2618 break;
2619
2620 case TGSI_OPCODE_ENDREP:
2621 assert (0);
2622 break;
2623
2624 case TGSI_OPCODE_PUSHA:
2625 assert (0);
2626 break;
2627
2628 case TGSI_OPCODE_POPA:
2629 assert (0);
2630 break;
2631
2632 case TGSI_OPCODE_CEIL:
2633 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2634 FETCH( &r[0], 0, chan_index );
2635 micro_ceil( &r[0], &r[0] );
2636 STORE( &r[0], 0, chan_index );
2637 }
2638 break;
2639
2640 case TGSI_OPCODE_I2F:
2641 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2642 FETCH( &r[0], 0, chan_index );
2643 micro_i2f( &r[0], &r[0] );
2644 STORE( &r[0], 0, chan_index );
2645 }
2646 break;
2647
2648 case TGSI_OPCODE_NOT:
2649 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2650 FETCH( &r[0], 0, chan_index );
2651 micro_not( &r[0], &r[0] );
2652 STORE( &r[0], 0, chan_index );
2653 }
2654 break;
2655
2656 case TGSI_OPCODE_TRUNC:
2657 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2658 FETCH( &r[0], 0, chan_index );
2659 micro_trunc( &r[0], &r[0] );
2660 STORE( &r[0], 0, chan_index );
2661 }
2662 break;
2663
2664 case TGSI_OPCODE_SHL:
2665 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2666 FETCH( &r[0], 0, chan_index );
2667 FETCH( &r[1], 1, chan_index );
2668 micro_shl( &r[0], &r[0], &r[1] );
2669 STORE( &r[0], 0, chan_index );
2670 }
2671 break;
2672
2673 case TGSI_OPCODE_SHR:
2674 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2675 FETCH( &r[0], 0, chan_index );
2676 FETCH( &r[1], 1, chan_index );
2677 micro_ishr( &r[0], &r[0], &r[1] );
2678 STORE( &r[0], 0, chan_index );
2679 }
2680 break;
2681
2682 case TGSI_OPCODE_AND:
2683 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2684 FETCH( &r[0], 0, chan_index );
2685 FETCH( &r[1], 1, chan_index );
2686 micro_and( &r[0], &r[0], &r[1] );
2687 STORE( &r[0], 0, chan_index );
2688 }
2689 break;
2690
2691 case TGSI_OPCODE_OR:
2692 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2693 FETCH( &r[0], 0, chan_index );
2694 FETCH( &r[1], 1, chan_index );
2695 micro_or( &r[0], &r[0], &r[1] );
2696 STORE( &r[0], 0, chan_index );
2697 }
2698 break;
2699
2700 case TGSI_OPCODE_MOD:
2701 assert (0);
2702 break;
2703
2704 case TGSI_OPCODE_XOR:
2705 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2706 FETCH( &r[0], 0, chan_index );
2707 FETCH( &r[1], 1, chan_index );
2708 micro_xor( &r[0], &r[0], &r[1] );
2709 STORE( &r[0], 0, chan_index );
2710 }
2711 break;
2712
2713 case TGSI_OPCODE_SAD:
2714 assert (0);
2715 break;
2716
2717 case TGSI_OPCODE_TXF:
2718 assert (0);
2719 break;
2720
2721 case TGSI_OPCODE_TXQ:
2722 assert (0);
2723 break;
2724
2725 case TGSI_OPCODE_EMIT:
2726 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += 16;
2727 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
2728 break;
2729
2730 case TGSI_OPCODE_ENDPRIM:
2731 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]++;
2732 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] = 0;
2733 break;
2734
2735 case TGSI_OPCODE_LOOP:
2736 /* fall-through (for now) */
2737 case TGSI_OPCODE_BGNLOOP2:
2738 /* push LoopMask and ContMasks */
2739 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2740 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
2741 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2742 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
2743 break;
2744
2745 case TGSI_OPCODE_ENDLOOP:
2746 /* fall-through (for now at least) */
2747 case TGSI_OPCODE_ENDLOOP2:
2748 /* Restore ContMask, but don't pop */
2749 assert(mach->ContStackTop > 0);
2750 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
2751 UPDATE_EXEC_MASK(mach);
2752 if (mach->ExecMask) {
2753 /* repeat loop: jump to instruction just past BGNLOOP */
2754 *pc = inst->InstructionExtLabel.Label + 1;
2755 }
2756 else {
2757 /* exit loop: pop LoopMask */
2758 assert(mach->LoopStackTop > 0);
2759 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
2760 /* pop ContMask */
2761 assert(mach->ContStackTop > 0);
2762 mach->ContMask = mach->ContStack[--mach->ContStackTop];
2763 }
2764 UPDATE_EXEC_MASK(mach);
2765 break;
2766
2767 case TGSI_OPCODE_BRK:
2768 /* turn off loop channels for each enabled exec channel */
2769 mach->LoopMask &= ~mach->ExecMask;
2770 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2771 UPDATE_EXEC_MASK(mach);
2772 break;
2773
2774 case TGSI_OPCODE_CONT:
2775 /* turn off cont channels for each enabled exec channel */
2776 mach->ContMask &= ~mach->ExecMask;
2777 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2778 UPDATE_EXEC_MASK(mach);
2779 break;
2780
2781 case TGSI_OPCODE_BGNSUB:
2782 /* no-op */
2783 break;
2784
2785 case TGSI_OPCODE_ENDSUB:
2786 /* no-op */
2787 break;
2788
2789 case TGSI_OPCODE_NOISE1:
2790 assert( 0 );
2791 break;
2792
2793 case TGSI_OPCODE_NOISE2:
2794 assert( 0 );
2795 break;
2796
2797 case TGSI_OPCODE_NOISE3:
2798 assert( 0 );
2799 break;
2800
2801 case TGSI_OPCODE_NOISE4:
2802 assert( 0 );
2803 break;
2804
2805 case TGSI_OPCODE_NOP:
2806 break;
2807
2808 default:
2809 assert( 0 );
2810 }
2811 }
2812
2813
2814 /**
2815 * Run TGSI interpreter.
2816 * \return bitmask of "alive" quad components
2817 */
2818 uint
2819 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
2820 {
2821 uint i;
2822 int pc = 0;
2823
2824 mach->CondMask = 0xf;
2825 mach->LoopMask = 0xf;
2826 mach->ContMask = 0xf;
2827 mach->FuncMask = 0xf;
2828 mach->ExecMask = 0xf;
2829
2830 mach->CondStackTop = 0; /* temporarily subvert this assertion */
2831 assert(mach->CondStackTop == 0);
2832 assert(mach->LoopStackTop == 0);
2833 assert(mach->ContStackTop == 0);
2834 assert(mach->CallStackTop == 0);
2835
2836 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
2837 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
2838
2839 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
2840 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
2841 mach->Primitives[0] = 0;
2842 }
2843
2844 for (i = 0; i < QUAD_SIZE; i++) {
2845 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
2846 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
2847 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
2848 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
2849 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
2850 }
2851
2852 /* execute declarations (interpolants) */
2853 for (i = 0; i < mach->NumDeclarations; i++) {
2854 exec_declaration( mach, mach->Declarations+i );
2855 }
2856
2857 /* execute instructions, until pc is set to -1 */
2858 while (pc != -1) {
2859 assert(pc < (int) mach->NumInstructions);
2860 exec_instruction( mach, mach->Instructions + pc, &pc );
2861 }
2862
2863 #if 0
2864 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
2865 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2866 /*
2867 * Scale back depth component.
2868 */
2869 for (i = 0; i < 4; i++)
2870 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
2871 }
2872 #endif
2873
2874 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
2875 }
2876
2877