1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_cmp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
142 micro_cos(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src
)
145 dst
->f
[0] = cosf(src
->f
[0]);
146 dst
->f
[1] = cosf(src
->f
[1]);
147 dst
->f
[2] = cosf(src
->f
[2]);
148 dst
->f
[3] = cosf(src
->f
[3]);
152 micro_d2f(union tgsi_exec_channel
*dst
,
153 const union tgsi_double_channel
*src
)
155 dst
->f
[0] = (float)src
->d
[0];
156 dst
->f
[1] = (float)src
->d
[1];
157 dst
->f
[2] = (float)src
->d
[2];
158 dst
->f
[3] = (float)src
->d
[3];
162 micro_d2i(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->i
[0] = (int)src
->d
[0];
166 dst
->i
[1] = (int)src
->d
[1];
167 dst
->i
[2] = (int)src
->d
[2];
168 dst
->i
[3] = (int)src
->d
[3];
172 micro_d2u(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->u
[0] = (unsigned)src
->d
[0];
176 dst
->u
[1] = (unsigned)src
->d
[1];
177 dst
->u
[2] = (unsigned)src
->d
[2];
178 dst
->u
[3] = (unsigned)src
->d
[3];
181 micro_dabs(union tgsi_double_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
185 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
186 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
187 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
191 micro_dadd(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
195 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
196 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
197 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
201 micro_ddiv(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] / src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] / src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] / src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] / src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddx_fine(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
225 dst
->f
[1] = src
->f
[TILE_TOP_RIGHT
] - src
->f
[TILE_TOP_LEFT
];
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
232 micro_ddy(union tgsi_exec_channel
*dst
,
233 const union tgsi_exec_channel
*src
)
238 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
242 micro_ddy_fine(union tgsi_exec_channel
*dst
,
243 const union tgsi_exec_channel
*src
)
246 dst
->f
[2] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
248 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_TOP_RIGHT
];
252 micro_dmul(union tgsi_double_channel
*dst
,
253 const union tgsi_double_channel
*src
)
255 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
256 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
257 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
258 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
262 micro_dmax(union tgsi_double_channel
*dst
,
263 const union tgsi_double_channel
*src
)
265 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
266 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
267 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
268 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
272 micro_dmin(union tgsi_double_channel
*dst
,
273 const union tgsi_double_channel
*src
)
275 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
276 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
277 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
278 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
282 micro_dneg(union tgsi_double_channel
*dst
,
283 const union tgsi_double_channel
*src
)
285 dst
->d
[0] = -src
->d
[0];
286 dst
->d
[1] = -src
->d
[1];
287 dst
->d
[2] = -src
->d
[2];
288 dst
->d
[3] = -src
->d
[3];
292 micro_dslt(union tgsi_double_channel
*dst
,
293 const union tgsi_double_channel
*src
)
295 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
296 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
297 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
298 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
302 micro_dsne(union tgsi_double_channel
*dst
,
303 const union tgsi_double_channel
*src
)
305 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
306 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
307 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
308 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
312 micro_dsge(union tgsi_double_channel
*dst
,
313 const union tgsi_double_channel
*src
)
315 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
316 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
317 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
318 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
322 micro_dseq(union tgsi_double_channel
*dst
,
323 const union tgsi_double_channel
*src
)
325 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
326 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
327 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
328 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
332 micro_drcp(union tgsi_double_channel
*dst
,
333 const union tgsi_double_channel
*src
)
335 dst
->d
[0] = 1.0 / src
->d
[0];
336 dst
->d
[1] = 1.0 / src
->d
[1];
337 dst
->d
[2] = 1.0 / src
->d
[2];
338 dst
->d
[3] = 1.0 / src
->d
[3];
342 micro_dsqrt(union tgsi_double_channel
*dst
,
343 const union tgsi_double_channel
*src
)
345 dst
->d
[0] = sqrt(src
->d
[0]);
346 dst
->d
[1] = sqrt(src
->d
[1]);
347 dst
->d
[2] = sqrt(src
->d
[2]);
348 dst
->d
[3] = sqrt(src
->d
[3]);
352 micro_drsq(union tgsi_double_channel
*dst
,
353 const union tgsi_double_channel
*src
)
355 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
356 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
357 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
358 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
362 micro_dmad(union tgsi_double_channel
*dst
,
363 const union tgsi_double_channel
*src
)
365 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
366 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
367 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
368 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
372 micro_dfrac(union tgsi_double_channel
*dst
,
373 const union tgsi_double_channel
*src
)
375 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
376 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
377 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
378 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
382 micro_dldexp(union tgsi_double_channel
*dst
,
383 const union tgsi_double_channel
*src0
,
384 union tgsi_exec_channel
*src1
)
386 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
387 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
388 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
389 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
393 micro_dfracexp(union tgsi_double_channel
*dst
,
394 union tgsi_exec_channel
*dst_exp
,
395 const union tgsi_double_channel
*src
)
397 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
398 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
399 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
400 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
404 micro_exp2(union tgsi_exec_channel
*dst
,
405 const union tgsi_exec_channel
*src
)
408 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
409 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
410 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
411 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
414 /* Inf is okay for this instruction, so clamp it to silence assertions. */
416 union tgsi_exec_channel clamped
;
418 for (i
= 0; i
< 4; i
++) {
419 if (src
->f
[i
] > 127.99999f
) {
420 clamped
.f
[i
] = 127.99999f
;
421 } else if (src
->f
[i
] < -126.99999f
) {
422 clamped
.f
[i
] = -126.99999f
;
424 clamped
.f
[i
] = src
->f
[i
];
430 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
431 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
432 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
433 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
434 #endif /* FAST_MATH */
438 micro_f2d(union tgsi_double_channel
*dst
,
439 const union tgsi_exec_channel
*src
)
441 dst
->d
[0] = (double)src
->f
[0];
442 dst
->d
[1] = (double)src
->f
[1];
443 dst
->d
[2] = (double)src
->f
[2];
444 dst
->d
[3] = (double)src
->f
[3];
448 micro_flr(union tgsi_exec_channel
*dst
,
449 const union tgsi_exec_channel
*src
)
451 dst
->f
[0] = floorf(src
->f
[0]);
452 dst
->f
[1] = floorf(src
->f
[1]);
453 dst
->f
[2] = floorf(src
->f
[2]);
454 dst
->f
[3] = floorf(src
->f
[3]);
458 micro_frc(union tgsi_exec_channel
*dst
,
459 const union tgsi_exec_channel
*src
)
461 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
462 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
463 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
464 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
468 micro_i2d(union tgsi_double_channel
*dst
,
469 const union tgsi_exec_channel
*src
)
471 dst
->d
[0] = (double)src
->i
[0];
472 dst
->d
[1] = (double)src
->i
[1];
473 dst
->d
[2] = (double)src
->i
[2];
474 dst
->d
[3] = (double)src
->i
[3];
478 micro_iabs(union tgsi_exec_channel
*dst
,
479 const union tgsi_exec_channel
*src
)
481 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
482 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
483 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
484 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
488 micro_ineg(union tgsi_exec_channel
*dst
,
489 const union tgsi_exec_channel
*src
)
491 dst
->i
[0] = -src
->i
[0];
492 dst
->i
[1] = -src
->i
[1];
493 dst
->i
[2] = -src
->i
[2];
494 dst
->i
[3] = -src
->i
[3];
498 micro_lg2(union tgsi_exec_channel
*dst
,
499 const union tgsi_exec_channel
*src
)
502 dst
->f
[0] = util_fast_log2(src
->f
[0]);
503 dst
->f
[1] = util_fast_log2(src
->f
[1]);
504 dst
->f
[2] = util_fast_log2(src
->f
[2]);
505 dst
->f
[3] = util_fast_log2(src
->f
[3]);
507 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
508 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
509 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
510 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
515 micro_lrp(union tgsi_exec_channel
*dst
,
516 const union tgsi_exec_channel
*src0
,
517 const union tgsi_exec_channel
*src1
,
518 const union tgsi_exec_channel
*src2
)
520 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
521 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
522 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
523 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
527 micro_mad(union tgsi_exec_channel
*dst
,
528 const union tgsi_exec_channel
*src0
,
529 const union tgsi_exec_channel
*src1
,
530 const union tgsi_exec_channel
*src2
)
532 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
533 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
534 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
535 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
539 micro_mov(union tgsi_exec_channel
*dst
,
540 const union tgsi_exec_channel
*src
)
542 dst
->u
[0] = src
->u
[0];
543 dst
->u
[1] = src
->u
[1];
544 dst
->u
[2] = src
->u
[2];
545 dst
->u
[3] = src
->u
[3];
549 micro_rcp(union tgsi_exec_channel
*dst
,
550 const union tgsi_exec_channel
*src
)
552 #if 0 /* for debugging */
553 assert(src
->f
[0] != 0.0f
);
554 assert(src
->f
[1] != 0.0f
);
555 assert(src
->f
[2] != 0.0f
);
556 assert(src
->f
[3] != 0.0f
);
558 dst
->f
[0] = 1.0f
/ src
->f
[0];
559 dst
->f
[1] = 1.0f
/ src
->f
[1];
560 dst
->f
[2] = 1.0f
/ src
->f
[2];
561 dst
->f
[3] = 1.0f
/ src
->f
[3];
565 micro_rnd(union tgsi_exec_channel
*dst
,
566 const union tgsi_exec_channel
*src
)
568 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
569 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
570 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
571 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
575 micro_rsq(union tgsi_exec_channel
*dst
,
576 const union tgsi_exec_channel
*src
)
578 #if 0 /* for debugging */
579 assert(src
->f
[0] != 0.0f
);
580 assert(src
->f
[1] != 0.0f
);
581 assert(src
->f
[2] != 0.0f
);
582 assert(src
->f
[3] != 0.0f
);
584 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
585 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
586 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
587 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
591 micro_sqrt(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src
)
594 dst
->f
[0] = sqrtf(src
->f
[0]);
595 dst
->f
[1] = sqrtf(src
->f
[1]);
596 dst
->f
[2] = sqrtf(src
->f
[2]);
597 dst
->f
[3] = sqrtf(src
->f
[3]);
601 micro_seq(union tgsi_exec_channel
*dst
,
602 const union tgsi_exec_channel
*src0
,
603 const union tgsi_exec_channel
*src1
)
605 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
606 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
607 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
608 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
612 micro_sge(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src0
,
614 const union tgsi_exec_channel
*src1
)
616 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
617 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
618 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
619 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
623 micro_sgn(union tgsi_exec_channel
*dst
,
624 const union tgsi_exec_channel
*src
)
626 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
627 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
628 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
629 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
633 micro_isgn(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
637 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
638 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
639 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
643 micro_sgt(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_sin(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src
)
657 dst
->f
[0] = sinf(src
->f
[0]);
658 dst
->f
[1] = sinf(src
->f
[1]);
659 dst
->f
[2] = sinf(src
->f
[2]);
660 dst
->f
[3] = sinf(src
->f
[3]);
664 micro_sle(union tgsi_exec_channel
*dst
,
665 const union tgsi_exec_channel
*src0
,
666 const union tgsi_exec_channel
*src1
)
668 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
669 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
670 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
671 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
675 micro_slt(union tgsi_exec_channel
*dst
,
676 const union tgsi_exec_channel
*src0
,
677 const union tgsi_exec_channel
*src1
)
679 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
680 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
681 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
682 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
686 micro_sne(union tgsi_exec_channel
*dst
,
687 const union tgsi_exec_channel
*src0
,
688 const union tgsi_exec_channel
*src1
)
690 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
691 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
692 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
693 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
697 micro_trunc(union tgsi_exec_channel
*dst
,
698 const union tgsi_exec_channel
*src
)
700 dst
->f
[0] = truncf(src
->f
[0]);
701 dst
->f
[1] = truncf(src
->f
[1]);
702 dst
->f
[2] = truncf(src
->f
[2]);
703 dst
->f
[3] = truncf(src
->f
[3]);
707 micro_u2d(union tgsi_double_channel
*dst
,
708 const union tgsi_exec_channel
*src
)
710 dst
->d
[0] = (double)src
->u
[0];
711 dst
->d
[1] = (double)src
->u
[1];
712 dst
->d
[2] = (double)src
->u
[2];
713 dst
->d
[3] = (double)src
->u
[3];
717 micro_i64abs(union tgsi_double_channel
*dst
,
718 const union tgsi_double_channel
*src
)
720 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
721 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
722 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
723 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
727 micro_i64sgn(union tgsi_double_channel
*dst
,
728 const union tgsi_double_channel
*src
)
730 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
731 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
732 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
733 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
737 micro_i64neg(union tgsi_double_channel
*dst
,
738 const union tgsi_double_channel
*src
)
740 dst
->i64
[0] = -src
->i64
[0];
741 dst
->i64
[1] = -src
->i64
[1];
742 dst
->i64
[2] = -src
->i64
[2];
743 dst
->i64
[3] = -src
->i64
[3];
747 micro_u64seq(union tgsi_double_channel
*dst
,
748 const union tgsi_double_channel
*src
)
750 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
751 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
752 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
753 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
757 micro_u64sne(union tgsi_double_channel
*dst
,
758 const union tgsi_double_channel
*src
)
760 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
761 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
762 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
763 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
767 micro_i64slt(union tgsi_double_channel
*dst
,
768 const union tgsi_double_channel
*src
)
770 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
771 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
772 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
773 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
777 micro_u64slt(union tgsi_double_channel
*dst
,
778 const union tgsi_double_channel
*src
)
780 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
781 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
782 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
783 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
787 micro_i64sge(union tgsi_double_channel
*dst
,
788 const union tgsi_double_channel
*src
)
790 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
791 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
792 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
793 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
797 micro_u64sge(union tgsi_double_channel
*dst
,
798 const union tgsi_double_channel
*src
)
800 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
801 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
802 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
803 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
807 micro_u64max(union tgsi_double_channel
*dst
,
808 const union tgsi_double_channel
*src
)
810 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
811 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
812 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
813 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
817 micro_i64max(union tgsi_double_channel
*dst
,
818 const union tgsi_double_channel
*src
)
820 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
821 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
822 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
823 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
827 micro_u64min(union tgsi_double_channel
*dst
,
828 const union tgsi_double_channel
*src
)
830 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
831 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
832 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
833 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
837 micro_i64min(union tgsi_double_channel
*dst
,
838 const union tgsi_double_channel
*src
)
840 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
841 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
842 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
843 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
847 micro_u64add(union tgsi_double_channel
*dst
,
848 const union tgsi_double_channel
*src
)
850 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
851 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
852 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
853 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
857 micro_u64mul(union tgsi_double_channel
*dst
,
858 const union tgsi_double_channel
*src
)
860 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
861 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
862 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
863 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
867 micro_u64div(union tgsi_double_channel
*dst
,
868 const union tgsi_double_channel
*src
)
870 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] / src
[1].u64
[0] : ~0ull;
871 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] / src
[1].u64
[1] : ~0ull;
872 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] / src
[1].u64
[2] : ~0ull;
873 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] / src
[1].u64
[3] : ~0ull;
877 micro_i64div(union tgsi_double_channel
*dst
,
878 const union tgsi_double_channel
*src
)
880 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] / src
[1].i64
[0] : 0;
881 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] / src
[1].i64
[1] : 0;
882 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] / src
[1].i64
[2] : 0;
883 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] / src
[1].i64
[3] : 0;
887 micro_u64mod(union tgsi_double_channel
*dst
,
888 const union tgsi_double_channel
*src
)
890 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] % src
[1].u64
[0] : ~0ull;
891 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] % src
[1].u64
[1] : ~0ull;
892 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] % src
[1].u64
[2] : ~0ull;
893 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] % src
[1].u64
[3] : ~0ull;
897 micro_i64mod(union tgsi_double_channel
*dst
,
898 const union tgsi_double_channel
*src
)
900 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] % src
[1].i64
[0] : ~0ll;
901 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] % src
[1].i64
[1] : ~0ll;
902 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] % src
[1].i64
[2] : ~0ll;
903 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] % src
[1].i64
[3] : ~0ll;
907 micro_u64shl(union tgsi_double_channel
*dst
,
908 const union tgsi_double_channel
*src0
,
909 union tgsi_exec_channel
*src1
)
911 unsigned masked_count
;
912 masked_count
= src1
->u
[0] & 0x3f;
913 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
914 masked_count
= src1
->u
[1] & 0x3f;
915 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
916 masked_count
= src1
->u
[2] & 0x3f;
917 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
918 masked_count
= src1
->u
[3] & 0x3f;
919 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
923 micro_i64shr(union tgsi_double_channel
*dst
,
924 const union tgsi_double_channel
*src0
,
925 union tgsi_exec_channel
*src1
)
927 unsigned masked_count
;
928 masked_count
= src1
->u
[0] & 0x3f;
929 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
930 masked_count
= src1
->u
[1] & 0x3f;
931 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
932 masked_count
= src1
->u
[2] & 0x3f;
933 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
934 masked_count
= src1
->u
[3] & 0x3f;
935 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
939 micro_u64shr(union tgsi_double_channel
*dst
,
940 const union tgsi_double_channel
*src0
,
941 union tgsi_exec_channel
*src1
)
943 unsigned masked_count
;
944 masked_count
= src1
->u
[0] & 0x3f;
945 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
946 masked_count
= src1
->u
[1] & 0x3f;
947 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
948 masked_count
= src1
->u
[2] & 0x3f;
949 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
950 masked_count
= src1
->u
[3] & 0x3f;
951 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
954 enum tgsi_exec_datatype
{
955 TGSI_EXEC_DATA_FLOAT
,
958 TGSI_EXEC_DATA_DOUBLE
,
959 TGSI_EXEC_DATA_INT64
,
960 TGSI_EXEC_DATA_UINT64
,
964 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
966 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
967 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
968 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
969 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
970 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
971 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
972 #define TEMP_PRIMITIVE_S1_I TGSI_EXEC_TEMP_PRIMITIVE_S1_I
973 #define TEMP_PRIMITIVE_S1_C TGSI_EXEC_TEMP_PRIMITIVE_S1_C
974 #define TEMP_PRIMITIVE_S2_I TGSI_EXEC_TEMP_PRIMITIVE_S2_I
975 #define TEMP_PRIMITIVE_S2_C TGSI_EXEC_TEMP_PRIMITIVE_S2_C
976 #define TEMP_PRIMITIVE_S3_I TGSI_EXEC_TEMP_PRIMITIVE_S3_I
977 #define TEMP_PRIMITIVE_S3_C TGSI_EXEC_TEMP_PRIMITIVE_S3_C
979 static const struct {
982 } temp_prim_idxs
[] = {
983 { TEMP_PRIMITIVE_I
, TEMP_PRIMITIVE_C
},
984 { TEMP_PRIMITIVE_S1_I
, TEMP_PRIMITIVE_S1_C
},
985 { TEMP_PRIMITIVE_S2_I
, TEMP_PRIMITIVE_S2_C
},
986 { TEMP_PRIMITIVE_S3_I
, TEMP_PRIMITIVE_S3_C
},
989 /** The execution mask depends on the conditional mask and the loop mask */
990 #define UPDATE_EXEC_MASK(MACH) \
991 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
994 static const union tgsi_exec_channel ZeroVec
=
995 { { 0.0, 0.0, 0.0, 0.0 } };
997 static const union tgsi_exec_channel OneVec
= {
998 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
1001 static const union tgsi_exec_channel P128Vec
= {
1002 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
1005 static const union tgsi_exec_channel M128Vec
= {
1006 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
1011 * Assert that none of the float values in 'chan' are infinite or NaN.
1012 * NaN and Inf may occur normally during program execution and should
1013 * not lead to crashes, etc. But when debugging, it's helpful to catch
1017 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
1019 assert(!util_is_inf_or_nan((chan
)->f
[0]));
1020 assert(!util_is_inf_or_nan((chan
)->f
[1]));
1021 assert(!util_is_inf_or_nan((chan
)->f
[2]));
1022 assert(!util_is_inf_or_nan((chan
)->f
[3]));
1028 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
1030 debug_printf("%s = {%f, %f, %f, %f}\n",
1031 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1038 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1040 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1042 debug_printf("Temp[%u] =\n", index
);
1043 for (i
= 0; i
< 4; i
++) {
1044 debug_printf(" %c: { %f, %f, %f, %f }\n",
1056 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1059 const unsigned *buf_sizes
)
1063 for (i
= 0; i
< num_bufs
; i
++) {
1064 mach
->Consts
[i
] = bufs
[i
];
1065 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1071 * Check if there's a potential src/dst register data dependency when
1072 * using SOA execution.
1075 * This would expand into:
1080 * The second instruction will have the wrong value for t0 if executed as-is.
1083 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
1087 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
1088 if (writemask
== TGSI_WRITEMASK_X
||
1089 writemask
== TGSI_WRITEMASK_Y
||
1090 writemask
== TGSI_WRITEMASK_Z
||
1091 writemask
== TGSI_WRITEMASK_W
||
1092 writemask
== TGSI_WRITEMASK_NONE
) {
1093 /* no chance of data dependency */
1097 /* loop over src regs */
1098 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1099 if ((inst
->Src
[i
].Register
.File
==
1100 inst
->Dst
[0].Register
.File
) &&
1101 ((inst
->Src
[i
].Register
.Index
==
1102 inst
->Dst
[0].Register
.Index
) ||
1103 inst
->Src
[i
].Register
.Indirect
||
1104 inst
->Dst
[0].Register
.Indirect
)) {
1105 /* loop over dest channels */
1106 uint channelsWritten
= 0x0;
1107 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1108 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1109 /* check if we're reading a channel that's been written */
1110 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
1111 if (channelsWritten
& (1 << swizzle
)) {
1115 channelsWritten
|= (1 << chan
);
1125 * Initialize machine state by expanding tokens to full instructions,
1126 * allocating temporary storage, setting up constants, etc.
1127 * After this, we can call tgsi_exec_machine_run() many times.
1130 tgsi_exec_machine_bind_shader(
1131 struct tgsi_exec_machine
*mach
,
1132 const struct tgsi_token
*tokens
,
1133 struct tgsi_sampler
*sampler
,
1134 struct tgsi_image
*image
,
1135 struct tgsi_buffer
*buffer
)
1138 struct tgsi_parse_context parse
;
1139 struct tgsi_full_instruction
*instructions
;
1140 struct tgsi_full_declaration
*declarations
;
1141 uint maxInstructions
= 10, numInstructions
= 0;
1142 uint maxDeclarations
= 10, numDeclarations
= 0;
1145 tgsi_dump(tokens
, 0);
1151 mach
->Tokens
= tokens
;
1152 mach
->Sampler
= sampler
;
1153 mach
->Image
= image
;
1154 mach
->Buffer
= buffer
;
1157 /* unbind and free all */
1158 FREE(mach
->Declarations
);
1159 mach
->Declarations
= NULL
;
1160 mach
->NumDeclarations
= 0;
1162 FREE(mach
->Instructions
);
1163 mach
->Instructions
= NULL
;
1164 mach
->NumInstructions
= 0;
1169 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1170 if (k
!= TGSI_PARSE_OK
) {
1171 debug_printf( "Problem parsing!\n" );
1176 mach
->NumOutputs
= 0;
1178 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1179 mach
->SysSemanticToIndex
[k
] = -1;
1181 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1182 !mach
->UsedGeometryShader
) {
1183 struct tgsi_exec_vector
*inputs
;
1184 struct tgsi_exec_vector
*outputs
;
1186 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1187 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1193 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1194 TGSI_MAX_TOTAL_VERTICES
, 16);
1201 align_free(mach
->Inputs
);
1202 align_free(mach
->Outputs
);
1204 mach
->Inputs
= inputs
;
1205 mach
->Outputs
= outputs
;
1206 mach
->UsedGeometryShader
= TRUE
;
1209 declarations
= (struct tgsi_full_declaration
*)
1210 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1212 if (!declarations
) {
1216 instructions
= (struct tgsi_full_instruction
*)
1217 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1219 if (!instructions
) {
1220 FREE( declarations
);
1224 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1227 tgsi_parse_token( &parse
);
1228 switch( parse
.FullToken
.Token
.Type
) {
1229 case TGSI_TOKEN_TYPE_DECLARATION
:
1230 /* save expanded declaration */
1231 if (numDeclarations
== maxDeclarations
) {
1232 declarations
= REALLOC(declarations
,
1234 * sizeof(struct tgsi_full_declaration
),
1235 (maxDeclarations
+ 10)
1236 * sizeof(struct tgsi_full_declaration
));
1237 maxDeclarations
+= 10;
1239 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1241 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1242 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1247 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1248 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1249 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1252 memcpy(declarations
+ numDeclarations
,
1253 &parse
.FullToken
.FullDeclaration
,
1254 sizeof(declarations
[0]));
1258 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1260 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1261 assert( size
<= 4 );
1262 if (mach
->ImmLimit
>= mach
->ImmsReserved
) {
1263 unsigned newReserved
= mach
->ImmsReserved
? 2 * mach
->ImmsReserved
: 128;
1264 float4
*imms
= REALLOC(mach
->Imms
, mach
->ImmsReserved
, newReserved
* sizeof(float4
));
1266 mach
->ImmsReserved
= newReserved
;
1269 debug_printf("Unable to (re)allocate space for immidiate constants\n");
1274 for( i
= 0; i
< size
; i
++ ) {
1275 mach
->Imms
[mach
->ImmLimit
][i
] =
1276 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1278 mach
->ImmLimit
+= 1;
1282 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1284 /* save expanded instruction */
1285 if (numInstructions
== maxInstructions
) {
1286 instructions
= REALLOC(instructions
,
1288 * sizeof(struct tgsi_full_instruction
),
1289 (maxInstructions
+ 10)
1290 * sizeof(struct tgsi_full_instruction
));
1291 maxInstructions
+= 10;
1294 memcpy(instructions
+ numInstructions
,
1295 &parse
.FullToken
.FullInstruction
,
1296 sizeof(instructions
[0]));
1301 case TGSI_TOKEN_TYPE_PROPERTY
:
1302 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1303 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1304 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1313 tgsi_parse_free (&parse
);
1315 FREE(mach
->Declarations
);
1316 mach
->Declarations
= declarations
;
1317 mach
->NumDeclarations
= numDeclarations
;
1319 FREE(mach
->Instructions
);
1320 mach
->Instructions
= instructions
;
1321 mach
->NumInstructions
= numInstructions
;
1325 struct tgsi_exec_machine
*
1326 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1328 struct tgsi_exec_machine
*mach
;
1331 mach
= align_malloc( sizeof *mach
, 16 );
1335 memset(mach
, 0, sizeof(*mach
));
1337 mach
->ShaderType
= shader_type
;
1338 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1339 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1341 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1342 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1343 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1344 if (!mach
->Inputs
|| !mach
->Outputs
)
1348 if (shader_type
== PIPE_SHADER_FRAGMENT
) {
1349 mach
->InputSampleOffsetApply
= align_malloc(sizeof(apply_sample_offset_func
) * PIPE_MAX_SHADER_INPUTS
, 16);
1350 if (!mach
->InputSampleOffsetApply
)
1355 /* silence warnings */
1364 align_free(mach
->InputSampleOffsetApply
);
1365 align_free(mach
->Inputs
);
1366 align_free(mach
->Outputs
);
1374 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1377 FREE(mach
->Instructions
);
1378 FREE(mach
->Declarations
);
1381 align_free(mach
->InputSampleOffsetApply
);
1382 align_free(mach
->Inputs
);
1383 align_free(mach
->Outputs
);
1390 micro_add(union tgsi_exec_channel
*dst
,
1391 const union tgsi_exec_channel
*src0
,
1392 const union tgsi_exec_channel
*src1
)
1394 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1395 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1396 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1397 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1402 union tgsi_exec_channel
*dst
,
1403 const union tgsi_exec_channel
*src0
,
1404 const union tgsi_exec_channel
*src1
)
1406 if (src1
->f
[0] != 0) {
1407 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1409 if (src1
->f
[1] != 0) {
1410 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1412 if (src1
->f
[2] != 0) {
1413 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1415 if (src1
->f
[3] != 0) {
1416 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1422 union tgsi_exec_channel
*dst
,
1423 const union tgsi_exec_channel
*src0
,
1424 const union tgsi_exec_channel
*src1
,
1425 const union tgsi_exec_channel
*src2
,
1426 const union tgsi_exec_channel
*src3
)
1428 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1429 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1430 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1431 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1435 micro_max(union tgsi_exec_channel
*dst
,
1436 const union tgsi_exec_channel
*src0
,
1437 const union tgsi_exec_channel
*src1
)
1439 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1440 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1441 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1442 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1446 micro_min(union tgsi_exec_channel
*dst
,
1447 const union tgsi_exec_channel
*src0
,
1448 const union tgsi_exec_channel
*src1
)
1450 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1451 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1452 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1453 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1457 micro_mul(union tgsi_exec_channel
*dst
,
1458 const union tgsi_exec_channel
*src0
,
1459 const union tgsi_exec_channel
*src1
)
1461 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1462 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1463 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1464 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1469 union tgsi_exec_channel
*dst
,
1470 const union tgsi_exec_channel
*src
)
1472 dst
->f
[0] = -src
->f
[0];
1473 dst
->f
[1] = -src
->f
[1];
1474 dst
->f
[2] = -src
->f
[2];
1475 dst
->f
[3] = -src
->f
[3];
1480 union tgsi_exec_channel
*dst
,
1481 const union tgsi_exec_channel
*src0
,
1482 const union tgsi_exec_channel
*src1
)
1485 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1486 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1487 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1488 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1490 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1491 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1492 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1493 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1498 micro_ldexp(union tgsi_exec_channel
*dst
,
1499 const union tgsi_exec_channel
*src0
,
1500 const union tgsi_exec_channel
*src1
)
1502 dst
->f
[0] = ldexpf(src0
->f
[0], src1
->i
[0]);
1503 dst
->f
[1] = ldexpf(src0
->f
[1], src1
->i
[1]);
1504 dst
->f
[2] = ldexpf(src0
->f
[2], src1
->i
[2]);
1505 dst
->f
[3] = ldexpf(src0
->f
[3], src1
->i
[3]);
1509 micro_sub(union tgsi_exec_channel
*dst
,
1510 const union tgsi_exec_channel
*src0
,
1511 const union tgsi_exec_channel
*src1
)
1513 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1514 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1515 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1516 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1520 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1523 const union tgsi_exec_channel
*index
,
1524 const union tgsi_exec_channel
*index2D
,
1525 union tgsi_exec_channel
*chan
)
1529 assert(swizzle
< 4);
1532 case TGSI_FILE_CONSTANT
:
1533 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1534 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1535 assert(mach
->Consts
[index2D
->i
[i
]]);
1537 if (index
->i
[i
] < 0) {
1540 /* NOTE: copying the const value as a uint instead of float */
1541 const uint constbuf
= index2D
->i
[i
];
1542 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1543 const int pos
= index
->i
[i
] * 4 + swizzle
;
1544 /* const buffer bounds check */
1545 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1547 /* Debug: print warning */
1548 static int count
= 0;
1550 debug_printf("TGSI Exec: const buffer index %d"
1551 " out of bounds\n", pos
);
1556 chan
->u
[i
] = buf
[pos
];
1561 case TGSI_FILE_INPUT
:
1562 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1564 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1565 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1566 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1567 index2D->i[i], index->i[i]);
1569 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1571 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1572 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1576 case TGSI_FILE_SYSTEM_VALUE
:
1577 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1578 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1582 case TGSI_FILE_TEMPORARY
:
1583 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1584 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1585 assert(index2D
->i
[i
] == 0);
1587 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1591 case TGSI_FILE_IMMEDIATE
:
1592 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1593 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1594 assert(index2D
->i
[i
] == 0);
1596 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1600 case TGSI_FILE_ADDRESS
:
1601 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1602 assert(index
->i
[i
] >= 0);
1603 assert(index2D
->i
[i
] == 0);
1605 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1609 case TGSI_FILE_OUTPUT
:
1610 /* vertex/fragment output vars can be read too */
1611 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1612 assert(index
->i
[i
] >= 0);
1613 assert(index2D
->i
[i
] == 0);
1615 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1621 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1628 get_index_registers(const struct tgsi_exec_machine
*mach
,
1629 const struct tgsi_full_src_register
*reg
,
1630 union tgsi_exec_channel
*index
,
1631 union tgsi_exec_channel
*index2D
)
1635 /* We start with a direct index into a register file.
1639 * file = Register.File
1640 * [1] = Register.Index
1645 index
->i
[3] = reg
->Register
.Index
;
1647 /* There is an extra source register that indirectly subscripts
1648 * a register file. The direct index now becomes an offset
1649 * that is being added to the indirect register.
1653 * ind = Indirect.File
1654 * [2] = Indirect.Index
1655 * .x = Indirect.SwizzleX
1657 if (reg
->Register
.Indirect
) {
1658 union tgsi_exec_channel index2
;
1659 union tgsi_exec_channel indir_index
;
1660 const uint execmask
= mach
->ExecMask
;
1663 /* which address register (always zero now) */
1667 index2
.i
[3] = reg
->Indirect
.Index
;
1668 /* get current value of address register[swizzle] */
1669 swizzle
= reg
->Indirect
.Swizzle
;
1670 fetch_src_file_channel(mach
,
1677 /* add value of address register to the offset */
1678 index
->i
[0] += indir_index
.i
[0];
1679 index
->i
[1] += indir_index
.i
[1];
1680 index
->i
[2] += indir_index
.i
[2];
1681 index
->i
[3] += indir_index
.i
[3];
1683 /* for disabled execution channels, zero-out the index to
1684 * avoid using a potential garbage value.
1686 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1687 if ((execmask
& (1 << i
)) == 0)
1692 /* There is an extra source register that is a second
1693 * subscript to a register file. Effectively it means that
1694 * the register file is actually a 2D array of registers.
1698 * [3] = Dimension.Index
1700 if (reg
->Register
.Dimension
) {
1704 index2D
->i
[3] = reg
->Dimension
.Index
;
1706 /* Again, the second subscript index can be addressed indirectly
1707 * identically to the first one.
1708 * Nothing stops us from indirectly addressing the indirect register,
1709 * but there is no need for that, so we won't exercise it.
1711 * file[ind[4].y+3][1],
1713 * ind = DimIndirect.File
1714 * [4] = DimIndirect.Index
1715 * .y = DimIndirect.SwizzleX
1717 if (reg
->Dimension
.Indirect
) {
1718 union tgsi_exec_channel index2
;
1719 union tgsi_exec_channel indir_index
;
1720 const uint execmask
= mach
->ExecMask
;
1726 index2
.i
[3] = reg
->DimIndirect
.Index
;
1728 swizzle
= reg
->DimIndirect
.Swizzle
;
1729 fetch_src_file_channel(mach
,
1730 reg
->DimIndirect
.File
,
1736 index2D
->i
[0] += indir_index
.i
[0];
1737 index2D
->i
[1] += indir_index
.i
[1];
1738 index2D
->i
[2] += indir_index
.i
[2];
1739 index2D
->i
[3] += indir_index
.i
[3];
1741 /* for disabled execution channels, zero-out the index to
1742 * avoid using a potential garbage value.
1744 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1745 if ((execmask
& (1 << i
)) == 0) {
1751 /* If by any chance there was a need for a 3D array of register
1752 * files, we would have to check whether Dimension is followed
1753 * by a dimension register and continue the saga.
1765 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1766 union tgsi_exec_channel
*chan
,
1767 const struct tgsi_full_src_register
*reg
,
1768 const uint chan_index
)
1770 union tgsi_exec_channel index
;
1771 union tgsi_exec_channel index2D
;
1774 get_index_registers(mach
, reg
, &index
, &index2D
);
1777 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1778 fetch_src_file_channel(mach
,
1787 fetch_source(const struct tgsi_exec_machine
*mach
,
1788 union tgsi_exec_channel
*chan
,
1789 const struct tgsi_full_src_register
*reg
,
1790 const uint chan_index
,
1791 enum tgsi_exec_datatype src_datatype
)
1793 fetch_source_d(mach
, chan
, reg
, chan_index
);
1795 if (reg
->Register
.Absolute
) {
1796 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1797 micro_abs(chan
, chan
);
1799 micro_iabs(chan
, chan
);
1803 if (reg
->Register
.Negate
) {
1804 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1805 micro_neg(chan
, chan
);
1807 micro_ineg(chan
, chan
);
1812 static union tgsi_exec_channel
*
1813 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1814 const union tgsi_exec_channel
*chan
,
1815 const struct tgsi_full_dst_register
*reg
,
1817 enum tgsi_exec_datatype dst_datatype
)
1819 static union tgsi_exec_channel null
;
1820 union tgsi_exec_channel
*dst
;
1821 union tgsi_exec_channel index2D
;
1822 int offset
= 0; /* indirection offset */
1826 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1827 check_inf_or_nan(chan
);
1830 /* There is an extra source register that indirectly subscripts
1831 * a register file. The direct index now becomes an offset
1832 * that is being added to the indirect register.
1836 * ind = Indirect.File
1837 * [2] = Indirect.Index
1838 * .x = Indirect.SwizzleX
1840 if (reg
->Register
.Indirect
) {
1841 union tgsi_exec_channel index
;
1842 union tgsi_exec_channel indir_index
;
1845 /* which address register (always zero for now) */
1849 index
.i
[3] = reg
->Indirect
.Index
;
1851 /* get current value of address register[swizzle] */
1852 swizzle
= reg
->Indirect
.Swizzle
;
1854 /* fetch values from the address/indirection register */
1855 fetch_src_file_channel(mach
,
1862 /* save indirection offset */
1863 offset
= indir_index
.i
[0];
1866 /* There is an extra source register that is a second
1867 * subscript to a register file. Effectively it means that
1868 * the register file is actually a 2D array of registers.
1872 * [3] = Dimension.Index
1874 if (reg
->Register
.Dimension
) {
1878 index2D
.i
[3] = reg
->Dimension
.Index
;
1880 /* Again, the second subscript index can be addressed indirectly
1881 * identically to the first one.
1882 * Nothing stops us from indirectly addressing the indirect register,
1883 * but there is no need for that, so we won't exercise it.
1885 * file[ind[4].y+3][1],
1887 * ind = DimIndirect.File
1888 * [4] = DimIndirect.Index
1889 * .y = DimIndirect.SwizzleX
1891 if (reg
->Dimension
.Indirect
) {
1892 union tgsi_exec_channel index2
;
1893 union tgsi_exec_channel indir_index
;
1894 const uint execmask
= mach
->ExecMask
;
1901 index2
.i
[3] = reg
->DimIndirect
.Index
;
1903 swizzle
= reg
->DimIndirect
.Swizzle
;
1904 fetch_src_file_channel(mach
,
1905 reg
->DimIndirect
.File
,
1911 index2D
.i
[0] += indir_index
.i
[0];
1912 index2D
.i
[1] += indir_index
.i
[1];
1913 index2D
.i
[2] += indir_index
.i
[2];
1914 index2D
.i
[3] += indir_index
.i
[3];
1916 /* for disabled execution channels, zero-out the index to
1917 * avoid using a potential garbage value.
1919 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1920 if ((execmask
& (1 << i
)) == 0) {
1926 /* If by any chance there was a need for a 3D array of register
1927 * files, we would have to check whether Dimension is followed
1928 * by a dimension register and continue the saga.
1937 switch (reg
->Register
.File
) {
1938 case TGSI_FILE_NULL
:
1942 case TGSI_FILE_OUTPUT
:
1943 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1944 + reg
->Register
.Index
;
1945 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1947 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1948 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1949 reg
->Register
.Index
);
1950 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1951 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1952 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1953 if (execmask
& (1 << i
))
1954 debug_printf("%f, ", chan
->f
[i
]);
1955 debug_printf(")\n");
1960 case TGSI_FILE_TEMPORARY
:
1961 index
= reg
->Register
.Index
;
1962 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1963 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1966 case TGSI_FILE_ADDRESS
:
1967 index
= reg
->Register
.Index
;
1968 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1980 store_dest_double(struct tgsi_exec_machine
*mach
,
1981 const union tgsi_exec_channel
*chan
,
1982 const struct tgsi_full_dst_register
*reg
,
1984 enum tgsi_exec_datatype dst_datatype
)
1986 union tgsi_exec_channel
*dst
;
1987 const uint execmask
= mach
->ExecMask
;
1990 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1995 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1996 if (execmask
& (1 << i
))
1997 dst
->i
[i
] = chan
->i
[i
];
2001 store_dest(struct tgsi_exec_machine
*mach
,
2002 const union tgsi_exec_channel
*chan
,
2003 const struct tgsi_full_dst_register
*reg
,
2004 const struct tgsi_full_instruction
*inst
,
2006 enum tgsi_exec_datatype dst_datatype
)
2008 union tgsi_exec_channel
*dst
;
2009 const uint execmask
= mach
->ExecMask
;
2012 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
2016 if (!inst
->Instruction
.Saturate
) {
2017 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2018 if (execmask
& (1 << i
))
2019 dst
->i
[i
] = chan
->i
[i
];
2022 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2023 if (execmask
& (1 << i
)) {
2024 if (chan
->f
[i
] < 0.0f
)
2026 else if (chan
->f
[i
] > 1.0f
)
2029 dst
->i
[i
] = chan
->i
[i
];
2034 #define FETCH(VAL,INDEX,CHAN)\
2035 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
2037 #define IFETCH(VAL,INDEX,CHAN)\
2038 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
2042 * Execute ARB-style KIL which is predicated by a src register.
2043 * Kill fragment if any of the four values is less than zero.
2046 exec_kill_if(struct tgsi_exec_machine
*mach
,
2047 const struct tgsi_full_instruction
*inst
)
2051 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2052 union tgsi_exec_channel r
[1];
2054 /* This mask stores component bits that were already tested. */
2057 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2062 /* unswizzle channel */
2063 swizzle
= tgsi_util_get_full_src_register_swizzle (
2067 /* check if the component has not been already tested */
2068 if (uniquemask
& (1 << swizzle
))
2070 uniquemask
|= 1 << swizzle
;
2072 FETCH(&r
[0], 0, chan_index
);
2073 for (i
= 0; i
< 4; i
++)
2074 if (r
[0].f
[i
] < 0.0f
)
2078 /* restrict to fragments currently executing */
2079 kilmask
&= mach
->ExecMask
;
2081 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2085 * Unconditional fragment kill/discard.
2088 exec_kill(struct tgsi_exec_machine
*mach
)
2090 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2092 /* kill fragment for all fragments currently executing */
2093 kilmask
= mach
->ExecMask
;
2094 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2098 emit_vertex(struct tgsi_exec_machine
*mach
,
2099 const struct tgsi_full_instruction
*inst
)
2101 union tgsi_exec_channel r
[1];
2103 unsigned *prim_count
;
2104 /* FIXME: check for exec mask correctly
2106 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2107 if ((mach->ExecMask & (1 << i)))
2109 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2110 stream_id
= r
[0].u
[0];
2111 prim_count
= &mach
->Temps
[temp_prim_idxs
[stream_id
].idx
].xyzw
[temp_prim_idxs
[stream_id
].chan
].u
[0];
2112 if (mach
->ExecMask
) {
2113 if (mach
->Primitives
[stream_id
][*prim_count
] >= mach
->MaxOutputVertices
)
2116 if (mach
->Primitives
[stream_id
][*prim_count
] == 0)
2117 mach
->PrimitiveOffsets
[stream_id
][*prim_count
] = mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0];
2118 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2119 mach
->Primitives
[stream_id
][*prim_count
]++;
2124 emit_primitive(struct tgsi_exec_machine
*mach
,
2125 const struct tgsi_full_instruction
*inst
)
2127 unsigned *prim_count
;
2128 union tgsi_exec_channel r
[1];
2129 unsigned stream_id
= 0;
2130 /* FIXME: check for exec mask correctly
2132 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2133 if ((mach->ExecMask & (1 << i)))
2136 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2137 stream_id
= r
[0].u
[0];
2139 prim_count
= &mach
->Temps
[temp_prim_idxs
[stream_id
].idx
].xyzw
[temp_prim_idxs
[stream_id
].chan
].u
[0];
2140 if (mach
->ExecMask
) {
2142 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2143 mach
->Primitives
[stream_id
][*prim_count
] = 0;
2148 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2150 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2152 mach
->Primitives
[0][mach
->Temps
[temp_prim_idxs
[0].idx
].xyzw
[temp_prim_idxs
[0].chan
].u
[0]];
2153 if (emitted_verts
) {
2154 emit_primitive(mach
, NULL
);
2161 * Fetch four texture samples using STR texture coordinates.
2164 fetch_texel( struct tgsi_sampler
*sampler
,
2165 const unsigned sview_idx
,
2166 const unsigned sampler_idx
,
2167 const union tgsi_exec_channel
*s
,
2168 const union tgsi_exec_channel
*t
,
2169 const union tgsi_exec_channel
*p
,
2170 const union tgsi_exec_channel
*c0
,
2171 const union tgsi_exec_channel
*c1
,
2172 float derivs
[3][2][TGSI_QUAD_SIZE
],
2173 const int8_t offset
[3],
2174 enum tgsi_sampler_control control
,
2175 union tgsi_exec_channel
*r
,
2176 union tgsi_exec_channel
*g
,
2177 union tgsi_exec_channel
*b
,
2178 union tgsi_exec_channel
*a
)
2181 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2183 /* FIXME: handle explicit derivs, offsets */
2184 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2185 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2187 for (j
= 0; j
< 4; j
++) {
2188 r
->f
[j
] = rgba
[0][j
];
2189 g
->f
[j
] = rgba
[1][j
];
2190 b
->f
[j
] = rgba
[2][j
];
2191 a
->f
[j
] = rgba
[3][j
];
2196 #define TEX_MODIFIER_NONE 0
2197 #define TEX_MODIFIER_PROJECTED 1
2198 #define TEX_MODIFIER_LOD_BIAS 2
2199 #define TEX_MODIFIER_EXPLICIT_LOD 3
2200 #define TEX_MODIFIER_LEVEL_ZERO 4
2201 #define TEX_MODIFIER_GATHER 5
2204 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2207 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2208 const struct tgsi_full_instruction
*inst
,
2211 if (inst
->Texture
.NumOffsets
== 1) {
2212 union tgsi_exec_channel index
;
2213 union tgsi_exec_channel offset
[3];
2214 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2215 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2216 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2217 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2218 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2219 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2220 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2221 offsets
[0] = offset
[0].i
[0];
2222 offsets
[1] = offset
[1].i
[0];
2223 offsets
[2] = offset
[2].i
[0];
2225 assert(inst
->Texture
.NumOffsets
== 0);
2226 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2232 * Fetch dx and dy values for one channel (s, t or r).
2233 * Put dx values into one float array, dy values into another.
2236 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2237 const struct tgsi_full_instruction
*inst
,
2240 float derivs
[2][TGSI_QUAD_SIZE
])
2242 union tgsi_exec_channel d
;
2243 FETCH(&d
, regdsrcx
, chan
);
2244 derivs
[0][0] = d
.f
[0];
2245 derivs
[0][1] = d
.f
[1];
2246 derivs
[0][2] = d
.f
[2];
2247 derivs
[0][3] = d
.f
[3];
2248 FETCH(&d
, regdsrcx
+ 1, chan
);
2249 derivs
[1][0] = d
.f
[0];
2250 derivs
[1][1] = d
.f
[1];
2251 derivs
[1][2] = d
.f
[2];
2252 derivs
[1][3] = d
.f
[3];
2256 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2257 const struct tgsi_full_instruction
*inst
,
2262 if (inst
->Src
[sampler
].Register
.Indirect
) {
2263 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2264 union tgsi_exec_channel indir_index
, index2
;
2265 const uint execmask
= mach
->ExecMask
;
2269 index2
.i
[3] = reg
->Indirect
.Index
;
2271 fetch_src_file_channel(mach
,
2273 reg
->Indirect
.Swizzle
,
2277 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2278 if (execmask
& (1 << i
)) {
2279 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2285 unit
= inst
->Src
[sampler
].Register
.Index
;
2291 * execute a texture instruction.
2293 * modifier is used to control the channel routing for the
2294 * instruction variants like proj, lod, and texture with lod bias.
2295 * sampler indicates which src register the sampler is contained in.
2298 exec_tex(struct tgsi_exec_machine
*mach
,
2299 const struct tgsi_full_instruction
*inst
,
2300 uint modifier
, uint sampler
)
2302 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2303 union tgsi_exec_channel r
[5];
2304 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2308 int dim
, shadow_ref
, i
;
2310 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2311 /* always fetch all 3 offsets, overkill but keeps code simple */
2312 fetch_texel_offsets(mach
, inst
, offsets
);
2314 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2315 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2317 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2318 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2321 if (shadow_ref
>= 0)
2322 assert(shadow_ref
>= dim
&& shadow_ref
< (int)ARRAY_SIZE(args
));
2324 /* fetch modifier to the last argument */
2325 if (modifier
!= TEX_MODIFIER_NONE
) {
2326 const int last
= ARRAY_SIZE(args
) - 1;
2328 /* fetch modifier from src0.w or src1.x */
2330 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2331 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2334 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2337 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2338 args
[last
] = &r
[last
];
2342 args
[last
] = &ZeroVec
;
2345 /* point unused arguments to zero vector */
2346 for (i
= dim
; i
< last
; i
++)
2349 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2350 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2351 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2352 control
= TGSI_SAMPLER_LOD_BIAS
;
2353 else if (modifier
== TEX_MODIFIER_GATHER
)
2354 control
= TGSI_SAMPLER_GATHER
;
2357 for (i
= dim
; i
< (int)ARRAY_SIZE(args
); i
++)
2361 /* fetch coordinates */
2362 for (i
= 0; i
< dim
; i
++) {
2363 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2366 micro_div(&r
[i
], &r
[i
], proj
);
2371 /* fetch reference value */
2372 if (shadow_ref
>= 0) {
2373 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2376 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2378 args
[shadow_ref
] = &r
[shadow_ref
];
2381 fetch_texel(mach
->Sampler
, unit
, unit
,
2382 args
[0], args
[1], args
[2], args
[3], args
[4],
2383 NULL
, offsets
, control
,
2384 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2387 debug_printf("fetch r: %g %g %g %g\n",
2388 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2389 debug_printf("fetch g: %g %g %g %g\n",
2390 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2391 debug_printf("fetch b: %g %g %g %g\n",
2392 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2393 debug_printf("fetch a: %g %g %g %g\n",
2394 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2397 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2398 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2399 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2405 exec_lodq(struct tgsi_exec_machine
*mach
,
2406 const struct tgsi_full_instruction
*inst
)
2408 uint resource_unit
, sampler_unit
;
2411 union tgsi_exec_channel coords
[4];
2412 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2413 union tgsi_exec_channel r
[2];
2415 resource_unit
= fetch_sampler_unit(mach
, inst
, 1);
2416 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2417 uint target
= mach
->SamplerViews
[resource_unit
].Resource
;
2418 dim
= tgsi_util_get_texture_coord_dim(target
);
2419 sampler_unit
= fetch_sampler_unit(mach
, inst
, 2);
2421 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2422 sampler_unit
= resource_unit
;
2424 assert(dim
<= ARRAY_SIZE(coords
));
2425 /* fetch coordinates */
2426 for (i
= 0; i
< dim
; i
++) {
2427 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2428 args
[i
] = &coords
[i
];
2430 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2433 mach
->Sampler
->query_lod(mach
->Sampler
, resource_unit
, sampler_unit
,
2438 TGSI_SAMPLER_LOD_NONE
,
2442 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2443 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2444 TGSI_EXEC_DATA_FLOAT
);
2446 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2447 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2448 TGSI_EXEC_DATA_FLOAT
);
2450 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2451 unsigned char swizzles
[4];
2453 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2454 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2455 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2456 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2458 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2459 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2460 if (swizzles
[chan
] >= 2) {
2461 store_dest(mach
, &ZeroVec
,
2462 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2464 store_dest(mach
, &r
[swizzles
[chan
]],
2465 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2470 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2471 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2472 TGSI_EXEC_DATA_FLOAT
);
2474 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2475 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2476 TGSI_EXEC_DATA_FLOAT
);
2482 exec_txd(struct tgsi_exec_machine
*mach
,
2483 const struct tgsi_full_instruction
*inst
)
2485 union tgsi_exec_channel r
[4];
2486 float derivs
[3][2][TGSI_QUAD_SIZE
];
2491 unit
= fetch_sampler_unit(mach
, inst
, 3);
2492 /* always fetch all 3 offsets, overkill but keeps code simple */
2493 fetch_texel_offsets(mach
, inst
, offsets
);
2495 switch (inst
->Texture
.Texture
) {
2496 case TGSI_TEXTURE_1D
:
2497 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2499 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2501 fetch_texel(mach
->Sampler
, unit
, unit
,
2502 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2503 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2504 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2507 case TGSI_TEXTURE_SHADOW1D
:
2508 case TGSI_TEXTURE_1D_ARRAY
:
2509 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2510 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2511 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2512 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2513 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2515 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2517 fetch_texel(mach
->Sampler
, unit
, unit
,
2518 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2519 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2520 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2523 case TGSI_TEXTURE_2D
:
2524 case TGSI_TEXTURE_RECT
:
2525 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2526 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2528 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2529 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2531 fetch_texel(mach
->Sampler
, unit
, unit
,
2532 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2533 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2534 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2538 case TGSI_TEXTURE_SHADOW2D
:
2539 case TGSI_TEXTURE_SHADOWRECT
:
2540 case TGSI_TEXTURE_2D_ARRAY
:
2541 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2542 /* only SHADOW2D_ARRAY actually needs W */
2543 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2544 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2545 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2546 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2548 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2549 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2551 fetch_texel(mach
->Sampler
, unit
, unit
,
2552 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2553 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2554 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2557 case TGSI_TEXTURE_3D
:
2558 case TGSI_TEXTURE_CUBE
:
2559 case TGSI_TEXTURE_CUBE_ARRAY
:
2560 case TGSI_TEXTURE_SHADOWCUBE
:
2561 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2562 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2563 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2564 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2565 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2567 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2568 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2569 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2571 fetch_texel(mach
->Sampler
, unit
, unit
,
2572 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2573 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2574 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2581 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2582 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2583 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2590 exec_txf(struct tgsi_exec_machine
*mach
,
2591 const struct tgsi_full_instruction
*inst
)
2593 union tgsi_exec_channel r
[4];
2596 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2601 unit
= fetch_sampler_unit(mach
, inst
, 1);
2602 /* always fetch all 3 offsets, overkill but keeps code simple */
2603 fetch_texel_offsets(mach
, inst
, offsets
);
2605 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2607 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2608 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2609 target
= mach
->SamplerViews
[unit
].Resource
;
2612 target
= inst
->Texture
.Texture
;
2615 case TGSI_TEXTURE_3D
:
2616 case TGSI_TEXTURE_2D_ARRAY
:
2617 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2618 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2619 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2621 case TGSI_TEXTURE_2D
:
2622 case TGSI_TEXTURE_RECT
:
2623 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2624 case TGSI_TEXTURE_SHADOW2D
:
2625 case TGSI_TEXTURE_SHADOWRECT
:
2626 case TGSI_TEXTURE_1D_ARRAY
:
2627 case TGSI_TEXTURE_2D_MSAA
:
2628 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2630 case TGSI_TEXTURE_BUFFER
:
2631 case TGSI_TEXTURE_1D
:
2632 case TGSI_TEXTURE_SHADOW1D
:
2633 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2640 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2643 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2644 r
[0].f
[j
] = rgba
[0][j
];
2645 r
[1].f
[j
] = rgba
[1][j
];
2646 r
[2].f
[j
] = rgba
[2][j
];
2647 r
[3].f
[j
] = rgba
[3][j
];
2650 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2651 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2652 unsigned char swizzles
[4];
2653 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2654 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2655 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2656 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2658 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2659 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2660 store_dest(mach
, &r
[swizzles
[chan
]],
2661 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2666 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2667 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2668 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2675 exec_txq(struct tgsi_exec_machine
*mach
,
2676 const struct tgsi_full_instruction
*inst
)
2679 union tgsi_exec_channel r
[4], src
;
2684 unit
= fetch_sampler_unit(mach
, inst
, 1);
2686 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2688 /* XXX: This interface can't return per-pixel values */
2689 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2691 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2692 for (j
= 0; j
< 4; j
++) {
2693 r
[j
].i
[i
] = result
[j
];
2697 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2698 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2699 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2700 TGSI_EXEC_DATA_INT
);
2706 exec_sample(struct tgsi_exec_machine
*mach
,
2707 const struct tgsi_full_instruction
*inst
,
2708 uint modifier
, boolean compare
)
2710 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2711 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2712 union tgsi_exec_channel r
[5], c1
;
2713 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2714 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2716 unsigned char swizzles
[4];
2719 /* always fetch all 3 offsets, overkill but keeps code simple */
2720 fetch_texel_offsets(mach
, inst
, offsets
);
2722 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2724 if (modifier
!= TEX_MODIFIER_NONE
) {
2725 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2726 FETCH(&c1
, 3, TGSI_CHAN_X
);
2728 control
= TGSI_SAMPLER_LOD_BIAS
;
2730 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2731 FETCH(&c1
, 3, TGSI_CHAN_X
);
2733 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2735 else if (modifier
== TEX_MODIFIER_GATHER
) {
2736 control
= TGSI_SAMPLER_GATHER
;
2739 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2740 control
= TGSI_SAMPLER_LOD_ZERO
;
2744 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2746 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2747 case TGSI_TEXTURE_1D
:
2749 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2750 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2751 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2752 NULL
, offsets
, control
,
2753 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2756 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2757 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2758 NULL
, offsets
, control
,
2759 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2763 case TGSI_TEXTURE_1D_ARRAY
:
2764 case TGSI_TEXTURE_2D
:
2765 case TGSI_TEXTURE_RECT
:
2766 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2768 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2769 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2770 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2771 NULL
, offsets
, control
,
2772 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2775 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2776 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2777 NULL
, offsets
, control
,
2778 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2782 case TGSI_TEXTURE_2D_ARRAY
:
2783 case TGSI_TEXTURE_3D
:
2784 case TGSI_TEXTURE_CUBE
:
2785 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2786 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2788 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2789 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2790 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2791 NULL
, offsets
, control
,
2792 &r
[0], &r
[1], &r
[2], &r
[3]);
2795 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2796 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2797 NULL
, offsets
, control
,
2798 &r
[0], &r
[1], &r
[2], &r
[3]);
2802 case TGSI_TEXTURE_CUBE_ARRAY
:
2803 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2804 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2805 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2807 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2808 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2809 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2810 NULL
, offsets
, control
,
2811 &r
[0], &r
[1], &r
[2], &r
[3]);
2814 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2815 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2816 NULL
, offsets
, control
,
2817 &r
[0], &r
[1], &r
[2], &r
[3]);
2826 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2827 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2828 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2829 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2831 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2832 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2833 store_dest(mach
, &r
[swizzles
[chan
]],
2834 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2840 exec_sample_d(struct tgsi_exec_machine
*mach
,
2841 const struct tgsi_full_instruction
*inst
)
2843 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2844 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2845 union tgsi_exec_channel r
[4];
2846 float derivs
[3][2][TGSI_QUAD_SIZE
];
2848 unsigned char swizzles
[4];
2851 /* always fetch all 3 offsets, overkill but keeps code simple */
2852 fetch_texel_offsets(mach
, inst
, offsets
);
2854 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2856 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2857 case TGSI_TEXTURE_1D
:
2858 case TGSI_TEXTURE_1D_ARRAY
:
2859 /* only 1D array actually needs Y */
2860 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2862 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2864 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2865 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2866 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2867 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2870 case TGSI_TEXTURE_2D
:
2871 case TGSI_TEXTURE_RECT
:
2872 case TGSI_TEXTURE_2D_ARRAY
:
2873 /* only 2D array actually needs Z */
2874 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2875 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2877 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2878 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2880 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2881 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2882 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2883 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2886 case TGSI_TEXTURE_3D
:
2887 case TGSI_TEXTURE_CUBE
:
2888 case TGSI_TEXTURE_CUBE_ARRAY
:
2889 /* only cube array actually needs W */
2890 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2891 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2892 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2894 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2895 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2896 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2898 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2899 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2900 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2901 &r
[0], &r
[1], &r
[2], &r
[3]);
2908 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2909 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2910 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2911 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2913 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2914 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2915 store_dest(mach
, &r
[swizzles
[chan
]],
2916 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2923 * Evaluate a constant-valued coefficient at the position of the
2928 struct tgsi_exec_machine
*mach
,
2934 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2935 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2940 interp_constant_offset(
2941 UNUSED
const struct tgsi_exec_machine
*mach
,
2942 UNUSED
unsigned attrib
,
2943 UNUSED
unsigned chan
,
2946 UNUSED
union tgsi_exec_channel
*out_chan
)
2951 * Evaluate a linear-valued coefficient at the position of the
2955 interp_linear_offset(
2956 const struct tgsi_exec_machine
*mach
,
2961 union tgsi_exec_channel
*out_chan
)
2963 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2964 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2965 const float delta
= ofs_x
* dadx
+ ofs_y
* dady
;
2966 out_chan
->f
[0] += delta
;
2967 out_chan
->f
[1] += delta
;
2968 out_chan
->f
[2] += delta
;
2969 out_chan
->f
[3] += delta
;
2973 eval_linear_coef(struct tgsi_exec_machine
*mach
,
2977 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2978 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2979 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2980 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2981 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2983 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2984 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2985 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2986 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2990 * Evaluate a perspective-valued coefficient at the position of the
2995 interp_perspective_offset(
2996 const struct tgsi_exec_machine
*mach
,
3001 union tgsi_exec_channel
*out_chan
)
3003 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
3004 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
3005 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
3006 const float delta
= ofs_x
* dadx
+ ofs_y
* dady
;
3007 out_chan
->f
[0] += delta
/ w
[0];
3008 out_chan
->f
[1] += delta
/ w
[1];
3009 out_chan
->f
[2] += delta
/ w
[2];
3010 out_chan
->f
[3] += delta
/ w
[3];
3014 eval_perspective_coef(
3015 struct tgsi_exec_machine
*mach
,
3019 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
3020 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
3021 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
3022 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
3023 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
3024 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
3025 /* divide by W here */
3026 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
3027 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
3028 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
3029 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
3033 typedef void (* eval_coef_func
)(
3034 struct tgsi_exec_machine
*mach
,
3039 exec_declaration(struct tgsi_exec_machine
*mach
,
3040 const struct tgsi_full_declaration
*decl
)
3042 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
3043 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
3047 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
3048 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
3049 uint first
, last
, mask
;
3051 first
= decl
->Range
.First
;
3052 last
= decl
->Range
.Last
;
3053 mask
= decl
->Declaration
.UsageMask
;
3055 /* XXX we could remove this special-case code since
3056 * mach->InterpCoefs[first].a0 should already have the
3057 * front/back-face value. But we should first update the
3058 * ureg code to emit the right UsageMask value (WRITEMASK_X).
3059 * Then, we could remove the tgsi_exec_machine::Face field.
3061 /* XXX make FACE a system value */
3062 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
3065 assert(decl
->Semantic
.Index
== 0);
3066 assert(first
== last
);
3068 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3069 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
3072 eval_coef_func eval
;
3073 apply_sample_offset_func interp
;
3076 switch (decl
->Interp
.Interpolate
) {
3077 case TGSI_INTERPOLATE_CONSTANT
:
3078 eval
= eval_constant_coef
;
3079 interp
= interp_constant_offset
;
3082 case TGSI_INTERPOLATE_LINEAR
:
3083 eval
= eval_linear_coef
;
3084 interp
= interp_linear_offset
;
3087 case TGSI_INTERPOLATE_PERSPECTIVE
:
3088 eval
= eval_perspective_coef
;
3089 interp
= interp_perspective_offset
;
3092 case TGSI_INTERPOLATE_COLOR
:
3093 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
3094 interp
= mach
->flatshade_color
? interp_constant_offset
: interp_perspective_offset
;
3102 for (i
= first
; i
<= last
; i
++)
3103 mach
->InputSampleOffsetApply
[i
] = interp
;
3105 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3106 if (mask
& (1 << j
)) {
3107 for (i
= first
; i
<= last
; i
++) {
3114 if (DEBUG_EXECUTION
) {
3116 for (i
= first
; i
<= last
; ++i
) {
3117 debug_printf("IN[%2u] = ", i
);
3118 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3122 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3123 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
3124 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
3125 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
3126 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
3135 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
3136 const union tgsi_exec_channel
*src
);
3139 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
3140 const struct tgsi_full_instruction
*inst
,
3142 enum tgsi_exec_datatype dst_datatype
,
3143 enum tgsi_exec_datatype src_datatype
)
3146 union tgsi_exec_channel src
;
3147 union tgsi_exec_channel dst
;
3149 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3151 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3152 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3153 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3159 exec_vector_unary(struct tgsi_exec_machine
*mach
,
3160 const struct tgsi_full_instruction
*inst
,
3162 enum tgsi_exec_datatype dst_datatype
,
3163 enum tgsi_exec_datatype src_datatype
)
3166 struct tgsi_exec_vector dst
;
3168 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3169 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3170 union tgsi_exec_channel src
;
3172 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3173 op(&dst
.xyzw
[chan
], &src
);
3176 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3177 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3178 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3183 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3184 const union tgsi_exec_channel
*src0
,
3185 const union tgsi_exec_channel
*src1
);
3188 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3189 const struct tgsi_full_instruction
*inst
,
3191 enum tgsi_exec_datatype dst_datatype
,
3192 enum tgsi_exec_datatype src_datatype
)
3195 union tgsi_exec_channel src
[2];
3196 union tgsi_exec_channel dst
;
3198 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3199 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3200 op(&dst
, &src
[0], &src
[1]);
3201 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3202 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3203 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3209 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3210 const struct tgsi_full_instruction
*inst
,
3212 enum tgsi_exec_datatype dst_datatype
,
3213 enum tgsi_exec_datatype src_datatype
)
3216 struct tgsi_exec_vector dst
;
3218 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3219 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3220 union tgsi_exec_channel src
[2];
3222 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3223 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3224 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3227 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3228 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3229 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3234 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3235 const union tgsi_exec_channel
*src0
,
3236 const union tgsi_exec_channel
*src1
,
3237 const union tgsi_exec_channel
*src2
);
3240 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3241 const struct tgsi_full_instruction
*inst
,
3242 micro_trinary_op op
,
3243 enum tgsi_exec_datatype dst_datatype
,
3244 enum tgsi_exec_datatype src_datatype
)
3247 struct tgsi_exec_vector dst
;
3249 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3250 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3251 union tgsi_exec_channel src
[3];
3253 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3254 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3255 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3256 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3259 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3260 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3261 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3266 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3267 const union tgsi_exec_channel
*src0
,
3268 const union tgsi_exec_channel
*src1
,
3269 const union tgsi_exec_channel
*src2
,
3270 const union tgsi_exec_channel
*src3
);
3273 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3274 const struct tgsi_full_instruction
*inst
,
3275 micro_quaternary_op op
,
3276 enum tgsi_exec_datatype dst_datatype
,
3277 enum tgsi_exec_datatype src_datatype
)
3280 struct tgsi_exec_vector dst
;
3282 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3283 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3284 union tgsi_exec_channel src
[4];
3286 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3287 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3288 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3289 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3290 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3293 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3294 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3295 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3301 exec_dp3(struct tgsi_exec_machine
*mach
,
3302 const struct tgsi_full_instruction
*inst
)
3305 union tgsi_exec_channel arg
[3];
3307 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3308 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3309 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3311 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3312 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3313 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3314 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3317 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3318 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3319 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3325 exec_dp4(struct tgsi_exec_machine
*mach
,
3326 const struct tgsi_full_instruction
*inst
)
3329 union tgsi_exec_channel arg
[3];
3331 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3332 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3333 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3335 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3336 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3337 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3338 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3341 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3342 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3343 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3349 exec_dp2(struct tgsi_exec_machine
*mach
,
3350 const struct tgsi_full_instruction
*inst
)
3353 union tgsi_exec_channel arg
[3];
3355 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3356 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3357 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3359 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3360 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3361 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3363 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3364 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3365 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3371 exec_pk2h(struct tgsi_exec_machine
*mach
,
3372 const struct tgsi_full_instruction
*inst
)
3375 union tgsi_exec_channel arg
[2], dst
;
3377 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3378 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3379 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3380 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3381 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3383 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3384 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3385 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3391 exec_up2h(struct tgsi_exec_machine
*mach
,
3392 const struct tgsi_full_instruction
*inst
)
3395 union tgsi_exec_channel arg
, dst
[2];
3397 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3398 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3399 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3400 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3402 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3403 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3404 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3410 micro_ucmp(union tgsi_exec_channel
*dst
,
3411 const union tgsi_exec_channel
*src0
,
3412 const union tgsi_exec_channel
*src1
,
3413 const union tgsi_exec_channel
*src2
)
3415 dst
->f
[0] = src0
->u
[0] ? src1
->f
[0] : src2
->f
[0];
3416 dst
->f
[1] = src0
->u
[1] ? src1
->f
[1] : src2
->f
[1];
3417 dst
->f
[2] = src0
->u
[2] ? src1
->f
[2] : src2
->f
[2];
3418 dst
->f
[3] = src0
->u
[3] ? src1
->f
[3] : src2
->f
[3];
3422 exec_ucmp(struct tgsi_exec_machine
*mach
,
3423 const struct tgsi_full_instruction
*inst
)
3426 struct tgsi_exec_vector dst
;
3428 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3429 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3430 union tgsi_exec_channel src
[3];
3432 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
,
3433 TGSI_EXEC_DATA_UINT
);
3434 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
,
3435 TGSI_EXEC_DATA_FLOAT
);
3436 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
,
3437 TGSI_EXEC_DATA_FLOAT
);
3438 micro_ucmp(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3441 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3442 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3443 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
,
3444 TGSI_EXEC_DATA_FLOAT
);
3450 exec_dst(struct tgsi_exec_machine
*mach
,
3451 const struct tgsi_full_instruction
*inst
)
3453 union tgsi_exec_channel r
[2];
3454 union tgsi_exec_channel d
[4];
3456 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3457 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3458 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3459 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3461 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3462 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3464 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3465 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3468 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3469 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3471 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3472 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3474 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3475 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3477 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3478 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3483 exec_log(struct tgsi_exec_machine
*mach
,
3484 const struct tgsi_full_instruction
*inst
)
3486 union tgsi_exec_channel r
[3];
3488 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3489 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3490 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3491 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3492 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3493 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3495 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3496 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3497 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3498 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3500 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3501 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3503 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3504 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3509 exec_exp(struct tgsi_exec_machine
*mach
,
3510 const struct tgsi_full_instruction
*inst
)
3512 union tgsi_exec_channel r
[3];
3514 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3515 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3516 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3517 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3518 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3520 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3521 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3522 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3524 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3525 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3526 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3528 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3529 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3534 exec_lit(struct tgsi_exec_machine
*mach
,
3535 const struct tgsi_full_instruction
*inst
)
3537 union tgsi_exec_channel r
[3];
3538 union tgsi_exec_channel d
[3];
3540 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3541 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3542 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3543 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3544 micro_max(&r
[1], &r
[1], &ZeroVec
);
3546 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3547 micro_min(&r
[2], &r
[2], &P128Vec
);
3548 micro_max(&r
[2], &r
[2], &M128Vec
);
3549 micro_pow(&r
[1], &r
[1], &r
[2]);
3550 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3551 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3553 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3554 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3555 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3558 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3559 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3562 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3563 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3568 exec_break(struct tgsi_exec_machine
*mach
)
3570 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3571 /* turn off loop channels for each enabled exec channel */
3572 mach
->LoopMask
&= ~mach
->ExecMask
;
3573 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3574 UPDATE_EXEC_MASK(mach
);
3576 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3578 mach
->Switch
.mask
= 0x0;
3580 UPDATE_EXEC_MASK(mach
);
3585 exec_switch(struct tgsi_exec_machine
*mach
,
3586 const struct tgsi_full_instruction
*inst
)
3588 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3589 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3591 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3592 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3593 mach
->Switch
.mask
= 0x0;
3594 mach
->Switch
.defaultMask
= 0x0;
3596 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3597 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3599 UPDATE_EXEC_MASK(mach
);
3603 exec_case(struct tgsi_exec_machine
*mach
,
3604 const struct tgsi_full_instruction
*inst
)
3606 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3607 union tgsi_exec_channel src
;
3610 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3612 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3615 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3618 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3621 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3625 mach
->Switch
.defaultMask
|= mask
;
3627 mach
->Switch
.mask
|= mask
& prevMask
;
3629 UPDATE_EXEC_MASK(mach
);
3632 /* FIXME: this will only work if default is last */
3634 exec_default(struct tgsi_exec_machine
*mach
)
3636 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3638 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3640 UPDATE_EXEC_MASK(mach
);
3644 exec_endswitch(struct tgsi_exec_machine
*mach
)
3646 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3647 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3649 UPDATE_EXEC_MASK(mach
);
3652 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3653 const union tgsi_double_channel
*src
);
3655 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3656 const union tgsi_double_channel
*src0
,
3657 union tgsi_exec_channel
*src1
);
3659 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3660 const union tgsi_exec_channel
*src
);
3662 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3663 const union tgsi_double_channel
*src
);
3666 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3667 union tgsi_double_channel
*chan
,
3668 const struct tgsi_full_src_register
*reg
,
3672 union tgsi_exec_channel src
[2];
3675 fetch_source_d(mach
, &src
[0], reg
, chan_0
);
3676 fetch_source_d(mach
, &src
[1], reg
, chan_1
);
3678 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3679 chan
->u
[i
][0] = src
[0].u
[i
];
3680 chan
->u
[i
][1] = src
[1].u
[i
];
3682 if (reg
->Register
.Absolute
) {
3683 micro_dabs(chan
, chan
);
3685 if (reg
->Register
.Negate
) {
3686 micro_dneg(chan
, chan
);
3691 store_double_channel(struct tgsi_exec_machine
*mach
,
3692 const union tgsi_double_channel
*chan
,
3693 const struct tgsi_full_dst_register
*reg
,
3694 const struct tgsi_full_instruction
*inst
,
3698 union tgsi_exec_channel dst
[2];
3700 union tgsi_double_channel temp
;
3701 const uint execmask
= mach
->ExecMask
;
3703 if (!inst
->Instruction
.Saturate
) {
3704 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3705 if (execmask
& (1 << i
)) {
3706 dst
[0].u
[i
] = chan
->u
[i
][0];
3707 dst
[1].u
[i
] = chan
->u
[i
][1];
3711 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3712 if (execmask
& (1 << i
)) {
3713 if (chan
->d
[i
] < 0.0)
3715 else if (chan
->d
[i
] > 1.0)
3718 temp
.d
[i
] = chan
->d
[i
];
3720 dst
[0].u
[i
] = temp
.u
[i
][0];
3721 dst
[1].u
[i
] = temp
.u
[i
][1];
3725 store_dest_double(mach
, &dst
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3726 if (chan_1
!= (unsigned)-1)
3727 store_dest_double(mach
, &dst
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3731 exec_double_unary(struct tgsi_exec_machine
*mach
,
3732 const struct tgsi_full_instruction
*inst
,
3735 union tgsi_double_channel src
;
3736 union tgsi_double_channel dst
;
3738 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3739 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3741 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3743 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3744 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3746 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3751 exec_double_binary(struct tgsi_exec_machine
*mach
,
3752 const struct tgsi_full_instruction
*inst
,
3754 enum tgsi_exec_datatype dst_datatype
)
3756 union tgsi_double_channel src
[2];
3757 union tgsi_double_channel dst
;
3758 int first_dest_chan
, second_dest_chan
;
3761 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3762 /* these are & because of the way DSLT etc store their destinations */
3763 if (wmask
& TGSI_WRITEMASK_XY
) {
3764 first_dest_chan
= TGSI_CHAN_X
;
3765 second_dest_chan
= TGSI_CHAN_Y
;
3766 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3767 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3768 second_dest_chan
= -1;
3771 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3772 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3774 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3777 if (wmask
& TGSI_WRITEMASK_ZW
) {
3778 first_dest_chan
= TGSI_CHAN_Z
;
3779 second_dest_chan
= TGSI_CHAN_W
;
3780 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3781 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3782 second_dest_chan
= -1;
3785 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3786 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3788 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3793 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3794 const struct tgsi_full_instruction
*inst
,
3797 union tgsi_double_channel src
[3];
3798 union tgsi_double_channel dst
;
3800 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3801 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3802 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3803 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3805 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3807 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3808 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3809 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3810 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3812 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3817 exec_dldexp(struct tgsi_exec_machine
*mach
,
3818 const struct tgsi_full_instruction
*inst
)
3820 union tgsi_double_channel src0
;
3821 union tgsi_exec_channel src1
;
3822 union tgsi_double_channel dst
;
3825 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3826 if (wmask
& TGSI_WRITEMASK_XY
) {
3827 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3828 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3829 micro_dldexp(&dst
, &src0
, &src1
);
3830 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3833 if (wmask
& TGSI_WRITEMASK_ZW
) {
3834 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3835 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3836 micro_dldexp(&dst
, &src0
, &src1
);
3837 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3842 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3843 const struct tgsi_full_instruction
*inst
)
3845 union tgsi_double_channel src
;
3846 union tgsi_double_channel dst
;
3847 union tgsi_exec_channel dst_exp
;
3849 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3850 micro_dfracexp(&dst
, &dst_exp
, &src
);
3851 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)
3852 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3853 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)
3854 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3855 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3856 if (inst
->Dst
[1].Register
.WriteMask
& (1 << chan
))
3857 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, chan
, TGSI_EXEC_DATA_INT
);
3862 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3863 const struct tgsi_full_instruction
*inst
,
3866 union tgsi_double_channel src0
;
3867 union tgsi_exec_channel src1
;
3868 union tgsi_double_channel dst
;
3871 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3872 if (wmask
& TGSI_WRITEMASK_XY
) {
3873 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3874 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3875 op(&dst
, &src0
, &src1
);
3876 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3879 if (wmask
& TGSI_WRITEMASK_ZW
) {
3880 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3881 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3882 op(&dst
, &src0
, &src1
);
3883 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3888 get_image_coord_dim(unsigned tgsi_tex
)
3892 case TGSI_TEXTURE_BUFFER
:
3893 case TGSI_TEXTURE_1D
:
3896 case TGSI_TEXTURE_2D
:
3897 case TGSI_TEXTURE_RECT
:
3898 case TGSI_TEXTURE_1D_ARRAY
:
3899 case TGSI_TEXTURE_2D_MSAA
:
3902 case TGSI_TEXTURE_3D
:
3903 case TGSI_TEXTURE_CUBE
:
3904 case TGSI_TEXTURE_2D_ARRAY
:
3905 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3906 case TGSI_TEXTURE_CUBE_ARRAY
:
3910 assert(!"unknown texture target");
3919 get_image_coord_sample(unsigned tgsi_tex
)
3923 case TGSI_TEXTURE_2D_MSAA
:
3926 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3936 exec_load_img(struct tgsi_exec_machine
*mach
,
3937 const struct tgsi_full_instruction
*inst
)
3939 union tgsi_exec_channel r
[4], sample_r
;
3945 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3946 struct tgsi_image_params params
;
3947 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3949 unit
= fetch_sampler_unit(mach
, inst
, 0);
3950 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3951 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3954 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3956 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3957 params
.format
= inst
->Memory
.Format
;
3959 for (i
= 0; i
< dim
; i
++) {
3960 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3964 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3966 mach
->Image
->load(mach
->Image
, ¶ms
,
3967 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3969 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3970 r
[0].f
[j
] = rgba
[0][j
];
3971 r
[1].f
[j
] = rgba
[1][j
];
3972 r
[2].f
[j
] = rgba
[2][j
];
3973 r
[3].f
[j
] = rgba
[3][j
];
3975 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3976 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3977 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3983 exec_load_buf(struct tgsi_exec_machine
*mach
,
3984 const struct tgsi_full_instruction
*inst
)
3986 union tgsi_exec_channel r
[4];
3990 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3991 struct tgsi_buffer_params params
;
3992 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3994 unit
= fetch_sampler_unit(mach
, inst
, 0);
3996 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3998 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4000 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
4002 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4003 r
[0].f
[j
] = rgba
[0][j
];
4004 r
[1].f
[j
] = rgba
[1][j
];
4005 r
[2].f
[j
] = rgba
[2][j
];
4006 r
[3].f
[j
] = rgba
[3][j
];
4008 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4009 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4010 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4016 exec_load_mem(struct tgsi_exec_machine
*mach
,
4017 const struct tgsi_full_instruction
*inst
)
4019 union tgsi_exec_channel r
[4];
4021 char *ptr
= mach
->LocalMem
;
4025 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4026 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4032 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4033 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4034 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4035 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
4040 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4041 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4042 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4048 exec_load(struct tgsi_exec_machine
*mach
,
4049 const struct tgsi_full_instruction
*inst
)
4051 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4052 exec_load_img(mach
, inst
);
4053 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4054 exec_load_buf(mach
, inst
);
4055 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4056 exec_load_mem(mach
, inst
);
4060 fetch_store_img_unit(struct tgsi_exec_machine
*mach
,
4061 const struct tgsi_full_dst_register
*dst
)
4065 if (dst
->Register
.Indirect
) {
4066 union tgsi_exec_channel indir_index
, index2
;
4067 const uint execmask
= mach
->ExecMask
;
4071 index2
.i
[3] = dst
->Indirect
.Index
;
4073 fetch_src_file_channel(mach
,
4075 dst
->Indirect
.Swizzle
,
4079 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4080 if (execmask
& (1 << i
)) {
4081 unit
= dst
->Register
.Index
+ indir_index
.i
[i
];
4086 unit
= dst
->Register
.Index
;
4092 exec_store_img(struct tgsi_exec_machine
*mach
,
4093 const struct tgsi_full_instruction
*inst
)
4095 union tgsi_exec_channel r
[3], sample_r
;
4096 union tgsi_exec_channel value
[4];
4097 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4098 struct tgsi_image_params params
;
4103 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4104 unit
= fetch_store_img_unit(mach
, &inst
->Dst
[0]);
4105 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4106 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4109 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4111 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4112 params
.format
= inst
->Memory
.Format
;
4114 for (i
= 0; i
< dim
; i
++) {
4115 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
4118 for (i
= 0; i
< 4; i
++) {
4119 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4122 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
4124 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4125 rgba
[0][j
] = value
[0].f
[j
];
4126 rgba
[1][j
] = value
[1].f
[j
];
4127 rgba
[2][j
] = value
[2].f
[j
];
4128 rgba
[3][j
] = value
[3].f
[j
];
4131 mach
->Image
->store(mach
->Image
, ¶ms
,
4132 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4137 exec_store_buf(struct tgsi_exec_machine
*mach
,
4138 const struct tgsi_full_instruction
*inst
)
4140 union tgsi_exec_channel r
[3];
4141 union tgsi_exec_channel value
[4];
4142 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4143 struct tgsi_buffer_params params
;
4146 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4148 unit
= fetch_store_img_unit(mach
, &inst
->Dst
[0]);
4150 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4152 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4154 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4155 for (i
= 0; i
< 4; i
++) {
4156 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4159 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4160 rgba
[0][j
] = value
[0].f
[j
];
4161 rgba
[1][j
] = value
[1].f
[j
];
4162 rgba
[2][j
] = value
[2].f
[j
];
4163 rgba
[3][j
] = value
[3].f
[j
];
4166 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4172 exec_store_mem(struct tgsi_exec_machine
*mach
,
4173 const struct tgsi_full_instruction
*inst
)
4175 union tgsi_exec_channel r
[3];
4176 union tgsi_exec_channel value
[4];
4178 char *ptr
= mach
->LocalMem
;
4179 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4180 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4182 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4184 for (i
= 0; i
< 4; i
++) {
4185 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4188 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4192 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4193 if (execmask
& (1 << i
)) {
4194 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4195 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4196 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4204 exec_store(struct tgsi_exec_machine
*mach
,
4205 const struct tgsi_full_instruction
*inst
)
4207 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4208 exec_store_img(mach
, inst
);
4209 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4210 exec_store_buf(mach
, inst
);
4211 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4212 exec_store_mem(mach
, inst
);
4216 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4217 const struct tgsi_full_instruction
*inst
)
4219 union tgsi_exec_channel r
[4], sample_r
;
4220 union tgsi_exec_channel value
[4], value2
[4];
4221 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4222 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4223 struct tgsi_image_params params
;
4228 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4229 unit
= fetch_sampler_unit(mach
, inst
, 0);
4230 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4231 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4234 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4236 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4237 params
.format
= inst
->Memory
.Format
;
4239 for (i
= 0; i
< dim
; i
++) {
4240 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4243 for (i
= 0; i
< 4; i
++) {
4244 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4245 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4246 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4249 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4251 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4252 rgba
[0][j
] = value
[0].f
[j
];
4253 rgba
[1][j
] = value
[1].f
[j
];
4254 rgba
[2][j
] = value
[2].f
[j
];
4255 rgba
[3][j
] = value
[3].f
[j
];
4257 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4258 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4259 rgba2
[0][j
] = value2
[0].f
[j
];
4260 rgba2
[1][j
] = value2
[1].f
[j
];
4261 rgba2
[2][j
] = value2
[2].f
[j
];
4262 rgba2
[3][j
] = value2
[3].f
[j
];
4266 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4267 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4270 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4271 r
[0].f
[j
] = rgba
[0][j
];
4272 r
[1].f
[j
] = rgba
[1][j
];
4273 r
[2].f
[j
] = rgba
[2][j
];
4274 r
[3].f
[j
] = rgba
[3][j
];
4276 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4277 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4278 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4284 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4285 const struct tgsi_full_instruction
*inst
)
4287 union tgsi_exec_channel r
[4];
4288 union tgsi_exec_channel value
[4], value2
[4];
4289 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4290 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4291 struct tgsi_buffer_params params
;
4294 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4296 unit
= fetch_sampler_unit(mach
, inst
, 0);
4298 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4300 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4302 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4304 for (i
= 0; i
< 4; i
++) {
4305 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4306 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4307 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4310 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4311 rgba
[0][j
] = value
[0].f
[j
];
4312 rgba
[1][j
] = value
[1].f
[j
];
4313 rgba
[2][j
] = value
[2].f
[j
];
4314 rgba
[3][j
] = value
[3].f
[j
];
4316 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4317 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4318 rgba2
[0][j
] = value2
[0].f
[j
];
4319 rgba2
[1][j
] = value2
[1].f
[j
];
4320 rgba2
[2][j
] = value2
[2].f
[j
];
4321 rgba2
[3][j
] = value2
[3].f
[j
];
4325 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4329 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4330 r
[0].f
[j
] = rgba
[0][j
];
4331 r
[1].f
[j
] = rgba
[1][j
];
4332 r
[2].f
[j
] = rgba
[2][j
];
4333 r
[3].f
[j
] = rgba
[3][j
];
4335 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4336 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4337 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4343 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4344 const struct tgsi_full_instruction
*inst
)
4346 union tgsi_exec_channel r
[4];
4347 union tgsi_exec_channel value
[4], value2
[4];
4348 char *ptr
= mach
->LocalMem
;
4352 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4353 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4354 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4356 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4361 for (i
= 0; i
< 4; i
++) {
4362 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4363 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4364 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4367 memcpy(&r
[0].u
[0], ptr
, 4);
4369 switch (inst
->Instruction
.Opcode
) {
4370 case TGSI_OPCODE_ATOMUADD
:
4371 val
+= value
[0].u
[0];
4373 case TGSI_OPCODE_ATOMXOR
:
4374 val
^= value
[0].u
[0];
4376 case TGSI_OPCODE_ATOMOR
:
4377 val
|= value
[0].u
[0];
4379 case TGSI_OPCODE_ATOMAND
:
4380 val
&= value
[0].u
[0];
4382 case TGSI_OPCODE_ATOMUMIN
:
4383 val
= MIN2(val
, value
[0].u
[0]);
4385 case TGSI_OPCODE_ATOMUMAX
:
4386 val
= MAX2(val
, value
[0].u
[0]);
4388 case TGSI_OPCODE_ATOMIMIN
:
4389 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4391 case TGSI_OPCODE_ATOMIMAX
:
4392 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4394 case TGSI_OPCODE_ATOMXCHG
:
4395 val
= value
[0].i
[0];
4397 case TGSI_OPCODE_ATOMCAS
:
4398 if (val
== value
[0].u
[0])
4399 val
= value2
[0].u
[0];
4401 case TGSI_OPCODE_ATOMFADD
:
4402 val
= fui(r
[0].f
[0] + value
[0].f
[0]);
4407 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4408 if (execmask
& (1 << i
))
4409 memcpy(ptr
, &val
, 4);
4411 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4412 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4413 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4419 exec_atomop(struct tgsi_exec_machine
*mach
,
4420 const struct tgsi_full_instruction
*inst
)
4422 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4423 exec_atomop_img(mach
, inst
);
4424 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4425 exec_atomop_buf(mach
, inst
);
4426 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4427 exec_atomop_mem(mach
, inst
);
4431 exec_resq_img(struct tgsi_exec_machine
*mach
,
4432 const struct tgsi_full_instruction
*inst
)
4435 union tgsi_exec_channel r
[4];
4438 struct tgsi_image_params params
;
4439 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4441 unit
= fetch_sampler_unit(mach
, inst
, 0);
4443 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4445 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4446 params
.format
= inst
->Memory
.Format
;
4448 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4450 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4451 for (j
= 0; j
< 4; j
++) {
4452 r
[j
].i
[i
] = result
[j
];
4456 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4457 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4458 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4459 TGSI_EXEC_DATA_INT
);
4465 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4466 const struct tgsi_full_instruction
*inst
)
4469 union tgsi_exec_channel r
[4];
4472 struct tgsi_buffer_params params
;
4473 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4475 unit
= fetch_sampler_unit(mach
, inst
, 0);
4477 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4480 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4482 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4486 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4487 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4488 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4489 TGSI_EXEC_DATA_INT
);
4495 exec_resq(struct tgsi_exec_machine
*mach
,
4496 const struct tgsi_full_instruction
*inst
)
4498 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4499 exec_resq_img(mach
, inst
);
4501 exec_resq_buf(mach
, inst
);
4505 micro_f2u64(union tgsi_double_channel
*dst
,
4506 const union tgsi_exec_channel
*src
)
4508 dst
->u64
[0] = (uint64_t)src
->f
[0];
4509 dst
->u64
[1] = (uint64_t)src
->f
[1];
4510 dst
->u64
[2] = (uint64_t)src
->f
[2];
4511 dst
->u64
[3] = (uint64_t)src
->f
[3];
4515 micro_f2i64(union tgsi_double_channel
*dst
,
4516 const union tgsi_exec_channel
*src
)
4518 dst
->i64
[0] = (int64_t)src
->f
[0];
4519 dst
->i64
[1] = (int64_t)src
->f
[1];
4520 dst
->i64
[2] = (int64_t)src
->f
[2];
4521 dst
->i64
[3] = (int64_t)src
->f
[3];
4525 micro_u2i64(union tgsi_double_channel
*dst
,
4526 const union tgsi_exec_channel
*src
)
4528 dst
->u64
[0] = (uint64_t)src
->u
[0];
4529 dst
->u64
[1] = (uint64_t)src
->u
[1];
4530 dst
->u64
[2] = (uint64_t)src
->u
[2];
4531 dst
->u64
[3] = (uint64_t)src
->u
[3];
4535 micro_i2i64(union tgsi_double_channel
*dst
,
4536 const union tgsi_exec_channel
*src
)
4538 dst
->i64
[0] = (int64_t)src
->i
[0];
4539 dst
->i64
[1] = (int64_t)src
->i
[1];
4540 dst
->i64
[2] = (int64_t)src
->i
[2];
4541 dst
->i64
[3] = (int64_t)src
->i
[3];
4545 micro_d2u64(union tgsi_double_channel
*dst
,
4546 const union tgsi_double_channel
*src
)
4548 dst
->u64
[0] = (uint64_t)src
->d
[0];
4549 dst
->u64
[1] = (uint64_t)src
->d
[1];
4550 dst
->u64
[2] = (uint64_t)src
->d
[2];
4551 dst
->u64
[3] = (uint64_t)src
->d
[3];
4555 micro_d2i64(union tgsi_double_channel
*dst
,
4556 const union tgsi_double_channel
*src
)
4558 dst
->i64
[0] = (int64_t)src
->d
[0];
4559 dst
->i64
[1] = (int64_t)src
->d
[1];
4560 dst
->i64
[2] = (int64_t)src
->d
[2];
4561 dst
->i64
[3] = (int64_t)src
->d
[3];
4565 micro_u642d(union tgsi_double_channel
*dst
,
4566 const union tgsi_double_channel
*src
)
4568 dst
->d
[0] = (double)src
->u64
[0];
4569 dst
->d
[1] = (double)src
->u64
[1];
4570 dst
->d
[2] = (double)src
->u64
[2];
4571 dst
->d
[3] = (double)src
->u64
[3];
4575 micro_i642d(union tgsi_double_channel
*dst
,
4576 const union tgsi_double_channel
*src
)
4578 dst
->d
[0] = (double)src
->i64
[0];
4579 dst
->d
[1] = (double)src
->i64
[1];
4580 dst
->d
[2] = (double)src
->i64
[2];
4581 dst
->d
[3] = (double)src
->i64
[3];
4585 micro_u642f(union tgsi_exec_channel
*dst
,
4586 const union tgsi_double_channel
*src
)
4588 dst
->f
[0] = (float)src
->u64
[0];
4589 dst
->f
[1] = (float)src
->u64
[1];
4590 dst
->f
[2] = (float)src
->u64
[2];
4591 dst
->f
[3] = (float)src
->u64
[3];
4595 micro_i642f(union tgsi_exec_channel
*dst
,
4596 const union tgsi_double_channel
*src
)
4598 dst
->f
[0] = (float)src
->i64
[0];
4599 dst
->f
[1] = (float)src
->i64
[1];
4600 dst
->f
[2] = (float)src
->i64
[2];
4601 dst
->f
[3] = (float)src
->i64
[3];
4605 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4606 const struct tgsi_full_instruction
*inst
,
4608 enum tgsi_exec_datatype src_datatype
)
4610 union tgsi_exec_channel src
;
4611 union tgsi_double_channel dst
;
4613 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4614 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4616 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4618 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4619 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4621 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4626 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4627 const struct tgsi_full_instruction
*inst
,
4629 enum tgsi_exec_datatype dst_datatype
)
4631 union tgsi_double_channel src
;
4632 union tgsi_exec_channel dst
;
4633 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4636 for (i
= 0; i
< 2; i
++) {
4639 wm
&= ~(1 << (bit
- 1));
4641 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4643 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4645 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4651 micro_i2f(union tgsi_exec_channel
*dst
,
4652 const union tgsi_exec_channel
*src
)
4654 dst
->f
[0] = (float)src
->i
[0];
4655 dst
->f
[1] = (float)src
->i
[1];
4656 dst
->f
[2] = (float)src
->i
[2];
4657 dst
->f
[3] = (float)src
->i
[3];
4661 micro_not(union tgsi_exec_channel
*dst
,
4662 const union tgsi_exec_channel
*src
)
4664 dst
->u
[0] = ~src
->u
[0];
4665 dst
->u
[1] = ~src
->u
[1];
4666 dst
->u
[2] = ~src
->u
[2];
4667 dst
->u
[3] = ~src
->u
[3];
4671 micro_shl(union tgsi_exec_channel
*dst
,
4672 const union tgsi_exec_channel
*src0
,
4673 const union tgsi_exec_channel
*src1
)
4675 unsigned masked_count
;
4676 masked_count
= src1
->u
[0] & 0x1f;
4677 dst
->u
[0] = src0
->u
[0] << masked_count
;
4678 masked_count
= src1
->u
[1] & 0x1f;
4679 dst
->u
[1] = src0
->u
[1] << masked_count
;
4680 masked_count
= src1
->u
[2] & 0x1f;
4681 dst
->u
[2] = src0
->u
[2] << masked_count
;
4682 masked_count
= src1
->u
[3] & 0x1f;
4683 dst
->u
[3] = src0
->u
[3] << masked_count
;
4687 micro_and(union tgsi_exec_channel
*dst
,
4688 const union tgsi_exec_channel
*src0
,
4689 const union tgsi_exec_channel
*src1
)
4691 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4692 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4693 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4694 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4698 micro_or(union tgsi_exec_channel
*dst
,
4699 const union tgsi_exec_channel
*src0
,
4700 const union tgsi_exec_channel
*src1
)
4702 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4703 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4704 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4705 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4709 micro_xor(union tgsi_exec_channel
*dst
,
4710 const union tgsi_exec_channel
*src0
,
4711 const union tgsi_exec_channel
*src1
)
4713 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4714 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4715 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4716 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4720 micro_mod(union tgsi_exec_channel
*dst
,
4721 const union tgsi_exec_channel
*src0
,
4722 const union tgsi_exec_channel
*src1
)
4724 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] % src1
->i
[0] : ~0;
4725 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] % src1
->i
[1] : ~0;
4726 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] % src1
->i
[2] : ~0;
4727 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] % src1
->i
[3] : ~0;
4731 micro_f2i(union tgsi_exec_channel
*dst
,
4732 const union tgsi_exec_channel
*src
)
4734 dst
->i
[0] = (int)src
->f
[0];
4735 dst
->i
[1] = (int)src
->f
[1];
4736 dst
->i
[2] = (int)src
->f
[2];
4737 dst
->i
[3] = (int)src
->f
[3];
4741 micro_fseq(union tgsi_exec_channel
*dst
,
4742 const union tgsi_exec_channel
*src0
,
4743 const union tgsi_exec_channel
*src1
)
4745 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4746 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4747 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4748 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4752 micro_fsge(union tgsi_exec_channel
*dst
,
4753 const union tgsi_exec_channel
*src0
,
4754 const union tgsi_exec_channel
*src1
)
4756 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4757 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4758 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4759 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4763 micro_fslt(union tgsi_exec_channel
*dst
,
4764 const union tgsi_exec_channel
*src0
,
4765 const union tgsi_exec_channel
*src1
)
4767 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4768 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4769 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4770 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4774 micro_fsne(union tgsi_exec_channel
*dst
,
4775 const union tgsi_exec_channel
*src0
,
4776 const union tgsi_exec_channel
*src1
)
4778 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4779 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4780 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4781 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4785 micro_idiv(union tgsi_exec_channel
*dst
,
4786 const union tgsi_exec_channel
*src0
,
4787 const union tgsi_exec_channel
*src1
)
4789 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4790 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4791 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4792 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4796 micro_imax(union tgsi_exec_channel
*dst
,
4797 const union tgsi_exec_channel
*src0
,
4798 const union tgsi_exec_channel
*src1
)
4800 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4801 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4802 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4803 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4807 micro_imin(union tgsi_exec_channel
*dst
,
4808 const union tgsi_exec_channel
*src0
,
4809 const union tgsi_exec_channel
*src1
)
4811 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4812 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4813 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4814 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4818 micro_isge(union tgsi_exec_channel
*dst
,
4819 const union tgsi_exec_channel
*src0
,
4820 const union tgsi_exec_channel
*src1
)
4822 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4823 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4824 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4825 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4829 micro_ishr(union tgsi_exec_channel
*dst
,
4830 const union tgsi_exec_channel
*src0
,
4831 const union tgsi_exec_channel
*src1
)
4833 unsigned masked_count
;
4834 masked_count
= src1
->i
[0] & 0x1f;
4835 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4836 masked_count
= src1
->i
[1] & 0x1f;
4837 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4838 masked_count
= src1
->i
[2] & 0x1f;
4839 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4840 masked_count
= src1
->i
[3] & 0x1f;
4841 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4845 micro_islt(union tgsi_exec_channel
*dst
,
4846 const union tgsi_exec_channel
*src0
,
4847 const union tgsi_exec_channel
*src1
)
4849 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4850 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4851 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4852 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4856 micro_f2u(union tgsi_exec_channel
*dst
,
4857 const union tgsi_exec_channel
*src
)
4859 dst
->u
[0] = (uint
)src
->f
[0];
4860 dst
->u
[1] = (uint
)src
->f
[1];
4861 dst
->u
[2] = (uint
)src
->f
[2];
4862 dst
->u
[3] = (uint
)src
->f
[3];
4866 micro_u2f(union tgsi_exec_channel
*dst
,
4867 const union tgsi_exec_channel
*src
)
4869 dst
->f
[0] = (float)src
->u
[0];
4870 dst
->f
[1] = (float)src
->u
[1];
4871 dst
->f
[2] = (float)src
->u
[2];
4872 dst
->f
[3] = (float)src
->u
[3];
4876 micro_uadd(union tgsi_exec_channel
*dst
,
4877 const union tgsi_exec_channel
*src0
,
4878 const union tgsi_exec_channel
*src1
)
4880 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4881 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4882 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4883 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4887 micro_udiv(union tgsi_exec_channel
*dst
,
4888 const union tgsi_exec_channel
*src0
,
4889 const union tgsi_exec_channel
*src1
)
4891 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4892 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4893 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4894 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4898 micro_umad(union tgsi_exec_channel
*dst
,
4899 const union tgsi_exec_channel
*src0
,
4900 const union tgsi_exec_channel
*src1
,
4901 const union tgsi_exec_channel
*src2
)
4903 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4904 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4905 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4906 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4910 micro_umax(union tgsi_exec_channel
*dst
,
4911 const union tgsi_exec_channel
*src0
,
4912 const union tgsi_exec_channel
*src1
)
4914 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4915 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4916 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4917 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4921 micro_umin(union tgsi_exec_channel
*dst
,
4922 const union tgsi_exec_channel
*src0
,
4923 const union tgsi_exec_channel
*src1
)
4925 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4926 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4927 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4928 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4932 micro_umod(union tgsi_exec_channel
*dst
,
4933 const union tgsi_exec_channel
*src0
,
4934 const union tgsi_exec_channel
*src1
)
4936 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4937 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4938 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4939 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4943 micro_umul(union tgsi_exec_channel
*dst
,
4944 const union tgsi_exec_channel
*src0
,
4945 const union tgsi_exec_channel
*src1
)
4947 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4948 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4949 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4950 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4954 micro_imul_hi(union tgsi_exec_channel
*dst
,
4955 const union tgsi_exec_channel
*src0
,
4956 const union tgsi_exec_channel
*src1
)
4958 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4959 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4960 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4961 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4962 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4967 micro_umul_hi(union tgsi_exec_channel
*dst
,
4968 const union tgsi_exec_channel
*src0
,
4969 const union tgsi_exec_channel
*src1
)
4971 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4972 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4973 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4974 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4975 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4980 micro_useq(union tgsi_exec_channel
*dst
,
4981 const union tgsi_exec_channel
*src0
,
4982 const union tgsi_exec_channel
*src1
)
4984 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4985 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4986 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4987 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4991 micro_usge(union tgsi_exec_channel
*dst
,
4992 const union tgsi_exec_channel
*src0
,
4993 const union tgsi_exec_channel
*src1
)
4995 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4996 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4997 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4998 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
5002 micro_ushr(union tgsi_exec_channel
*dst
,
5003 const union tgsi_exec_channel
*src0
,
5004 const union tgsi_exec_channel
*src1
)
5006 unsigned masked_count
;
5007 masked_count
= src1
->u
[0] & 0x1f;
5008 dst
->u
[0] = src0
->u
[0] >> masked_count
;
5009 masked_count
= src1
->u
[1] & 0x1f;
5010 dst
->u
[1] = src0
->u
[1] >> masked_count
;
5011 masked_count
= src1
->u
[2] & 0x1f;
5012 dst
->u
[2] = src0
->u
[2] >> masked_count
;
5013 masked_count
= src1
->u
[3] & 0x1f;
5014 dst
->u
[3] = src0
->u
[3] >> masked_count
;
5018 micro_uslt(union tgsi_exec_channel
*dst
,
5019 const union tgsi_exec_channel
*src0
,
5020 const union tgsi_exec_channel
*src1
)
5022 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
5023 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
5024 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
5025 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
5029 micro_usne(union tgsi_exec_channel
*dst
,
5030 const union tgsi_exec_channel
*src0
,
5031 const union tgsi_exec_channel
*src1
)
5033 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
5034 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
5035 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
5036 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
5040 micro_uarl(union tgsi_exec_channel
*dst
,
5041 const union tgsi_exec_channel
*src
)
5043 dst
->i
[0] = src
->u
[0];
5044 dst
->i
[1] = src
->u
[1];
5045 dst
->i
[2] = src
->u
[2];
5046 dst
->i
[3] = src
->u
[3];
5050 * Signed bitfield extract (i.e. sign-extend the extracted bits)
5053 micro_ibfe(union tgsi_exec_channel
*dst
,
5054 const union tgsi_exec_channel
*src0
,
5055 const union tgsi_exec_channel
*src1
,
5056 const union tgsi_exec_channel
*src2
)
5059 for (i
= 0; i
< 4; i
++) {
5060 int width
= src2
->i
[i
];
5061 int offset
= src1
->i
[i
] & 0x1f;
5062 if (width
== 32 && offset
== 0) {
5063 dst
->i
[i
] = src0
->i
[i
];
5069 else if (width
+ offset
< 32)
5070 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
5072 dst
->i
[i
] = src0
->i
[i
] >> offset
;
5077 * Unsigned bitfield extract
5080 micro_ubfe(union tgsi_exec_channel
*dst
,
5081 const union tgsi_exec_channel
*src0
,
5082 const union tgsi_exec_channel
*src1
,
5083 const union tgsi_exec_channel
*src2
)
5086 for (i
= 0; i
< 4; i
++) {
5087 int width
= src2
->u
[i
];
5088 int offset
= src1
->u
[i
] & 0x1f;
5089 if (width
== 32 && offset
== 0) {
5090 dst
->u
[i
] = src0
->u
[i
];
5096 else if (width
+ offset
< 32)
5097 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
5099 dst
->u
[i
] = src0
->u
[i
] >> offset
;
5104 * Bitfield insert: copy low bits from src1 into a region of src0.
5107 micro_bfi(union tgsi_exec_channel
*dst
,
5108 const union tgsi_exec_channel
*src0
,
5109 const union tgsi_exec_channel
*src1
,
5110 const union tgsi_exec_channel
*src2
,
5111 const union tgsi_exec_channel
*src3
)
5114 for (i
= 0; i
< 4; i
++) {
5115 int width
= src3
->u
[i
];
5116 int offset
= src2
->u
[i
] & 0x1f;
5118 dst
->u
[i
] = src1
->u
[i
];
5120 int bitmask
= ((1 << width
) - 1) << offset
;
5121 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
5127 micro_brev(union tgsi_exec_channel
*dst
,
5128 const union tgsi_exec_channel
*src
)
5130 dst
->u
[0] = util_bitreverse(src
->u
[0]);
5131 dst
->u
[1] = util_bitreverse(src
->u
[1]);
5132 dst
->u
[2] = util_bitreverse(src
->u
[2]);
5133 dst
->u
[3] = util_bitreverse(src
->u
[3]);
5137 micro_popc(union tgsi_exec_channel
*dst
,
5138 const union tgsi_exec_channel
*src
)
5140 dst
->u
[0] = util_bitcount(src
->u
[0]);
5141 dst
->u
[1] = util_bitcount(src
->u
[1]);
5142 dst
->u
[2] = util_bitcount(src
->u
[2]);
5143 dst
->u
[3] = util_bitcount(src
->u
[3]);
5147 micro_lsb(union tgsi_exec_channel
*dst
,
5148 const union tgsi_exec_channel
*src
)
5150 dst
->i
[0] = ffs(src
->u
[0]) - 1;
5151 dst
->i
[1] = ffs(src
->u
[1]) - 1;
5152 dst
->i
[2] = ffs(src
->u
[2]) - 1;
5153 dst
->i
[3] = ffs(src
->u
[3]) - 1;
5157 micro_imsb(union tgsi_exec_channel
*dst
,
5158 const union tgsi_exec_channel
*src
)
5160 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
5161 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
5162 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
5163 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
5167 micro_umsb(union tgsi_exec_channel
*dst
,
5168 const union tgsi_exec_channel
*src
)
5170 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
5171 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
5172 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5173 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5178 exec_interp_at_sample(struct tgsi_exec_machine
*mach
,
5179 const struct tgsi_full_instruction
*inst
)
5181 union tgsi_exec_channel index
;
5182 union tgsi_exec_channel index2D
;
5183 union tgsi_exec_channel result
[TGSI_NUM_CHANNELS
];
5184 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5186 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5187 assert(inst
->Src
[1].Register
.File
== TGSI_FILE_IMMEDIATE
);
5189 get_index_registers(mach
, reg
, &index
, &index2D
);
5190 float sample
= mach
->Imms
[inst
->Src
[1].Register
.Index
][inst
->Src
[1].Register
.SwizzleX
];
5192 /* Short cut: sample 0 is like a normal fetch */
5193 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5194 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5197 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
,
5199 if (sample
!= 0.0f
) {
5201 /* TODO: define the samples > 0, but so far we only do fake MSAA */
5205 unsigned pos
= index2D
.i
[chan
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
.i
[chan
];
5207 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
5208 mach
->InputSampleOffsetApply
[pos
](mach
, pos
, chan
, x
, y
, &result
[chan
]);
5210 store_dest(mach
, &result
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5216 exec_interp_at_offset(struct tgsi_exec_machine
*mach
,
5217 const struct tgsi_full_instruction
*inst
)
5219 union tgsi_exec_channel index
;
5220 union tgsi_exec_channel index2D
;
5221 union tgsi_exec_channel ofsx
;
5222 union tgsi_exec_channel ofsy
;
5223 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5225 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5227 get_index_registers(mach
, reg
, &index
, &index2D
);
5228 unsigned pos
= index2D
.i
[0] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
.i
[0];
5230 fetch_source(mach
, &ofsx
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
5231 fetch_source(mach
, &ofsy
, &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
5233 for (int chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5234 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5236 union tgsi_exec_channel result
;
5237 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
, &result
);
5238 mach
->InputSampleOffsetApply
[pos
](mach
, pos
, chan
, ofsx
.f
[chan
], ofsy
.f
[chan
], &result
);
5239 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5245 exec_interp_at_centroid(struct tgsi_exec_machine
*mach
,
5246 const struct tgsi_full_instruction
*inst
)
5248 union tgsi_exec_channel index
;
5249 union tgsi_exec_channel index2D
;
5250 union tgsi_exec_channel result
[TGSI_NUM_CHANNELS
];
5251 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5253 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5254 get_index_registers(mach
, reg
, &index
, &index2D
);
5256 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5257 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5260 /* Here we should add the change to use a sample that lies within the
5261 * primitive (Section 15.2):
5263 * "When interpolating variables declared using centroid in ,
5264 * the variable is sampled at a location within the pixel covered
5265 * by the primitive generating the fragment.
5267 * The built-in functions interpolateAtCentroid ... will sample
5268 * variables as though they were declared with the centroid ...
5271 * Since we only support 1 sample currently, this is just a pass-through.
5273 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
,
5275 store_dest(mach
, &result
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5282 * Execute a TGSI instruction.
5283 * Returns TRUE if a barrier instruction is hit,
5288 struct tgsi_exec_machine
*mach
,
5289 const struct tgsi_full_instruction
*inst
,
5292 union tgsi_exec_channel r
[10];
5296 switch (inst
->Instruction
.Opcode
) {
5297 case TGSI_OPCODE_ARL
:
5298 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5301 case TGSI_OPCODE_MOV
:
5302 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5305 case TGSI_OPCODE_LIT
:
5306 exec_lit(mach
, inst
);
5309 case TGSI_OPCODE_RCP
:
5310 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5313 case TGSI_OPCODE_RSQ
:
5314 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5317 case TGSI_OPCODE_EXP
:
5318 exec_exp(mach
, inst
);
5321 case TGSI_OPCODE_LOG
:
5322 exec_log(mach
, inst
);
5325 case TGSI_OPCODE_MUL
:
5326 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5329 case TGSI_OPCODE_ADD
:
5330 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5333 case TGSI_OPCODE_DP3
:
5334 exec_dp3(mach
, inst
);
5337 case TGSI_OPCODE_DP4
:
5338 exec_dp4(mach
, inst
);
5341 case TGSI_OPCODE_DST
:
5342 exec_dst(mach
, inst
);
5345 case TGSI_OPCODE_MIN
:
5346 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5349 case TGSI_OPCODE_MAX
:
5350 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5353 case TGSI_OPCODE_SLT
:
5354 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5357 case TGSI_OPCODE_SGE
:
5358 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5361 case TGSI_OPCODE_MAD
:
5362 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5365 case TGSI_OPCODE_LRP
:
5366 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5369 case TGSI_OPCODE_SQRT
:
5370 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5373 case TGSI_OPCODE_FRC
:
5374 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5377 case TGSI_OPCODE_FLR
:
5378 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5381 case TGSI_OPCODE_ROUND
:
5382 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5385 case TGSI_OPCODE_EX2
:
5386 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5389 case TGSI_OPCODE_LG2
:
5390 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5393 case TGSI_OPCODE_POW
:
5394 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5397 case TGSI_OPCODE_LDEXP
:
5398 exec_vector_binary(mach
, inst
, micro_ldexp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5401 case TGSI_OPCODE_COS
:
5402 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5405 case TGSI_OPCODE_DDX_FINE
:
5406 exec_vector_unary(mach
, inst
, micro_ddx_fine
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5409 case TGSI_OPCODE_DDX
:
5410 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5413 case TGSI_OPCODE_DDY_FINE
:
5414 exec_vector_unary(mach
, inst
, micro_ddy_fine
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5417 case TGSI_OPCODE_DDY
:
5418 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5421 case TGSI_OPCODE_KILL
:
5425 case TGSI_OPCODE_KILL_IF
:
5426 exec_kill_if (mach
, inst
);
5429 case TGSI_OPCODE_PK2H
:
5430 exec_pk2h(mach
, inst
);
5433 case TGSI_OPCODE_PK2US
:
5437 case TGSI_OPCODE_PK4B
:
5441 case TGSI_OPCODE_PK4UB
:
5445 case TGSI_OPCODE_SEQ
:
5446 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5449 case TGSI_OPCODE_SGT
:
5450 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5453 case TGSI_OPCODE_SIN
:
5454 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5457 case TGSI_OPCODE_SLE
:
5458 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5461 case TGSI_OPCODE_SNE
:
5462 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5465 case TGSI_OPCODE_TEX
:
5466 /* simple texture lookup */
5467 /* src[0] = texcoord */
5468 /* src[1] = sampler unit */
5469 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5472 case TGSI_OPCODE_TXB
:
5473 /* Texture lookup with lod bias */
5474 /* src[0] = texcoord (src[0].w = LOD bias) */
5475 /* src[1] = sampler unit */
5476 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5479 case TGSI_OPCODE_TXD
:
5480 /* Texture lookup with explict partial derivatives */
5481 /* src[0] = texcoord */
5482 /* src[1] = d[strq]/dx */
5483 /* src[2] = d[strq]/dy */
5484 /* src[3] = sampler unit */
5485 exec_txd(mach
, inst
);
5488 case TGSI_OPCODE_TXL
:
5489 /* Texture lookup with explit LOD */
5490 /* src[0] = texcoord (src[0].w = LOD) */
5491 /* src[1] = sampler unit */
5492 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5495 case TGSI_OPCODE_TXP
:
5496 /* Texture lookup with projection */
5497 /* src[0] = texcoord (src[0].w = projection) */
5498 /* src[1] = sampler unit */
5499 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5502 case TGSI_OPCODE_TG4
:
5503 /* src[0] = texcoord */
5504 /* src[1] = component */
5505 /* src[2] = sampler unit */
5506 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5509 case TGSI_OPCODE_LODQ
:
5510 /* src[0] = texcoord */
5511 /* src[1] = sampler unit */
5512 exec_lodq(mach
, inst
);
5515 case TGSI_OPCODE_UP2H
:
5516 exec_up2h(mach
, inst
);
5519 case TGSI_OPCODE_UP2US
:
5523 case TGSI_OPCODE_UP4B
:
5527 case TGSI_OPCODE_UP4UB
:
5531 case TGSI_OPCODE_ARR
:
5532 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5535 case TGSI_OPCODE_CAL
:
5536 /* skip the call if no execution channels are enabled */
5537 if (mach
->ExecMask
) {
5540 /* First, record the depths of the execution stacks.
5541 * This is important for deeply nested/looped return statements.
5542 * We have to unwind the stacks by the correct amount. For a
5543 * real code generator, we could determine the number of entries
5544 * to pop off each stack with simple static analysis and avoid
5545 * implementing this data structure at run time.
5547 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5548 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5549 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5550 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5551 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5552 /* note that PC was already incremented above */
5553 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5555 mach
->CallStackTop
++;
5557 /* Second, push the Cond, Loop, Cont, Func stacks */
5558 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5559 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5560 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5561 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5562 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5563 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5565 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5566 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5567 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5568 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5569 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5570 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5572 /* Finally, jump to the subroutine. The label is a pointer
5573 * (an instruction number) to the BGNSUB instruction.
5575 *pc
= inst
->Label
.Label
;
5576 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5577 == TGSI_OPCODE_BGNSUB
);
5581 case TGSI_OPCODE_RET
:
5582 mach
->FuncMask
&= ~mach
->ExecMask
;
5583 UPDATE_EXEC_MASK(mach
);
5585 if (mach
->FuncMask
== 0x0) {
5586 /* really return now (otherwise, keep executing */
5588 if (mach
->CallStackTop
== 0) {
5589 /* returning from main() */
5590 mach
->CondStackTop
= 0;
5591 mach
->LoopStackTop
= 0;
5592 mach
->ContStackTop
= 0;
5593 mach
->LoopLabelStackTop
= 0;
5594 mach
->SwitchStackTop
= 0;
5595 mach
->BreakStackTop
= 0;
5600 assert(mach
->CallStackTop
> 0);
5601 mach
->CallStackTop
--;
5603 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5604 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5606 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5607 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5609 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5610 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5612 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5613 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5615 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5616 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5618 assert(mach
->FuncStackTop
> 0);
5619 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5621 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5623 UPDATE_EXEC_MASK(mach
);
5627 case TGSI_OPCODE_SSG
:
5628 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5631 case TGSI_OPCODE_CMP
:
5632 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5635 case TGSI_OPCODE_DIV
:
5636 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5639 case TGSI_OPCODE_DP2
:
5640 exec_dp2(mach
, inst
);
5643 case TGSI_OPCODE_IF
:
5645 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5646 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5647 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5648 /* update CondMask */
5650 mach
->CondMask
&= ~0x1;
5653 mach
->CondMask
&= ~0x2;
5656 mach
->CondMask
&= ~0x4;
5659 mach
->CondMask
&= ~0x8;
5661 UPDATE_EXEC_MASK(mach
);
5662 /* Todo: If CondMask==0, jump to ELSE */
5665 case TGSI_OPCODE_UIF
:
5667 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5668 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5669 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5670 /* update CondMask */
5672 mach
->CondMask
&= ~0x1;
5675 mach
->CondMask
&= ~0x2;
5678 mach
->CondMask
&= ~0x4;
5681 mach
->CondMask
&= ~0x8;
5683 UPDATE_EXEC_MASK(mach
);
5684 /* Todo: If CondMask==0, jump to ELSE */
5687 case TGSI_OPCODE_ELSE
:
5688 /* invert CondMask wrt previous mask */
5691 assert(mach
->CondStackTop
> 0);
5692 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5693 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5694 UPDATE_EXEC_MASK(mach
);
5695 /* Todo: If CondMask==0, jump to ENDIF */
5699 case TGSI_OPCODE_ENDIF
:
5701 assert(mach
->CondStackTop
> 0);
5702 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5703 UPDATE_EXEC_MASK(mach
);
5706 case TGSI_OPCODE_END
:
5707 /* make sure we end primitives which haven't
5708 * been explicitly emitted */
5709 conditional_emit_primitive(mach
);
5710 /* halt execution */
5714 case TGSI_OPCODE_CEIL
:
5715 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5718 case TGSI_OPCODE_I2F
:
5719 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5722 case TGSI_OPCODE_NOT
:
5723 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5726 case TGSI_OPCODE_TRUNC
:
5727 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5730 case TGSI_OPCODE_SHL
:
5731 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5734 case TGSI_OPCODE_AND
:
5735 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5738 case TGSI_OPCODE_OR
:
5739 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5742 case TGSI_OPCODE_MOD
:
5743 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5746 case TGSI_OPCODE_XOR
:
5747 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5750 case TGSI_OPCODE_TXF
:
5751 exec_txf(mach
, inst
);
5754 case TGSI_OPCODE_TXQ
:
5755 exec_txq(mach
, inst
);
5758 case TGSI_OPCODE_EMIT
:
5759 emit_vertex(mach
, inst
);
5762 case TGSI_OPCODE_ENDPRIM
:
5763 emit_primitive(mach
, inst
);
5766 case TGSI_OPCODE_BGNLOOP
:
5767 /* push LoopMask and ContMasks */
5768 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5769 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5770 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5771 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5773 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5774 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5775 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5776 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5777 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5780 case TGSI_OPCODE_ENDLOOP
:
5781 /* Restore ContMask, but don't pop */
5782 assert(mach
->ContStackTop
> 0);
5783 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5784 UPDATE_EXEC_MASK(mach
);
5785 if (mach
->ExecMask
) {
5786 /* repeat loop: jump to instruction just past BGNLOOP */
5787 assert(mach
->LoopLabelStackTop
> 0);
5788 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5791 /* exit loop: pop LoopMask */
5792 assert(mach
->LoopStackTop
> 0);
5793 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5795 assert(mach
->ContStackTop
> 0);
5796 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5797 assert(mach
->LoopLabelStackTop
> 0);
5798 --mach
->LoopLabelStackTop
;
5800 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5802 UPDATE_EXEC_MASK(mach
);
5805 case TGSI_OPCODE_BRK
:
5809 case TGSI_OPCODE_CONT
:
5810 /* turn off cont channels for each enabled exec channel */
5811 mach
->ContMask
&= ~mach
->ExecMask
;
5812 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5813 UPDATE_EXEC_MASK(mach
);
5816 case TGSI_OPCODE_BGNSUB
:
5820 case TGSI_OPCODE_ENDSUB
:
5822 * XXX: This really should be a no-op. We should never reach this opcode.
5825 assert(mach
->CallStackTop
> 0);
5826 mach
->CallStackTop
--;
5828 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5829 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5831 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5832 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5834 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5835 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5837 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5838 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5840 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5841 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5843 assert(mach
->FuncStackTop
> 0);
5844 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5846 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5848 UPDATE_EXEC_MASK(mach
);
5851 case TGSI_OPCODE_NOP
:
5854 case TGSI_OPCODE_F2I
:
5855 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5858 case TGSI_OPCODE_FSEQ
:
5859 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5862 case TGSI_OPCODE_FSGE
:
5863 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5866 case TGSI_OPCODE_FSLT
:
5867 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5870 case TGSI_OPCODE_FSNE
:
5871 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5874 case TGSI_OPCODE_IDIV
:
5875 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5878 case TGSI_OPCODE_IMAX
:
5879 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5882 case TGSI_OPCODE_IMIN
:
5883 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5886 case TGSI_OPCODE_INEG
:
5887 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5890 case TGSI_OPCODE_ISGE
:
5891 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5894 case TGSI_OPCODE_ISHR
:
5895 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5898 case TGSI_OPCODE_ISLT
:
5899 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5902 case TGSI_OPCODE_F2U
:
5903 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5906 case TGSI_OPCODE_U2F
:
5907 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5910 case TGSI_OPCODE_UADD
:
5911 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5914 case TGSI_OPCODE_UDIV
:
5915 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5918 case TGSI_OPCODE_UMAD
:
5919 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5922 case TGSI_OPCODE_UMAX
:
5923 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5926 case TGSI_OPCODE_UMIN
:
5927 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5930 case TGSI_OPCODE_UMOD
:
5931 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5934 case TGSI_OPCODE_UMUL
:
5935 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5938 case TGSI_OPCODE_IMUL_HI
:
5939 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5942 case TGSI_OPCODE_UMUL_HI
:
5943 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5946 case TGSI_OPCODE_USEQ
:
5947 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5950 case TGSI_OPCODE_USGE
:
5951 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5954 case TGSI_OPCODE_USHR
:
5955 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5958 case TGSI_OPCODE_USLT
:
5959 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5962 case TGSI_OPCODE_USNE
:
5963 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5966 case TGSI_OPCODE_SWITCH
:
5967 exec_switch(mach
, inst
);
5970 case TGSI_OPCODE_CASE
:
5971 exec_case(mach
, inst
);
5974 case TGSI_OPCODE_DEFAULT
:
5978 case TGSI_OPCODE_ENDSWITCH
:
5979 exec_endswitch(mach
);
5982 case TGSI_OPCODE_SAMPLE_I
:
5983 exec_txf(mach
, inst
);
5986 case TGSI_OPCODE_SAMPLE_I_MS
:
5987 exec_txf(mach
, inst
);
5990 case TGSI_OPCODE_SAMPLE
:
5991 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5994 case TGSI_OPCODE_SAMPLE_B
:
5995 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5998 case TGSI_OPCODE_SAMPLE_C
:
5999 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
6002 case TGSI_OPCODE_SAMPLE_C_LZ
:
6003 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
6006 case TGSI_OPCODE_SAMPLE_D
:
6007 exec_sample_d(mach
, inst
);
6010 case TGSI_OPCODE_SAMPLE_L
:
6011 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
6014 case TGSI_OPCODE_GATHER4
:
6015 exec_sample(mach
, inst
, TEX_MODIFIER_GATHER
, FALSE
);
6018 case TGSI_OPCODE_SVIEWINFO
:
6019 exec_txq(mach
, inst
);
6022 case TGSI_OPCODE_SAMPLE_POS
:
6026 case TGSI_OPCODE_SAMPLE_INFO
:
6030 case TGSI_OPCODE_LOD
:
6031 exec_lodq(mach
, inst
);
6034 case TGSI_OPCODE_UARL
:
6035 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
6038 case TGSI_OPCODE_UCMP
:
6039 exec_ucmp(mach
, inst
);
6042 case TGSI_OPCODE_IABS
:
6043 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
6046 case TGSI_OPCODE_ISSG
:
6047 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
6050 case TGSI_OPCODE_TEX2
:
6051 /* simple texture lookup */
6052 /* src[0] = texcoord */
6053 /* src[1] = compare */
6054 /* src[2] = sampler unit */
6055 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
6057 case TGSI_OPCODE_TXB2
:
6058 /* simple texture lookup */
6059 /* src[0] = texcoord */
6061 /* src[2] = sampler unit */
6062 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
6064 case TGSI_OPCODE_TXL2
:
6065 /* simple texture lookup */
6066 /* src[0] = texcoord */
6068 /* src[2] = sampler unit */
6069 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
6072 case TGSI_OPCODE_IBFE
:
6073 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
6075 case TGSI_OPCODE_UBFE
:
6076 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6078 case TGSI_OPCODE_BFI
:
6079 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6081 case TGSI_OPCODE_BREV
:
6082 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6084 case TGSI_OPCODE_POPC
:
6085 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6087 case TGSI_OPCODE_LSB
:
6088 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
6090 case TGSI_OPCODE_IMSB
:
6091 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
6093 case TGSI_OPCODE_UMSB
:
6094 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
6097 case TGSI_OPCODE_F2D
:
6098 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
6101 case TGSI_OPCODE_D2F
:
6102 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
6105 case TGSI_OPCODE_DABS
:
6106 exec_double_unary(mach
, inst
, micro_dabs
);
6109 case TGSI_OPCODE_DNEG
:
6110 exec_double_unary(mach
, inst
, micro_dneg
);
6113 case TGSI_OPCODE_DADD
:
6114 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
6117 case TGSI_OPCODE_DDIV
:
6118 exec_double_binary(mach
, inst
, micro_ddiv
, TGSI_EXEC_DATA_DOUBLE
);
6121 case TGSI_OPCODE_DMUL
:
6122 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
6125 case TGSI_OPCODE_DMAX
:
6126 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
6129 case TGSI_OPCODE_DMIN
:
6130 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
6133 case TGSI_OPCODE_DSLT
:
6134 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
6137 case TGSI_OPCODE_DSGE
:
6138 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
6141 case TGSI_OPCODE_DSEQ
:
6142 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
6145 case TGSI_OPCODE_DSNE
:
6146 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
6149 case TGSI_OPCODE_DRCP
:
6150 exec_double_unary(mach
, inst
, micro_drcp
);
6153 case TGSI_OPCODE_DSQRT
:
6154 exec_double_unary(mach
, inst
, micro_dsqrt
);
6157 case TGSI_OPCODE_DRSQ
:
6158 exec_double_unary(mach
, inst
, micro_drsq
);
6161 case TGSI_OPCODE_DMAD
:
6162 exec_double_trinary(mach
, inst
, micro_dmad
);
6165 case TGSI_OPCODE_DFRAC
:
6166 exec_double_unary(mach
, inst
, micro_dfrac
);
6169 case TGSI_OPCODE_DLDEXP
:
6170 exec_dldexp(mach
, inst
);
6173 case TGSI_OPCODE_DFRACEXP
:
6174 exec_dfracexp(mach
, inst
);
6177 case TGSI_OPCODE_I2D
:
6178 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
6181 case TGSI_OPCODE_D2I
:
6182 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
6185 case TGSI_OPCODE_U2D
:
6186 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
6189 case TGSI_OPCODE_D2U
:
6190 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
6193 case TGSI_OPCODE_LOAD
:
6194 exec_load(mach
, inst
);
6197 case TGSI_OPCODE_STORE
:
6198 exec_store(mach
, inst
);
6201 case TGSI_OPCODE_ATOMUADD
:
6202 case TGSI_OPCODE_ATOMXCHG
:
6203 case TGSI_OPCODE_ATOMCAS
:
6204 case TGSI_OPCODE_ATOMAND
:
6205 case TGSI_OPCODE_ATOMOR
:
6206 case TGSI_OPCODE_ATOMXOR
:
6207 case TGSI_OPCODE_ATOMUMIN
:
6208 case TGSI_OPCODE_ATOMUMAX
:
6209 case TGSI_OPCODE_ATOMIMIN
:
6210 case TGSI_OPCODE_ATOMIMAX
:
6211 case TGSI_OPCODE_ATOMFADD
:
6212 exec_atomop(mach
, inst
);
6215 case TGSI_OPCODE_RESQ
:
6216 exec_resq(mach
, inst
);
6218 case TGSI_OPCODE_BARRIER
:
6219 case TGSI_OPCODE_MEMBAR
:
6223 case TGSI_OPCODE_I64ABS
:
6224 exec_double_unary(mach
, inst
, micro_i64abs
);
6227 case TGSI_OPCODE_I64SSG
:
6228 exec_double_unary(mach
, inst
, micro_i64sgn
);
6231 case TGSI_OPCODE_I64NEG
:
6232 exec_double_unary(mach
, inst
, micro_i64neg
);
6235 case TGSI_OPCODE_U64SEQ
:
6236 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
6239 case TGSI_OPCODE_U64SNE
:
6240 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
6243 case TGSI_OPCODE_I64SLT
:
6244 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
6246 case TGSI_OPCODE_U64SLT
:
6247 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
6250 case TGSI_OPCODE_I64SGE
:
6251 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
6253 case TGSI_OPCODE_U64SGE
:
6254 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
6257 case TGSI_OPCODE_I64MIN
:
6258 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
6260 case TGSI_OPCODE_U64MIN
:
6261 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
6263 case TGSI_OPCODE_I64MAX
:
6264 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
6266 case TGSI_OPCODE_U64MAX
:
6267 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
6269 case TGSI_OPCODE_U64ADD
:
6270 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
6272 case TGSI_OPCODE_U64MUL
:
6273 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
6275 case TGSI_OPCODE_U64SHL
:
6276 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
6278 case TGSI_OPCODE_I64SHR
:
6279 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
6281 case TGSI_OPCODE_U64SHR
:
6282 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
6284 case TGSI_OPCODE_U64DIV
:
6285 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6287 case TGSI_OPCODE_I64DIV
:
6288 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6290 case TGSI_OPCODE_U64MOD
:
6291 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6293 case TGSI_OPCODE_I64MOD
:
6294 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6297 case TGSI_OPCODE_F2U64
:
6298 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6301 case TGSI_OPCODE_F2I64
:
6302 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6305 case TGSI_OPCODE_U2I64
:
6306 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6308 case TGSI_OPCODE_I2I64
:
6309 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6312 case TGSI_OPCODE_D2U64
:
6313 exec_double_unary(mach
, inst
, micro_d2u64
);
6316 case TGSI_OPCODE_D2I64
:
6317 exec_double_unary(mach
, inst
, micro_d2i64
);
6320 case TGSI_OPCODE_U642F
:
6321 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6323 case TGSI_OPCODE_I642F
:
6324 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6327 case TGSI_OPCODE_U642D
:
6328 exec_double_unary(mach
, inst
, micro_u642d
);
6330 case TGSI_OPCODE_I642D
:
6331 exec_double_unary(mach
, inst
, micro_i642d
);
6333 case TGSI_OPCODE_INTERP_SAMPLE
:
6334 exec_interp_at_sample(mach
, inst
);
6336 case TGSI_OPCODE_INTERP_OFFSET
:
6337 exec_interp_at_offset(mach
, inst
);
6339 case TGSI_OPCODE_INTERP_CENTROID
:
6340 exec_interp_at_centroid(mach
, inst
);
6349 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6351 uint default_mask
= 0xf;
6353 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6354 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6356 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6357 for (unsigned i
= 0; i
< TGSI_MAX_VERTEX_STREAMS
; i
++) {
6358 mach
->Temps
[temp_prim_idxs
[i
].idx
].xyzw
[temp_prim_idxs
[i
].chan
].u
[0] = 0;
6359 mach
->Primitives
[i
][0] = 0;
6361 /* GS runs on a single primitive for now */
6365 if (mach
->NonHelperMask
== 0)
6366 mach
->NonHelperMask
= default_mask
;
6367 mach
->CondMask
= default_mask
;
6368 mach
->LoopMask
= default_mask
;
6369 mach
->ContMask
= default_mask
;
6370 mach
->FuncMask
= default_mask
;
6371 mach
->ExecMask
= default_mask
;
6373 mach
->Switch
.mask
= default_mask
;
6375 assert(mach
->CondStackTop
== 0);
6376 assert(mach
->LoopStackTop
== 0);
6377 assert(mach
->ContStackTop
== 0);
6378 assert(mach
->SwitchStackTop
== 0);
6379 assert(mach
->BreakStackTop
== 0);
6380 assert(mach
->CallStackTop
== 0);
6384 * Run TGSI interpreter.
6385 * \return bitmask of "alive" quad components
6388 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6392 mach
->pc
= start_pc
;
6395 tgsi_exec_machine_setup_masks(mach
);
6397 /* execute declarations (interpolants) */
6398 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6399 exec_declaration( mach
, mach
->Declarations
+i
);
6405 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6406 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6410 memset(mach
->Temps
, 0, sizeof(temps
));
6412 memset(mach
->Outputs
, 0, sizeof(outputs
));
6413 memset(temps
, 0, sizeof(temps
));
6414 memset(outputs
, 0, sizeof(outputs
));
6418 /* execute instructions, until pc is set to -1 */
6419 while (mach
->pc
!= -1) {
6420 boolean barrier_hit
;
6424 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6427 assert(mach
->pc
< (int) mach
->NumInstructions
);
6428 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6430 /* for compute shaders if we hit a barrier return now for later rescheduling */
6431 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6435 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6436 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6439 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6440 debug_printf("TEMP[%2u] = ", i
);
6441 for (j
= 0; j
< 4; j
++) {
6445 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6446 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6447 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6448 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6449 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6453 if (mach
->Outputs
) {
6454 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6455 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6458 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6459 debug_printf("OUT[%2u] = ", i
);
6460 for (j
= 0; j
< 4; j
++) {
6464 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6465 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6466 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6467 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6468 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6478 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6479 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6481 * Scale back depth component.
6483 for (i
= 0; i
< 4; i
++)
6484 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6488 /* Strictly speaking, these assertions aren't really needed but they
6489 * can potentially catch some bugs in the control flow code.
6491 assert(mach
->CondStackTop
== 0);
6492 assert(mach
->LoopStackTop
== 0);
6493 assert(mach
->ContStackTop
== 0);
6494 assert(mach
->SwitchStackTop
== 0);
6495 assert(mach
->BreakStackTop
== 0);
6496 assert(mach
->CallStackTop
== 0);
6498 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];