1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
66 #define DEBUG_EXECUTION 0
71 #define TILE_TOP_LEFT 0
72 #define TILE_TOP_RIGHT 1
73 #define TILE_BOTTOM_LEFT 2
74 #define TILE_BOTTOM_RIGHT 3
76 union tgsi_double_channel
{
77 double d
[TGSI_QUAD_SIZE
];
78 unsigned u
[TGSI_QUAD_SIZE
][2];
81 struct tgsi_double_vector
{
82 union tgsi_double_channel xy
;
83 union tgsi_double_channel zw
;
87 micro_abs(union tgsi_exec_channel
*dst
,
88 const union tgsi_exec_channel
*src
)
90 dst
->f
[0] = fabsf(src
->f
[0]);
91 dst
->f
[1] = fabsf(src
->f
[1]);
92 dst
->f
[2] = fabsf(src
->f
[2]);
93 dst
->f
[3] = fabsf(src
->f
[3]);
97 micro_arl(union tgsi_exec_channel
*dst
,
98 const union tgsi_exec_channel
*src
)
100 dst
->i
[0] = (int)floorf(src
->f
[0]);
101 dst
->i
[1] = (int)floorf(src
->f
[1]);
102 dst
->i
[2] = (int)floorf(src
->f
[2]);
103 dst
->i
[3] = (int)floorf(src
->f
[3]);
107 micro_arr(union tgsi_exec_channel
*dst
,
108 const union tgsi_exec_channel
*src
)
110 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
111 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
112 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
113 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
117 micro_ceil(union tgsi_exec_channel
*dst
,
118 const union tgsi_exec_channel
*src
)
120 dst
->f
[0] = ceilf(src
->f
[0]);
121 dst
->f
[1] = ceilf(src
->f
[1]);
122 dst
->f
[2] = ceilf(src
->f
[2]);
123 dst
->f
[3] = ceilf(src
->f
[3]);
127 micro_clamp(union tgsi_exec_channel
*dst
,
128 const union tgsi_exec_channel
*src0
,
129 const union tgsi_exec_channel
*src1
,
130 const union tgsi_exec_channel
*src2
)
132 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
133 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
134 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
135 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
139 micro_cmp(union tgsi_exec_channel
*dst
,
140 const union tgsi_exec_channel
*src0
,
141 const union tgsi_exec_channel
*src1
,
142 const union tgsi_exec_channel
*src2
)
144 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
145 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
146 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
147 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
151 micro_cos(union tgsi_exec_channel
*dst
,
152 const union tgsi_exec_channel
*src
)
154 dst
->f
[0] = cosf(src
->f
[0]);
155 dst
->f
[1] = cosf(src
->f
[1]);
156 dst
->f
[2] = cosf(src
->f
[2]);
157 dst
->f
[3] = cosf(src
->f
[3]);
161 micro_d2f(union tgsi_exec_channel
*dst
,
162 const union tgsi_double_channel
*src
)
164 dst
->f
[0] = (float)src
->d
[0];
165 dst
->f
[1] = (float)src
->d
[1];
166 dst
->f
[2] = (float)src
->d
[2];
167 dst
->f
[3] = (float)src
->d
[3];
171 micro_d2i(union tgsi_exec_channel
*dst
,
172 const union tgsi_double_channel
*src
)
174 dst
->i
[0] = (int)src
->d
[0];
175 dst
->i
[1] = (int)src
->d
[1];
176 dst
->i
[2] = (int)src
->d
[2];
177 dst
->i
[3] = (int)src
->d
[3];
181 micro_d2u(union tgsi_exec_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->u
[0] = (unsigned)src
->d
[0];
185 dst
->u
[1] = (unsigned)src
->d
[1];
186 dst
->u
[2] = (unsigned)src
->d
[2];
187 dst
->u
[3] = (unsigned)src
->d
[3];
190 micro_dabs(union tgsi_double_channel
*dst
,
191 const union tgsi_double_channel
*src
)
193 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
194 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
195 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
196 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
200 micro_dadd(union tgsi_double_channel
*dst
,
201 const union tgsi_double_channel
*src
)
203 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
204 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
205 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
206 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
210 micro_ddx(union tgsi_exec_channel
*dst
,
211 const union tgsi_exec_channel
*src
)
216 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
220 micro_ddy(union tgsi_exec_channel
*dst
,
221 const union tgsi_exec_channel
*src
)
226 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
230 micro_dmul(union tgsi_double_channel
*dst
,
231 const union tgsi_double_channel
*src
)
233 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
234 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
235 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
236 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
240 micro_dmax(union tgsi_double_channel
*dst
,
241 const union tgsi_double_channel
*src
)
243 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
244 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
245 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
246 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
250 micro_dmin(union tgsi_double_channel
*dst
,
251 const union tgsi_double_channel
*src
)
253 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
254 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
255 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
256 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
260 micro_dneg(union tgsi_double_channel
*dst
,
261 const union tgsi_double_channel
*src
)
263 dst
->d
[0] = -src
->d
[0];
264 dst
->d
[1] = -src
->d
[1];
265 dst
->d
[2] = -src
->d
[2];
266 dst
->d
[3] = -src
->d
[3];
270 micro_dslt(union tgsi_double_channel
*dst
,
271 const union tgsi_double_channel
*src
)
273 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
274 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
275 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
276 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
280 micro_dsne(union tgsi_double_channel
*dst
,
281 const union tgsi_double_channel
*src
)
283 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
284 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
285 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
286 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
290 micro_dsge(union tgsi_double_channel
*dst
,
291 const union tgsi_double_channel
*src
)
293 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
294 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
295 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
296 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
300 micro_dseq(union tgsi_double_channel
*dst
,
301 const union tgsi_double_channel
*src
)
303 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
304 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
305 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
306 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
310 micro_drcp(union tgsi_double_channel
*dst
,
311 const union tgsi_double_channel
*src
)
313 dst
->d
[0] = 1.0 / src
->d
[0];
314 dst
->d
[1] = 1.0 / src
->d
[1];
315 dst
->d
[2] = 1.0 / src
->d
[2];
316 dst
->d
[3] = 1.0 / src
->d
[3];
320 micro_dsqrt(union tgsi_double_channel
*dst
,
321 const union tgsi_double_channel
*src
)
323 dst
->d
[0] = sqrt(src
->d
[0]);
324 dst
->d
[1] = sqrt(src
->d
[1]);
325 dst
->d
[2] = sqrt(src
->d
[2]);
326 dst
->d
[3] = sqrt(src
->d
[3]);
330 micro_drsq(union tgsi_double_channel
*dst
,
331 const union tgsi_double_channel
*src
)
333 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
334 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
335 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
336 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
340 micro_dmad(union tgsi_double_channel
*dst
,
341 const union tgsi_double_channel
*src
)
343 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
344 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
345 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
346 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
350 micro_dfrac(union tgsi_double_channel
*dst
,
351 const union tgsi_double_channel
*src
)
353 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
354 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
355 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
356 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
360 micro_dldexp(union tgsi_double_channel
*dst
,
361 const union tgsi_double_channel
*src0
,
362 union tgsi_exec_channel
*src1
)
364 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
365 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
366 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
367 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
371 micro_dfracexp(union tgsi_double_channel
*dst
,
372 union tgsi_exec_channel
*dst_exp
,
373 const union tgsi_double_channel
*src
)
375 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
376 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
377 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
378 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
382 micro_exp2(union tgsi_exec_channel
*dst
,
383 const union tgsi_exec_channel
*src
)
386 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
387 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
388 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
389 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
392 /* Inf is okay for this instruction, so clamp it to silence assertions. */
394 union tgsi_exec_channel clamped
;
396 for (i
= 0; i
< 4; i
++) {
397 if (src
->f
[i
] > 127.99999f
) {
398 clamped
.f
[i
] = 127.99999f
;
399 } else if (src
->f
[i
] < -126.99999f
) {
400 clamped
.f
[i
] = -126.99999f
;
402 clamped
.f
[i
] = src
->f
[i
];
408 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
409 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
410 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
411 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
412 #endif /* FAST_MATH */
416 micro_f2d(union tgsi_double_channel
*dst
,
417 const union tgsi_exec_channel
*src
)
419 dst
->d
[0] = (double)src
->f
[0];
420 dst
->d
[1] = (double)src
->f
[1];
421 dst
->d
[2] = (double)src
->f
[2];
422 dst
->d
[3] = (double)src
->f
[3];
426 micro_flr(union tgsi_exec_channel
*dst
,
427 const union tgsi_exec_channel
*src
)
429 dst
->f
[0] = floorf(src
->f
[0]);
430 dst
->f
[1] = floorf(src
->f
[1]);
431 dst
->f
[2] = floorf(src
->f
[2]);
432 dst
->f
[3] = floorf(src
->f
[3]);
436 micro_frc(union tgsi_exec_channel
*dst
,
437 const union tgsi_exec_channel
*src
)
439 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
440 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
441 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
442 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
446 micro_i2d(union tgsi_double_channel
*dst
,
447 const union tgsi_exec_channel
*src
)
449 dst
->d
[0] = (double)src
->i
[0];
450 dst
->d
[1] = (double)src
->i
[1];
451 dst
->d
[2] = (double)src
->i
[2];
452 dst
->d
[3] = (double)src
->i
[3];
456 micro_iabs(union tgsi_exec_channel
*dst
,
457 const union tgsi_exec_channel
*src
)
459 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
460 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
461 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
462 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
466 micro_ineg(union tgsi_exec_channel
*dst
,
467 const union tgsi_exec_channel
*src
)
469 dst
->i
[0] = -src
->i
[0];
470 dst
->i
[1] = -src
->i
[1];
471 dst
->i
[2] = -src
->i
[2];
472 dst
->i
[3] = -src
->i
[3];
476 micro_lg2(union tgsi_exec_channel
*dst
,
477 const union tgsi_exec_channel
*src
)
480 dst
->f
[0] = util_fast_log2(src
->f
[0]);
481 dst
->f
[1] = util_fast_log2(src
->f
[1]);
482 dst
->f
[2] = util_fast_log2(src
->f
[2]);
483 dst
->f
[3] = util_fast_log2(src
->f
[3]);
485 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
486 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
487 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
488 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
493 micro_lrp(union tgsi_exec_channel
*dst
,
494 const union tgsi_exec_channel
*src0
,
495 const union tgsi_exec_channel
*src1
,
496 const union tgsi_exec_channel
*src2
)
498 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
499 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
500 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
501 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
505 micro_mad(union tgsi_exec_channel
*dst
,
506 const union tgsi_exec_channel
*src0
,
507 const union tgsi_exec_channel
*src1
,
508 const union tgsi_exec_channel
*src2
)
510 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
511 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
512 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
513 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
517 micro_mov(union tgsi_exec_channel
*dst
,
518 const union tgsi_exec_channel
*src
)
520 dst
->u
[0] = src
->u
[0];
521 dst
->u
[1] = src
->u
[1];
522 dst
->u
[2] = src
->u
[2];
523 dst
->u
[3] = src
->u
[3];
527 micro_rcp(union tgsi_exec_channel
*dst
,
528 const union tgsi_exec_channel
*src
)
530 #if 0 /* for debugging */
531 assert(src
->f
[0] != 0.0f
);
532 assert(src
->f
[1] != 0.0f
);
533 assert(src
->f
[2] != 0.0f
);
534 assert(src
->f
[3] != 0.0f
);
536 dst
->f
[0] = 1.0f
/ src
->f
[0];
537 dst
->f
[1] = 1.0f
/ src
->f
[1];
538 dst
->f
[2] = 1.0f
/ src
->f
[2];
539 dst
->f
[3] = 1.0f
/ src
->f
[3];
543 micro_rnd(union tgsi_exec_channel
*dst
,
544 const union tgsi_exec_channel
*src
)
546 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
547 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
548 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
549 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
553 micro_rsq(union tgsi_exec_channel
*dst
,
554 const union tgsi_exec_channel
*src
)
556 #if 0 /* for debugging */
557 assert(src
->f
[0] != 0.0f
);
558 assert(src
->f
[1] != 0.0f
);
559 assert(src
->f
[2] != 0.0f
);
560 assert(src
->f
[3] != 0.0f
);
562 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
563 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
564 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
565 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
569 micro_sqrt(union tgsi_exec_channel
*dst
,
570 const union tgsi_exec_channel
*src
)
572 dst
->f
[0] = sqrtf(src
->f
[0]);
573 dst
->f
[1] = sqrtf(src
->f
[1]);
574 dst
->f
[2] = sqrtf(src
->f
[2]);
575 dst
->f
[3] = sqrtf(src
->f
[3]);
579 micro_seq(union tgsi_exec_channel
*dst
,
580 const union tgsi_exec_channel
*src0
,
581 const union tgsi_exec_channel
*src1
)
583 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
584 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
585 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
586 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
590 micro_sge(union tgsi_exec_channel
*dst
,
591 const union tgsi_exec_channel
*src0
,
592 const union tgsi_exec_channel
*src1
)
594 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
595 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
596 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
597 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
601 micro_sgn(union tgsi_exec_channel
*dst
,
602 const union tgsi_exec_channel
*src
)
604 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
605 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
611 micro_isgn(union tgsi_exec_channel
*dst
,
612 const union tgsi_exec_channel
*src
)
614 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
615 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
616 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
617 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
621 micro_sgt(union tgsi_exec_channel
*dst
,
622 const union tgsi_exec_channel
*src0
,
623 const union tgsi_exec_channel
*src1
)
625 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
626 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
627 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
628 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
632 micro_sin(union tgsi_exec_channel
*dst
,
633 const union tgsi_exec_channel
*src
)
635 dst
->f
[0] = sinf(src
->f
[0]);
636 dst
->f
[1] = sinf(src
->f
[1]);
637 dst
->f
[2] = sinf(src
->f
[2]);
638 dst
->f
[3] = sinf(src
->f
[3]);
642 micro_sle(union tgsi_exec_channel
*dst
,
643 const union tgsi_exec_channel
*src0
,
644 const union tgsi_exec_channel
*src1
)
646 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
647 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
648 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
649 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
653 micro_slt(union tgsi_exec_channel
*dst
,
654 const union tgsi_exec_channel
*src0
,
655 const union tgsi_exec_channel
*src1
)
657 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
658 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
659 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
660 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
664 micro_sne(union tgsi_exec_channel
*dst
,
665 const union tgsi_exec_channel
*src0
,
666 const union tgsi_exec_channel
*src1
)
668 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
669 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
670 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
671 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
675 micro_trunc(union tgsi_exec_channel
*dst
,
676 const union tgsi_exec_channel
*src
)
678 dst
->f
[0] = (float)(int)src
->f
[0];
679 dst
->f
[1] = (float)(int)src
->f
[1];
680 dst
->f
[2] = (float)(int)src
->f
[2];
681 dst
->f
[3] = (float)(int)src
->f
[3];
685 micro_u2d(union tgsi_double_channel
*dst
,
686 const union tgsi_exec_channel
*src
)
688 dst
->d
[0] = (double)src
->u
[0];
689 dst
->d
[1] = (double)src
->u
[1];
690 dst
->d
[2] = (double)src
->u
[2];
691 dst
->d
[3] = (double)src
->u
[3];
694 enum tgsi_exec_datatype
{
695 TGSI_EXEC_DATA_FLOAT
,
698 TGSI_EXEC_DATA_DOUBLE
702 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
704 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
705 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
706 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
707 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
708 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
709 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
712 /** The execution mask depends on the conditional mask and the loop mask */
713 #define UPDATE_EXEC_MASK(MACH) \
714 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
717 static const union tgsi_exec_channel ZeroVec
=
718 { { 0.0, 0.0, 0.0, 0.0 } };
720 static const union tgsi_exec_channel OneVec
= {
721 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
724 static const union tgsi_exec_channel P128Vec
= {
725 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
728 static const union tgsi_exec_channel M128Vec
= {
729 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
734 * Assert that none of the float values in 'chan' are infinite or NaN.
735 * NaN and Inf may occur normally during program execution and should
736 * not lead to crashes, etc. But when debugging, it's helpful to catch
740 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
742 assert(!util_is_inf_or_nan((chan
)->f
[0]));
743 assert(!util_is_inf_or_nan((chan
)->f
[1]));
744 assert(!util_is_inf_or_nan((chan
)->f
[2]));
745 assert(!util_is_inf_or_nan((chan
)->f
[3]));
751 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
753 debug_printf("%s = {%f, %f, %f, %f}\n",
754 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
761 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
763 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
765 debug_printf("Temp[%u] =\n", index
);
766 for (i
= 0; i
< 4; i
++) {
767 debug_printf(" %c: { %f, %f, %f, %f }\n",
779 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
782 const unsigned *buf_sizes
)
786 for (i
= 0; i
< num_bufs
; i
++) {
787 mach
->Consts
[i
] = bufs
[i
];
788 mach
->ConstsSize
[i
] = buf_sizes
[i
];
794 * Check if there's a potential src/dst register data dependency when
795 * using SOA execution.
798 * This would expand into:
803 * The second instruction will have the wrong value for t0 if executed as-is.
806 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
810 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
811 if (writemask
== TGSI_WRITEMASK_X
||
812 writemask
== TGSI_WRITEMASK_Y
||
813 writemask
== TGSI_WRITEMASK_Z
||
814 writemask
== TGSI_WRITEMASK_W
||
815 writemask
== TGSI_WRITEMASK_NONE
) {
816 /* no chance of data dependency */
820 /* loop over src regs */
821 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
822 if ((inst
->Src
[i
].Register
.File
==
823 inst
->Dst
[0].Register
.File
) &&
824 ((inst
->Src
[i
].Register
.Index
==
825 inst
->Dst
[0].Register
.Index
) ||
826 inst
->Src
[i
].Register
.Indirect
||
827 inst
->Dst
[0].Register
.Indirect
)) {
828 /* loop over dest channels */
829 uint channelsWritten
= 0x0;
830 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
831 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
832 /* check if we're reading a channel that's been written */
833 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
834 if (channelsWritten
& (1 << swizzle
)) {
838 channelsWritten
|= (1 << chan
);
848 * Initialize machine state by expanding tokens to full instructions,
849 * allocating temporary storage, setting up constants, etc.
850 * After this, we can call tgsi_exec_machine_run() many times.
853 tgsi_exec_machine_bind_shader(
854 struct tgsi_exec_machine
*mach
,
855 const struct tgsi_token
*tokens
,
856 struct tgsi_sampler
*sampler
)
859 struct tgsi_parse_context parse
;
860 struct tgsi_full_instruction
*instructions
;
861 struct tgsi_full_declaration
*declarations
;
862 uint maxInstructions
= 10, numInstructions
= 0;
863 uint maxDeclarations
= 10, numDeclarations
= 0;
866 tgsi_dump(tokens
, 0);
872 mach
->Tokens
= tokens
;
873 mach
->Sampler
= sampler
;
876 /* unbind and free all */
877 FREE(mach
->Declarations
);
878 mach
->Declarations
= NULL
;
879 mach
->NumDeclarations
= 0;
881 FREE(mach
->Instructions
);
882 mach
->Instructions
= NULL
;
883 mach
->NumInstructions
= 0;
888 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
889 if (k
!= TGSI_PARSE_OK
) {
890 debug_printf( "Problem parsing!\n" );
894 mach
->Processor
= parse
.FullHeader
.Processor
.Processor
;
896 mach
->NumOutputs
= 0;
898 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
&&
899 !mach
->UsedGeometryShader
) {
900 struct tgsi_exec_vector
*inputs
;
901 struct tgsi_exec_vector
*outputs
;
903 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
904 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
910 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
911 TGSI_MAX_TOTAL_VERTICES
, 16);
918 align_free(mach
->Inputs
);
919 align_free(mach
->Outputs
);
921 mach
->Inputs
= inputs
;
922 mach
->Outputs
= outputs
;
923 mach
->UsedGeometryShader
= TRUE
;
926 declarations
= (struct tgsi_full_declaration
*)
927 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
933 instructions
= (struct tgsi_full_instruction
*)
934 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
937 FREE( declarations
);
941 while( !tgsi_parse_end_of_tokens( &parse
) ) {
944 tgsi_parse_token( &parse
);
945 switch( parse
.FullToken
.Token
.Type
) {
946 case TGSI_TOKEN_TYPE_DECLARATION
:
947 /* save expanded declaration */
948 if (numDeclarations
== maxDeclarations
) {
949 declarations
= REALLOC(declarations
,
951 * sizeof(struct tgsi_full_declaration
),
952 (maxDeclarations
+ 10)
953 * sizeof(struct tgsi_full_declaration
));
954 maxDeclarations
+= 10;
956 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
958 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
959 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
964 memcpy(declarations
+ numDeclarations
,
965 &parse
.FullToken
.FullDeclaration
,
966 sizeof(declarations
[0]));
970 case TGSI_TOKEN_TYPE_IMMEDIATE
:
972 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
974 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
976 for( i
= 0; i
< size
; i
++ ) {
977 mach
->Imms
[mach
->ImmLimit
][i
] =
978 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
984 case TGSI_TOKEN_TYPE_INSTRUCTION
:
986 /* save expanded instruction */
987 if (numInstructions
== maxInstructions
) {
988 instructions
= REALLOC(instructions
,
990 * sizeof(struct tgsi_full_instruction
),
991 (maxInstructions
+ 10)
992 * sizeof(struct tgsi_full_instruction
));
993 maxInstructions
+= 10;
996 memcpy(instructions
+ numInstructions
,
997 &parse
.FullToken
.FullInstruction
,
998 sizeof(instructions
[0]));
1003 case TGSI_TOKEN_TYPE_PROPERTY
:
1004 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
1005 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1006 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1015 tgsi_parse_free (&parse
);
1017 FREE(mach
->Declarations
);
1018 mach
->Declarations
= declarations
;
1019 mach
->NumDeclarations
= numDeclarations
;
1021 FREE(mach
->Instructions
);
1022 mach
->Instructions
= instructions
;
1023 mach
->NumInstructions
= numInstructions
;
1027 struct tgsi_exec_machine
*
1028 tgsi_exec_machine_create( void )
1030 struct tgsi_exec_machine
*mach
;
1033 mach
= align_malloc( sizeof *mach
, 16 );
1037 memset(mach
, 0, sizeof(*mach
));
1039 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1040 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1041 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
1043 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1044 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1045 if (!mach
->Inputs
|| !mach
->Outputs
)
1048 /* Setup constants needed by the SSE2 executor. */
1049 for( i
= 0; i
< 4; i
++ ) {
1050 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1051 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1052 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1053 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1054 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1055 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1056 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1057 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1058 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1059 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1063 /* silence warnings */
1072 align_free(mach
->Inputs
);
1073 align_free(mach
->Outputs
);
1081 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1084 FREE(mach
->Instructions
);
1085 FREE(mach
->Declarations
);
1087 align_free(mach
->Inputs
);
1088 align_free(mach
->Outputs
);
1095 micro_add(union tgsi_exec_channel
*dst
,
1096 const union tgsi_exec_channel
*src0
,
1097 const union tgsi_exec_channel
*src1
)
1099 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1100 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1101 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1102 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1107 union tgsi_exec_channel
*dst
,
1108 const union tgsi_exec_channel
*src0
,
1109 const union tgsi_exec_channel
*src1
)
1111 if (src1
->f
[0] != 0) {
1112 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1114 if (src1
->f
[1] != 0) {
1115 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1117 if (src1
->f
[2] != 0) {
1118 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1120 if (src1
->f
[3] != 0) {
1121 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1127 union tgsi_exec_channel
*dst
,
1128 const union tgsi_exec_channel
*src0
,
1129 const union tgsi_exec_channel
*src1
,
1130 const union tgsi_exec_channel
*src2
,
1131 const union tgsi_exec_channel
*src3
)
1133 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1134 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1135 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1136 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1140 micro_max(union tgsi_exec_channel
*dst
,
1141 const union tgsi_exec_channel
*src0
,
1142 const union tgsi_exec_channel
*src1
)
1144 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1145 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1146 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1147 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1151 micro_min(union tgsi_exec_channel
*dst
,
1152 const union tgsi_exec_channel
*src0
,
1153 const union tgsi_exec_channel
*src1
)
1155 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1156 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1157 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1158 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1162 micro_mul(union tgsi_exec_channel
*dst
,
1163 const union tgsi_exec_channel
*src0
,
1164 const union tgsi_exec_channel
*src1
)
1166 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1167 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1168 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1169 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1174 union tgsi_exec_channel
*dst
,
1175 const union tgsi_exec_channel
*src
)
1177 dst
->f
[0] = -src
->f
[0];
1178 dst
->f
[1] = -src
->f
[1];
1179 dst
->f
[2] = -src
->f
[2];
1180 dst
->f
[3] = -src
->f
[3];
1185 union tgsi_exec_channel
*dst
,
1186 const union tgsi_exec_channel
*src0
,
1187 const union tgsi_exec_channel
*src1
)
1190 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1191 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1192 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1193 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1195 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1196 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1197 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1198 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1203 micro_sub(union tgsi_exec_channel
*dst
,
1204 const union tgsi_exec_channel
*src0
,
1205 const union tgsi_exec_channel
*src1
)
1207 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1208 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1209 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1210 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1214 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1215 const uint chan_index
,
1218 const union tgsi_exec_channel
*index
,
1219 const union tgsi_exec_channel
*index2D
,
1220 union tgsi_exec_channel
*chan
)
1224 assert(swizzle
< 4);
1227 case TGSI_FILE_CONSTANT
:
1228 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1229 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1230 assert(mach
->Consts
[index2D
->i
[i
]]);
1232 if (index
->i
[i
] < 0) {
1235 /* NOTE: copying the const value as a uint instead of float */
1236 const uint constbuf
= index2D
->i
[i
];
1237 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1238 const int pos
= index
->i
[i
] * 4 + swizzle
;
1239 /* const buffer bounds check */
1240 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1242 /* Debug: print warning */
1243 static int count
= 0;
1245 debug_printf("TGSI Exec: const buffer index %d"
1246 " out of bounds\n", pos
);
1251 chan
->u
[i
] = buf
[pos
];
1256 case TGSI_FILE_INPUT
:
1257 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1259 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1260 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1261 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1262 index2D->i[i], index->i[i]);
1264 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1266 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1267 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1271 case TGSI_FILE_SYSTEM_VALUE
:
1272 /* XXX no swizzling at this point. Will be needed if we put
1273 * gl_FragCoord, for example, in a sys value register.
1275 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1276 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].u
[i
];
1280 case TGSI_FILE_TEMPORARY
:
1281 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1282 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1283 assert(index2D
->i
[i
] == 0);
1285 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1289 case TGSI_FILE_IMMEDIATE
:
1290 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1291 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1292 assert(index2D
->i
[i
] == 0);
1294 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1298 case TGSI_FILE_ADDRESS
:
1299 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1300 assert(index
->i
[i
] >= 0);
1301 assert(index2D
->i
[i
] == 0);
1303 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1307 case TGSI_FILE_PREDICATE
:
1308 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1309 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1310 assert(index2D
->i
[i
] == 0);
1312 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1316 case TGSI_FILE_OUTPUT
:
1317 /* vertex/fragment output vars can be read too */
1318 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1319 assert(index
->i
[i
] >= 0);
1320 assert(index2D
->i
[i
] == 0);
1322 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1328 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1335 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1336 union tgsi_exec_channel
*chan
,
1337 const struct tgsi_full_src_register
*reg
,
1338 const uint chan_index
,
1339 enum tgsi_exec_datatype src_datatype
)
1341 union tgsi_exec_channel index
;
1342 union tgsi_exec_channel index2D
;
1345 /* We start with a direct index into a register file.
1349 * file = Register.File
1350 * [1] = Register.Index
1355 index
.i
[3] = reg
->Register
.Index
;
1357 /* There is an extra source register that indirectly subscripts
1358 * a register file. The direct index now becomes an offset
1359 * that is being added to the indirect register.
1363 * ind = Indirect.File
1364 * [2] = Indirect.Index
1365 * .x = Indirect.SwizzleX
1367 if (reg
->Register
.Indirect
) {
1368 union tgsi_exec_channel index2
;
1369 union tgsi_exec_channel indir_index
;
1370 const uint execmask
= mach
->ExecMask
;
1373 /* which address register (always zero now) */
1377 index2
.i
[3] = reg
->Indirect
.Index
;
1378 /* get current value of address register[swizzle] */
1379 swizzle
= reg
->Indirect
.Swizzle
;
1380 fetch_src_file_channel(mach
,
1388 /* add value of address register to the offset */
1389 index
.i
[0] += indir_index
.i
[0];
1390 index
.i
[1] += indir_index
.i
[1];
1391 index
.i
[2] += indir_index
.i
[2];
1392 index
.i
[3] += indir_index
.i
[3];
1394 /* for disabled execution channels, zero-out the index to
1395 * avoid using a potential garbage value.
1397 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1398 if ((execmask
& (1 << i
)) == 0)
1403 /* There is an extra source register that is a second
1404 * subscript to a register file. Effectively it means that
1405 * the register file is actually a 2D array of registers.
1409 * [3] = Dimension.Index
1411 if (reg
->Register
.Dimension
) {
1415 index2D
.i
[3] = reg
->Dimension
.Index
;
1417 /* Again, the second subscript index can be addressed indirectly
1418 * identically to the first one.
1419 * Nothing stops us from indirectly addressing the indirect register,
1420 * but there is no need for that, so we won't exercise it.
1422 * file[ind[4].y+3][1],
1424 * ind = DimIndirect.File
1425 * [4] = DimIndirect.Index
1426 * .y = DimIndirect.SwizzleX
1428 if (reg
->Dimension
.Indirect
) {
1429 union tgsi_exec_channel index2
;
1430 union tgsi_exec_channel indir_index
;
1431 const uint execmask
= mach
->ExecMask
;
1437 index2
.i
[3] = reg
->DimIndirect
.Index
;
1439 swizzle
= reg
->DimIndirect
.Swizzle
;
1440 fetch_src_file_channel(mach
,
1442 reg
->DimIndirect
.File
,
1448 index2D
.i
[0] += indir_index
.i
[0];
1449 index2D
.i
[1] += indir_index
.i
[1];
1450 index2D
.i
[2] += indir_index
.i
[2];
1451 index2D
.i
[3] += indir_index
.i
[3];
1453 /* for disabled execution channels, zero-out the index to
1454 * avoid using a potential garbage value.
1456 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1457 if ((execmask
& (1 << i
)) == 0) {
1463 /* If by any chance there was a need for a 3D array of register
1464 * files, we would have to check whether Dimension is followed
1465 * by a dimension register and continue the saga.
1474 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1475 fetch_src_file_channel(mach
,
1485 fetch_source(const struct tgsi_exec_machine
*mach
,
1486 union tgsi_exec_channel
*chan
,
1487 const struct tgsi_full_src_register
*reg
,
1488 const uint chan_index
,
1489 enum tgsi_exec_datatype src_datatype
)
1491 fetch_source_d(mach
, chan
, reg
, chan_index
, src_datatype
);
1493 if (reg
->Register
.Absolute
) {
1494 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1495 micro_abs(chan
, chan
);
1497 micro_iabs(chan
, chan
);
1501 if (reg
->Register
.Negate
) {
1502 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1503 micro_neg(chan
, chan
);
1505 micro_ineg(chan
, chan
);
1510 static union tgsi_exec_channel
*
1511 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1512 const union tgsi_exec_channel
*chan
,
1513 const struct tgsi_full_dst_register
*reg
,
1514 const struct tgsi_full_instruction
*inst
,
1516 enum tgsi_exec_datatype dst_datatype
)
1519 static union tgsi_exec_channel null
;
1520 union tgsi_exec_channel
*dst
;
1521 union tgsi_exec_channel index2D
;
1522 uint execmask
= mach
->ExecMask
;
1523 int offset
= 0; /* indirection offset */
1527 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1528 check_inf_or_nan(chan
);
1531 /* There is an extra source register that indirectly subscripts
1532 * a register file. The direct index now becomes an offset
1533 * that is being added to the indirect register.
1537 * ind = Indirect.File
1538 * [2] = Indirect.Index
1539 * .x = Indirect.SwizzleX
1541 if (reg
->Register
.Indirect
) {
1542 union tgsi_exec_channel index
;
1543 union tgsi_exec_channel indir_index
;
1546 /* which address register (always zero for now) */
1550 index
.i
[3] = reg
->Indirect
.Index
;
1552 /* get current value of address register[swizzle] */
1553 swizzle
= reg
->Indirect
.Swizzle
;
1555 /* fetch values from the address/indirection register */
1556 fetch_src_file_channel(mach
,
1564 /* save indirection offset */
1565 offset
= indir_index
.i
[0];
1568 /* There is an extra source register that is a second
1569 * subscript to a register file. Effectively it means that
1570 * the register file is actually a 2D array of registers.
1574 * [3] = Dimension.Index
1576 if (reg
->Register
.Dimension
) {
1580 index2D
.i
[3] = reg
->Dimension
.Index
;
1582 /* Again, the second subscript index can be addressed indirectly
1583 * identically to the first one.
1584 * Nothing stops us from indirectly addressing the indirect register,
1585 * but there is no need for that, so we won't exercise it.
1587 * file[ind[4].y+3][1],
1589 * ind = DimIndirect.File
1590 * [4] = DimIndirect.Index
1591 * .y = DimIndirect.SwizzleX
1593 if (reg
->Dimension
.Indirect
) {
1594 union tgsi_exec_channel index2
;
1595 union tgsi_exec_channel indir_index
;
1596 const uint execmask
= mach
->ExecMask
;
1603 index2
.i
[3] = reg
->DimIndirect
.Index
;
1605 swizzle
= reg
->DimIndirect
.Swizzle
;
1606 fetch_src_file_channel(mach
,
1608 reg
->DimIndirect
.File
,
1614 index2D
.i
[0] += indir_index
.i
[0];
1615 index2D
.i
[1] += indir_index
.i
[1];
1616 index2D
.i
[2] += indir_index
.i
[2];
1617 index2D
.i
[3] += indir_index
.i
[3];
1619 /* for disabled execution channels, zero-out the index to
1620 * avoid using a potential garbage value.
1622 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1623 if ((execmask
& (1 << i
)) == 0) {
1629 /* If by any chance there was a need for a 3D array of register
1630 * files, we would have to check whether Dimension is followed
1631 * by a dimension register and continue the saga.
1640 switch (reg
->Register
.File
) {
1641 case TGSI_FILE_NULL
:
1645 case TGSI_FILE_OUTPUT
:
1646 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1647 + reg
->Register
.Index
;
1648 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1650 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1651 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1652 reg
->Register
.Index
);
1653 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1654 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1655 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1656 if (execmask
& (1 << i
))
1657 debug_printf("%f, ", chan
->f
[i
]);
1658 debug_printf(")\n");
1663 case TGSI_FILE_TEMPORARY
:
1664 index
= reg
->Register
.Index
;
1665 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1666 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1669 case TGSI_FILE_ADDRESS
:
1670 index
= reg
->Register
.Index
;
1671 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1674 case TGSI_FILE_PREDICATE
:
1675 index
= reg
->Register
.Index
;
1676 assert(index
< TGSI_EXEC_NUM_PREDS
);
1677 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1685 if (inst
->Instruction
.Predicate
) {
1687 union tgsi_exec_channel
*pred
;
1689 switch (chan_index
) {
1691 swizzle
= inst
->Predicate
.SwizzleX
;
1694 swizzle
= inst
->Predicate
.SwizzleY
;
1697 swizzle
= inst
->Predicate
.SwizzleZ
;
1700 swizzle
= inst
->Predicate
.SwizzleW
;
1707 assert(inst
->Predicate
.Index
== 0);
1709 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1711 if (inst
->Predicate
.Negate
) {
1712 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1714 execmask
&= ~(1 << i
);
1718 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1720 execmask
&= ~(1 << i
);
1730 store_dest_double(struct tgsi_exec_machine
*mach
,
1731 const union tgsi_exec_channel
*chan
,
1732 const struct tgsi_full_dst_register
*reg
,
1733 const struct tgsi_full_instruction
*inst
,
1735 enum tgsi_exec_datatype dst_datatype
)
1737 union tgsi_exec_channel
*dst
;
1738 const uint execmask
= mach
->ExecMask
;
1741 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1747 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1748 if (execmask
& (1 << i
))
1749 dst
->i
[i
] = chan
->i
[i
];
1753 store_dest(struct tgsi_exec_machine
*mach
,
1754 const union tgsi_exec_channel
*chan
,
1755 const struct tgsi_full_dst_register
*reg
,
1756 const struct tgsi_full_instruction
*inst
,
1758 enum tgsi_exec_datatype dst_datatype
)
1760 union tgsi_exec_channel
*dst
;
1761 const uint execmask
= mach
->ExecMask
;
1764 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1769 if (!inst
->Instruction
.Saturate
) {
1770 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1771 if (execmask
& (1 << i
))
1772 dst
->i
[i
] = chan
->i
[i
];
1775 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1776 if (execmask
& (1 << i
)) {
1777 if (chan
->f
[i
] < 0.0f
)
1779 else if (chan
->f
[i
] > 1.0f
)
1782 dst
->i
[i
] = chan
->i
[i
];
1787 #define FETCH(VAL,INDEX,CHAN)\
1788 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1790 #define IFETCH(VAL,INDEX,CHAN)\
1791 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1795 * Execute ARB-style KIL which is predicated by a src register.
1796 * Kill fragment if any of the four values is less than zero.
1799 exec_kill_if(struct tgsi_exec_machine
*mach
,
1800 const struct tgsi_full_instruction
*inst
)
1804 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1805 union tgsi_exec_channel r
[1];
1807 /* This mask stores component bits that were already tested. */
1810 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1815 /* unswizzle channel */
1816 swizzle
= tgsi_util_get_full_src_register_swizzle (
1820 /* check if the component has not been already tested */
1821 if (uniquemask
& (1 << swizzle
))
1823 uniquemask
|= 1 << swizzle
;
1825 FETCH(&r
[0], 0, chan_index
);
1826 for (i
= 0; i
< 4; i
++)
1827 if (r
[0].f
[i
] < 0.0f
)
1831 /* restrict to fragments currently executing */
1832 kilmask
&= mach
->ExecMask
;
1834 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1838 * Unconditional fragment kill/discard.
1841 exec_kill(struct tgsi_exec_machine
*mach
,
1842 const struct tgsi_full_instruction
*inst
)
1844 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1846 /* kill fragment for all fragments currently executing */
1847 kilmask
= mach
->ExecMask
;
1848 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1852 emit_vertex(struct tgsi_exec_machine
*mach
)
1854 /* FIXME: check for exec mask correctly
1856 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1857 if ((mach->ExecMask & (1 << i)))
1859 if (mach
->ExecMask
) {
1860 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
1863 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1864 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1869 emit_primitive(struct tgsi_exec_machine
*mach
)
1871 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1872 /* FIXME: check for exec mask correctly
1874 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1875 if ((mach->ExecMask & (1 << i)))
1877 if (mach
->ExecMask
) {
1879 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1880 mach
->Primitives
[*prim_count
] = 0;
1885 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1887 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1889 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1890 if (emitted_verts
) {
1891 emit_primitive(mach
);
1898 * Fetch four texture samples using STR texture coordinates.
1901 fetch_texel( struct tgsi_sampler
*sampler
,
1902 const unsigned sview_idx
,
1903 const unsigned sampler_idx
,
1904 const union tgsi_exec_channel
*s
,
1905 const union tgsi_exec_channel
*t
,
1906 const union tgsi_exec_channel
*p
,
1907 const union tgsi_exec_channel
*c0
,
1908 const union tgsi_exec_channel
*c1
,
1909 float derivs
[3][2][TGSI_QUAD_SIZE
],
1910 const int8_t offset
[3],
1911 enum tgsi_sampler_control control
,
1912 union tgsi_exec_channel
*r
,
1913 union tgsi_exec_channel
*g
,
1914 union tgsi_exec_channel
*b
,
1915 union tgsi_exec_channel
*a
)
1918 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1920 /* FIXME: handle explicit derivs, offsets */
1921 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
1922 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
1924 for (j
= 0; j
< 4; j
++) {
1925 r
->f
[j
] = rgba
[0][j
];
1926 g
->f
[j
] = rgba
[1][j
];
1927 b
->f
[j
] = rgba
[2][j
];
1928 a
->f
[j
] = rgba
[3][j
];
1933 #define TEX_MODIFIER_NONE 0
1934 #define TEX_MODIFIER_PROJECTED 1
1935 #define TEX_MODIFIER_LOD_BIAS 2
1936 #define TEX_MODIFIER_EXPLICIT_LOD 3
1937 #define TEX_MODIFIER_LEVEL_ZERO 4
1938 #define TEX_MODIFIER_GATHER 5
1941 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1944 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
1945 const struct tgsi_full_instruction
*inst
,
1948 if (inst
->Texture
.NumOffsets
== 1) {
1949 union tgsi_exec_channel index
;
1950 union tgsi_exec_channel offset
[3];
1951 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
1952 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1953 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
1954 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1955 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
1956 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1957 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
1958 offsets
[0] = offset
[0].i
[0];
1959 offsets
[1] = offset
[1].i
[0];
1960 offsets
[2] = offset
[2].i
[0];
1962 assert(inst
->Texture
.NumOffsets
== 0);
1963 offsets
[0] = offsets
[1] = offsets
[2] = 0;
1969 * Fetch dx and dy values for one channel (s, t or r).
1970 * Put dx values into one float array, dy values into another.
1973 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
1974 const struct tgsi_full_instruction
*inst
,
1977 float derivs
[2][TGSI_QUAD_SIZE
])
1979 union tgsi_exec_channel d
;
1980 FETCH(&d
, regdsrcx
, chan
);
1981 derivs
[0][0] = d
.f
[0];
1982 derivs
[0][1] = d
.f
[1];
1983 derivs
[0][2] = d
.f
[2];
1984 derivs
[0][3] = d
.f
[3];
1985 FETCH(&d
, regdsrcx
+ 1, chan
);
1986 derivs
[1][0] = d
.f
[0];
1987 derivs
[1][1] = d
.f
[1];
1988 derivs
[1][2] = d
.f
[2];
1989 derivs
[1][3] = d
.f
[3];
1993 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
1994 const struct tgsi_full_instruction
*inst
,
1999 if (inst
->Src
[sampler
].Register
.Indirect
) {
2000 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2001 union tgsi_exec_channel indir_index
, index2
;
2006 index2
.i
[3] = reg
->Indirect
.Index
;
2008 fetch_src_file_channel(mach
,
2011 reg
->Indirect
.Swizzle
,
2015 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[0];
2017 unit
= inst
->Src
[sampler
].Register
.Index
;
2023 * execute a texture instruction.
2025 * modifier is used to control the channel routing for the
2026 * instruction variants like proj, lod, and texture with lod bias.
2027 * sampler indicates which src register the sampler is contained in.
2030 exec_tex(struct tgsi_exec_machine
*mach
,
2031 const struct tgsi_full_instruction
*inst
,
2032 uint modifier
, uint sampler
)
2034 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2035 union tgsi_exec_channel r
[5];
2036 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2040 int dim
, shadow_ref
, i
;
2042 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2043 /* always fetch all 3 offsets, overkill but keeps code simple */
2044 fetch_texel_offsets(mach
, inst
, offsets
);
2046 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2047 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2049 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
, &shadow_ref
);
2052 if (shadow_ref
>= 0)
2053 assert(shadow_ref
>= dim
&& shadow_ref
< Elements(args
));
2055 /* fetch modifier to the last argument */
2056 if (modifier
!= TEX_MODIFIER_NONE
) {
2057 const int last
= Elements(args
) - 1;
2059 /* fetch modifier from src0.w or src1.x */
2061 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2062 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2065 assert(shadow_ref
!= 4);
2066 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2069 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2070 args
[last
] = &r
[last
];
2074 args
[last
] = &ZeroVec
;
2077 /* point unused arguments to zero vector */
2078 for (i
= dim
; i
< last
; i
++)
2081 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2082 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2083 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2084 control
= TGSI_SAMPLER_LOD_BIAS
;
2085 else if (modifier
== TEX_MODIFIER_GATHER
)
2086 control
= TGSI_SAMPLER_GATHER
;
2089 for (i
= dim
; i
< Elements(args
); i
++)
2093 /* fetch coordinates */
2094 for (i
= 0; i
< dim
; i
++) {
2095 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2098 micro_div(&r
[i
], &r
[i
], proj
);
2103 /* fetch reference value */
2104 if (shadow_ref
>= 0) {
2105 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2108 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2110 args
[shadow_ref
] = &r
[shadow_ref
];
2113 fetch_texel(mach
->Sampler
, unit
, unit
,
2114 args
[0], args
[1], args
[2], args
[3], args
[4],
2115 NULL
, offsets
, control
,
2116 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2119 debug_printf("fetch r: %g %g %g %g\n",
2120 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2121 debug_printf("fetch g: %g %g %g %g\n",
2122 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2123 debug_printf("fetch b: %g %g %g %g\n",
2124 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2125 debug_printf("fetch a: %g %g %g %g\n",
2126 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2129 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2130 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2131 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2137 exec_lodq(struct tgsi_exec_machine
*mach
,
2138 const struct tgsi_full_instruction
*inst
)
2143 union tgsi_exec_channel coords
[4];
2144 const union tgsi_exec_channel
*args
[Elements(coords
)];
2145 union tgsi_exec_channel r
[2];
2147 unit
= fetch_sampler_unit(mach
, inst
, 1);
2148 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
, NULL
);
2149 assert(dim
<= Elements(coords
));
2150 /* fetch coordinates */
2151 for (i
= 0; i
< dim
; i
++) {
2152 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2153 args
[i
] = &coords
[i
];
2155 for (i
= dim
; i
< Elements(coords
); i
++) {
2158 mach
->Sampler
->query_lod(mach
->Sampler
, unit
, unit
,
2163 TGSI_SAMPLER_LOD_NONE
,
2167 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2168 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2169 TGSI_EXEC_DATA_FLOAT
);
2171 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2172 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2173 TGSI_EXEC_DATA_FLOAT
);
2178 exec_txd(struct tgsi_exec_machine
*mach
,
2179 const struct tgsi_full_instruction
*inst
)
2181 union tgsi_exec_channel r
[4];
2182 float derivs
[3][2][TGSI_QUAD_SIZE
];
2187 unit
= fetch_sampler_unit(mach
, inst
, 3);
2188 /* always fetch all 3 offsets, overkill but keeps code simple */
2189 fetch_texel_offsets(mach
, inst
, offsets
);
2191 switch (inst
->Texture
.Texture
) {
2192 case TGSI_TEXTURE_1D
:
2193 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2195 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2197 fetch_texel(mach
->Sampler
, unit
, unit
,
2198 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2199 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2200 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2203 case TGSI_TEXTURE_SHADOW1D
:
2204 case TGSI_TEXTURE_1D_ARRAY
:
2205 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2206 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2207 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2208 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2209 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2211 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2213 fetch_texel(mach
->Sampler
, unit
, unit
,
2214 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2215 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2216 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2219 case TGSI_TEXTURE_2D
:
2220 case TGSI_TEXTURE_RECT
:
2221 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2222 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2224 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2225 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2227 fetch_texel(mach
->Sampler
, unit
, unit
,
2228 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2229 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2230 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2234 case TGSI_TEXTURE_SHADOW2D
:
2235 case TGSI_TEXTURE_SHADOWRECT
:
2236 case TGSI_TEXTURE_2D_ARRAY
:
2237 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2238 /* only SHADOW2D_ARRAY actually needs W */
2239 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2240 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2241 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2242 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2244 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2245 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2247 fetch_texel(mach
->Sampler
, unit
, unit
,
2248 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2249 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2250 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2253 case TGSI_TEXTURE_3D
:
2254 case TGSI_TEXTURE_CUBE
:
2255 case TGSI_TEXTURE_CUBE_ARRAY
:
2256 case TGSI_TEXTURE_SHADOWCUBE
:
2257 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2258 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2259 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2260 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2261 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2263 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2264 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2265 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2267 fetch_texel(mach
->Sampler
, unit
, unit
,
2268 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2269 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2270 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2277 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2278 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2279 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2286 exec_txf(struct tgsi_exec_machine
*mach
,
2287 const struct tgsi_full_instruction
*inst
)
2289 union tgsi_exec_channel r
[4];
2292 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2297 unit
= fetch_sampler_unit(mach
, inst
, 1);
2298 /* always fetch all 3 offsets, overkill but keeps code simple */
2299 fetch_texel_offsets(mach
, inst
, offsets
);
2301 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2303 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2304 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2305 target
= mach
->SamplerViews
[unit
].Resource
;
2308 target
= inst
->Texture
.Texture
;
2311 case TGSI_TEXTURE_3D
:
2312 case TGSI_TEXTURE_2D_ARRAY
:
2313 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2314 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2315 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2317 case TGSI_TEXTURE_2D
:
2318 case TGSI_TEXTURE_RECT
:
2319 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2320 case TGSI_TEXTURE_SHADOW2D
:
2321 case TGSI_TEXTURE_SHADOWRECT
:
2322 case TGSI_TEXTURE_1D_ARRAY
:
2323 case TGSI_TEXTURE_2D_MSAA
:
2324 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2326 case TGSI_TEXTURE_BUFFER
:
2327 case TGSI_TEXTURE_1D
:
2328 case TGSI_TEXTURE_SHADOW1D
:
2329 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2336 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2339 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2340 r
[0].f
[j
] = rgba
[0][j
];
2341 r
[1].f
[j
] = rgba
[1][j
];
2342 r
[2].f
[j
] = rgba
[2][j
];
2343 r
[3].f
[j
] = rgba
[3][j
];
2346 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2347 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2348 unsigned char swizzles
[4];
2349 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2350 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2351 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2352 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2354 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2355 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2356 store_dest(mach
, &r
[swizzles
[chan
]],
2357 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2362 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2363 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2364 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2371 exec_txq(struct tgsi_exec_machine
*mach
,
2372 const struct tgsi_full_instruction
*inst
)
2375 union tgsi_exec_channel r
[4], src
;
2380 unit
= fetch_sampler_unit(mach
, inst
, 1);
2382 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2384 /* XXX: This interface can't return per-pixel values */
2385 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2387 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2388 for (j
= 0; j
< 4; j
++) {
2389 r
[j
].i
[i
] = result
[j
];
2393 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2394 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2395 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2396 TGSI_EXEC_DATA_INT
);
2402 exec_sample(struct tgsi_exec_machine
*mach
,
2403 const struct tgsi_full_instruction
*inst
,
2404 uint modifier
, boolean compare
)
2406 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2407 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2408 union tgsi_exec_channel r
[5], c1
;
2409 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2410 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2412 unsigned char swizzles
[4];
2415 /* always fetch all 3 offsets, overkill but keeps code simple */
2416 fetch_texel_offsets(mach
, inst
, offsets
);
2418 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2420 if (modifier
!= TEX_MODIFIER_NONE
) {
2421 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2422 FETCH(&c1
, 3, TGSI_CHAN_X
);
2424 control
= TGSI_SAMPLER_LOD_BIAS
;
2426 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2427 FETCH(&c1
, 3, TGSI_CHAN_X
);
2429 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2432 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2433 control
= TGSI_SAMPLER_LOD_ZERO
;
2437 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2439 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2440 case TGSI_TEXTURE_1D
:
2442 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2443 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2444 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2445 NULL
, offsets
, control
,
2446 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2449 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2450 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2451 NULL
, offsets
, control
,
2452 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2456 case TGSI_TEXTURE_1D_ARRAY
:
2457 case TGSI_TEXTURE_2D
:
2458 case TGSI_TEXTURE_RECT
:
2459 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2461 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2462 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2463 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2464 NULL
, offsets
, control
,
2465 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2468 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2469 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2470 NULL
, offsets
, control
,
2471 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2475 case TGSI_TEXTURE_2D_ARRAY
:
2476 case TGSI_TEXTURE_3D
:
2477 case TGSI_TEXTURE_CUBE
:
2478 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2479 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2481 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2482 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2483 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2484 NULL
, offsets
, control
,
2485 &r
[0], &r
[1], &r
[2], &r
[3]);
2488 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2489 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2490 NULL
, offsets
, control
,
2491 &r
[0], &r
[1], &r
[2], &r
[3]);
2495 case TGSI_TEXTURE_CUBE_ARRAY
:
2496 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2497 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2498 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2500 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2501 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2502 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2503 NULL
, offsets
, control
,
2504 &r
[0], &r
[1], &r
[2], &r
[3]);
2507 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2508 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2509 NULL
, offsets
, control
,
2510 &r
[0], &r
[1], &r
[2], &r
[3]);
2519 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2520 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2521 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2522 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2524 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2525 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2526 store_dest(mach
, &r
[swizzles
[chan
]],
2527 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2533 exec_sample_d(struct tgsi_exec_machine
*mach
,
2534 const struct tgsi_full_instruction
*inst
)
2536 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2537 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2538 union tgsi_exec_channel r
[4];
2539 float derivs
[3][2][TGSI_QUAD_SIZE
];
2541 unsigned char swizzles
[4];
2544 /* always fetch all 3 offsets, overkill but keeps code simple */
2545 fetch_texel_offsets(mach
, inst
, offsets
);
2547 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2549 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2550 case TGSI_TEXTURE_1D
:
2551 case TGSI_TEXTURE_1D_ARRAY
:
2552 /* only 1D array actually needs Y */
2553 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2555 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2557 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2558 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2559 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2560 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2563 case TGSI_TEXTURE_2D
:
2564 case TGSI_TEXTURE_RECT
:
2565 case TGSI_TEXTURE_2D_ARRAY
:
2566 /* only 2D array actually needs Z */
2567 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2568 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2570 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2571 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2573 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2574 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2575 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2576 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2579 case TGSI_TEXTURE_3D
:
2580 case TGSI_TEXTURE_CUBE
:
2581 case TGSI_TEXTURE_CUBE_ARRAY
:
2582 /* only cube array actually needs W */
2583 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2584 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2585 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2587 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2588 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2589 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2591 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2592 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2593 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2594 &r
[0], &r
[1], &r
[2], &r
[3]);
2601 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2602 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2603 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2604 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2606 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2607 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2608 store_dest(mach
, &r
[swizzles
[chan
]],
2609 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2616 * Evaluate a constant-valued coefficient at the position of the
2621 struct tgsi_exec_machine
*mach
,
2627 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2628 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2633 * Evaluate a linear-valued coefficient at the position of the
2638 struct tgsi_exec_machine
*mach
,
2642 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2643 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2644 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2645 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2646 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2647 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2648 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2649 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2650 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2654 * Evaluate a perspective-valued coefficient at the position of the
2658 eval_perspective_coef(
2659 struct tgsi_exec_machine
*mach
,
2663 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2664 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2665 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2666 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2667 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2668 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2669 /* divide by W here */
2670 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2671 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2672 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2673 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2677 typedef void (* eval_coef_func
)(
2678 struct tgsi_exec_machine
*mach
,
2683 exec_declaration(struct tgsi_exec_machine
*mach
,
2684 const struct tgsi_full_declaration
*decl
)
2686 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2687 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2691 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
2692 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2693 uint first
, last
, mask
;
2695 first
= decl
->Range
.First
;
2696 last
= decl
->Range
.Last
;
2697 mask
= decl
->Declaration
.UsageMask
;
2699 /* XXX we could remove this special-case code since
2700 * mach->InterpCoefs[first].a0 should already have the
2701 * front/back-face value. But we should first update the
2702 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2703 * Then, we could remove the tgsi_exec_machine::Face field.
2705 /* XXX make FACE a system value */
2706 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2709 assert(decl
->Semantic
.Index
== 0);
2710 assert(first
== last
);
2712 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2713 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2716 eval_coef_func eval
;
2719 switch (decl
->Interp
.Interpolate
) {
2720 case TGSI_INTERPOLATE_CONSTANT
:
2721 eval
= eval_constant_coef
;
2724 case TGSI_INTERPOLATE_LINEAR
:
2725 eval
= eval_linear_coef
;
2728 case TGSI_INTERPOLATE_PERSPECTIVE
:
2729 eval
= eval_perspective_coef
;
2732 case TGSI_INTERPOLATE_COLOR
:
2733 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2741 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2742 if (mask
& (1 << j
)) {
2743 for (i
= first
; i
<= last
; i
++) {
2750 if (DEBUG_EXECUTION
) {
2752 for (i
= first
; i
<= last
; ++i
) {
2753 debug_printf("IN[%2u] = ", i
);
2754 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2758 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2759 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2760 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2761 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2762 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2769 if (decl
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
2770 mach
->SysSemanticToIndex
[decl
->Declaration
.Semantic
] = decl
->Range
.First
;
2774 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2775 const union tgsi_exec_channel
*src
);
2778 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2779 const struct tgsi_full_instruction
*inst
,
2781 enum tgsi_exec_datatype dst_datatype
,
2782 enum tgsi_exec_datatype src_datatype
)
2785 union tgsi_exec_channel src
;
2786 union tgsi_exec_channel dst
;
2788 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2790 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2791 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2792 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2798 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2799 const struct tgsi_full_instruction
*inst
,
2801 enum tgsi_exec_datatype dst_datatype
,
2802 enum tgsi_exec_datatype src_datatype
)
2805 struct tgsi_exec_vector dst
;
2807 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2808 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2809 union tgsi_exec_channel src
;
2811 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2812 op(&dst
.xyzw
[chan
], &src
);
2815 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2816 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2817 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2822 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2823 const union tgsi_exec_channel
*src0
,
2824 const union tgsi_exec_channel
*src1
);
2827 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2828 const struct tgsi_full_instruction
*inst
,
2830 enum tgsi_exec_datatype dst_datatype
,
2831 enum tgsi_exec_datatype src_datatype
)
2834 union tgsi_exec_channel src
[2];
2835 union tgsi_exec_channel dst
;
2837 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2838 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
2839 op(&dst
, &src
[0], &src
[1]);
2840 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2841 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2842 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2848 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2849 const struct tgsi_full_instruction
*inst
,
2851 enum tgsi_exec_datatype dst_datatype
,
2852 enum tgsi_exec_datatype src_datatype
)
2855 struct tgsi_exec_vector dst
;
2857 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2858 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2859 union tgsi_exec_channel src
[2];
2861 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2862 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2863 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2866 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2867 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2868 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2873 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2874 const union tgsi_exec_channel
*src0
,
2875 const union tgsi_exec_channel
*src1
,
2876 const union tgsi_exec_channel
*src2
);
2879 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2880 const struct tgsi_full_instruction
*inst
,
2881 micro_trinary_op op
,
2882 enum tgsi_exec_datatype dst_datatype
,
2883 enum tgsi_exec_datatype src_datatype
)
2886 struct tgsi_exec_vector dst
;
2888 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2889 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2890 union tgsi_exec_channel src
[3];
2892 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2893 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2894 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2895 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2898 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2899 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2900 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2905 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
2906 const union tgsi_exec_channel
*src0
,
2907 const union tgsi_exec_channel
*src1
,
2908 const union tgsi_exec_channel
*src2
,
2909 const union tgsi_exec_channel
*src3
);
2912 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
2913 const struct tgsi_full_instruction
*inst
,
2914 micro_quaternary_op op
,
2915 enum tgsi_exec_datatype dst_datatype
,
2916 enum tgsi_exec_datatype src_datatype
)
2919 struct tgsi_exec_vector dst
;
2921 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2922 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2923 union tgsi_exec_channel src
[4];
2925 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2926 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2927 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2928 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
2929 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
2932 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2933 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2934 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2940 exec_dp3(struct tgsi_exec_machine
*mach
,
2941 const struct tgsi_full_instruction
*inst
)
2944 union tgsi_exec_channel arg
[3];
2946 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2947 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2948 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2950 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2951 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2952 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2953 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2956 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2957 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2958 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2964 exec_dp4(struct tgsi_exec_machine
*mach
,
2965 const struct tgsi_full_instruction
*inst
)
2968 union tgsi_exec_channel arg
[3];
2970 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2971 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2972 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2974 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2975 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2976 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2977 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2980 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2981 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2982 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2988 exec_dp2a(struct tgsi_exec_machine
*mach
,
2989 const struct tgsi_full_instruction
*inst
)
2992 union tgsi_exec_channel arg
[3];
2994 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2995 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2996 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2998 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2999 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3000 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3002 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3003 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3005 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3006 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3007 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3013 exec_dph(struct tgsi_exec_machine
*mach
,
3014 const struct tgsi_full_instruction
*inst
)
3017 union tgsi_exec_channel arg
[3];
3019 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3020 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3021 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3023 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3024 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3025 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3027 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3028 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3029 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3031 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3032 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3034 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3035 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3036 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3042 exec_dp2(struct tgsi_exec_machine
*mach
,
3043 const struct tgsi_full_instruction
*inst
)
3046 union tgsi_exec_channel arg
[3];
3048 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3049 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3050 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3052 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3053 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3054 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3056 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3057 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3058 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3064 exec_pk2h(struct tgsi_exec_machine
*mach
,
3065 const struct tgsi_full_instruction
*inst
)
3068 union tgsi_exec_channel arg
[2], dst
;
3070 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3071 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3072 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3073 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3074 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3076 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3077 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3078 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3084 exec_up2h(struct tgsi_exec_machine
*mach
,
3085 const struct tgsi_full_instruction
*inst
)
3088 union tgsi_exec_channel arg
, dst
[2];
3090 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3091 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3092 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3093 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3095 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3096 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3097 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3103 exec_scs(struct tgsi_exec_machine
*mach
,
3104 const struct tgsi_full_instruction
*inst
)
3106 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
3107 union tgsi_exec_channel arg
;
3108 union tgsi_exec_channel result
;
3110 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3112 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3113 micro_cos(&result
, &arg
);
3114 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3116 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3117 micro_sin(&result
, &arg
);
3118 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3121 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3122 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3124 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3125 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3130 exec_xpd(struct tgsi_exec_machine
*mach
,
3131 const struct tgsi_full_instruction
*inst
)
3133 union tgsi_exec_channel r
[6];
3134 union tgsi_exec_channel d
[3];
3136 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3137 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3139 micro_mul(&r
[2], &r
[0], &r
[1]);
3141 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3142 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3144 micro_mul(&r
[5], &r
[3], &r
[4] );
3145 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
3147 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3149 micro_mul(&r
[3], &r
[3], &r
[2]);
3151 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3153 micro_mul(&r
[1], &r
[1], &r
[5]);
3154 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
3156 micro_mul(&r
[5], &r
[5], &r
[4]);
3157 micro_mul(&r
[0], &r
[0], &r
[2]);
3158 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
3160 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3161 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3163 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3164 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3166 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3167 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3169 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3170 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3175 exec_dst(struct tgsi_exec_machine
*mach
,
3176 const struct tgsi_full_instruction
*inst
)
3178 union tgsi_exec_channel r
[2];
3179 union tgsi_exec_channel d
[4];
3181 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3182 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3183 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3184 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3186 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3187 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3189 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3190 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3193 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3194 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3196 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3197 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3199 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3200 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3202 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3203 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3208 exec_log(struct tgsi_exec_machine
*mach
,
3209 const struct tgsi_full_instruction
*inst
)
3211 union tgsi_exec_channel r
[3];
3213 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3214 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3215 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3216 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3217 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3218 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3220 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3221 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3222 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3223 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3225 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3226 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3228 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3229 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3234 exec_exp(struct tgsi_exec_machine
*mach
,
3235 const struct tgsi_full_instruction
*inst
)
3237 union tgsi_exec_channel r
[3];
3239 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3240 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3241 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3242 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3243 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3245 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3246 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3247 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3249 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3250 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3251 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3253 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3254 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3259 exec_lit(struct tgsi_exec_machine
*mach
,
3260 const struct tgsi_full_instruction
*inst
)
3262 union tgsi_exec_channel r
[3];
3263 union tgsi_exec_channel d
[3];
3265 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3266 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3267 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3268 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3269 micro_max(&r
[1], &r
[1], &ZeroVec
);
3271 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3272 micro_min(&r
[2], &r
[2], &P128Vec
);
3273 micro_max(&r
[2], &r
[2], &M128Vec
);
3274 micro_pow(&r
[1], &r
[1], &r
[2]);
3275 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3276 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3278 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3279 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3280 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3283 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3284 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3287 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3288 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3293 exec_break(struct tgsi_exec_machine
*mach
)
3295 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3296 /* turn off loop channels for each enabled exec channel */
3297 mach
->LoopMask
&= ~mach
->ExecMask
;
3298 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3299 UPDATE_EXEC_MASK(mach
);
3301 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3303 mach
->Switch
.mask
= 0x0;
3305 UPDATE_EXEC_MASK(mach
);
3310 exec_switch(struct tgsi_exec_machine
*mach
,
3311 const struct tgsi_full_instruction
*inst
)
3313 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3314 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3316 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3317 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3318 mach
->Switch
.mask
= 0x0;
3319 mach
->Switch
.defaultMask
= 0x0;
3321 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3322 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3324 UPDATE_EXEC_MASK(mach
);
3328 exec_case(struct tgsi_exec_machine
*mach
,
3329 const struct tgsi_full_instruction
*inst
)
3331 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3332 union tgsi_exec_channel src
;
3335 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3337 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3340 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3343 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3346 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3350 mach
->Switch
.defaultMask
|= mask
;
3352 mach
->Switch
.mask
|= mask
& prevMask
;
3354 UPDATE_EXEC_MASK(mach
);
3357 /* FIXME: this will only work if default is last */
3359 exec_default(struct tgsi_exec_machine
*mach
)
3361 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3363 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3365 UPDATE_EXEC_MASK(mach
);
3369 exec_endswitch(struct tgsi_exec_machine
*mach
)
3371 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3372 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3374 UPDATE_EXEC_MASK(mach
);
3377 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3378 const union tgsi_double_channel
*src
);
3381 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3382 union tgsi_double_channel
*chan
,
3383 const struct tgsi_full_src_register
*reg
,
3387 union tgsi_exec_channel src
[2];
3390 fetch_source_d(mach
, &src
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3391 fetch_source_d(mach
, &src
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3393 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3394 chan
->u
[i
][0] = src
[0].u
[i
];
3395 chan
->u
[i
][1] = src
[1].u
[i
];
3397 if (reg
->Register
.Absolute
) {
3398 micro_dabs(chan
, chan
);
3400 if (reg
->Register
.Negate
) {
3401 micro_dneg(chan
, chan
);
3406 store_double_channel(struct tgsi_exec_machine
*mach
,
3407 const union tgsi_double_channel
*chan
,
3408 const struct tgsi_full_dst_register
*reg
,
3409 const struct tgsi_full_instruction
*inst
,
3413 union tgsi_exec_channel dst
[2];
3415 union tgsi_double_channel temp
;
3416 const uint execmask
= mach
->ExecMask
;
3418 if (!inst
->Instruction
.Saturate
) {
3419 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3420 if (execmask
& (1 << i
)) {
3421 dst
[0].u
[i
] = chan
->u
[i
][0];
3422 dst
[1].u
[i
] = chan
->u
[i
][1];
3426 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3427 if (execmask
& (1 << i
)) {
3428 if (chan
->d
[i
] < 0.0)
3430 else if (chan
->d
[i
] > 1.0)
3433 temp
.d
[i
] = chan
->d
[i
];
3435 dst
[0].u
[i
] = temp
.u
[i
][0];
3436 dst
[1].u
[i
] = temp
.u
[i
][1];
3440 store_dest_double(mach
, &dst
[0], reg
, inst
, chan_0
, TGSI_EXEC_DATA_UINT
);
3442 store_dest_double(mach
, &dst
[1], reg
, inst
, chan_1
, TGSI_EXEC_DATA_UINT
);
3446 exec_double_unary(struct tgsi_exec_machine
*mach
,
3447 const struct tgsi_full_instruction
*inst
,
3450 union tgsi_double_channel src
;
3451 union tgsi_double_channel dst
;
3453 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3454 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3456 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3458 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3459 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3461 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3466 exec_double_binary(struct tgsi_exec_machine
*mach
,
3467 const struct tgsi_full_instruction
*inst
,
3469 enum tgsi_exec_datatype dst_datatype
)
3471 union tgsi_double_channel src
[2];
3472 union tgsi_double_channel dst
;
3473 int first_dest_chan
, second_dest_chan
;
3476 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3477 /* these are & because of the way DSLT etc store their destinations */
3478 if (wmask
& TGSI_WRITEMASK_XY
) {
3479 first_dest_chan
= TGSI_CHAN_X
;
3480 second_dest_chan
= TGSI_CHAN_Y
;
3481 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3482 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3483 second_dest_chan
= -1;
3486 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3487 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3489 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3492 if (wmask
& TGSI_WRITEMASK_ZW
) {
3493 first_dest_chan
= TGSI_CHAN_Z
;
3494 second_dest_chan
= TGSI_CHAN_W
;
3495 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3496 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3497 second_dest_chan
= -1;
3500 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3501 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3503 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3508 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3509 const struct tgsi_full_instruction
*inst
,
3512 union tgsi_double_channel src
[3];
3513 union tgsi_double_channel dst
;
3515 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3516 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3517 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3518 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3520 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3522 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3523 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3524 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3525 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3527 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3532 exec_f2d(struct tgsi_exec_machine
*mach
,
3533 const struct tgsi_full_instruction
*inst
)
3535 union tgsi_exec_channel src
;
3536 union tgsi_double_channel dst
;
3538 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3539 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3540 micro_f2d(&dst
, &src
);
3541 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3543 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3544 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3545 micro_f2d(&dst
, &src
);
3546 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3551 exec_d2f(struct tgsi_exec_machine
*mach
,
3552 const struct tgsi_full_instruction
*inst
)
3554 union tgsi_double_channel src
;
3555 union tgsi_exec_channel dst
;
3556 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3559 for (i
= 0; i
< 2; i
++) {
3562 wm
&= ~(1 << (bit
- 1));
3564 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3566 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3567 micro_d2f(&dst
, &src
);
3568 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_FLOAT
);
3574 exec_i2d(struct tgsi_exec_machine
*mach
,
3575 const struct tgsi_full_instruction
*inst
)
3577 union tgsi_exec_channel src
;
3578 union tgsi_double_channel dst
;
3580 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3581 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3582 micro_i2d(&dst
, &src
);
3583 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3585 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3586 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_INT
);
3587 micro_i2d(&dst
, &src
);
3588 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3593 exec_d2i(struct tgsi_exec_machine
*mach
,
3594 const struct tgsi_full_instruction
*inst
)
3596 union tgsi_double_channel src
;
3597 union tgsi_exec_channel dst
;
3598 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3601 for (i
= 0; i
< 2; i
++) {
3604 wm
&= ~(1 << (bit
- 1));
3606 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3608 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3609 micro_d2i(&dst
, &src
);
3610 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_INT
);
3615 exec_u2d(struct tgsi_exec_machine
*mach
,
3616 const struct tgsi_full_instruction
*inst
)
3618 union tgsi_exec_channel src
;
3619 union tgsi_double_channel dst
;
3621 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3622 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3623 micro_u2d(&dst
, &src
);
3624 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3626 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3627 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_UINT
);
3628 micro_u2d(&dst
, &src
);
3629 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3634 exec_d2u(struct tgsi_exec_machine
*mach
,
3635 const struct tgsi_full_instruction
*inst
)
3637 union tgsi_double_channel src
;
3638 union tgsi_exec_channel dst
;
3639 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3642 for (i
= 0; i
< 2; i
++) {
3645 wm
&= ~(1 << (bit
- 1));
3647 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3649 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3650 micro_d2u(&dst
, &src
);
3651 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_UINT
);
3657 exec_dldexp(struct tgsi_exec_machine
*mach
,
3658 const struct tgsi_full_instruction
*inst
)
3660 union tgsi_double_channel src0
;
3661 union tgsi_exec_channel src1
;
3662 union tgsi_double_channel dst
;
3665 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3666 if (wmask
& TGSI_WRITEMASK_XY
) {
3667 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3668 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3669 micro_dldexp(&dst
, &src0
, &src1
);
3670 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3673 if (wmask
& TGSI_WRITEMASK_ZW
) {
3674 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3675 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3676 micro_dldexp(&dst
, &src0
, &src1
);
3677 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3682 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3683 const struct tgsi_full_instruction
*inst
)
3685 union tgsi_double_channel src
;
3686 union tgsi_double_channel dst
;
3687 union tgsi_exec_channel dst_exp
;
3689 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)) {
3690 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3691 micro_dfracexp(&dst
, &dst_exp
, &src
);
3692 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3693 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3695 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)) {
3696 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3697 micro_dfracexp(&dst
, &dst_exp
, &src
);
3698 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3699 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3705 micro_i2f(union tgsi_exec_channel
*dst
,
3706 const union tgsi_exec_channel
*src
)
3708 dst
->f
[0] = (float)src
->i
[0];
3709 dst
->f
[1] = (float)src
->i
[1];
3710 dst
->f
[2] = (float)src
->i
[2];
3711 dst
->f
[3] = (float)src
->i
[3];
3715 micro_not(union tgsi_exec_channel
*dst
,
3716 const union tgsi_exec_channel
*src
)
3718 dst
->u
[0] = ~src
->u
[0];
3719 dst
->u
[1] = ~src
->u
[1];
3720 dst
->u
[2] = ~src
->u
[2];
3721 dst
->u
[3] = ~src
->u
[3];
3725 micro_shl(union tgsi_exec_channel
*dst
,
3726 const union tgsi_exec_channel
*src0
,
3727 const union tgsi_exec_channel
*src1
)
3729 unsigned masked_count
;
3730 masked_count
= src1
->u
[0] & 0x1f;
3731 dst
->u
[0] = src0
->u
[0] << masked_count
;
3732 masked_count
= src1
->u
[1] & 0x1f;
3733 dst
->u
[1] = src0
->u
[1] << masked_count
;
3734 masked_count
= src1
->u
[2] & 0x1f;
3735 dst
->u
[2] = src0
->u
[2] << masked_count
;
3736 masked_count
= src1
->u
[3] & 0x1f;
3737 dst
->u
[3] = src0
->u
[3] << masked_count
;
3741 micro_and(union tgsi_exec_channel
*dst
,
3742 const union tgsi_exec_channel
*src0
,
3743 const union tgsi_exec_channel
*src1
)
3745 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
3746 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
3747 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
3748 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
3752 micro_or(union tgsi_exec_channel
*dst
,
3753 const union tgsi_exec_channel
*src0
,
3754 const union tgsi_exec_channel
*src1
)
3756 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
3757 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
3758 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
3759 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
3763 micro_xor(union tgsi_exec_channel
*dst
,
3764 const union tgsi_exec_channel
*src0
,
3765 const union tgsi_exec_channel
*src1
)
3767 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
3768 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
3769 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
3770 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
3774 micro_mod(union tgsi_exec_channel
*dst
,
3775 const union tgsi_exec_channel
*src0
,
3776 const union tgsi_exec_channel
*src1
)
3778 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
3779 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
3780 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
3781 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
3785 micro_f2i(union tgsi_exec_channel
*dst
,
3786 const union tgsi_exec_channel
*src
)
3788 dst
->i
[0] = (int)src
->f
[0];
3789 dst
->i
[1] = (int)src
->f
[1];
3790 dst
->i
[2] = (int)src
->f
[2];
3791 dst
->i
[3] = (int)src
->f
[3];
3795 micro_fseq(union tgsi_exec_channel
*dst
,
3796 const union tgsi_exec_channel
*src0
,
3797 const union tgsi_exec_channel
*src1
)
3799 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
3800 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
3801 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
3802 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
3806 micro_fsge(union tgsi_exec_channel
*dst
,
3807 const union tgsi_exec_channel
*src0
,
3808 const union tgsi_exec_channel
*src1
)
3810 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
3811 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
3812 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
3813 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
3817 micro_fslt(union tgsi_exec_channel
*dst
,
3818 const union tgsi_exec_channel
*src0
,
3819 const union tgsi_exec_channel
*src1
)
3821 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
3822 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
3823 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
3824 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
3828 micro_fsne(union tgsi_exec_channel
*dst
,
3829 const union tgsi_exec_channel
*src0
,
3830 const union tgsi_exec_channel
*src1
)
3832 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
3833 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
3834 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
3835 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
3839 micro_idiv(union tgsi_exec_channel
*dst
,
3840 const union tgsi_exec_channel
*src0
,
3841 const union tgsi_exec_channel
*src1
)
3843 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
3844 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
3845 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
3846 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
3850 micro_imax(union tgsi_exec_channel
*dst
,
3851 const union tgsi_exec_channel
*src0
,
3852 const union tgsi_exec_channel
*src1
)
3854 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3855 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3856 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3857 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3861 micro_imin(union tgsi_exec_channel
*dst
,
3862 const union tgsi_exec_channel
*src0
,
3863 const union tgsi_exec_channel
*src1
)
3865 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3866 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3867 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3868 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3872 micro_isge(union tgsi_exec_channel
*dst
,
3873 const union tgsi_exec_channel
*src0
,
3874 const union tgsi_exec_channel
*src1
)
3876 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
3877 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
3878 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
3879 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
3883 micro_ishr(union tgsi_exec_channel
*dst
,
3884 const union tgsi_exec_channel
*src0
,
3885 const union tgsi_exec_channel
*src1
)
3887 unsigned masked_count
;
3888 masked_count
= src1
->i
[0] & 0x1f;
3889 dst
->i
[0] = src0
->i
[0] >> masked_count
;
3890 masked_count
= src1
->i
[1] & 0x1f;
3891 dst
->i
[1] = src0
->i
[1] >> masked_count
;
3892 masked_count
= src1
->i
[2] & 0x1f;
3893 dst
->i
[2] = src0
->i
[2] >> masked_count
;
3894 masked_count
= src1
->i
[3] & 0x1f;
3895 dst
->i
[3] = src0
->i
[3] >> masked_count
;
3899 micro_islt(union tgsi_exec_channel
*dst
,
3900 const union tgsi_exec_channel
*src0
,
3901 const union tgsi_exec_channel
*src1
)
3903 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
3904 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
3905 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
3906 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
3910 micro_f2u(union tgsi_exec_channel
*dst
,
3911 const union tgsi_exec_channel
*src
)
3913 dst
->u
[0] = (uint
)src
->f
[0];
3914 dst
->u
[1] = (uint
)src
->f
[1];
3915 dst
->u
[2] = (uint
)src
->f
[2];
3916 dst
->u
[3] = (uint
)src
->f
[3];
3920 micro_u2f(union tgsi_exec_channel
*dst
,
3921 const union tgsi_exec_channel
*src
)
3923 dst
->f
[0] = (float)src
->u
[0];
3924 dst
->f
[1] = (float)src
->u
[1];
3925 dst
->f
[2] = (float)src
->u
[2];
3926 dst
->f
[3] = (float)src
->u
[3];
3930 micro_uadd(union tgsi_exec_channel
*dst
,
3931 const union tgsi_exec_channel
*src0
,
3932 const union tgsi_exec_channel
*src1
)
3934 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
3935 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
3936 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
3937 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
3941 micro_udiv(union tgsi_exec_channel
*dst
,
3942 const union tgsi_exec_channel
*src0
,
3943 const union tgsi_exec_channel
*src1
)
3945 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
3946 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
3947 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
3948 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
3952 micro_umad(union tgsi_exec_channel
*dst
,
3953 const union tgsi_exec_channel
*src0
,
3954 const union tgsi_exec_channel
*src1
,
3955 const union tgsi_exec_channel
*src2
)
3957 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
3958 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
3959 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
3960 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
3964 micro_umax(union tgsi_exec_channel
*dst
,
3965 const union tgsi_exec_channel
*src0
,
3966 const union tgsi_exec_channel
*src1
)
3968 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3969 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3970 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3971 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3975 micro_umin(union tgsi_exec_channel
*dst
,
3976 const union tgsi_exec_channel
*src0
,
3977 const union tgsi_exec_channel
*src1
)
3979 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3980 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3981 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3982 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3986 micro_umod(union tgsi_exec_channel
*dst
,
3987 const union tgsi_exec_channel
*src0
,
3988 const union tgsi_exec_channel
*src1
)
3990 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
3991 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
3992 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
3993 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
3997 micro_umul(union tgsi_exec_channel
*dst
,
3998 const union tgsi_exec_channel
*src0
,
3999 const union tgsi_exec_channel
*src1
)
4001 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4002 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4003 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4004 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4008 micro_imul_hi(union tgsi_exec_channel
*dst
,
4009 const union tgsi_exec_channel
*src0
,
4010 const union tgsi_exec_channel
*src1
)
4012 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4013 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4014 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4015 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4016 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4021 micro_umul_hi(union tgsi_exec_channel
*dst
,
4022 const union tgsi_exec_channel
*src0
,
4023 const union tgsi_exec_channel
*src1
)
4025 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4026 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4027 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4028 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4029 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4034 micro_useq(union tgsi_exec_channel
*dst
,
4035 const union tgsi_exec_channel
*src0
,
4036 const union tgsi_exec_channel
*src1
)
4038 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4039 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4040 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4041 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4045 micro_usge(union tgsi_exec_channel
*dst
,
4046 const union tgsi_exec_channel
*src0
,
4047 const union tgsi_exec_channel
*src1
)
4049 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4050 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4051 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4052 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4056 micro_ushr(union tgsi_exec_channel
*dst
,
4057 const union tgsi_exec_channel
*src0
,
4058 const union tgsi_exec_channel
*src1
)
4060 unsigned masked_count
;
4061 masked_count
= src1
->u
[0] & 0x1f;
4062 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4063 masked_count
= src1
->u
[1] & 0x1f;
4064 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4065 masked_count
= src1
->u
[2] & 0x1f;
4066 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4067 masked_count
= src1
->u
[3] & 0x1f;
4068 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4072 micro_uslt(union tgsi_exec_channel
*dst
,
4073 const union tgsi_exec_channel
*src0
,
4074 const union tgsi_exec_channel
*src1
)
4076 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4077 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4078 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4079 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4083 micro_usne(union tgsi_exec_channel
*dst
,
4084 const union tgsi_exec_channel
*src0
,
4085 const union tgsi_exec_channel
*src1
)
4087 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4088 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4089 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4090 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4094 micro_uarl(union tgsi_exec_channel
*dst
,
4095 const union tgsi_exec_channel
*src
)
4097 dst
->i
[0] = src
->u
[0];
4098 dst
->i
[1] = src
->u
[1];
4099 dst
->i
[2] = src
->u
[2];
4100 dst
->i
[3] = src
->u
[3];
4104 micro_ucmp(union tgsi_exec_channel
*dst
,
4105 const union tgsi_exec_channel
*src0
,
4106 const union tgsi_exec_channel
*src1
,
4107 const union tgsi_exec_channel
*src2
)
4109 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
4110 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
4111 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
4112 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
4116 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4119 micro_ibfe(union tgsi_exec_channel
*dst
,
4120 const union tgsi_exec_channel
*src0
,
4121 const union tgsi_exec_channel
*src1
,
4122 const union tgsi_exec_channel
*src2
)
4125 for (i
= 0; i
< 4; i
++) {
4126 int width
= src2
->i
[i
] & 0x1f;
4127 int offset
= src1
->i
[i
] & 0x1f;
4130 else if (width
+ offset
< 32)
4131 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
4133 dst
->i
[i
] = src0
->i
[i
] >> offset
;
4138 * Unsigned bitfield extract
4141 micro_ubfe(union tgsi_exec_channel
*dst
,
4142 const union tgsi_exec_channel
*src0
,
4143 const union tgsi_exec_channel
*src1
,
4144 const union tgsi_exec_channel
*src2
)
4147 for (i
= 0; i
< 4; i
++) {
4148 int width
= src2
->u
[i
] & 0x1f;
4149 int offset
= src1
->u
[i
] & 0x1f;
4152 else if (width
+ offset
< 32)
4153 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
4155 dst
->u
[i
] = src0
->u
[i
] >> offset
;
4160 * Bitfield insert: copy low bits from src1 into a region of src0.
4163 micro_bfi(union tgsi_exec_channel
*dst
,
4164 const union tgsi_exec_channel
*src0
,
4165 const union tgsi_exec_channel
*src1
,
4166 const union tgsi_exec_channel
*src2
,
4167 const union tgsi_exec_channel
*src3
)
4170 for (i
= 0; i
< 4; i
++) {
4171 int width
= src3
->u
[i
] & 0x1f;
4172 int offset
= src2
->u
[i
] & 0x1f;
4173 int bitmask
= ((1 << width
) - 1) << offset
;
4174 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
4179 micro_brev(union tgsi_exec_channel
*dst
,
4180 const union tgsi_exec_channel
*src
)
4182 dst
->u
[0] = util_bitreverse(src
->u
[0]);
4183 dst
->u
[1] = util_bitreverse(src
->u
[1]);
4184 dst
->u
[2] = util_bitreverse(src
->u
[2]);
4185 dst
->u
[3] = util_bitreverse(src
->u
[3]);
4189 micro_popc(union tgsi_exec_channel
*dst
,
4190 const union tgsi_exec_channel
*src
)
4192 dst
->u
[0] = util_bitcount(src
->u
[0]);
4193 dst
->u
[1] = util_bitcount(src
->u
[1]);
4194 dst
->u
[2] = util_bitcount(src
->u
[2]);
4195 dst
->u
[3] = util_bitcount(src
->u
[3]);
4199 micro_lsb(union tgsi_exec_channel
*dst
,
4200 const union tgsi_exec_channel
*src
)
4202 dst
->i
[0] = ffs(src
->u
[0]) - 1;
4203 dst
->i
[1] = ffs(src
->u
[1]) - 1;
4204 dst
->i
[2] = ffs(src
->u
[2]) - 1;
4205 dst
->i
[3] = ffs(src
->u
[3]) - 1;
4209 micro_imsb(union tgsi_exec_channel
*dst
,
4210 const union tgsi_exec_channel
*src
)
4212 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
4213 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
4214 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
4215 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
4219 micro_umsb(union tgsi_exec_channel
*dst
,
4220 const union tgsi_exec_channel
*src
)
4222 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
4223 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
4224 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
4225 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
4230 struct tgsi_exec_machine
*mach
,
4231 const struct tgsi_full_instruction
*inst
,
4234 union tgsi_exec_channel r
[10];
4238 switch (inst
->Instruction
.Opcode
) {
4239 case TGSI_OPCODE_ARL
:
4240 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4243 case TGSI_OPCODE_MOV
:
4244 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4247 case TGSI_OPCODE_LIT
:
4248 exec_lit(mach
, inst
);
4251 case TGSI_OPCODE_RCP
:
4252 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4255 case TGSI_OPCODE_RSQ
:
4256 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4259 case TGSI_OPCODE_EXP
:
4260 exec_exp(mach
, inst
);
4263 case TGSI_OPCODE_LOG
:
4264 exec_log(mach
, inst
);
4267 case TGSI_OPCODE_MUL
:
4268 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4271 case TGSI_OPCODE_ADD
:
4272 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4275 case TGSI_OPCODE_DP3
:
4276 exec_dp3(mach
, inst
);
4279 case TGSI_OPCODE_DP4
:
4280 exec_dp4(mach
, inst
);
4283 case TGSI_OPCODE_DST
:
4284 exec_dst(mach
, inst
);
4287 case TGSI_OPCODE_MIN
:
4288 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4291 case TGSI_OPCODE_MAX
:
4292 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4295 case TGSI_OPCODE_SLT
:
4296 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4299 case TGSI_OPCODE_SGE
:
4300 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4303 case TGSI_OPCODE_MAD
:
4304 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4307 case TGSI_OPCODE_SUB
:
4308 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4311 case TGSI_OPCODE_LRP
:
4312 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4315 case TGSI_OPCODE_SQRT
:
4316 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4319 case TGSI_OPCODE_DP2A
:
4320 exec_dp2a(mach
, inst
);
4323 case TGSI_OPCODE_FRC
:
4324 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4327 case TGSI_OPCODE_CLAMP
:
4328 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4331 case TGSI_OPCODE_FLR
:
4332 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4335 case TGSI_OPCODE_ROUND
:
4336 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4339 case TGSI_OPCODE_EX2
:
4340 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4343 case TGSI_OPCODE_LG2
:
4344 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4347 case TGSI_OPCODE_POW
:
4348 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4351 case TGSI_OPCODE_XPD
:
4352 exec_xpd(mach
, inst
);
4355 case TGSI_OPCODE_ABS
:
4356 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4359 case TGSI_OPCODE_DPH
:
4360 exec_dph(mach
, inst
);
4363 case TGSI_OPCODE_COS
:
4364 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4367 case TGSI_OPCODE_DDX
:
4368 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4371 case TGSI_OPCODE_DDY
:
4372 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4375 case TGSI_OPCODE_KILL
:
4376 exec_kill (mach
, inst
);
4379 case TGSI_OPCODE_KILL_IF
:
4380 exec_kill_if (mach
, inst
);
4383 case TGSI_OPCODE_PK2H
:
4384 exec_pk2h(mach
, inst
);
4387 case TGSI_OPCODE_PK2US
:
4391 case TGSI_OPCODE_PK4B
:
4395 case TGSI_OPCODE_PK4UB
:
4399 case TGSI_OPCODE_SEQ
:
4400 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4403 case TGSI_OPCODE_SGT
:
4404 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4407 case TGSI_OPCODE_SIN
:
4408 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4411 case TGSI_OPCODE_SLE
:
4412 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4415 case TGSI_OPCODE_SNE
:
4416 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4419 case TGSI_OPCODE_TEX
:
4420 /* simple texture lookup */
4421 /* src[0] = texcoord */
4422 /* src[1] = sampler unit */
4423 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
4426 case TGSI_OPCODE_TXB
:
4427 /* Texture lookup with lod bias */
4428 /* src[0] = texcoord (src[0].w = LOD bias) */
4429 /* src[1] = sampler unit */
4430 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
4433 case TGSI_OPCODE_TXD
:
4434 /* Texture lookup with explict partial derivatives */
4435 /* src[0] = texcoord */
4436 /* src[1] = d[strq]/dx */
4437 /* src[2] = d[strq]/dy */
4438 /* src[3] = sampler unit */
4439 exec_txd(mach
, inst
);
4442 case TGSI_OPCODE_TXL
:
4443 /* Texture lookup with explit LOD */
4444 /* src[0] = texcoord (src[0].w = LOD) */
4445 /* src[1] = sampler unit */
4446 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
4449 case TGSI_OPCODE_TXP
:
4450 /* Texture lookup with projection */
4451 /* src[0] = texcoord (src[0].w = projection) */
4452 /* src[1] = sampler unit */
4453 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
4456 case TGSI_OPCODE_TG4
:
4457 /* src[0] = texcoord */
4458 /* src[1] = component */
4459 /* src[2] = sampler unit */
4460 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
4463 case TGSI_OPCODE_LODQ
:
4464 /* src[0] = texcoord */
4465 /* src[1] = sampler unit */
4466 exec_lodq(mach
, inst
);
4469 case TGSI_OPCODE_UP2H
:
4470 exec_up2h(mach
, inst
);
4473 case TGSI_OPCODE_UP2US
:
4477 case TGSI_OPCODE_UP4B
:
4481 case TGSI_OPCODE_UP4UB
:
4485 case TGSI_OPCODE_ARR
:
4486 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4489 case TGSI_OPCODE_CAL
:
4490 /* skip the call if no execution channels are enabled */
4491 if (mach
->ExecMask
) {
4494 /* First, record the depths of the execution stacks.
4495 * This is important for deeply nested/looped return statements.
4496 * We have to unwind the stacks by the correct amount. For a
4497 * real code generator, we could determine the number of entries
4498 * to pop off each stack with simple static analysis and avoid
4499 * implementing this data structure at run time.
4501 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
4502 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
4503 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
4504 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
4505 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
4506 /* note that PC was already incremented above */
4507 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
4509 mach
->CallStackTop
++;
4511 /* Second, push the Cond, Loop, Cont, Func stacks */
4512 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4513 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4514 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4515 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
4516 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4517 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
4519 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4520 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4521 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4522 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
4523 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4524 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
4526 /* Finally, jump to the subroutine. The label is a pointer
4527 * (an instruction number) to the BGNSUB instruction.
4529 *pc
= inst
->Label
.Label
;
4530 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
4531 == TGSI_OPCODE_BGNSUB
);
4535 case TGSI_OPCODE_RET
:
4536 mach
->FuncMask
&= ~mach
->ExecMask
;
4537 UPDATE_EXEC_MASK(mach
);
4539 if (mach
->FuncMask
== 0x0) {
4540 /* really return now (otherwise, keep executing */
4542 if (mach
->CallStackTop
== 0) {
4543 /* returning from main() */
4544 mach
->CondStackTop
= 0;
4545 mach
->LoopStackTop
= 0;
4550 assert(mach
->CallStackTop
> 0);
4551 mach
->CallStackTop
--;
4553 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
4554 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
4556 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
4557 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
4559 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
4560 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
4562 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
4563 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
4565 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
4566 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
4568 assert(mach
->FuncStackTop
> 0);
4569 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4571 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4573 UPDATE_EXEC_MASK(mach
);
4577 case TGSI_OPCODE_SSG
:
4578 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4581 case TGSI_OPCODE_CMP
:
4582 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4585 case TGSI_OPCODE_SCS
:
4586 exec_scs(mach
, inst
);
4589 case TGSI_OPCODE_DIV
:
4590 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4593 case TGSI_OPCODE_DP2
:
4594 exec_dp2(mach
, inst
);
4597 case TGSI_OPCODE_IF
:
4599 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4600 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4601 FETCH( &r
[0], 0, TGSI_CHAN_X
);
4602 /* update CondMask */
4604 mach
->CondMask
&= ~0x1;
4607 mach
->CondMask
&= ~0x2;
4610 mach
->CondMask
&= ~0x4;
4613 mach
->CondMask
&= ~0x8;
4615 UPDATE_EXEC_MASK(mach
);
4616 /* Todo: If CondMask==0, jump to ELSE */
4619 case TGSI_OPCODE_UIF
:
4621 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4622 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4623 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
4624 /* update CondMask */
4626 mach
->CondMask
&= ~0x1;
4629 mach
->CondMask
&= ~0x2;
4632 mach
->CondMask
&= ~0x4;
4635 mach
->CondMask
&= ~0x8;
4637 UPDATE_EXEC_MASK(mach
);
4638 /* Todo: If CondMask==0, jump to ELSE */
4641 case TGSI_OPCODE_ELSE
:
4642 /* invert CondMask wrt previous mask */
4645 assert(mach
->CondStackTop
> 0);
4646 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
4647 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
4648 UPDATE_EXEC_MASK(mach
);
4649 /* Todo: If CondMask==0, jump to ENDIF */
4653 case TGSI_OPCODE_ENDIF
:
4655 assert(mach
->CondStackTop
> 0);
4656 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
4657 UPDATE_EXEC_MASK(mach
);
4660 case TGSI_OPCODE_END
:
4661 /* make sure we end primitives which haven't
4662 * been explicitly emitted */
4663 conditional_emit_primitive(mach
);
4664 /* halt execution */
4668 case TGSI_OPCODE_PUSHA
:
4672 case TGSI_OPCODE_POPA
:
4676 case TGSI_OPCODE_CEIL
:
4677 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4680 case TGSI_OPCODE_I2F
:
4681 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
4684 case TGSI_OPCODE_NOT
:
4685 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4688 case TGSI_OPCODE_TRUNC
:
4689 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4692 case TGSI_OPCODE_SHL
:
4693 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4696 case TGSI_OPCODE_AND
:
4697 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4700 case TGSI_OPCODE_OR
:
4701 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4704 case TGSI_OPCODE_MOD
:
4705 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4708 case TGSI_OPCODE_XOR
:
4709 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4712 case TGSI_OPCODE_SAD
:
4716 case TGSI_OPCODE_TXF
:
4717 exec_txf(mach
, inst
);
4720 case TGSI_OPCODE_TXQ
:
4721 exec_txq(mach
, inst
);
4724 case TGSI_OPCODE_EMIT
:
4728 case TGSI_OPCODE_ENDPRIM
:
4729 emit_primitive(mach
);
4732 case TGSI_OPCODE_BGNLOOP
:
4733 /* push LoopMask and ContMasks */
4734 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4735 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4736 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4737 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4739 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4740 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4741 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
4742 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4743 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
4746 case TGSI_OPCODE_ENDLOOP
:
4747 /* Restore ContMask, but don't pop */
4748 assert(mach
->ContStackTop
> 0);
4749 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
4750 UPDATE_EXEC_MASK(mach
);
4751 if (mach
->ExecMask
) {
4752 /* repeat loop: jump to instruction just past BGNLOOP */
4753 assert(mach
->LoopLabelStackTop
> 0);
4754 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
4757 /* exit loop: pop LoopMask */
4758 assert(mach
->LoopStackTop
> 0);
4759 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
4761 assert(mach
->ContStackTop
> 0);
4762 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
4763 assert(mach
->LoopLabelStackTop
> 0);
4764 --mach
->LoopLabelStackTop
;
4766 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
4768 UPDATE_EXEC_MASK(mach
);
4771 case TGSI_OPCODE_BRK
:
4775 case TGSI_OPCODE_CONT
:
4776 /* turn off cont channels for each enabled exec channel */
4777 mach
->ContMask
&= ~mach
->ExecMask
;
4778 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4779 UPDATE_EXEC_MASK(mach
);
4782 case TGSI_OPCODE_BGNSUB
:
4786 case TGSI_OPCODE_ENDSUB
:
4788 * XXX: This really should be a no-op. We should never reach this opcode.
4791 assert(mach
->CallStackTop
> 0);
4792 mach
->CallStackTop
--;
4794 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
4795 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
4797 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
4798 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
4800 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
4801 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
4803 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
4804 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
4806 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
4807 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
4809 assert(mach
->FuncStackTop
> 0);
4810 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4812 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4814 UPDATE_EXEC_MASK(mach
);
4817 case TGSI_OPCODE_NOP
:
4820 case TGSI_OPCODE_BREAKC
:
4821 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4822 /* update CondMask */
4823 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
4824 mach
->LoopMask
&= ~0x1;
4826 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
4827 mach
->LoopMask
&= ~0x2;
4829 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
4830 mach
->LoopMask
&= ~0x4;
4832 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
4833 mach
->LoopMask
&= ~0x8;
4835 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4836 UPDATE_EXEC_MASK(mach
);
4839 case TGSI_OPCODE_F2I
:
4840 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4843 case TGSI_OPCODE_FSEQ
:
4844 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4847 case TGSI_OPCODE_FSGE
:
4848 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4851 case TGSI_OPCODE_FSLT
:
4852 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4855 case TGSI_OPCODE_FSNE
:
4856 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4859 case TGSI_OPCODE_IDIV
:
4860 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4863 case TGSI_OPCODE_IMAX
:
4864 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4867 case TGSI_OPCODE_IMIN
:
4868 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4871 case TGSI_OPCODE_INEG
:
4872 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4875 case TGSI_OPCODE_ISGE
:
4876 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4879 case TGSI_OPCODE_ISHR
:
4880 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4883 case TGSI_OPCODE_ISLT
:
4884 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4887 case TGSI_OPCODE_F2U
:
4888 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4891 case TGSI_OPCODE_U2F
:
4892 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
4895 case TGSI_OPCODE_UADD
:
4896 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4899 case TGSI_OPCODE_UDIV
:
4900 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4903 case TGSI_OPCODE_UMAD
:
4904 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4907 case TGSI_OPCODE_UMAX
:
4908 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4911 case TGSI_OPCODE_UMIN
:
4912 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4915 case TGSI_OPCODE_UMOD
:
4916 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4919 case TGSI_OPCODE_UMUL
:
4920 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4923 case TGSI_OPCODE_IMUL_HI
:
4924 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4927 case TGSI_OPCODE_UMUL_HI
:
4928 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4931 case TGSI_OPCODE_USEQ
:
4932 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4935 case TGSI_OPCODE_USGE
:
4936 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4939 case TGSI_OPCODE_USHR
:
4940 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4943 case TGSI_OPCODE_USLT
:
4944 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4947 case TGSI_OPCODE_USNE
:
4948 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4951 case TGSI_OPCODE_SWITCH
:
4952 exec_switch(mach
, inst
);
4955 case TGSI_OPCODE_CASE
:
4956 exec_case(mach
, inst
);
4959 case TGSI_OPCODE_DEFAULT
:
4963 case TGSI_OPCODE_ENDSWITCH
:
4964 exec_endswitch(mach
);
4967 case TGSI_OPCODE_SAMPLE_I
:
4968 exec_txf(mach
, inst
);
4971 case TGSI_OPCODE_SAMPLE_I_MS
:
4972 exec_txf(mach
, inst
);
4975 case TGSI_OPCODE_SAMPLE
:
4976 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
4979 case TGSI_OPCODE_SAMPLE_B
:
4980 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
4983 case TGSI_OPCODE_SAMPLE_C
:
4984 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
4987 case TGSI_OPCODE_SAMPLE_C_LZ
:
4988 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
4991 case TGSI_OPCODE_SAMPLE_D
:
4992 exec_sample_d(mach
, inst
);
4995 case TGSI_OPCODE_SAMPLE_L
:
4996 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
4999 case TGSI_OPCODE_GATHER4
:
5003 case TGSI_OPCODE_SVIEWINFO
:
5004 exec_txq(mach
, inst
);
5007 case TGSI_OPCODE_SAMPLE_POS
:
5011 case TGSI_OPCODE_SAMPLE_INFO
:
5015 case TGSI_OPCODE_UARL
:
5016 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5019 case TGSI_OPCODE_UCMP
:
5020 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5023 case TGSI_OPCODE_IABS
:
5024 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5027 case TGSI_OPCODE_ISSG
:
5028 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5031 case TGSI_OPCODE_TEX2
:
5032 /* simple texture lookup */
5033 /* src[0] = texcoord */
5034 /* src[1] = compare */
5035 /* src[2] = sampler unit */
5036 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5038 case TGSI_OPCODE_TXB2
:
5039 /* simple texture lookup */
5040 /* src[0] = texcoord */
5042 /* src[2] = sampler unit */
5043 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5045 case TGSI_OPCODE_TXL2
:
5046 /* simple texture lookup */
5047 /* src[0] = texcoord */
5049 /* src[2] = sampler unit */
5050 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5053 case TGSI_OPCODE_IBFE
:
5054 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5056 case TGSI_OPCODE_UBFE
:
5057 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5059 case TGSI_OPCODE_BFI
:
5060 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5062 case TGSI_OPCODE_BREV
:
5063 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5065 case TGSI_OPCODE_POPC
:
5066 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5068 case TGSI_OPCODE_LSB
:
5069 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5071 case TGSI_OPCODE_IMSB
:
5072 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5074 case TGSI_OPCODE_UMSB
:
5075 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5078 case TGSI_OPCODE_F2D
:
5079 exec_f2d(mach
, inst
);
5082 case TGSI_OPCODE_D2F
:
5083 exec_d2f(mach
, inst
);
5086 case TGSI_OPCODE_DABS
:
5087 exec_double_unary(mach
, inst
, micro_dabs
);
5090 case TGSI_OPCODE_DNEG
:
5091 exec_double_unary(mach
, inst
, micro_dneg
);
5094 case TGSI_OPCODE_DADD
:
5095 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5098 case TGSI_OPCODE_DMUL
:
5099 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
5102 case TGSI_OPCODE_DMAX
:
5103 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
5106 case TGSI_OPCODE_DMIN
:
5107 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
5110 case TGSI_OPCODE_DSLT
:
5111 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
5114 case TGSI_OPCODE_DSGE
:
5115 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
5118 case TGSI_OPCODE_DSEQ
:
5119 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
5122 case TGSI_OPCODE_DSNE
:
5123 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
5126 case TGSI_OPCODE_DRCP
:
5127 exec_double_unary(mach
, inst
, micro_drcp
);
5130 case TGSI_OPCODE_DSQRT
:
5131 exec_double_unary(mach
, inst
, micro_dsqrt
);
5134 case TGSI_OPCODE_DRSQ
:
5135 exec_double_unary(mach
, inst
, micro_drsq
);
5138 case TGSI_OPCODE_DMAD
:
5139 exec_double_trinary(mach
, inst
, micro_dmad
);
5142 case TGSI_OPCODE_DFRAC
:
5143 exec_double_unary(mach
, inst
, micro_dfrac
);
5146 case TGSI_OPCODE_DLDEXP
:
5147 exec_dldexp(mach
, inst
);
5150 case TGSI_OPCODE_DFRACEXP
:
5151 exec_dfracexp(mach
, inst
);
5154 case TGSI_OPCODE_I2D
:
5155 exec_i2d(mach
, inst
);
5158 case TGSI_OPCODE_D2I
:
5159 exec_d2i(mach
, inst
);
5162 case TGSI_OPCODE_U2D
:
5163 exec_u2d(mach
, inst
);
5166 case TGSI_OPCODE_D2U
:
5167 exec_d2u(mach
, inst
);
5176 * Run TGSI interpreter.
5177 * \return bitmask of "alive" quad components
5180 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
)
5184 uint default_mask
= 0xf;
5186 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
5187 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
5189 if( mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
5190 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
5191 mach
->Primitives
[0] = 0;
5192 /* GS runs on a single primitive for now */
5196 mach
->CondMask
= default_mask
;
5197 mach
->LoopMask
= default_mask
;
5198 mach
->ContMask
= default_mask
;
5199 mach
->FuncMask
= default_mask
;
5200 mach
->ExecMask
= default_mask
;
5202 mach
->Switch
.mask
= default_mask
;
5204 assert(mach
->CondStackTop
== 0);
5205 assert(mach
->LoopStackTop
== 0);
5206 assert(mach
->ContStackTop
== 0);
5207 assert(mach
->SwitchStackTop
== 0);
5208 assert(mach
->BreakStackTop
== 0);
5209 assert(mach
->CallStackTop
== 0);
5212 /* execute declarations (interpolants) */
5213 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
5214 exec_declaration( mach
, mach
->Declarations
+i
);
5219 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
5220 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
5223 memset(mach
->Temps
, 0, sizeof(temps
));
5224 memset(mach
->Outputs
, 0, sizeof(outputs
));
5225 memset(temps
, 0, sizeof(temps
));
5226 memset(outputs
, 0, sizeof(outputs
));
5229 /* execute instructions, until pc is set to -1 */
5235 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
5238 assert(pc
< (int) mach
->NumInstructions
);
5239 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
5242 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
5243 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
5246 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
5247 debug_printf("TEMP[%2u] = ", i
);
5248 for (j
= 0; j
< 4; j
++) {
5252 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5253 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
5254 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
5255 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
5256 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
5260 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
5261 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
5264 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
5265 debug_printf("OUT[%2u] = ", i
);
5266 for (j
= 0; j
< 4; j
++) {
5270 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5271 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
5272 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
5273 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
5274 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
5283 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5284 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
5286 * Scale back depth component.
5288 for (i
= 0; i
< 4; i
++)
5289 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
5293 /* Strictly speaking, these assertions aren't really needed but they
5294 * can potentially catch some bugs in the control flow code.
5296 assert(mach
->CondStackTop
== 0);
5297 assert(mach
->LoopStackTop
== 0);
5298 assert(mach
->ContStackTop
== 0);
5299 assert(mach
->SwitchStackTop
== 0);
5300 assert(mach
->BreakStackTop
== 0);
5301 assert(mach
->CallStackTop
== 0);
5303 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];