1 /**************************************************************************
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
65 #define DEBUG_EXECUTION 0
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
76 micro_abs(union tgsi_exec_channel
*dst
,
77 const union tgsi_exec_channel
*src
)
79 dst
->f
[0] = fabsf(src
->f
[0]);
80 dst
->f
[1] = fabsf(src
->f
[1]);
81 dst
->f
[2] = fabsf(src
->f
[2]);
82 dst
->f
[3] = fabsf(src
->f
[3]);
86 micro_arl(union tgsi_exec_channel
*dst
,
87 const union tgsi_exec_channel
*src
)
89 dst
->i
[0] = (int)floorf(src
->f
[0]);
90 dst
->i
[1] = (int)floorf(src
->f
[1]);
91 dst
->i
[2] = (int)floorf(src
->f
[2]);
92 dst
->i
[3] = (int)floorf(src
->f
[3]);
96 micro_arr(union tgsi_exec_channel
*dst
,
97 const union tgsi_exec_channel
*src
)
99 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
100 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
101 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
102 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
106 micro_ceil(union tgsi_exec_channel
*dst
,
107 const union tgsi_exec_channel
*src
)
109 dst
->f
[0] = ceilf(src
->f
[0]);
110 dst
->f
[1] = ceilf(src
->f
[1]);
111 dst
->f
[2] = ceilf(src
->f
[2]);
112 dst
->f
[3] = ceilf(src
->f
[3]);
116 micro_clamp(union tgsi_exec_channel
*dst
,
117 const union tgsi_exec_channel
*src0
,
118 const union tgsi_exec_channel
*src1
,
119 const union tgsi_exec_channel
*src2
)
121 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
122 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
123 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
124 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
128 micro_cmp(union tgsi_exec_channel
*dst
,
129 const union tgsi_exec_channel
*src0
,
130 const union tgsi_exec_channel
*src1
,
131 const union tgsi_exec_channel
*src2
)
133 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
134 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
135 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
136 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
140 micro_cnd(union tgsi_exec_channel
*dst
,
141 const union tgsi_exec_channel
*src0
,
142 const union tgsi_exec_channel
*src1
,
143 const union tgsi_exec_channel
*src2
)
145 dst
->f
[0] = src2
->f
[0] > 0.5f
? src0
->f
[0] : src1
->f
[0];
146 dst
->f
[1] = src2
->f
[1] > 0.5f
? src0
->f
[1] : src1
->f
[1];
147 dst
->f
[2] = src2
->f
[2] > 0.5f
? src0
->f
[2] : src1
->f
[2];
148 dst
->f
[3] = src2
->f
[3] > 0.5f
? src0
->f
[3] : src1
->f
[3];
152 micro_cos(union tgsi_exec_channel
*dst
,
153 const union tgsi_exec_channel
*src
)
155 dst
->f
[0] = cosf(src
->f
[0]);
156 dst
->f
[1] = cosf(src
->f
[1]);
157 dst
->f
[2] = cosf(src
->f
[2]);
158 dst
->f
[3] = cosf(src
->f
[3]);
162 micro_ddx(union tgsi_exec_channel
*dst
,
163 const union tgsi_exec_channel
*src
)
168 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
172 micro_ddy(union tgsi_exec_channel
*dst
,
173 const union tgsi_exec_channel
*src
)
178 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
182 micro_exp2(union tgsi_exec_channel
*dst
,
183 const union tgsi_exec_channel
*src
)
186 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
187 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
188 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
189 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
194 union tgsi_exec_channel clamped
;
196 for (i
= 0; i
< 4; i
++) {
197 if (src
->f
[i
] > 127.99999f
) {
198 clamped
.f
[i
] = 127.99999f
;
199 } else if (src
->f
[i
] < -126.99999f
) {
200 clamped
.f
[i
] = -126.99999f
;
202 clamped
.f
[i
] = src
->f
[i
];
208 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
209 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
210 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
211 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
212 #endif /* FAST_MATH */
216 micro_flr(union tgsi_exec_channel
*dst
,
217 const union tgsi_exec_channel
*src
)
219 dst
->f
[0] = floorf(src
->f
[0]);
220 dst
->f
[1] = floorf(src
->f
[1]);
221 dst
->f
[2] = floorf(src
->f
[2]);
222 dst
->f
[3] = floorf(src
->f
[3]);
226 micro_frc(union tgsi_exec_channel
*dst
,
227 const union tgsi_exec_channel
*src
)
229 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
230 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
231 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
232 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
236 micro_iabs(union tgsi_exec_channel
*dst
,
237 const union tgsi_exec_channel
*src
)
239 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
240 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
241 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
242 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
246 micro_ineg(union tgsi_exec_channel
*dst
,
247 const union tgsi_exec_channel
*src
)
249 dst
->i
[0] = -src
->i
[0];
250 dst
->i
[1] = -src
->i
[1];
251 dst
->i
[2] = -src
->i
[2];
252 dst
->i
[3] = -src
->i
[3];
256 micro_lg2(union tgsi_exec_channel
*dst
,
257 const union tgsi_exec_channel
*src
)
260 dst
->f
[0] = util_fast_log2(src
->f
[0]);
261 dst
->f
[1] = util_fast_log2(src
->f
[1]);
262 dst
->f
[2] = util_fast_log2(src
->f
[2]);
263 dst
->f
[3] = util_fast_log2(src
->f
[3]);
265 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
266 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
267 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
268 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
273 micro_lrp(union tgsi_exec_channel
*dst
,
274 const union tgsi_exec_channel
*src0
,
275 const union tgsi_exec_channel
*src1
,
276 const union tgsi_exec_channel
*src2
)
278 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
279 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
280 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
281 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
285 micro_mad(union tgsi_exec_channel
*dst
,
286 const union tgsi_exec_channel
*src0
,
287 const union tgsi_exec_channel
*src1
,
288 const union tgsi_exec_channel
*src2
)
290 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
291 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
292 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
293 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
297 micro_mov(union tgsi_exec_channel
*dst
,
298 const union tgsi_exec_channel
*src
)
300 dst
->u
[0] = src
->u
[0];
301 dst
->u
[1] = src
->u
[1];
302 dst
->u
[2] = src
->u
[2];
303 dst
->u
[3] = src
->u
[3];
307 micro_rcp(union tgsi_exec_channel
*dst
,
308 const union tgsi_exec_channel
*src
)
310 #if 0 /* for debugging */
311 assert(src
->f
[0] != 0.0f
);
312 assert(src
->f
[1] != 0.0f
);
313 assert(src
->f
[2] != 0.0f
);
314 assert(src
->f
[3] != 0.0f
);
316 dst
->f
[0] = 1.0f
/ src
->f
[0];
317 dst
->f
[1] = 1.0f
/ src
->f
[1];
318 dst
->f
[2] = 1.0f
/ src
->f
[2];
319 dst
->f
[3] = 1.0f
/ src
->f
[3];
323 micro_rnd(union tgsi_exec_channel
*dst
,
324 const union tgsi_exec_channel
*src
)
326 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
327 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
328 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
329 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
333 micro_rsq(union tgsi_exec_channel
*dst
,
334 const union tgsi_exec_channel
*src
)
336 #if 0 /* for debugging */
337 assert(src
->f
[0] != 0.0f
);
338 assert(src
->f
[1] != 0.0f
);
339 assert(src
->f
[2] != 0.0f
);
340 assert(src
->f
[3] != 0.0f
);
342 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
343 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
344 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
345 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
349 micro_sqrt(union tgsi_exec_channel
*dst
,
350 const union tgsi_exec_channel
*src
)
352 dst
->f
[0] = sqrtf(src
->f
[0]);
353 dst
->f
[1] = sqrtf(src
->f
[1]);
354 dst
->f
[2] = sqrtf(src
->f
[2]);
355 dst
->f
[3] = sqrtf(src
->f
[3]);
359 micro_seq(union tgsi_exec_channel
*dst
,
360 const union tgsi_exec_channel
*src0
,
361 const union tgsi_exec_channel
*src1
)
363 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
364 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
365 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
366 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
370 micro_sge(union tgsi_exec_channel
*dst
,
371 const union tgsi_exec_channel
*src0
,
372 const union tgsi_exec_channel
*src1
)
374 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
375 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
376 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
377 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
381 micro_sgn(union tgsi_exec_channel
*dst
,
382 const union tgsi_exec_channel
*src
)
384 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
385 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
386 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
387 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
391 micro_isgn(union tgsi_exec_channel
*dst
,
392 const union tgsi_exec_channel
*src
)
394 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
395 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
396 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
397 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
401 micro_sgt(union tgsi_exec_channel
*dst
,
402 const union tgsi_exec_channel
*src0
,
403 const union tgsi_exec_channel
*src1
)
405 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
406 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
407 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
408 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
412 micro_sin(union tgsi_exec_channel
*dst
,
413 const union tgsi_exec_channel
*src
)
415 dst
->f
[0] = sinf(src
->f
[0]);
416 dst
->f
[1] = sinf(src
->f
[1]);
417 dst
->f
[2] = sinf(src
->f
[2]);
418 dst
->f
[3] = sinf(src
->f
[3]);
422 micro_sle(union tgsi_exec_channel
*dst
,
423 const union tgsi_exec_channel
*src0
,
424 const union tgsi_exec_channel
*src1
)
426 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
427 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
428 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
429 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
433 micro_slt(union tgsi_exec_channel
*dst
,
434 const union tgsi_exec_channel
*src0
,
435 const union tgsi_exec_channel
*src1
)
437 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
438 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
439 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
440 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
444 micro_sne(union tgsi_exec_channel
*dst
,
445 const union tgsi_exec_channel
*src0
,
446 const union tgsi_exec_channel
*src1
)
448 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
449 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
450 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
451 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
455 micro_sfl(union tgsi_exec_channel
*dst
)
464 micro_str(union tgsi_exec_channel
*dst
)
473 micro_trunc(union tgsi_exec_channel
*dst
,
474 const union tgsi_exec_channel
*src
)
476 dst
->f
[0] = (float)(int)src
->f
[0];
477 dst
->f
[1] = (float)(int)src
->f
[1];
478 dst
->f
[2] = (float)(int)src
->f
[2];
479 dst
->f
[3] = (float)(int)src
->f
[3];
483 enum tgsi_exec_datatype
{
484 TGSI_EXEC_DATA_FLOAT
,
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
505 static const union tgsi_exec_channel ZeroVec
=
506 { { 0.0, 0.0, 0.0, 0.0 } };
508 static const union tgsi_exec_channel OneVec
= {
509 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
512 static const union tgsi_exec_channel P128Vec
= {
513 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
516 static const union tgsi_exec_channel M128Vec
= {
517 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
528 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
530 assert(!util_is_inf_or_nan((chan
)->f
[0]));
531 assert(!util_is_inf_or_nan((chan
)->f
[1]));
532 assert(!util_is_inf_or_nan((chan
)->f
[2]));
533 assert(!util_is_inf_or_nan((chan
)->f
[3]));
539 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
549 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
551 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
553 debug_printf("Temp[%u] =\n", index
);
554 for (i
= 0; i
< 4; i
++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
570 const unsigned *buf_sizes
)
574 for (i
= 0; i
< num_bufs
; i
++) {
575 mach
->Consts
[i
] = bufs
[i
];
576 mach
->ConstsSize
[i
] = buf_sizes
[i
];
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
586 * This would expand into:
591 * The second instruction will have the wrong value for t0 if executed as-is.
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
598 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
599 if (writemask
== TGSI_WRITEMASK_X
||
600 writemask
== TGSI_WRITEMASK_Y
||
601 writemask
== TGSI_WRITEMASK_Z
||
602 writemask
== TGSI_WRITEMASK_W
||
603 writemask
== TGSI_WRITEMASK_NONE
) {
604 /* no chance of data dependency */
608 /* loop over src regs */
609 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
610 if ((inst
->Src
[i
].Register
.File
==
611 inst
->Dst
[0].Register
.File
) &&
612 ((inst
->Src
[i
].Register
.Index
==
613 inst
->Dst
[0].Register
.Index
) ||
614 inst
->Src
[i
].Register
.Indirect
||
615 inst
->Dst
[0].Register
.Indirect
)) {
616 /* loop over dest channels */
617 uint channelsWritten
= 0x0;
618 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
619 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
622 if (channelsWritten
& (1 << swizzle
)) {
626 channelsWritten
|= (1 << chan
);
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine
*mach
,
643 const struct tgsi_token
*tokens
,
644 struct tgsi_sampler
*sampler
)
647 struct tgsi_parse_context parse
;
648 struct tgsi_full_instruction
*instructions
;
649 struct tgsi_full_declaration
*declarations
;
650 uint maxInstructions
= 10, numInstructions
= 0;
651 uint maxDeclarations
= 10, numDeclarations
= 0;
654 tgsi_dump(tokens
, 0);
660 mach
->Tokens
= tokens
;
661 mach
->Sampler
= sampler
;
664 /* unbind and free all */
665 FREE(mach
->Declarations
);
666 mach
->Declarations
= NULL
;
667 mach
->NumDeclarations
= 0;
669 FREE(mach
->Instructions
);
670 mach
->Instructions
= NULL
;
671 mach
->NumInstructions
= 0;
676 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
677 if (k
!= TGSI_PARSE_OK
) {
678 debug_printf( "Problem parsing!\n" );
682 mach
->Processor
= parse
.FullHeader
.Processor
.Processor
;
684 mach
->NumOutputs
= 0;
686 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
&&
687 !mach
->UsedGeometryShader
) {
688 struct tgsi_exec_vector
*inputs
;
689 struct tgsi_exec_vector
*outputs
;
691 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
692 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
,
698 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
699 TGSI_MAX_TOTAL_VERTICES
, 16);
706 align_free(mach
->Inputs
);
707 align_free(mach
->Outputs
);
709 mach
->Inputs
= inputs
;
710 mach
->Outputs
= outputs
;
711 mach
->UsedGeometryShader
= TRUE
;
714 declarations
= (struct tgsi_full_declaration
*)
715 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
721 instructions
= (struct tgsi_full_instruction
*)
722 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
725 FREE( declarations
);
729 while( !tgsi_parse_end_of_tokens( &parse
) ) {
732 tgsi_parse_token( &parse
);
733 switch( parse
.FullToken
.Token
.Type
) {
734 case TGSI_TOKEN_TYPE_DECLARATION
:
735 /* save expanded declaration */
736 if (numDeclarations
== maxDeclarations
) {
737 declarations
= REALLOC(declarations
,
739 * sizeof(struct tgsi_full_declaration
),
740 (maxDeclarations
+ 10)
741 * sizeof(struct tgsi_full_declaration
));
742 maxDeclarations
+= 10;
744 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
746 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
747 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
752 memcpy(declarations
+ numDeclarations
,
753 &parse
.FullToken
.FullDeclaration
,
754 sizeof(declarations
[0]));
758 case TGSI_TOKEN_TYPE_IMMEDIATE
:
760 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
762 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
764 for( i
= 0; i
< size
; i
++ ) {
765 mach
->Imms
[mach
->ImmLimit
][i
] =
766 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
772 case TGSI_TOKEN_TYPE_INSTRUCTION
:
774 /* save expanded instruction */
775 if (numInstructions
== maxInstructions
) {
776 instructions
= REALLOC(instructions
,
778 * sizeof(struct tgsi_full_instruction
),
779 (maxInstructions
+ 10)
780 * sizeof(struct tgsi_full_instruction
));
781 maxInstructions
+= 10;
784 memcpy(instructions
+ numInstructions
,
785 &parse
.FullToken
.FullInstruction
,
786 sizeof(instructions
[0]));
791 case TGSI_TOKEN_TYPE_PROPERTY
:
798 tgsi_parse_free (&parse
);
800 FREE(mach
->Declarations
);
801 mach
->Declarations
= declarations
;
802 mach
->NumDeclarations
= numDeclarations
;
804 FREE(mach
->Instructions
);
805 mach
->Instructions
= instructions
;
806 mach
->NumInstructions
= numInstructions
;
810 struct tgsi_exec_machine
*
811 tgsi_exec_machine_create( void )
813 struct tgsi_exec_machine
*mach
;
816 mach
= align_malloc( sizeof *mach
, 16 );
820 memset(mach
, 0, sizeof(*mach
));
822 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
823 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
824 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
826 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_ATTRIBS
, 16);
827 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_ATTRIBS
, 16);
828 if (!mach
->Inputs
|| !mach
->Outputs
)
831 /* Setup constants needed by the SSE2 executor. */
832 for( i
= 0; i
< 4; i
++ ) {
833 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
834 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
835 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
836 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
837 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
838 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
839 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
840 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
841 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
842 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
846 /* silence warnings */
855 align_free(mach
->Inputs
);
856 align_free(mach
->Outputs
);
864 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
867 FREE(mach
->Instructions
);
868 FREE(mach
->Declarations
);
870 align_free(mach
->Inputs
);
871 align_free(mach
->Outputs
);
878 micro_add(union tgsi_exec_channel
*dst
,
879 const union tgsi_exec_channel
*src0
,
880 const union tgsi_exec_channel
*src1
)
882 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
883 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
884 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
885 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
890 union tgsi_exec_channel
*dst
,
891 const union tgsi_exec_channel
*src0
,
892 const union tgsi_exec_channel
*src1
)
894 if (src1
->f
[0] != 0) {
895 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
897 if (src1
->f
[1] != 0) {
898 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
900 if (src1
->f
[2] != 0) {
901 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
903 if (src1
->f
[3] != 0) {
904 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
909 micro_rcc(union tgsi_exec_channel
*dst
,
910 const union tgsi_exec_channel
*src
)
914 for (i
= 0; i
< 4; i
++) {
915 float recip
= 1.0f
/ src
->f
[i
];
918 if (recip
> 1.884467e+019f
) {
919 dst
->f
[i
] = 1.884467e+019f
;
921 else if (recip
< 5.42101e-020f
) {
922 dst
->f
[i
] = 5.42101e-020f
;
929 if (recip
< -1.884467e+019f
) {
930 dst
->f
[i
] = -1.884467e+019f
;
932 else if (recip
> -5.42101e-020f
) {
933 dst
->f
[i
] = -5.42101e-020f
;
944 union tgsi_exec_channel
*dst
,
945 const union tgsi_exec_channel
*src0
,
946 const union tgsi_exec_channel
*src1
,
947 const union tgsi_exec_channel
*src2
,
948 const union tgsi_exec_channel
*src3
)
950 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
951 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
952 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
953 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
957 micro_max(union tgsi_exec_channel
*dst
,
958 const union tgsi_exec_channel
*src0
,
959 const union tgsi_exec_channel
*src1
)
961 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
962 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
963 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
964 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
968 micro_min(union tgsi_exec_channel
*dst
,
969 const union tgsi_exec_channel
*src0
,
970 const union tgsi_exec_channel
*src1
)
972 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
973 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
974 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
975 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
979 micro_mul(union tgsi_exec_channel
*dst
,
980 const union tgsi_exec_channel
*src0
,
981 const union tgsi_exec_channel
*src1
)
983 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
984 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
985 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
986 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
991 union tgsi_exec_channel
*dst
,
992 const union tgsi_exec_channel
*src
)
994 dst
->f
[0] = -src
->f
[0];
995 dst
->f
[1] = -src
->f
[1];
996 dst
->f
[2] = -src
->f
[2];
997 dst
->f
[3] = -src
->f
[3];
1002 union tgsi_exec_channel
*dst
,
1003 const union tgsi_exec_channel
*src0
,
1004 const union tgsi_exec_channel
*src1
)
1007 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1008 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1009 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1010 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1012 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1013 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1014 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1015 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1020 micro_sub(union tgsi_exec_channel
*dst
,
1021 const union tgsi_exec_channel
*src0
,
1022 const union tgsi_exec_channel
*src1
)
1024 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1025 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1026 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1027 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1031 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1032 const uint chan_index
,
1035 const union tgsi_exec_channel
*index
,
1036 const union tgsi_exec_channel
*index2D
,
1037 union tgsi_exec_channel
*chan
)
1041 assert(swizzle
< 4);
1044 case TGSI_FILE_CONSTANT
:
1045 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1046 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1047 assert(mach
->Consts
[index2D
->i
[i
]]);
1049 if (index
->i
[i
] < 0) {
1052 /* NOTE: copying the const value as a uint instead of float */
1053 const uint constbuf
= index2D
->i
[i
];
1054 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1055 const int pos
= index
->i
[i
] * 4 + swizzle
;
1056 /* const buffer bounds check */
1057 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1059 /* Debug: print warning */
1060 static int count
= 0;
1062 debug_printf("TGSI Exec: const buffer index %d"
1063 " out of bounds\n", pos
);
1068 chan
->u
[i
] = buf
[pos
];
1073 case TGSI_FILE_INPUT
:
1074 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1076 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1077 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1078 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1079 index2D->i[i], index->i[i]);
1081 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1083 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1084 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1088 case TGSI_FILE_SYSTEM_VALUE
:
1089 /* XXX no swizzling at this point. Will be needed if we put
1090 * gl_FragCoord, for example, in a sys value register.
1092 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1093 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].u
[i
];
1097 case TGSI_FILE_TEMPORARY
:
1098 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1099 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1100 assert(index2D
->i
[i
] == 0);
1102 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1106 case TGSI_FILE_IMMEDIATE
:
1107 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1108 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1109 assert(index2D
->i
[i
] == 0);
1111 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1115 case TGSI_FILE_ADDRESS
:
1116 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1117 assert(index
->i
[i
] >= 0);
1118 assert(index2D
->i
[i
] == 0);
1120 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1124 case TGSI_FILE_PREDICATE
:
1125 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1126 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1127 assert(index2D
->i
[i
] == 0);
1129 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1133 case TGSI_FILE_OUTPUT
:
1134 /* vertex/fragment output vars can be read too */
1135 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1136 assert(index
->i
[i
] >= 0);
1137 assert(index2D
->i
[i
] == 0);
1139 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1145 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1152 fetch_source(const struct tgsi_exec_machine
*mach
,
1153 union tgsi_exec_channel
*chan
,
1154 const struct tgsi_full_src_register
*reg
,
1155 const uint chan_index
,
1156 enum tgsi_exec_datatype src_datatype
)
1158 union tgsi_exec_channel index
;
1159 union tgsi_exec_channel index2D
;
1162 /* We start with a direct index into a register file.
1166 * file = Register.File
1167 * [1] = Register.Index
1172 index
.i
[3] = reg
->Register
.Index
;
1174 /* There is an extra source register that indirectly subscripts
1175 * a register file. The direct index now becomes an offset
1176 * that is being added to the indirect register.
1180 * ind = Indirect.File
1181 * [2] = Indirect.Index
1182 * .x = Indirect.SwizzleX
1184 if (reg
->Register
.Indirect
) {
1185 union tgsi_exec_channel index2
;
1186 union tgsi_exec_channel indir_index
;
1187 const uint execmask
= mach
->ExecMask
;
1190 /* which address register (always zero now) */
1194 index2
.i
[3] = reg
->Indirect
.Index
;
1195 /* get current value of address register[swizzle] */
1196 swizzle
= reg
->Indirect
.Swizzle
;
1197 fetch_src_file_channel(mach
,
1205 /* add value of address register to the offset */
1206 index
.i
[0] += indir_index
.i
[0];
1207 index
.i
[1] += indir_index
.i
[1];
1208 index
.i
[2] += indir_index
.i
[2];
1209 index
.i
[3] += indir_index
.i
[3];
1211 /* for disabled execution channels, zero-out the index to
1212 * avoid using a potential garbage value.
1214 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1215 if ((execmask
& (1 << i
)) == 0)
1220 /* There is an extra source register that is a second
1221 * subscript to a register file. Effectively it means that
1222 * the register file is actually a 2D array of registers.
1226 * [3] = Dimension.Index
1228 if (reg
->Register
.Dimension
) {
1232 index2D
.i
[3] = reg
->Dimension
.Index
;
1234 /* Again, the second subscript index can be addressed indirectly
1235 * identically to the first one.
1236 * Nothing stops us from indirectly addressing the indirect register,
1237 * but there is no need for that, so we won't exercise it.
1239 * file[ind[4].y+3][1],
1241 * ind = DimIndirect.File
1242 * [4] = DimIndirect.Index
1243 * .y = DimIndirect.SwizzleX
1245 if (reg
->Dimension
.Indirect
) {
1246 union tgsi_exec_channel index2
;
1247 union tgsi_exec_channel indir_index
;
1248 const uint execmask
= mach
->ExecMask
;
1254 index2
.i
[3] = reg
->DimIndirect
.Index
;
1256 swizzle
= reg
->DimIndirect
.Swizzle
;
1257 fetch_src_file_channel(mach
,
1259 reg
->DimIndirect
.File
,
1265 index2D
.i
[0] += indir_index
.i
[0];
1266 index2D
.i
[1] += indir_index
.i
[1];
1267 index2D
.i
[2] += indir_index
.i
[2];
1268 index2D
.i
[3] += indir_index
.i
[3];
1270 /* for disabled execution channels, zero-out the index to
1271 * avoid using a potential garbage value.
1273 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1274 if ((execmask
& (1 << i
)) == 0) {
1280 /* If by any chance there was a need for a 3D array of register
1281 * files, we would have to check whether Dimension is followed
1282 * by a dimension register and continue the saga.
1291 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1292 fetch_src_file_channel(mach
,
1300 if (reg
->Register
.Absolute
) {
1301 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1302 micro_abs(chan
, chan
);
1304 micro_iabs(chan
, chan
);
1308 if (reg
->Register
.Negate
) {
1309 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1310 micro_neg(chan
, chan
);
1312 micro_ineg(chan
, chan
);
1318 store_dest(struct tgsi_exec_machine
*mach
,
1319 const union tgsi_exec_channel
*chan
,
1320 const struct tgsi_full_dst_register
*reg
,
1321 const struct tgsi_full_instruction
*inst
,
1323 enum tgsi_exec_datatype dst_datatype
)
1326 union tgsi_exec_channel null
;
1327 union tgsi_exec_channel
*dst
;
1328 union tgsi_exec_channel index2D
;
1329 uint execmask
= mach
->ExecMask
;
1330 int offset
= 0; /* indirection offset */
1334 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1335 check_inf_or_nan(chan
);
1338 /* There is an extra source register that indirectly subscripts
1339 * a register file. The direct index now becomes an offset
1340 * that is being added to the indirect register.
1344 * ind = Indirect.File
1345 * [2] = Indirect.Index
1346 * .x = Indirect.SwizzleX
1348 if (reg
->Register
.Indirect
) {
1349 union tgsi_exec_channel index
;
1350 union tgsi_exec_channel indir_index
;
1353 /* which address register (always zero for now) */
1357 index
.i
[3] = reg
->Indirect
.Index
;
1359 /* get current value of address register[swizzle] */
1360 swizzle
= reg
->Indirect
.Swizzle
;
1362 /* fetch values from the address/indirection register */
1363 fetch_src_file_channel(mach
,
1371 /* save indirection offset */
1372 offset
= indir_index
.i
[0];
1375 /* There is an extra source register that is a second
1376 * subscript to a register file. Effectively it means that
1377 * the register file is actually a 2D array of registers.
1381 * [3] = Dimension.Index
1383 if (reg
->Register
.Dimension
) {
1387 index2D
.i
[3] = reg
->Dimension
.Index
;
1389 /* Again, the second subscript index can be addressed indirectly
1390 * identically to the first one.
1391 * Nothing stops us from indirectly addressing the indirect register,
1392 * but there is no need for that, so we won't exercise it.
1394 * file[ind[4].y+3][1],
1396 * ind = DimIndirect.File
1397 * [4] = DimIndirect.Index
1398 * .y = DimIndirect.SwizzleX
1400 if (reg
->Dimension
.Indirect
) {
1401 union tgsi_exec_channel index2
;
1402 union tgsi_exec_channel indir_index
;
1403 const uint execmask
= mach
->ExecMask
;
1410 index2
.i
[3] = reg
->DimIndirect
.Index
;
1412 swizzle
= reg
->DimIndirect
.Swizzle
;
1413 fetch_src_file_channel(mach
,
1415 reg
->DimIndirect
.File
,
1421 index2D
.i
[0] += indir_index
.i
[0];
1422 index2D
.i
[1] += indir_index
.i
[1];
1423 index2D
.i
[2] += indir_index
.i
[2];
1424 index2D
.i
[3] += indir_index
.i
[3];
1426 /* for disabled execution channels, zero-out the index to
1427 * avoid using a potential garbage value.
1429 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1430 if ((execmask
& (1 << i
)) == 0) {
1436 /* If by any chance there was a need for a 3D array of register
1437 * files, we would have to check whether Dimension is followed
1438 * by a dimension register and continue the saga.
1447 switch (reg
->Register
.File
) {
1448 case TGSI_FILE_NULL
:
1452 case TGSI_FILE_OUTPUT
:
1453 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1454 + reg
->Register
.Index
;
1455 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1457 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1458 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1459 reg
->Register
.Index
);
1460 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1461 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1462 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1463 if (execmask
& (1 << i
))
1464 debug_printf("%f, ", chan
->f
[i
]);
1465 debug_printf(")\n");
1470 case TGSI_FILE_TEMPORARY
:
1471 index
= reg
->Register
.Index
;
1472 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1473 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1476 case TGSI_FILE_ADDRESS
:
1477 index
= reg
->Register
.Index
;
1478 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1481 case TGSI_FILE_PREDICATE
:
1482 index
= reg
->Register
.Index
;
1483 assert(index
< TGSI_EXEC_NUM_PREDS
);
1484 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1492 if (inst
->Instruction
.Predicate
) {
1494 union tgsi_exec_channel
*pred
;
1496 switch (chan_index
) {
1498 swizzle
= inst
->Predicate
.SwizzleX
;
1501 swizzle
= inst
->Predicate
.SwizzleY
;
1504 swizzle
= inst
->Predicate
.SwizzleZ
;
1507 swizzle
= inst
->Predicate
.SwizzleW
;
1514 assert(inst
->Predicate
.Index
== 0);
1516 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1518 if (inst
->Predicate
.Negate
) {
1519 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1521 execmask
&= ~(1 << i
);
1525 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1527 execmask
&= ~(1 << i
);
1533 switch (inst
->Instruction
.Saturate
) {
1535 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1536 if (execmask
& (1 << i
))
1537 dst
->i
[i
] = chan
->i
[i
];
1540 case TGSI_SAT_ZERO_ONE
:
1541 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1542 if (execmask
& (1 << i
)) {
1543 if (chan
->f
[i
] < 0.0f
)
1545 else if (chan
->f
[i
] > 1.0f
)
1548 dst
->i
[i
] = chan
->i
[i
];
1552 case TGSI_SAT_MINUS_PLUS_ONE
:
1553 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1554 if (execmask
& (1 << i
)) {
1555 if (chan
->f
[i
] < -1.0f
)
1557 else if (chan
->f
[i
] > 1.0f
)
1560 dst
->i
[i
] = chan
->i
[i
];
1569 #define FETCH(VAL,INDEX,CHAN)\
1570 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1572 #define IFETCH(VAL,INDEX,CHAN)\
1573 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1577 * Execute ARB-style KIL which is predicated by a src register.
1578 * Kill fragment if any of the four values is less than zero.
1581 exec_kill_if(struct tgsi_exec_machine
*mach
,
1582 const struct tgsi_full_instruction
*inst
)
1586 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1587 union tgsi_exec_channel r
[1];
1589 /* This mask stores component bits that were already tested. */
1592 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1597 /* unswizzle channel */
1598 swizzle
= tgsi_util_get_full_src_register_swizzle (
1602 /* check if the component has not been already tested */
1603 if (uniquemask
& (1 << swizzle
))
1605 uniquemask
|= 1 << swizzle
;
1607 FETCH(&r
[0], 0, chan_index
);
1608 for (i
= 0; i
< 4; i
++)
1609 if (r
[0].f
[i
] < 0.0f
)
1613 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1617 * Unconditional fragment kill/discard.
1620 exec_kill(struct tgsi_exec_machine
*mach
,
1621 const struct tgsi_full_instruction
*inst
)
1623 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1625 /* kill fragment for all fragments currently executing */
1626 kilmask
= mach
->ExecMask
;
1627 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1631 emit_vertex(struct tgsi_exec_machine
*mach
)
1633 /* FIXME: check for exec mask correctly
1635 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1636 if ((mach->ExecMask & (1 << i)))
1638 if (mach
->ExecMask
) {
1639 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1640 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1645 emit_primitive(struct tgsi_exec_machine
*mach
)
1647 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1648 /* FIXME: check for exec mask correctly
1650 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1651 if ((mach->ExecMask & (1 << i)))
1653 if (mach
->ExecMask
) {
1655 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1656 mach
->Primitives
[*prim_count
] = 0;
1661 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1663 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1665 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1666 if (emitted_verts
) {
1667 emit_primitive(mach
);
1674 * Fetch four texture samples using STR texture coordinates.
1677 fetch_texel( struct tgsi_sampler
*sampler
,
1678 const unsigned sview_idx
,
1679 const unsigned sampler_idx
,
1680 const union tgsi_exec_channel
*s
,
1681 const union tgsi_exec_channel
*t
,
1682 const union tgsi_exec_channel
*p
,
1683 const union tgsi_exec_channel
*c0
,
1684 const union tgsi_exec_channel
*c1
,
1685 float derivs
[3][2][TGSI_QUAD_SIZE
],
1686 const int8_t offset
[3],
1687 enum tgsi_sampler_control control
,
1688 union tgsi_exec_channel
*r
,
1689 union tgsi_exec_channel
*g
,
1690 union tgsi_exec_channel
*b
,
1691 union tgsi_exec_channel
*a
)
1694 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1696 /* FIXME: handle explicit derivs, offsets */
1697 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
1698 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
1700 for (j
= 0; j
< 4; j
++) {
1701 r
->f
[j
] = rgba
[0][j
];
1702 g
->f
[j
] = rgba
[1][j
];
1703 b
->f
[j
] = rgba
[2][j
];
1704 a
->f
[j
] = rgba
[3][j
];
1709 #define TEX_MODIFIER_NONE 0
1710 #define TEX_MODIFIER_PROJECTED 1
1711 #define TEX_MODIFIER_LOD_BIAS 2
1712 #define TEX_MODIFIER_EXPLICIT_LOD 3
1713 #define TEX_MODIFIER_LEVEL_ZERO 4
1717 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1720 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
1721 const struct tgsi_full_instruction
*inst
,
1724 if (inst
->Texture
.NumOffsets
== 1) {
1725 union tgsi_exec_channel index
;
1726 union tgsi_exec_channel offset
[3];
1727 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
1728 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1729 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
1730 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1731 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
1732 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1733 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
1734 offsets
[0] = offset
[0].i
[0];
1735 offsets
[1] = offset
[1].i
[0];
1736 offsets
[2] = offset
[2].i
[0];
1738 assert(inst
->Texture
.NumOffsets
== 0);
1739 offsets
[0] = offsets
[1] = offsets
[2] = 0;
1745 * Fetch dx and dy values for one channel (s, t or r).
1746 * Put dx values into one float array, dy values into another.
1749 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
1750 const struct tgsi_full_instruction
*inst
,
1753 float derivs
[2][TGSI_QUAD_SIZE
])
1755 union tgsi_exec_channel d
;
1756 FETCH(&d
, regdsrcx
, chan
);
1757 derivs
[0][0] = d
.f
[0];
1758 derivs
[0][1] = d
.f
[1];
1759 derivs
[0][2] = d
.f
[2];
1760 derivs
[0][3] = d
.f
[3];
1761 FETCH(&d
, regdsrcx
+ 1, chan
);
1762 derivs
[1][0] = d
.f
[0];
1763 derivs
[1][1] = d
.f
[1];
1764 derivs
[1][2] = d
.f
[2];
1765 derivs
[1][3] = d
.f
[3];
1770 * execute a texture instruction.
1772 * modifier is used to control the channel routing for the\
1773 * instruction variants like proj, lod, and texture with lod bias.
1774 * sampler indicates which src register the sampler is contained in.
1777 exec_tex(struct tgsi_exec_machine
*mach
,
1778 const struct tgsi_full_instruction
*inst
,
1779 uint modifier
, uint sampler
)
1781 const uint unit
= inst
->Src
[sampler
].Register
.Index
;
1782 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
1783 union tgsi_exec_channel r
[5];
1784 enum tgsi_sampler_control control
= tgsi_sampler_lod_none
;
1787 int dim
, shadow_ref
, i
;
1789 /* always fetch all 3 offsets, overkill but keeps code simple */
1790 fetch_texel_offsets(mach
, inst
, offsets
);
1792 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
1793 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
1795 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
, &shadow_ref
);
1798 if (shadow_ref
>= 0)
1799 assert(shadow_ref
>= dim
&& shadow_ref
< Elements(args
));
1801 /* fetch modifier to the last argument */
1802 if (modifier
!= TEX_MODIFIER_NONE
) {
1803 const int last
= Elements(args
) - 1;
1805 /* fetch modifier from src0.w or src1.x */
1807 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
1808 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
1811 assert(shadow_ref
!= 4);
1812 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
1815 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
1816 args
[last
] = &r
[last
];
1820 args
[last
] = &ZeroVec
;
1823 /* point unused arguments to zero vector */
1824 for (i
= dim
; i
< last
; i
++)
1827 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
1828 control
= tgsi_sampler_lod_explicit
;
1829 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
1830 control
= tgsi_sampler_lod_bias
;
1833 for (i
= dim
; i
< Elements(args
); i
++)
1837 /* fetch coordinates */
1838 for (i
= 0; i
< dim
; i
++) {
1839 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
1842 micro_div(&r
[i
], &r
[i
], proj
);
1847 /* fetch reference value */
1848 if (shadow_ref
>= 0) {
1849 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
1852 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
1854 args
[shadow_ref
] = &r
[shadow_ref
];
1857 fetch_texel(mach
->Sampler
, unit
, unit
,
1858 args
[0], args
[1], args
[2], args
[3], args
[4],
1859 NULL
, offsets
, control
,
1860 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1863 debug_printf("fetch r: %g %g %g %g\n",
1864 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
1865 debug_printf("fetch g: %g %g %g %g\n",
1866 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
1867 debug_printf("fetch b: %g %g %g %g\n",
1868 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
1869 debug_printf("fetch a: %g %g %g %g\n",
1870 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
1873 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1874 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1875 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1882 exec_txd(struct tgsi_exec_machine
*mach
,
1883 const struct tgsi_full_instruction
*inst
)
1885 const uint unit
= inst
->Src
[3].Register
.Index
;
1886 union tgsi_exec_channel r
[4];
1887 float derivs
[3][2][TGSI_QUAD_SIZE
];
1891 /* always fetch all 3 offsets, overkill but keeps code simple */
1892 fetch_texel_offsets(mach
, inst
, offsets
);
1894 switch (inst
->Texture
.Texture
) {
1895 case TGSI_TEXTURE_1D
:
1896 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1898 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1900 fetch_texel(mach
->Sampler
, unit
, unit
,
1901 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1902 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1903 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1906 case TGSI_TEXTURE_SHADOW1D
:
1907 case TGSI_TEXTURE_1D_ARRAY
:
1908 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1909 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1910 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1911 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1912 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1914 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1916 fetch_texel(mach
->Sampler
, unit
, unit
,
1917 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1918 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1919 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1922 case TGSI_TEXTURE_2D
:
1923 case TGSI_TEXTURE_RECT
:
1924 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1925 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1927 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1928 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1930 fetch_texel(mach
->Sampler
, unit
, unit
,
1931 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
1932 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1933 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1937 case TGSI_TEXTURE_SHADOW2D
:
1938 case TGSI_TEXTURE_SHADOWRECT
:
1939 case TGSI_TEXTURE_2D_ARRAY
:
1940 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1941 /* only SHADOW2D_ARRAY actually needs W */
1942 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1943 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1944 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1945 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1947 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1948 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1950 fetch_texel(mach
->Sampler
, unit
, unit
,
1951 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
1952 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1953 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1956 case TGSI_TEXTURE_3D
:
1957 case TGSI_TEXTURE_CUBE
:
1958 case TGSI_TEXTURE_CUBE_ARRAY
:
1959 /* only TEXTURE_CUBE_ARRAY actually needs W */
1960 FETCH(&r
[0], 0, TGSI_CHAN_X
);
1961 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
1962 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
1963 FETCH(&r
[3], 0, TGSI_CHAN_W
);
1965 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
1966 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
1967 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
1969 fetch_texel(mach
->Sampler
, unit
, unit
,
1970 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
1971 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
1972 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1979 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1980 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1981 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1988 exec_txf(struct tgsi_exec_machine
*mach
,
1989 const struct tgsi_full_instruction
*inst
)
1991 const uint unit
= inst
->Src
[1].Register
.Index
;
1992 union tgsi_exec_channel r
[4];
1994 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1999 /* always fetch all 3 offsets, overkill but keeps code simple */
2000 fetch_texel_offsets(mach
, inst
, offsets
);
2002 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2004 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
) {
2005 target
= mach
->SamplerViews
[unit
].Resource
;
2008 target
= inst
->Texture
.Texture
;
2011 case TGSI_TEXTURE_3D
:
2012 case TGSI_TEXTURE_2D_ARRAY
:
2013 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2014 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2016 case TGSI_TEXTURE_2D
:
2017 case TGSI_TEXTURE_RECT
:
2018 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2019 case TGSI_TEXTURE_SHADOW2D
:
2020 case TGSI_TEXTURE_SHADOWRECT
:
2021 case TGSI_TEXTURE_1D_ARRAY
:
2022 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2024 case TGSI_TEXTURE_BUFFER
:
2025 case TGSI_TEXTURE_1D
:
2026 case TGSI_TEXTURE_SHADOW1D
:
2027 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2034 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2037 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2038 r
[0].f
[j
] = rgba
[0][j
];
2039 r
[1].f
[j
] = rgba
[1][j
];
2040 r
[2].f
[j
] = rgba
[2][j
];
2041 r
[3].f
[j
] = rgba
[3][j
];
2044 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
) {
2045 unsigned char swizzles
[4];
2046 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2047 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2048 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2049 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2051 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2052 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2053 store_dest(mach
, &r
[swizzles
[chan
]],
2054 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2059 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2060 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2061 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2068 exec_txq(struct tgsi_exec_machine
*mach
,
2069 const struct tgsi_full_instruction
*inst
)
2071 const uint unit
= inst
->Src
[1].Register
.Index
;
2073 union tgsi_exec_channel r
[4], src
;
2077 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2079 /* XXX: This interface can't return per-pixel values */
2080 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2082 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2083 for (j
= 0; j
< 4; j
++) {
2084 r
[j
].i
[i
] = result
[j
];
2088 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2089 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2090 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2091 TGSI_EXEC_DATA_INT
);
2097 exec_sample(struct tgsi_exec_machine
*mach
,
2098 const struct tgsi_full_instruction
*inst
,
2099 uint modifier
, boolean compare
)
2101 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2102 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2103 union tgsi_exec_channel r
[4], c1
;
2104 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2105 enum tgsi_sampler_control control
= tgsi_sampler_lod_none
;
2107 unsigned char swizzles
[4];
2110 /* always fetch all 3 offsets, overkill but keeps code simple */
2111 fetch_texel_offsets(mach
, inst
, offsets
);
2113 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2115 if (modifier
!= TEX_MODIFIER_NONE
) {
2116 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2117 FETCH(&c1
, 3, TGSI_CHAN_X
);
2119 control
= tgsi_sampler_lod_bias
;
2121 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2122 FETCH(&c1
, 3, TGSI_CHAN_X
);
2124 control
= tgsi_sampler_lod_explicit
;
2127 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2128 control
= tgsi_sampler_lod_zero
;
2132 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2134 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2135 case TGSI_TEXTURE_1D
:
2137 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2138 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2139 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2140 NULL
, offsets
, control
,
2141 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2144 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2145 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2146 NULL
, offsets
, control
,
2147 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2151 case TGSI_TEXTURE_1D_ARRAY
:
2152 case TGSI_TEXTURE_2D
:
2153 case TGSI_TEXTURE_RECT
:
2154 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2156 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2157 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2158 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2159 NULL
, offsets
, control
,
2160 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2163 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2164 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2165 NULL
, offsets
, control
,
2166 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2170 case TGSI_TEXTURE_2D_ARRAY
:
2171 case TGSI_TEXTURE_3D
:
2172 case TGSI_TEXTURE_CUBE
:
2173 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2174 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2176 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2177 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2178 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2179 NULL
, offsets
, control
,
2180 &r
[0], &r
[1], &r
[2], &r
[3]);
2183 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2184 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2185 NULL
, offsets
, control
,
2186 &r
[0], &r
[1], &r
[2], &r
[3]);
2190 case TGSI_TEXTURE_CUBE_ARRAY
:
2191 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2192 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2193 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2195 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2196 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2197 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2198 NULL
, offsets
, control
,
2199 &r
[0], &r
[1], &r
[2], &r
[3]);
2202 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2203 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2204 NULL
, offsets
, control
,
2205 &r
[0], &r
[1], &r
[2], &r
[3]);
2214 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2215 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2216 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2217 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2219 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2220 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2221 store_dest(mach
, &r
[swizzles
[chan
]],
2222 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2228 exec_sample_d(struct tgsi_exec_machine
*mach
,
2229 const struct tgsi_full_instruction
*inst
)
2231 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2232 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2233 union tgsi_exec_channel r
[4];
2234 float derivs
[3][2][TGSI_QUAD_SIZE
];
2236 unsigned char swizzles
[4];
2239 /* always fetch all 3 offsets, overkill but keeps code simple */
2240 fetch_texel_offsets(mach
, inst
, offsets
);
2242 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2244 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2245 case TGSI_TEXTURE_1D
:
2246 case TGSI_TEXTURE_1D_ARRAY
:
2247 /* only 1D array actually needs Y */
2248 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2250 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2252 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2253 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2254 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2255 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2258 case TGSI_TEXTURE_2D
:
2259 case TGSI_TEXTURE_RECT
:
2260 case TGSI_TEXTURE_2D_ARRAY
:
2261 /* only 2D array actually needs Z */
2262 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2263 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2265 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2266 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2268 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2269 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2270 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2271 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2274 case TGSI_TEXTURE_3D
:
2275 case TGSI_TEXTURE_CUBE
:
2276 case TGSI_TEXTURE_CUBE_ARRAY
:
2277 /* only cube array actually needs W */
2278 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2279 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2280 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2282 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2283 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2284 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2286 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2287 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2288 derivs
, offsets
, tgsi_sampler_derivs_explicit
,
2289 &r
[0], &r
[1], &r
[2], &r
[3]);
2296 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2297 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2298 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2299 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2301 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2302 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2303 store_dest(mach
, &r
[swizzles
[chan
]],
2304 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2311 * Evaluate a constant-valued coefficient at the position of the
2316 struct tgsi_exec_machine
*mach
,
2322 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2323 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2328 * Evaluate a linear-valued coefficient at the position of the
2333 struct tgsi_exec_machine
*mach
,
2337 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2338 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2339 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2340 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2341 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2342 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2343 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2344 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2345 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2349 * Evaluate a perspective-valued coefficient at the position of the
2353 eval_perspective_coef(
2354 struct tgsi_exec_machine
*mach
,
2358 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2359 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2360 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2361 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2362 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2363 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2364 /* divide by W here */
2365 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2366 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2367 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2368 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2372 typedef void (* eval_coef_func
)(
2373 struct tgsi_exec_machine
*mach
,
2378 exec_declaration(struct tgsi_exec_machine
*mach
,
2379 const struct tgsi_full_declaration
*decl
)
2381 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2382 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2386 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
2387 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2388 uint first
, last
, mask
;
2390 first
= decl
->Range
.First
;
2391 last
= decl
->Range
.Last
;
2392 mask
= decl
->Declaration
.UsageMask
;
2394 /* XXX we could remove this special-case code since
2395 * mach->InterpCoefs[first].a0 should already have the
2396 * front/back-face value. But we should first update the
2397 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2398 * Then, we could remove the tgsi_exec_machine::Face field.
2400 /* XXX make FACE a system value */
2401 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2404 assert(decl
->Semantic
.Index
== 0);
2405 assert(first
== last
);
2407 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2408 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2411 eval_coef_func eval
;
2414 switch (decl
->Interp
.Interpolate
) {
2415 case TGSI_INTERPOLATE_CONSTANT
:
2416 eval
= eval_constant_coef
;
2419 case TGSI_INTERPOLATE_LINEAR
:
2420 eval
= eval_linear_coef
;
2423 case TGSI_INTERPOLATE_PERSPECTIVE
:
2424 eval
= eval_perspective_coef
;
2427 case TGSI_INTERPOLATE_COLOR
:
2428 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2436 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2437 if (mask
& (1 << j
)) {
2438 for (i
= first
; i
<= last
; i
++) {
2445 if (DEBUG_EXECUTION
) {
2447 for (i
= first
; i
<= last
; ++i
) {
2448 debug_printf("IN[%2u] = ", i
);
2449 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2453 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2454 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2455 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2456 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2457 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2464 if (decl
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
2465 mach
->SysSemanticToIndex
[decl
->Declaration
.Semantic
] = decl
->Range
.First
;
2470 typedef void (* micro_op
)(union tgsi_exec_channel
*dst
);
2473 exec_vector(struct tgsi_exec_machine
*mach
,
2474 const struct tgsi_full_instruction
*inst
,
2476 enum tgsi_exec_datatype dst_datatype
)
2480 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2481 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2482 union tgsi_exec_channel dst
;
2485 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2490 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2491 const union tgsi_exec_channel
*src
);
2494 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2495 const struct tgsi_full_instruction
*inst
,
2497 enum tgsi_exec_datatype dst_datatype
,
2498 enum tgsi_exec_datatype src_datatype
)
2501 union tgsi_exec_channel src
;
2502 union tgsi_exec_channel dst
;
2504 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2506 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2507 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2508 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2514 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2515 const struct tgsi_full_instruction
*inst
,
2517 enum tgsi_exec_datatype dst_datatype
,
2518 enum tgsi_exec_datatype src_datatype
)
2521 struct tgsi_exec_vector dst
;
2523 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2524 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2525 union tgsi_exec_channel src
;
2527 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2528 op(&dst
.xyzw
[chan
], &src
);
2531 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2532 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2533 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2538 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2539 const union tgsi_exec_channel
*src0
,
2540 const union tgsi_exec_channel
*src1
);
2543 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2544 const struct tgsi_full_instruction
*inst
,
2546 enum tgsi_exec_datatype dst_datatype
,
2547 enum tgsi_exec_datatype src_datatype
)
2550 union tgsi_exec_channel src
[2];
2551 union tgsi_exec_channel dst
;
2553 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2554 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
2555 op(&dst
, &src
[0], &src
[1]);
2556 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2557 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2558 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2564 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2565 const struct tgsi_full_instruction
*inst
,
2567 enum tgsi_exec_datatype dst_datatype
,
2568 enum tgsi_exec_datatype src_datatype
)
2571 struct tgsi_exec_vector dst
;
2573 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2574 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2575 union tgsi_exec_channel src
[2];
2577 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2578 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2579 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2582 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2583 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2584 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2589 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2590 const union tgsi_exec_channel
*src0
,
2591 const union tgsi_exec_channel
*src1
,
2592 const union tgsi_exec_channel
*src2
);
2595 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2596 const struct tgsi_full_instruction
*inst
,
2597 micro_trinary_op op
,
2598 enum tgsi_exec_datatype dst_datatype
,
2599 enum tgsi_exec_datatype src_datatype
)
2602 struct tgsi_exec_vector dst
;
2604 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2605 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2606 union tgsi_exec_channel src
[3];
2608 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2609 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2610 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2611 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2614 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2615 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2616 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2622 exec_dp3(struct tgsi_exec_machine
*mach
,
2623 const struct tgsi_full_instruction
*inst
)
2626 union tgsi_exec_channel arg
[3];
2628 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2629 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2630 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2632 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2633 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2634 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2635 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2638 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2639 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2640 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2646 exec_dp4(struct tgsi_exec_machine
*mach
,
2647 const struct tgsi_full_instruction
*inst
)
2650 union tgsi_exec_channel arg
[3];
2652 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2653 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2654 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2656 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2657 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2658 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2659 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2662 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2663 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2664 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2670 exec_dp2a(struct tgsi_exec_machine
*mach
,
2671 const struct tgsi_full_instruction
*inst
)
2674 union tgsi_exec_channel arg
[3];
2676 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2677 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2678 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2680 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2681 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2682 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2684 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2685 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2687 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2688 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2689 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2695 exec_dph(struct tgsi_exec_machine
*mach
,
2696 const struct tgsi_full_instruction
*inst
)
2699 union tgsi_exec_channel arg
[3];
2701 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2702 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2703 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2705 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2706 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2707 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2709 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2710 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2711 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2713 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2714 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2716 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2717 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2718 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2724 exec_dp2(struct tgsi_exec_machine
*mach
,
2725 const struct tgsi_full_instruction
*inst
)
2728 union tgsi_exec_channel arg
[3];
2730 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2731 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2732 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2734 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2735 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2736 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2738 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2739 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2740 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2746 exec_nrm4(struct tgsi_exec_machine
*mach
,
2747 const struct tgsi_full_instruction
*inst
)
2750 union tgsi_exec_channel arg
[4];
2751 union tgsi_exec_channel scale
;
2753 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2754 micro_mul(&scale
, &arg
[0], &arg
[0]);
2756 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2757 union tgsi_exec_channel product
;
2759 fetch_source(mach
, &arg
[chan
], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2760 micro_mul(&product
, &arg
[chan
], &arg
[chan
]);
2761 micro_add(&scale
, &scale
, &product
);
2764 micro_rsq(&scale
, &scale
);
2766 for (chan
= TGSI_CHAN_X
; chan
<= TGSI_CHAN_W
; chan
++) {
2767 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2768 micro_mul(&arg
[chan
], &arg
[chan
], &scale
);
2769 store_dest(mach
, &arg
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2775 exec_nrm3(struct tgsi_exec_machine
*mach
,
2776 const struct tgsi_full_instruction
*inst
)
2778 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2780 union tgsi_exec_channel arg
[3];
2781 union tgsi_exec_channel scale
;
2783 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2784 micro_mul(&scale
, &arg
[0], &arg
[0]);
2786 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2787 union tgsi_exec_channel product
;
2789 fetch_source(mach
, &arg
[chan
], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2790 micro_mul(&product
, &arg
[chan
], &arg
[chan
]);
2791 micro_add(&scale
, &scale
, &product
);
2794 micro_rsq(&scale
, &scale
);
2796 for (chan
= TGSI_CHAN_X
; chan
<= TGSI_CHAN_Z
; chan
++) {
2797 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2798 micro_mul(&arg
[chan
], &arg
[chan
], &scale
);
2799 store_dest(mach
, &arg
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2804 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2805 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2810 exec_scs(struct tgsi_exec_machine
*mach
,
2811 const struct tgsi_full_instruction
*inst
)
2813 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
2814 union tgsi_exec_channel arg
;
2815 union tgsi_exec_channel result
;
2817 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2819 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2820 micro_cos(&result
, &arg
);
2821 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2823 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2824 micro_sin(&result
, &arg
);
2825 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2828 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2829 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2831 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2832 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2837 exec_x2d(struct tgsi_exec_machine
*mach
,
2838 const struct tgsi_full_instruction
*inst
)
2840 union tgsi_exec_channel r
[4];
2841 union tgsi_exec_channel d
[2];
2843 fetch_source(mach
, &r
[0], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2844 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2845 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XZ
) {
2846 fetch_source(mach
, &r
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2847 micro_mul(&r
[2], &r
[2], &r
[0]);
2848 fetch_source(mach
, &r
[3], &inst
->Src
[2], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2849 micro_mul(&r
[3], &r
[3], &r
[1]);
2850 micro_add(&r
[2], &r
[2], &r
[3]);
2851 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2852 micro_add(&d
[0], &r
[2], &r
[3]);
2854 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YW
) {
2855 fetch_source(mach
, &r
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2856 micro_mul(&r
[2], &r
[2], &r
[0]);
2857 fetch_source(mach
, &r
[3], &inst
->Src
[2], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2858 micro_mul(&r
[3], &r
[3], &r
[1]);
2859 micro_add(&r
[2], &r
[2], &r
[3]);
2860 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2861 micro_add(&d
[1], &r
[2], &r
[3]);
2863 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2864 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2866 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2867 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2869 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2870 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2872 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2873 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2878 exec_rfl(struct tgsi_exec_machine
*mach
,
2879 const struct tgsi_full_instruction
*inst
)
2881 union tgsi_exec_channel r
[9];
2883 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2884 /* r0 = dp3(src0, src0) */
2885 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2886 micro_mul(&r
[0], &r
[2], &r
[2]);
2887 fetch_source(mach
, &r
[4], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2888 micro_mul(&r
[8], &r
[4], &r
[4]);
2889 micro_add(&r
[0], &r
[0], &r
[8]);
2890 fetch_source(mach
, &r
[6], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2891 micro_mul(&r
[8], &r
[6], &r
[6]);
2892 micro_add(&r
[0], &r
[0], &r
[8]);
2894 /* r1 = dp3(src0, src1) */
2895 fetch_source(mach
, &r
[3], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2896 micro_mul(&r
[1], &r
[2], &r
[3]);
2897 fetch_source(mach
, &r
[5], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2898 micro_mul(&r
[8], &r
[4], &r
[5]);
2899 micro_add(&r
[1], &r
[1], &r
[8]);
2900 fetch_source(mach
, &r
[7], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2901 micro_mul(&r
[8], &r
[6], &r
[7]);
2902 micro_add(&r
[1], &r
[1], &r
[8]);
2904 /* r1 = 2 * r1 / r0 */
2905 micro_add(&r
[1], &r
[1], &r
[1]);
2906 micro_div(&r
[1], &r
[1], &r
[0]);
2908 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2909 micro_mul(&r
[2], &r
[2], &r
[1]);
2910 micro_sub(&r
[2], &r
[2], &r
[3]);
2911 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2913 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2914 micro_mul(&r
[4], &r
[4], &r
[1]);
2915 micro_sub(&r
[4], &r
[4], &r
[5]);
2916 store_dest(mach
, &r
[4], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2918 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2919 micro_mul(&r
[6], &r
[6], &r
[1]);
2920 micro_sub(&r
[6], &r
[6], &r
[7]);
2921 store_dest(mach
, &r
[6], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2924 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2925 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2930 exec_xpd(struct tgsi_exec_machine
*mach
,
2931 const struct tgsi_full_instruction
*inst
)
2933 union tgsi_exec_channel r
[6];
2934 union tgsi_exec_channel d
[3];
2936 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2937 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2939 micro_mul(&r
[2], &r
[0], &r
[1]);
2941 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2942 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2944 micro_mul(&r
[5], &r
[3], &r
[4] );
2945 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
2947 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2949 micro_mul(&r
[3], &r
[3], &r
[2]);
2951 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2953 micro_mul(&r
[1], &r
[1], &r
[5]);
2954 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
2956 micro_mul(&r
[5], &r
[5], &r
[4]);
2957 micro_mul(&r
[0], &r
[0], &r
[2]);
2958 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
2960 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2961 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2963 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2964 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2966 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2967 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2969 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2970 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2975 exec_dst(struct tgsi_exec_machine
*mach
,
2976 const struct tgsi_full_instruction
*inst
)
2978 union tgsi_exec_channel r
[2];
2979 union tgsi_exec_channel d
[4];
2981 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2982 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2983 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2984 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
2986 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2987 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2989 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2990 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2993 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2994 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2996 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2997 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2999 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3000 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3002 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3003 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3008 exec_log(struct tgsi_exec_machine
*mach
,
3009 const struct tgsi_full_instruction
*inst
)
3011 union tgsi_exec_channel r
[3];
3013 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3014 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3015 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3016 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3017 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3018 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3020 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3021 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3022 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3023 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3025 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3026 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3028 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3029 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3034 exec_exp(struct tgsi_exec_machine
*mach
,
3035 const struct tgsi_full_instruction
*inst
)
3037 union tgsi_exec_channel r
[3];
3039 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3040 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3041 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3042 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3043 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3045 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3046 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3047 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3049 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3050 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3051 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3053 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3054 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3059 exec_lit(struct tgsi_exec_machine
*mach
,
3060 const struct tgsi_full_instruction
*inst
)
3062 union tgsi_exec_channel r
[3];
3063 union tgsi_exec_channel d
[3];
3065 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3066 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3067 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3068 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3069 micro_max(&r
[1], &r
[1], &ZeroVec
);
3071 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3072 micro_min(&r
[2], &r
[2], &P128Vec
);
3073 micro_max(&r
[2], &r
[2], &M128Vec
);
3074 micro_pow(&r
[1], &r
[1], &r
[2]);
3075 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3076 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3078 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3079 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3080 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3083 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3084 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3087 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3088 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3093 exec_break(struct tgsi_exec_machine
*mach
)
3095 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3096 /* turn off loop channels for each enabled exec channel */
3097 mach
->LoopMask
&= ~mach
->ExecMask
;
3098 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3099 UPDATE_EXEC_MASK(mach
);
3101 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3103 mach
->Switch
.mask
= 0x0;
3105 UPDATE_EXEC_MASK(mach
);
3110 exec_switch(struct tgsi_exec_machine
*mach
,
3111 const struct tgsi_full_instruction
*inst
)
3113 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3114 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3116 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3117 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3118 mach
->Switch
.mask
= 0x0;
3119 mach
->Switch
.defaultMask
= 0x0;
3121 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3122 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3124 UPDATE_EXEC_MASK(mach
);
3128 exec_case(struct tgsi_exec_machine
*mach
,
3129 const struct tgsi_full_instruction
*inst
)
3131 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3132 union tgsi_exec_channel src
;
3135 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3137 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3140 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3143 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3146 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3150 mach
->Switch
.defaultMask
|= mask
;
3152 mach
->Switch
.mask
|= mask
& prevMask
;
3154 UPDATE_EXEC_MASK(mach
);
3157 /* FIXME: this will only work if default is last */
3159 exec_default(struct tgsi_exec_machine
*mach
)
3161 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3163 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3165 UPDATE_EXEC_MASK(mach
);
3169 exec_endswitch(struct tgsi_exec_machine
*mach
)
3171 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3172 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3174 UPDATE_EXEC_MASK(mach
);
3178 micro_i2f(union tgsi_exec_channel
*dst
,
3179 const union tgsi_exec_channel
*src
)
3181 dst
->f
[0] = (float)src
->i
[0];
3182 dst
->f
[1] = (float)src
->i
[1];
3183 dst
->f
[2] = (float)src
->i
[2];
3184 dst
->f
[3] = (float)src
->i
[3];
3188 micro_not(union tgsi_exec_channel
*dst
,
3189 const union tgsi_exec_channel
*src
)
3191 dst
->u
[0] = ~src
->u
[0];
3192 dst
->u
[1] = ~src
->u
[1];
3193 dst
->u
[2] = ~src
->u
[2];
3194 dst
->u
[3] = ~src
->u
[3];
3198 micro_shl(union tgsi_exec_channel
*dst
,
3199 const union tgsi_exec_channel
*src0
,
3200 const union tgsi_exec_channel
*src1
)
3202 unsigned masked_count
;
3203 masked_count
= src1
->u
[0] & 0x1f;
3204 dst
->u
[0] = src0
->u
[0] << masked_count
;
3205 masked_count
= src1
->u
[1] & 0x1f;
3206 dst
->u
[1] = src0
->u
[1] << masked_count
;
3207 masked_count
= src1
->u
[2] & 0x1f;
3208 dst
->u
[2] = src0
->u
[2] << masked_count
;
3209 masked_count
= src1
->u
[3] & 0x1f;
3210 dst
->u
[3] = src0
->u
[3] << masked_count
;
3214 micro_and(union tgsi_exec_channel
*dst
,
3215 const union tgsi_exec_channel
*src0
,
3216 const union tgsi_exec_channel
*src1
)
3218 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
3219 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
3220 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
3221 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
3225 micro_or(union tgsi_exec_channel
*dst
,
3226 const union tgsi_exec_channel
*src0
,
3227 const union tgsi_exec_channel
*src1
)
3229 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
3230 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
3231 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
3232 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
3236 micro_xor(union tgsi_exec_channel
*dst
,
3237 const union tgsi_exec_channel
*src0
,
3238 const union tgsi_exec_channel
*src1
)
3240 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
3241 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
3242 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
3243 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
3247 micro_mod(union tgsi_exec_channel
*dst
,
3248 const union tgsi_exec_channel
*src0
,
3249 const union tgsi_exec_channel
*src1
)
3251 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
3252 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
3253 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
3254 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
3258 micro_f2i(union tgsi_exec_channel
*dst
,
3259 const union tgsi_exec_channel
*src
)
3261 dst
->i
[0] = (int)src
->f
[0];
3262 dst
->i
[1] = (int)src
->f
[1];
3263 dst
->i
[2] = (int)src
->f
[2];
3264 dst
->i
[3] = (int)src
->f
[3];
3268 micro_fseq(union tgsi_exec_channel
*dst
,
3269 const union tgsi_exec_channel
*src0
,
3270 const union tgsi_exec_channel
*src1
)
3272 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
3273 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
3274 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
3275 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
3279 micro_fsge(union tgsi_exec_channel
*dst
,
3280 const union tgsi_exec_channel
*src0
,
3281 const union tgsi_exec_channel
*src1
)
3283 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
3284 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
3285 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
3286 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
3290 micro_fslt(union tgsi_exec_channel
*dst
,
3291 const union tgsi_exec_channel
*src0
,
3292 const union tgsi_exec_channel
*src1
)
3294 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
3295 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
3296 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
3297 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
3301 micro_fsne(union tgsi_exec_channel
*dst
,
3302 const union tgsi_exec_channel
*src0
,
3303 const union tgsi_exec_channel
*src1
)
3305 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
3306 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
3307 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
3308 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
3312 micro_idiv(union tgsi_exec_channel
*dst
,
3313 const union tgsi_exec_channel
*src0
,
3314 const union tgsi_exec_channel
*src1
)
3316 dst
->i
[0] = src0
->i
[0] / src1
->i
[0];
3317 dst
->i
[1] = src0
->i
[1] / src1
->i
[1];
3318 dst
->i
[2] = src0
->i
[2] / src1
->i
[2];
3319 dst
->i
[3] = src0
->i
[3] / src1
->i
[3];
3323 micro_imax(union tgsi_exec_channel
*dst
,
3324 const union tgsi_exec_channel
*src0
,
3325 const union tgsi_exec_channel
*src1
)
3327 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3328 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3329 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3330 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3334 micro_imin(union tgsi_exec_channel
*dst
,
3335 const union tgsi_exec_channel
*src0
,
3336 const union tgsi_exec_channel
*src1
)
3338 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
3339 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
3340 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
3341 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
3345 micro_isge(union tgsi_exec_channel
*dst
,
3346 const union tgsi_exec_channel
*src0
,
3347 const union tgsi_exec_channel
*src1
)
3349 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
3350 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
3351 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
3352 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
3356 micro_ishr(union tgsi_exec_channel
*dst
,
3357 const union tgsi_exec_channel
*src0
,
3358 const union tgsi_exec_channel
*src1
)
3360 unsigned masked_count
;
3361 masked_count
= src1
->i
[0] & 0x1f;
3362 dst
->i
[0] = src0
->i
[0] >> masked_count
;
3363 masked_count
= src1
->i
[1] & 0x1f;
3364 dst
->i
[1] = src0
->i
[1] >> masked_count
;
3365 masked_count
= src1
->i
[2] & 0x1f;
3366 dst
->i
[2] = src0
->i
[2] >> masked_count
;
3367 masked_count
= src1
->i
[3] & 0x1f;
3368 dst
->i
[3] = src0
->i
[3] >> masked_count
;
3372 micro_islt(union tgsi_exec_channel
*dst
,
3373 const union tgsi_exec_channel
*src0
,
3374 const union tgsi_exec_channel
*src1
)
3376 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
3377 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
3378 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
3379 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
3383 micro_f2u(union tgsi_exec_channel
*dst
,
3384 const union tgsi_exec_channel
*src
)
3386 dst
->u
[0] = (uint
)src
->f
[0];
3387 dst
->u
[1] = (uint
)src
->f
[1];
3388 dst
->u
[2] = (uint
)src
->f
[2];
3389 dst
->u
[3] = (uint
)src
->f
[3];
3393 micro_u2f(union tgsi_exec_channel
*dst
,
3394 const union tgsi_exec_channel
*src
)
3396 dst
->f
[0] = (float)src
->u
[0];
3397 dst
->f
[1] = (float)src
->u
[1];
3398 dst
->f
[2] = (float)src
->u
[2];
3399 dst
->f
[3] = (float)src
->u
[3];
3403 micro_uadd(union tgsi_exec_channel
*dst
,
3404 const union tgsi_exec_channel
*src0
,
3405 const union tgsi_exec_channel
*src1
)
3407 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
3408 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
3409 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
3410 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
3414 micro_udiv(union tgsi_exec_channel
*dst
,
3415 const union tgsi_exec_channel
*src0
,
3416 const union tgsi_exec_channel
*src1
)
3418 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
3419 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
3420 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
3421 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
3425 micro_umad(union tgsi_exec_channel
*dst
,
3426 const union tgsi_exec_channel
*src0
,
3427 const union tgsi_exec_channel
*src1
,
3428 const union tgsi_exec_channel
*src2
)
3430 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
3431 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
3432 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
3433 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
3437 micro_umax(union tgsi_exec_channel
*dst
,
3438 const union tgsi_exec_channel
*src0
,
3439 const union tgsi_exec_channel
*src1
)
3441 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3442 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3443 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3444 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3448 micro_umin(union tgsi_exec_channel
*dst
,
3449 const union tgsi_exec_channel
*src0
,
3450 const union tgsi_exec_channel
*src1
)
3452 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
3453 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
3454 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
3455 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
3459 micro_umod(union tgsi_exec_channel
*dst
,
3460 const union tgsi_exec_channel
*src0
,
3461 const union tgsi_exec_channel
*src1
)
3463 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
3464 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
3465 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
3466 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
3470 micro_umul(union tgsi_exec_channel
*dst
,
3471 const union tgsi_exec_channel
*src0
,
3472 const union tgsi_exec_channel
*src1
)
3474 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
3475 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
3476 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
3477 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
3481 micro_imul_hi(union tgsi_exec_channel
*dst
,
3482 const union tgsi_exec_channel
*src0
,
3483 const union tgsi_exec_channel
*src1
)
3485 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3486 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
3487 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
3488 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
3489 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
3494 micro_umul_hi(union tgsi_exec_channel
*dst
,
3495 const union tgsi_exec_channel
*src0
,
3496 const union tgsi_exec_channel
*src1
)
3498 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3499 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
3500 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
3501 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
3502 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
3507 micro_useq(union tgsi_exec_channel
*dst
,
3508 const union tgsi_exec_channel
*src0
,
3509 const union tgsi_exec_channel
*src1
)
3511 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
3512 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
3513 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
3514 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
3518 micro_usge(union tgsi_exec_channel
*dst
,
3519 const union tgsi_exec_channel
*src0
,
3520 const union tgsi_exec_channel
*src1
)
3522 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
3523 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
3524 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
3525 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
3529 micro_ushr(union tgsi_exec_channel
*dst
,
3530 const union tgsi_exec_channel
*src0
,
3531 const union tgsi_exec_channel
*src1
)
3533 unsigned masked_count
;
3534 masked_count
= src1
->u
[0] & 0x1f;
3535 dst
->u
[0] = src0
->u
[0] >> masked_count
;
3536 masked_count
= src1
->u
[1] & 0x1f;
3537 dst
->u
[1] = src0
->u
[1] >> masked_count
;
3538 masked_count
= src1
->u
[2] & 0x1f;
3539 dst
->u
[2] = src0
->u
[2] >> masked_count
;
3540 masked_count
= src1
->u
[3] & 0x1f;
3541 dst
->u
[3] = src0
->u
[3] >> masked_count
;
3545 micro_uslt(union tgsi_exec_channel
*dst
,
3546 const union tgsi_exec_channel
*src0
,
3547 const union tgsi_exec_channel
*src1
)
3549 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
3550 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
3551 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
3552 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
3556 micro_usne(union tgsi_exec_channel
*dst
,
3557 const union tgsi_exec_channel
*src0
,
3558 const union tgsi_exec_channel
*src1
)
3560 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
3561 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
3562 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
3563 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
3567 micro_uarl(union tgsi_exec_channel
*dst
,
3568 const union tgsi_exec_channel
*src
)
3570 dst
->i
[0] = src
->u
[0];
3571 dst
->i
[1] = src
->u
[1];
3572 dst
->i
[2] = src
->u
[2];
3573 dst
->i
[3] = src
->u
[3];
3577 micro_ucmp(union tgsi_exec_channel
*dst
,
3578 const union tgsi_exec_channel
*src0
,
3579 const union tgsi_exec_channel
*src1
,
3580 const union tgsi_exec_channel
*src2
)
3582 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
3583 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
3584 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
3585 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
3590 struct tgsi_exec_machine
*mach
,
3591 const struct tgsi_full_instruction
*inst
,
3594 union tgsi_exec_channel r
[10];
3598 switch (inst
->Instruction
.Opcode
) {
3599 case TGSI_OPCODE_ARL
:
3600 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3603 case TGSI_OPCODE_MOV
:
3604 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
3607 case TGSI_OPCODE_LIT
:
3608 exec_lit(mach
, inst
);
3611 case TGSI_OPCODE_RCP
:
3612 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3615 case TGSI_OPCODE_RSQ
:
3616 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3619 case TGSI_OPCODE_EXP
:
3620 exec_exp(mach
, inst
);
3623 case TGSI_OPCODE_LOG
:
3624 exec_log(mach
, inst
);
3627 case TGSI_OPCODE_MUL
:
3628 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3631 case TGSI_OPCODE_ADD
:
3632 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3635 case TGSI_OPCODE_DP3
:
3636 exec_dp3(mach
, inst
);
3639 case TGSI_OPCODE_DP4
:
3640 exec_dp4(mach
, inst
);
3643 case TGSI_OPCODE_DST
:
3644 exec_dst(mach
, inst
);
3647 case TGSI_OPCODE_MIN
:
3648 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3651 case TGSI_OPCODE_MAX
:
3652 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3655 case TGSI_OPCODE_SLT
:
3656 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3659 case TGSI_OPCODE_SGE
:
3660 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3663 case TGSI_OPCODE_MAD
:
3664 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3667 case TGSI_OPCODE_SUB
:
3668 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3671 case TGSI_OPCODE_LRP
:
3672 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3675 case TGSI_OPCODE_CND
:
3676 exec_vector_trinary(mach
, inst
, micro_cnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3679 case TGSI_OPCODE_SQRT
:
3680 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3683 case TGSI_OPCODE_DP2A
:
3684 exec_dp2a(mach
, inst
);
3687 case TGSI_OPCODE_FRC
:
3688 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3691 case TGSI_OPCODE_CLAMP
:
3692 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3695 case TGSI_OPCODE_FLR
:
3696 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3699 case TGSI_OPCODE_ROUND
:
3700 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3703 case TGSI_OPCODE_EX2
:
3704 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3707 case TGSI_OPCODE_LG2
:
3708 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3711 case TGSI_OPCODE_POW
:
3712 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3715 case TGSI_OPCODE_XPD
:
3716 exec_xpd(mach
, inst
);
3719 case TGSI_OPCODE_ABS
:
3720 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3723 case TGSI_OPCODE_RCC
:
3724 exec_scalar_unary(mach
, inst
, micro_rcc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3727 case TGSI_OPCODE_DPH
:
3728 exec_dph(mach
, inst
);
3731 case TGSI_OPCODE_COS
:
3732 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3735 case TGSI_OPCODE_DDX
:
3736 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3739 case TGSI_OPCODE_DDY
:
3740 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3743 case TGSI_OPCODE_KILL
:
3744 exec_kill (mach
, inst
);
3747 case TGSI_OPCODE_KILL_IF
:
3748 exec_kill_if (mach
, inst
);
3751 case TGSI_OPCODE_PK2H
:
3755 case TGSI_OPCODE_PK2US
:
3759 case TGSI_OPCODE_PK4B
:
3763 case TGSI_OPCODE_PK4UB
:
3767 case TGSI_OPCODE_RFL
:
3768 exec_rfl(mach
, inst
);
3771 case TGSI_OPCODE_SEQ
:
3772 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3775 case TGSI_OPCODE_SFL
:
3776 exec_vector(mach
, inst
, micro_sfl
, TGSI_EXEC_DATA_FLOAT
);
3779 case TGSI_OPCODE_SGT
:
3780 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3783 case TGSI_OPCODE_SIN
:
3784 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3787 case TGSI_OPCODE_SLE
:
3788 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3791 case TGSI_OPCODE_SNE
:
3792 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3795 case TGSI_OPCODE_STR
:
3796 exec_vector(mach
, inst
, micro_str
, TGSI_EXEC_DATA_FLOAT
);
3799 case TGSI_OPCODE_TEX
:
3800 /* simple texture lookup */
3801 /* src[0] = texcoord */
3802 /* src[1] = sampler unit */
3803 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
3806 case TGSI_OPCODE_TXB
:
3807 /* Texture lookup with lod bias */
3808 /* src[0] = texcoord (src[0].w = LOD bias) */
3809 /* src[1] = sampler unit */
3810 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
3813 case TGSI_OPCODE_TXD
:
3814 /* Texture lookup with explict partial derivatives */
3815 /* src[0] = texcoord */
3816 /* src[1] = d[strq]/dx */
3817 /* src[2] = d[strq]/dy */
3818 /* src[3] = sampler unit */
3819 exec_txd(mach
, inst
);
3822 case TGSI_OPCODE_TXL
:
3823 /* Texture lookup with explit LOD */
3824 /* src[0] = texcoord (src[0].w = LOD) */
3825 /* src[1] = sampler unit */
3826 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
3829 case TGSI_OPCODE_TXP
:
3830 /* Texture lookup with projection */
3831 /* src[0] = texcoord (src[0].w = projection) */
3832 /* src[1] = sampler unit */
3833 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
3836 case TGSI_OPCODE_UP2H
:
3840 case TGSI_OPCODE_UP2US
:
3844 case TGSI_OPCODE_UP4B
:
3848 case TGSI_OPCODE_UP4UB
:
3852 case TGSI_OPCODE_X2D
:
3853 exec_x2d(mach
, inst
);
3856 case TGSI_OPCODE_ARA
:
3860 case TGSI_OPCODE_ARR
:
3861 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3864 case TGSI_OPCODE_BRA
:
3868 case TGSI_OPCODE_CAL
:
3869 /* skip the call if no execution channels are enabled */
3870 if (mach
->ExecMask
) {
3873 /* First, record the depths of the execution stacks.
3874 * This is important for deeply nested/looped return statements.
3875 * We have to unwind the stacks by the correct amount. For a
3876 * real code generator, we could determine the number of entries
3877 * to pop off each stack with simple static analysis and avoid
3878 * implementing this data structure at run time.
3880 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
3881 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
3882 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
3883 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
3884 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
3885 /* note that PC was already incremented above */
3886 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
3888 mach
->CallStackTop
++;
3890 /* Second, push the Cond, Loop, Cont, Func stacks */
3891 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3892 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3893 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3894 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3895 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3896 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
3898 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3899 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
3900 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
3901 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3902 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3903 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
3905 /* Finally, jump to the subroutine */
3906 *pc
= inst
->Label
.Label
;
3910 case TGSI_OPCODE_RET
:
3911 mach
->FuncMask
&= ~mach
->ExecMask
;
3912 UPDATE_EXEC_MASK(mach
);
3914 if (mach
->FuncMask
== 0x0) {
3915 /* really return now (otherwise, keep executing */
3917 if (mach
->CallStackTop
== 0) {
3918 /* returning from main() */
3919 mach
->CondStackTop
= 0;
3920 mach
->LoopStackTop
= 0;
3925 assert(mach
->CallStackTop
> 0);
3926 mach
->CallStackTop
--;
3928 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
3929 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
3931 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
3932 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
3934 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
3935 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
3937 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
3938 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
3940 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
3941 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
3943 assert(mach
->FuncStackTop
> 0);
3944 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
3946 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
3948 UPDATE_EXEC_MASK(mach
);
3952 case TGSI_OPCODE_SSG
:
3953 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3956 case TGSI_OPCODE_CMP
:
3957 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3960 case TGSI_OPCODE_SCS
:
3961 exec_scs(mach
, inst
);
3964 case TGSI_OPCODE_NRM
:
3965 exec_nrm3(mach
, inst
);
3968 case TGSI_OPCODE_NRM4
:
3969 exec_nrm4(mach
, inst
);
3972 case TGSI_OPCODE_DIV
:
3973 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3976 case TGSI_OPCODE_DP2
:
3977 exec_dp2(mach
, inst
);
3980 case TGSI_OPCODE_IF
:
3982 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3983 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3984 FETCH( &r
[0], 0, TGSI_CHAN_X
);
3985 /* update CondMask */
3987 mach
->CondMask
&= ~0x1;
3990 mach
->CondMask
&= ~0x2;
3993 mach
->CondMask
&= ~0x4;
3996 mach
->CondMask
&= ~0x8;
3998 UPDATE_EXEC_MASK(mach
);
3999 /* Todo: If CondMask==0, jump to ELSE */
4002 case TGSI_OPCODE_UIF
:
4004 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4005 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4006 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
4007 /* update CondMask */
4009 mach
->CondMask
&= ~0x1;
4012 mach
->CondMask
&= ~0x2;
4015 mach
->CondMask
&= ~0x4;
4018 mach
->CondMask
&= ~0x8;
4020 UPDATE_EXEC_MASK(mach
);
4021 /* Todo: If CondMask==0, jump to ELSE */
4024 case TGSI_OPCODE_ELSE
:
4025 /* invert CondMask wrt previous mask */
4028 assert(mach
->CondStackTop
> 0);
4029 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
4030 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
4031 UPDATE_EXEC_MASK(mach
);
4032 /* Todo: If CondMask==0, jump to ENDIF */
4036 case TGSI_OPCODE_ENDIF
:
4038 assert(mach
->CondStackTop
> 0);
4039 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
4040 UPDATE_EXEC_MASK(mach
);
4043 case TGSI_OPCODE_END
:
4044 /* make sure we end primitives which haven't
4045 * been explicitly emitted */
4046 conditional_emit_primitive(mach
);
4047 /* halt execution */
4051 case TGSI_OPCODE_PUSHA
:
4055 case TGSI_OPCODE_POPA
:
4059 case TGSI_OPCODE_CEIL
:
4060 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4063 case TGSI_OPCODE_I2F
:
4064 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
4067 case TGSI_OPCODE_NOT
:
4068 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4071 case TGSI_OPCODE_TRUNC
:
4072 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4075 case TGSI_OPCODE_SHL
:
4076 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4079 case TGSI_OPCODE_AND
:
4080 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4083 case TGSI_OPCODE_OR
:
4084 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4087 case TGSI_OPCODE_MOD
:
4088 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4091 case TGSI_OPCODE_XOR
:
4092 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4095 case TGSI_OPCODE_SAD
:
4099 case TGSI_OPCODE_TXF
:
4100 exec_txf(mach
, inst
);
4103 case TGSI_OPCODE_TXQ
:
4104 exec_txq(mach
, inst
);
4107 case TGSI_OPCODE_EMIT
:
4111 case TGSI_OPCODE_ENDPRIM
:
4112 emit_primitive(mach
);
4115 case TGSI_OPCODE_BGNLOOP
:
4116 /* push LoopMask and ContMasks */
4117 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4118 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4119 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4120 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4122 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4123 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4124 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
4125 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4126 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
4129 case TGSI_OPCODE_ENDLOOP
:
4130 /* Restore ContMask, but don't pop */
4131 assert(mach
->ContStackTop
> 0);
4132 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
4133 UPDATE_EXEC_MASK(mach
);
4134 if (mach
->ExecMask
) {
4135 /* repeat loop: jump to instruction just past BGNLOOP */
4136 assert(mach
->LoopLabelStackTop
> 0);
4137 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
4140 /* exit loop: pop LoopMask */
4141 assert(mach
->LoopStackTop
> 0);
4142 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
4144 assert(mach
->ContStackTop
> 0);
4145 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
4146 assert(mach
->LoopLabelStackTop
> 0);
4147 --mach
->LoopLabelStackTop
;
4149 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
4151 UPDATE_EXEC_MASK(mach
);
4154 case TGSI_OPCODE_BRK
:
4158 case TGSI_OPCODE_CONT
:
4159 /* turn off cont channels for each enabled exec channel */
4160 mach
->ContMask
&= ~mach
->ExecMask
;
4161 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4162 UPDATE_EXEC_MASK(mach
);
4165 case TGSI_OPCODE_BGNSUB
:
4169 case TGSI_OPCODE_ENDSUB
:
4171 * XXX: This really should be a no-op. We should never reach this opcode.
4174 assert(mach
->CallStackTop
> 0);
4175 mach
->CallStackTop
--;
4177 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
4178 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
4180 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
4181 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
4183 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
4184 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
4186 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
4187 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
4189 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
4190 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
4192 assert(mach
->FuncStackTop
> 0);
4193 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
4195 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
4197 UPDATE_EXEC_MASK(mach
);
4200 case TGSI_OPCODE_NOP
:
4203 case TGSI_OPCODE_BREAKC
:
4204 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4205 /* update CondMask */
4206 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
4207 mach
->LoopMask
&= ~0x1;
4209 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
4210 mach
->LoopMask
&= ~0x2;
4212 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
4213 mach
->LoopMask
&= ~0x4;
4215 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
4216 mach
->LoopMask
&= ~0x8;
4218 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4219 UPDATE_EXEC_MASK(mach
);
4222 case TGSI_OPCODE_F2I
:
4223 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4226 case TGSI_OPCODE_FSEQ
:
4227 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4230 case TGSI_OPCODE_FSGE
:
4231 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4234 case TGSI_OPCODE_FSLT
:
4235 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4238 case TGSI_OPCODE_FSNE
:
4239 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4242 case TGSI_OPCODE_IDIV
:
4243 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4246 case TGSI_OPCODE_IMAX
:
4247 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4250 case TGSI_OPCODE_IMIN
:
4251 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4254 case TGSI_OPCODE_INEG
:
4255 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4258 case TGSI_OPCODE_ISGE
:
4259 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4262 case TGSI_OPCODE_ISHR
:
4263 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4266 case TGSI_OPCODE_ISLT
:
4267 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4270 case TGSI_OPCODE_F2U
:
4271 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4274 case TGSI_OPCODE_U2F
:
4275 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
4278 case TGSI_OPCODE_UADD
:
4279 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4282 case TGSI_OPCODE_UDIV
:
4283 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4286 case TGSI_OPCODE_UMAD
:
4287 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4290 case TGSI_OPCODE_UMAX
:
4291 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4294 case TGSI_OPCODE_UMIN
:
4295 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4298 case TGSI_OPCODE_UMOD
:
4299 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4302 case TGSI_OPCODE_UMUL
:
4303 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4306 case TGSI_OPCODE_IMUL_HI
:
4307 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4310 case TGSI_OPCODE_UMUL_HI
:
4311 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4314 case TGSI_OPCODE_USEQ
:
4315 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4318 case TGSI_OPCODE_USGE
:
4319 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4322 case TGSI_OPCODE_USHR
:
4323 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4326 case TGSI_OPCODE_USLT
:
4327 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4330 case TGSI_OPCODE_USNE
:
4331 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4334 case TGSI_OPCODE_SWITCH
:
4335 exec_switch(mach
, inst
);
4338 case TGSI_OPCODE_CASE
:
4339 exec_case(mach
, inst
);
4342 case TGSI_OPCODE_DEFAULT
:
4346 case TGSI_OPCODE_ENDSWITCH
:
4347 exec_endswitch(mach
);
4350 case TGSI_OPCODE_SAMPLE_I
:
4351 exec_txf(mach
, inst
);
4354 case TGSI_OPCODE_SAMPLE_I_MS
:
4358 case TGSI_OPCODE_SAMPLE
:
4359 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
4362 case TGSI_OPCODE_SAMPLE_B
:
4363 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
4366 case TGSI_OPCODE_SAMPLE_C
:
4367 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
4370 case TGSI_OPCODE_SAMPLE_C_LZ
:
4371 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
4374 case TGSI_OPCODE_SAMPLE_D
:
4375 exec_sample_d(mach
, inst
);
4378 case TGSI_OPCODE_SAMPLE_L
:
4379 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
4382 case TGSI_OPCODE_GATHER4
:
4386 case TGSI_OPCODE_SVIEWINFO
:
4387 exec_txq(mach
, inst
);
4390 case TGSI_OPCODE_SAMPLE_POS
:
4394 case TGSI_OPCODE_SAMPLE_INFO
:
4398 case TGSI_OPCODE_UARL
:
4399 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
4402 case TGSI_OPCODE_UCMP
:
4403 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
4406 case TGSI_OPCODE_IABS
:
4407 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4410 case TGSI_OPCODE_ISSG
:
4411 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
4414 case TGSI_OPCODE_TEX2
:
4415 /* simple texture lookup */
4416 /* src[0] = texcoord */
4417 /* src[1] = compare */
4418 /* src[2] = sampler unit */
4419 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
4421 case TGSI_OPCODE_TXB2
:
4422 /* simple texture lookup */
4423 /* src[0] = texcoord */
4425 /* src[2] = sampler unit */
4426 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
4428 case TGSI_OPCODE_TXL2
:
4429 /* simple texture lookup */
4430 /* src[0] = texcoord */
4432 /* src[2] = sampler unit */
4433 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
4442 * Run TGSI interpreter.
4443 * \return bitmask of "alive" quad components
4446 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
)
4450 uint default_mask
= 0xf;
4452 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
4453 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
4455 if( mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
4456 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
4457 mach
->Primitives
[0] = 0;
4458 /* GS runs on a single primitive for now */
4462 mach
->CondMask
= default_mask
;
4463 mach
->LoopMask
= default_mask
;
4464 mach
->ContMask
= default_mask
;
4465 mach
->FuncMask
= default_mask
;
4466 mach
->ExecMask
= default_mask
;
4468 mach
->Switch
.mask
= default_mask
;
4470 assert(mach
->CondStackTop
== 0);
4471 assert(mach
->LoopStackTop
== 0);
4472 assert(mach
->ContStackTop
== 0);
4473 assert(mach
->SwitchStackTop
== 0);
4474 assert(mach
->BreakStackTop
== 0);
4475 assert(mach
->CallStackTop
== 0);
4478 /* execute declarations (interpolants) */
4479 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
4480 exec_declaration( mach
, mach
->Declarations
+i
);
4485 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
4486 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
4489 memset(mach
->Temps
, 0, sizeof(temps
));
4490 memset(mach
->Outputs
, 0, sizeof(outputs
));
4491 memset(temps
, 0, sizeof(temps
));
4492 memset(outputs
, 0, sizeof(outputs
));
4495 /* execute instructions, until pc is set to -1 */
4501 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
4504 assert(pc
< (int) mach
->NumInstructions
);
4505 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
4508 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
4509 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
4512 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
4513 debug_printf("TEMP[%2u] = ", i
);
4514 for (j
= 0; j
< 4; j
++) {
4518 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4519 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
4520 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
4521 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
4522 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
4526 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
4527 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
4530 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
4531 debug_printf("OUT[%2u] = ", i
);
4532 for (j
= 0; j
< 4; j
++) {
4536 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4537 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
4538 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
4539 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
4540 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
4549 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4550 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
4552 * Scale back depth component.
4554 for (i
= 0; i
< 4; i
++)
4555 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
4559 /* Strictly speaking, these assertions aren't really needed but they
4560 * can potentially catch some bugs in the control flow code.
4562 assert(mach
->CondStackTop
== 0);
4563 assert(mach
->LoopStackTop
== 0);
4564 assert(mach
->ContStackTop
== 0);
4565 assert(mach
->SwitchStackTop
== 0);
4566 assert(mach
->BreakStackTop
== 0);
4567 assert(mach
->CallStackTop
== 0);
4569 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];