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softpipe: fix shadow 2d texture array sampling
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
381 {
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
386 }
387
388 static void
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
391 {
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
396 }
397
398 static void
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
402 {
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
407 }
408
409 static void
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_sfl(union tgsi_exec_channel *dst)
433 {
434 dst->f[0] = 0.0f;
435 dst->f[1] = 0.0f;
436 dst->f[2] = 0.0f;
437 dst->f[3] = 0.0f;
438 }
439
440 static void
441 micro_str(union tgsi_exec_channel *dst)
442 {
443 dst->f[0] = 1.0f;
444 dst->f[1] = 1.0f;
445 dst->f[2] = 1.0f;
446 dst->f[3] = 1.0f;
447 }
448
449 static void
450 micro_trunc(union tgsi_exec_channel *dst,
451 const union tgsi_exec_channel *src)
452 {
453 dst->f[0] = (float)(int)src->f[0];
454 dst->f[1] = (float)(int)src->f[1];
455 dst->f[2] = (float)(int)src->f[2];
456 dst->f[3] = (float)(int)src->f[3];
457 }
458
459
460 #define CHAN_X 0
461 #define CHAN_Y 1
462 #define CHAN_Z 2
463 #define CHAN_W 3
464
465 enum tgsi_exec_datatype {
466 TGSI_EXEC_DATA_FLOAT,
467 TGSI_EXEC_DATA_INT,
468 TGSI_EXEC_DATA_UINT
469 };
470
471 /*
472 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
473 */
474 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
475 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
476 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
477 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
478 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
479 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
480
481
482 /** The execution mask depends on the conditional mask and the loop mask */
483 #define UPDATE_EXEC_MASK(MACH) \
484 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
485
486
487 static const union tgsi_exec_channel ZeroVec =
488 { { 0.0, 0.0, 0.0, 0.0 } };
489
490 static const union tgsi_exec_channel OneVec = {
491 {1.0f, 1.0f, 1.0f, 1.0f}
492 };
493
494 static const union tgsi_exec_channel P128Vec = {
495 {128.0f, 128.0f, 128.0f, 128.0f}
496 };
497
498 static const union tgsi_exec_channel M128Vec = {
499 {-128.0f, -128.0f, -128.0f, -128.0f}
500 };
501
502
503 /**
504 * Assert that none of the float values in 'chan' are infinite or NaN.
505 * NaN and Inf may occur normally during program execution and should
506 * not lead to crashes, etc. But when debugging, it's helpful to catch
507 * them.
508 */
509 static INLINE void
510 check_inf_or_nan(const union tgsi_exec_channel *chan)
511 {
512 assert(!util_is_inf_or_nan((chan)->f[0]));
513 assert(!util_is_inf_or_nan((chan)->f[1]));
514 assert(!util_is_inf_or_nan((chan)->f[2]));
515 assert(!util_is_inf_or_nan((chan)->f[3]));
516 }
517
518
519 #ifdef DEBUG
520 static void
521 print_chan(const char *msg, const union tgsi_exec_channel *chan)
522 {
523 debug_printf("%s = {%f, %f, %f, %f}\n",
524 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
525 }
526 #endif
527
528
529 #ifdef DEBUG
530 static void
531 print_temp(const struct tgsi_exec_machine *mach, uint index)
532 {
533 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
534 int i;
535 debug_printf("Temp[%u] =\n", index);
536 for (i = 0; i < 4; i++) {
537 debug_printf(" %c: { %f, %f, %f, %f }\n",
538 "XYZW"[i],
539 tmp->xyzw[i].f[0],
540 tmp->xyzw[i].f[1],
541 tmp->xyzw[i].f[2],
542 tmp->xyzw[i].f[3]);
543 }
544 }
545 #endif
546
547
548 void
549 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
550 unsigned num_bufs,
551 const void **bufs,
552 const unsigned *buf_sizes)
553 {
554 unsigned i;
555
556 for (i = 0; i < num_bufs; i++) {
557 mach->Consts[i] = bufs[i];
558 mach->ConstsSize[i] = buf_sizes[i];
559 }
560 }
561
562
563 /**
564 * Check if there's a potential src/dst register data dependency when
565 * using SOA execution.
566 * Example:
567 * MOV T, T.yxwz;
568 * This would expand into:
569 * MOV t0, t1;
570 * MOV t1, t0;
571 * MOV t2, t3;
572 * MOV t3, t2;
573 * The second instruction will have the wrong value for t0 if executed as-is.
574 */
575 boolean
576 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
577 {
578 uint i, chan;
579
580 uint writemask = inst->Dst[0].Register.WriteMask;
581 if (writemask == TGSI_WRITEMASK_X ||
582 writemask == TGSI_WRITEMASK_Y ||
583 writemask == TGSI_WRITEMASK_Z ||
584 writemask == TGSI_WRITEMASK_W ||
585 writemask == TGSI_WRITEMASK_NONE) {
586 /* no chance of data dependency */
587 return FALSE;
588 }
589
590 /* loop over src regs */
591 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
592 if ((inst->Src[i].Register.File ==
593 inst->Dst[0].Register.File) &&
594 ((inst->Src[i].Register.Index ==
595 inst->Dst[0].Register.Index) ||
596 inst->Src[i].Register.Indirect ||
597 inst->Dst[0].Register.Indirect)) {
598 /* loop over dest channels */
599 uint channelsWritten = 0x0;
600 for (chan = 0; chan < NUM_CHANNELS; chan++) {
601 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
602 /* check if we're reading a channel that's been written */
603 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
604 if (channelsWritten & (1 << swizzle)) {
605 return TRUE;
606 }
607
608 channelsWritten |= (1 << chan);
609 }
610 }
611 }
612 }
613 return FALSE;
614 }
615
616
617 /**
618 * Initialize machine state by expanding tokens to full instructions,
619 * allocating temporary storage, setting up constants, etc.
620 * After this, we can call tgsi_exec_machine_run() many times.
621 */
622 void
623 tgsi_exec_machine_bind_shader(
624 struct tgsi_exec_machine *mach,
625 const struct tgsi_token *tokens,
626 uint numSamplers,
627 struct tgsi_sampler **samplers)
628 {
629 uint k;
630 struct tgsi_parse_context parse;
631 struct tgsi_full_instruction *instructions;
632 struct tgsi_full_declaration *declarations;
633 uint maxInstructions = 10, numInstructions = 0;
634 uint maxDeclarations = 10, numDeclarations = 0;
635
636 #if 0
637 tgsi_dump(tokens, 0);
638 #endif
639
640 util_init_math();
641
642 if (numSamplers) {
643 assert(samplers);
644 }
645
646 mach->Tokens = tokens;
647 mach->Samplers = samplers;
648
649 if (!tokens) {
650 /* unbind and free all */
651 if (mach->Declarations) {
652 FREE( mach->Declarations );
653 }
654 mach->Declarations = NULL;
655 mach->NumDeclarations = 0;
656
657 if (mach->Instructions) {
658 FREE( mach->Instructions );
659 }
660 mach->Instructions = NULL;
661 mach->NumInstructions = 0;
662
663 return;
664 }
665
666 k = tgsi_parse_init (&parse, mach->Tokens);
667 if (k != TGSI_PARSE_OK) {
668 debug_printf( "Problem parsing!\n" );
669 return;
670 }
671
672 mach->Processor = parse.FullHeader.Processor.Processor;
673 mach->ImmLimit = 0;
674
675 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
676 !mach->UsedGeometryShader) {
677 struct tgsi_exec_vector *inputs;
678 struct tgsi_exec_vector *outputs;
679
680 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
681 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
682 16);
683
684 if (!inputs)
685 return;
686
687 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
688 TGSI_MAX_TOTAL_VERTICES, 16);
689
690 if (!outputs) {
691 align_free(inputs);
692 return;
693 }
694
695 align_free(mach->Inputs);
696 align_free(mach->Outputs);
697
698 mach->Inputs = inputs;
699 mach->Outputs = outputs;
700 mach->UsedGeometryShader = TRUE;
701 }
702
703 declarations = (struct tgsi_full_declaration *)
704 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
705
706 if (!declarations) {
707 return;
708 }
709
710 instructions = (struct tgsi_full_instruction *)
711 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
712
713 if (!instructions) {
714 FREE( declarations );
715 return;
716 }
717
718 while( !tgsi_parse_end_of_tokens( &parse ) ) {
719 uint i;
720
721 tgsi_parse_token( &parse );
722 switch( parse.FullToken.Token.Type ) {
723 case TGSI_TOKEN_TYPE_DECLARATION:
724 /* save expanded declaration */
725 if (numDeclarations == maxDeclarations) {
726 declarations = REALLOC(declarations,
727 maxDeclarations
728 * sizeof(struct tgsi_full_declaration),
729 (maxDeclarations + 10)
730 * sizeof(struct tgsi_full_declaration));
731 maxDeclarations += 10;
732 }
733 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
734 unsigned reg;
735 for (reg = parse.FullToken.FullDeclaration.Range.First;
736 reg <= parse.FullToken.FullDeclaration.Range.Last;
737 ++reg) {
738 ++mach->NumOutputs;
739 }
740 }
741 if (parse.FullToken.FullDeclaration.Declaration.File ==
742 TGSI_FILE_IMMEDIATE_ARRAY) {
743 unsigned reg;
744 struct tgsi_full_declaration *decl =
745 &parse.FullToken.FullDeclaration;
746 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
747 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
748 for( i = 0; i < 4; i++ ) {
749 int idx = reg * 4 + i;
750 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
751 }
752 }
753 }
754 memcpy(declarations + numDeclarations,
755 &parse.FullToken.FullDeclaration,
756 sizeof(declarations[0]));
757 numDeclarations++;
758 break;
759
760 case TGSI_TOKEN_TYPE_IMMEDIATE:
761 {
762 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
763 assert( size <= 4 );
764 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
765
766 for( i = 0; i < size; i++ ) {
767 mach->Imms[mach->ImmLimit][i] =
768 parse.FullToken.FullImmediate.u[i].Float;
769 }
770 mach->ImmLimit += 1;
771 }
772 break;
773
774 case TGSI_TOKEN_TYPE_INSTRUCTION:
775
776 /* save expanded instruction */
777 if (numInstructions == maxInstructions) {
778 instructions = REALLOC(instructions,
779 maxInstructions
780 * sizeof(struct tgsi_full_instruction),
781 (maxInstructions + 10)
782 * sizeof(struct tgsi_full_instruction));
783 maxInstructions += 10;
784 }
785
786 memcpy(instructions + numInstructions,
787 &parse.FullToken.FullInstruction,
788 sizeof(instructions[0]));
789
790 numInstructions++;
791 break;
792
793 case TGSI_TOKEN_TYPE_PROPERTY:
794 break;
795
796 default:
797 assert( 0 );
798 }
799 }
800 tgsi_parse_free (&parse);
801
802 if (mach->Declarations) {
803 FREE( mach->Declarations );
804 }
805 mach->Declarations = declarations;
806 mach->NumDeclarations = numDeclarations;
807
808 if (mach->Instructions) {
809 FREE( mach->Instructions );
810 }
811 mach->Instructions = instructions;
812 mach->NumInstructions = numInstructions;
813 }
814
815
816 struct tgsi_exec_machine *
817 tgsi_exec_machine_create( void )
818 {
819 struct tgsi_exec_machine *mach;
820 uint i;
821
822 mach = align_malloc( sizeof *mach, 16 );
823 if (!mach)
824 goto fail;
825
826 memset(mach, 0, sizeof(*mach));
827
828 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
829 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
830 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
831
832 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
833 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
834 if (!mach->Inputs || !mach->Outputs)
835 goto fail;
836
837 /* Setup constants needed by the SSE2 executor. */
838 for( i = 0; i < 4; i++ ) {
839 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
840 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
841 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
842 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
843 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
844 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
845 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
846 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
847 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
848 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
849 }
850
851 #ifdef DEBUG
852 /* silence warnings */
853 (void) print_chan;
854 (void) print_temp;
855 #endif
856
857 return mach;
858
859 fail:
860 if (mach) {
861 align_free(mach->Inputs);
862 align_free(mach->Outputs);
863 align_free(mach);
864 }
865 return NULL;
866 }
867
868
869 void
870 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
871 {
872 if (mach) {
873 if (mach->Instructions)
874 FREE(mach->Instructions);
875 if (mach->Declarations)
876 FREE(mach->Declarations);
877
878 align_free(mach->Inputs);
879 align_free(mach->Outputs);
880
881 align_free(mach);
882 }
883 }
884
885 static void
886 micro_add(union tgsi_exec_channel *dst,
887 const union tgsi_exec_channel *src0,
888 const union tgsi_exec_channel *src1)
889 {
890 dst->f[0] = src0->f[0] + src1->f[0];
891 dst->f[1] = src0->f[1] + src1->f[1];
892 dst->f[2] = src0->f[2] + src1->f[2];
893 dst->f[3] = src0->f[3] + src1->f[3];
894 }
895
896 static void
897 micro_div(
898 union tgsi_exec_channel *dst,
899 const union tgsi_exec_channel *src0,
900 const union tgsi_exec_channel *src1 )
901 {
902 if (src1->f[0] != 0) {
903 dst->f[0] = src0->f[0] / src1->f[0];
904 }
905 if (src1->f[1] != 0) {
906 dst->f[1] = src0->f[1] / src1->f[1];
907 }
908 if (src1->f[2] != 0) {
909 dst->f[2] = src0->f[2] / src1->f[2];
910 }
911 if (src1->f[3] != 0) {
912 dst->f[3] = src0->f[3] / src1->f[3];
913 }
914 }
915
916 static void
917 micro_rcc(union tgsi_exec_channel *dst,
918 const union tgsi_exec_channel *src)
919 {
920 uint i;
921
922 for (i = 0; i < 4; i++) {
923 float recip = 1.0f / src->f[i];
924
925 if (recip > 0.0f) {
926 if (recip > 1.884467e+019f) {
927 dst->f[i] = 1.884467e+019f;
928 }
929 else if (recip < 5.42101e-020f) {
930 dst->f[i] = 5.42101e-020f;
931 }
932 else {
933 dst->f[i] = recip;
934 }
935 }
936 else {
937 if (recip < -1.884467e+019f) {
938 dst->f[i] = -1.884467e+019f;
939 }
940 else if (recip > -5.42101e-020f) {
941 dst->f[i] = -5.42101e-020f;
942 }
943 else {
944 dst->f[i] = recip;
945 }
946 }
947 }
948 }
949
950 static void
951 micro_lt(
952 union tgsi_exec_channel *dst,
953 const union tgsi_exec_channel *src0,
954 const union tgsi_exec_channel *src1,
955 const union tgsi_exec_channel *src2,
956 const union tgsi_exec_channel *src3 )
957 {
958 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
959 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
960 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
961 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
962 }
963
964 static void
965 micro_max(union tgsi_exec_channel *dst,
966 const union tgsi_exec_channel *src0,
967 const union tgsi_exec_channel *src1)
968 {
969 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
970 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
971 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
972 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
973 }
974
975 static void
976 micro_min(union tgsi_exec_channel *dst,
977 const union tgsi_exec_channel *src0,
978 const union tgsi_exec_channel *src1)
979 {
980 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
981 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
982 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
983 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
984 }
985
986 static void
987 micro_mul(union tgsi_exec_channel *dst,
988 const union tgsi_exec_channel *src0,
989 const union tgsi_exec_channel *src1)
990 {
991 dst->f[0] = src0->f[0] * src1->f[0];
992 dst->f[1] = src0->f[1] * src1->f[1];
993 dst->f[2] = src0->f[2] * src1->f[2];
994 dst->f[3] = src0->f[3] * src1->f[3];
995 }
996
997 static void
998 micro_neg(
999 union tgsi_exec_channel *dst,
1000 const union tgsi_exec_channel *src )
1001 {
1002 dst->f[0] = -src->f[0];
1003 dst->f[1] = -src->f[1];
1004 dst->f[2] = -src->f[2];
1005 dst->f[3] = -src->f[3];
1006 }
1007
1008 static void
1009 micro_pow(
1010 union tgsi_exec_channel *dst,
1011 const union tgsi_exec_channel *src0,
1012 const union tgsi_exec_channel *src1 )
1013 {
1014 #if FAST_MATH
1015 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1016 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1017 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1018 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1019 #else
1020 dst->f[0] = powf( src0->f[0], src1->f[0] );
1021 dst->f[1] = powf( src0->f[1], src1->f[1] );
1022 dst->f[2] = powf( src0->f[2], src1->f[2] );
1023 dst->f[3] = powf( src0->f[3], src1->f[3] );
1024 #endif
1025 }
1026
1027 static void
1028 micro_sub(union tgsi_exec_channel *dst,
1029 const union tgsi_exec_channel *src0,
1030 const union tgsi_exec_channel *src1)
1031 {
1032 dst->f[0] = src0->f[0] - src1->f[0];
1033 dst->f[1] = src0->f[1] - src1->f[1];
1034 dst->f[2] = src0->f[2] - src1->f[2];
1035 dst->f[3] = src0->f[3] - src1->f[3];
1036 }
1037
1038 static void
1039 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1040 const uint file,
1041 const uint swizzle,
1042 const union tgsi_exec_channel *index,
1043 const union tgsi_exec_channel *index2D,
1044 union tgsi_exec_channel *chan)
1045 {
1046 uint i;
1047
1048 assert(swizzle < 4);
1049
1050 switch (file) {
1051 case TGSI_FILE_CONSTANT:
1052 for (i = 0; i < QUAD_SIZE; i++) {
1053 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1054 assert(mach->Consts[index2D->i[i]]);
1055
1056 if (index->i[i] < 0) {
1057 chan->u[i] = 0;
1058 } else {
1059 /* NOTE: copying the const value as a uint instead of float */
1060 const uint constbuf = index2D->i[i];
1061 const uint *buf = (const uint *)mach->Consts[constbuf];
1062 const int pos = index->i[i] * 4 + swizzle;
1063 /* const buffer bounds check */
1064 if (pos < 0 || pos >= mach->ConstsSize[constbuf]) {
1065 if (0) {
1066 /* Debug: print warning */
1067 static int count = 0;
1068 if (count++ < 100)
1069 debug_printf("TGSI Exec: const buffer index %d"
1070 " out of bounds\n", pos);
1071 }
1072 chan->u[i] = 0;
1073 }
1074 else
1075 chan->u[i] = buf[pos];
1076 }
1077 }
1078 break;
1079
1080 case TGSI_FILE_INPUT:
1081 for (i = 0; i < QUAD_SIZE; i++) {
1082 /*
1083 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1084 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1085 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1086 index2D->i[i], index->i[i]);
1087 }*/
1088 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1089 assert(pos >= 0);
1090 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1091 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1092 }
1093 break;
1094
1095 case TGSI_FILE_SYSTEM_VALUE:
1096 /* XXX no swizzling at this point. Will be needed if we put
1097 * gl_FragCoord, for example, in a sys value register.
1098 */
1099 for (i = 0; i < QUAD_SIZE; i++) {
1100 chan->f[i] = mach->SystemValue[index->i[i]][0];
1101 }
1102 break;
1103
1104 case TGSI_FILE_TEMPORARY:
1105 for (i = 0; i < QUAD_SIZE; i++) {
1106 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1107 assert(index2D->i[i] == 0);
1108
1109 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1110 }
1111 break;
1112
1113 case TGSI_FILE_TEMPORARY_ARRAY:
1114 for (i = 0; i < QUAD_SIZE; i++) {
1115 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1116 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1117
1118 chan->u[i] =
1119 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1120 }
1121 break;
1122
1123 case TGSI_FILE_IMMEDIATE:
1124 for (i = 0; i < QUAD_SIZE; i++) {
1125 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1126 assert(index2D->i[i] == 0);
1127
1128 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1129 }
1130 break;
1131
1132 case TGSI_FILE_IMMEDIATE_ARRAY:
1133 for (i = 0; i < QUAD_SIZE; i++) {
1134 assert(index2D->i[i] == 0);
1135
1136 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1137 }
1138 break;
1139
1140 case TGSI_FILE_ADDRESS:
1141 for (i = 0; i < QUAD_SIZE; i++) {
1142 assert(index->i[i] >= 0);
1143 assert(index2D->i[i] == 0);
1144
1145 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1146 }
1147 break;
1148
1149 case TGSI_FILE_PREDICATE:
1150 for (i = 0; i < QUAD_SIZE; i++) {
1151 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1152 assert(index2D->i[i] == 0);
1153
1154 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1155 }
1156 break;
1157
1158 case TGSI_FILE_OUTPUT:
1159 /* vertex/fragment output vars can be read too */
1160 for (i = 0; i < QUAD_SIZE; i++) {
1161 assert(index->i[i] >= 0);
1162 assert(index2D->i[i] == 0);
1163
1164 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1165 }
1166 break;
1167
1168 default:
1169 assert(0);
1170 for (i = 0; i < QUAD_SIZE; i++) {
1171 chan->u[i] = 0;
1172 }
1173 }
1174 }
1175
1176 static void
1177 fetch_source(const struct tgsi_exec_machine *mach,
1178 union tgsi_exec_channel *chan,
1179 const struct tgsi_full_src_register *reg,
1180 const uint chan_index,
1181 enum tgsi_exec_datatype src_datatype)
1182 {
1183 union tgsi_exec_channel index;
1184 union tgsi_exec_channel index2D;
1185 uint swizzle;
1186
1187 /* We start with a direct index into a register file.
1188 *
1189 * file[1],
1190 * where:
1191 * file = Register.File
1192 * [1] = Register.Index
1193 */
1194 index.i[0] =
1195 index.i[1] =
1196 index.i[2] =
1197 index.i[3] = reg->Register.Index;
1198
1199 /* There is an extra source register that indirectly subscripts
1200 * a register file. The direct index now becomes an offset
1201 * that is being added to the indirect register.
1202 *
1203 * file[ind[2].x+1],
1204 * where:
1205 * ind = Indirect.File
1206 * [2] = Indirect.Index
1207 * .x = Indirect.SwizzleX
1208 */
1209 if (reg->Register.Indirect) {
1210 union tgsi_exec_channel index2;
1211 union tgsi_exec_channel indir_index;
1212 const uint execmask = mach->ExecMask;
1213 uint i;
1214
1215 /* which address register (always zero now) */
1216 index2.i[0] =
1217 index2.i[1] =
1218 index2.i[2] =
1219 index2.i[3] = reg->Indirect.Index;
1220 assert(reg->Indirect.File == TGSI_FILE_ADDRESS);
1221 /* get current value of address register[swizzle] */
1222 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1223 fetch_src_file_channel(mach,
1224 reg->Indirect.File,
1225 swizzle,
1226 &index2,
1227 &ZeroVec,
1228 &indir_index);
1229
1230 /* add value of address register to the offset */
1231 index.i[0] += indir_index.i[0];
1232 index.i[1] += indir_index.i[1];
1233 index.i[2] += indir_index.i[2];
1234 index.i[3] += indir_index.i[3];
1235
1236 /* for disabled execution channels, zero-out the index to
1237 * avoid using a potential garbage value.
1238 */
1239 for (i = 0; i < QUAD_SIZE; i++) {
1240 if ((execmask & (1 << i)) == 0)
1241 index.i[i] = 0;
1242 }
1243 }
1244
1245 /* There is an extra source register that is a second
1246 * subscript to a register file. Effectively it means that
1247 * the register file is actually a 2D array of registers.
1248 *
1249 * file[3][1],
1250 * where:
1251 * [3] = Dimension.Index
1252 */
1253 if (reg->Register.Dimension) {
1254 index2D.i[0] =
1255 index2D.i[1] =
1256 index2D.i[2] =
1257 index2D.i[3] = reg->Dimension.Index;
1258
1259 /* Again, the second subscript index can be addressed indirectly
1260 * identically to the first one.
1261 * Nothing stops us from indirectly addressing the indirect register,
1262 * but there is no need for that, so we won't exercise it.
1263 *
1264 * file[ind[4].y+3][1],
1265 * where:
1266 * ind = DimIndirect.File
1267 * [4] = DimIndirect.Index
1268 * .y = DimIndirect.SwizzleX
1269 */
1270 if (reg->Dimension.Indirect) {
1271 union tgsi_exec_channel index2;
1272 union tgsi_exec_channel indir_index;
1273 const uint execmask = mach->ExecMask;
1274 uint i;
1275
1276 index2.i[0] =
1277 index2.i[1] =
1278 index2.i[2] =
1279 index2.i[3] = reg->DimIndirect.Index;
1280
1281 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1282 fetch_src_file_channel(mach,
1283 reg->DimIndirect.File,
1284 swizzle,
1285 &index2,
1286 &ZeroVec,
1287 &indir_index);
1288
1289 index2D.i[0] += indir_index.i[0];
1290 index2D.i[1] += indir_index.i[1];
1291 index2D.i[2] += indir_index.i[2];
1292 index2D.i[3] += indir_index.i[3];
1293
1294 /* for disabled execution channels, zero-out the index to
1295 * avoid using a potential garbage value.
1296 */
1297 for (i = 0; i < QUAD_SIZE; i++) {
1298 if ((execmask & (1 << i)) == 0) {
1299 index2D.i[i] = 0;
1300 }
1301 }
1302 }
1303
1304 /* If by any chance there was a need for a 3D array of register
1305 * files, we would have to check whether Dimension is followed
1306 * by a dimension register and continue the saga.
1307 */
1308 } else {
1309 index2D.i[0] =
1310 index2D.i[1] =
1311 index2D.i[2] =
1312 index2D.i[3] = 0;
1313 }
1314
1315 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1316 fetch_src_file_channel(mach,
1317 reg->Register.File,
1318 swizzle,
1319 &index,
1320 &index2D,
1321 chan);
1322
1323 if (reg->Register.Absolute) {
1324 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1325 micro_abs(chan, chan);
1326 } else {
1327 micro_iabs(chan, chan);
1328 }
1329 }
1330
1331 if (reg->Register.Negate) {
1332 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1333 micro_neg(chan, chan);
1334 } else {
1335 micro_ineg(chan, chan);
1336 }
1337 }
1338 }
1339
1340 static void
1341 store_dest(struct tgsi_exec_machine *mach,
1342 const union tgsi_exec_channel *chan,
1343 const struct tgsi_full_dst_register *reg,
1344 const struct tgsi_full_instruction *inst,
1345 uint chan_index,
1346 enum tgsi_exec_datatype dst_datatype)
1347 {
1348 uint i;
1349 union tgsi_exec_channel null;
1350 union tgsi_exec_channel *dst;
1351 union tgsi_exec_channel index2D;
1352 uint execmask = mach->ExecMask;
1353 int offset = 0; /* indirection offset */
1354 int index;
1355
1356 /* for debugging */
1357 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1358 check_inf_or_nan(chan);
1359 }
1360
1361 /* There is an extra source register that indirectly subscripts
1362 * a register file. The direct index now becomes an offset
1363 * that is being added to the indirect register.
1364 *
1365 * file[ind[2].x+1],
1366 * where:
1367 * ind = Indirect.File
1368 * [2] = Indirect.Index
1369 * .x = Indirect.SwizzleX
1370 */
1371 if (reg->Register.Indirect) {
1372 union tgsi_exec_channel index;
1373 union tgsi_exec_channel indir_index;
1374 uint swizzle;
1375
1376 /* which address register (always zero for now) */
1377 index.i[0] =
1378 index.i[1] =
1379 index.i[2] =
1380 index.i[3] = reg->Indirect.Index;
1381
1382 /* get current value of address register[swizzle] */
1383 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1384
1385 /* fetch values from the address/indirection register */
1386 fetch_src_file_channel(mach,
1387 reg->Indirect.File,
1388 swizzle,
1389 &index,
1390 &ZeroVec,
1391 &indir_index);
1392
1393 /* save indirection offset */
1394 offset = indir_index.i[0];
1395 }
1396
1397 /* There is an extra source register that is a second
1398 * subscript to a register file. Effectively it means that
1399 * the register file is actually a 2D array of registers.
1400 *
1401 * file[3][1],
1402 * where:
1403 * [3] = Dimension.Index
1404 */
1405 if (reg->Register.Dimension) {
1406 index2D.i[0] =
1407 index2D.i[1] =
1408 index2D.i[2] =
1409 index2D.i[3] = reg->Dimension.Index;
1410
1411 /* Again, the second subscript index can be addressed indirectly
1412 * identically to the first one.
1413 * Nothing stops us from indirectly addressing the indirect register,
1414 * but there is no need for that, so we won't exercise it.
1415 *
1416 * file[ind[4].y+3][1],
1417 * where:
1418 * ind = DimIndirect.File
1419 * [4] = DimIndirect.Index
1420 * .y = DimIndirect.SwizzleX
1421 */
1422 if (reg->Dimension.Indirect) {
1423 union tgsi_exec_channel index2;
1424 union tgsi_exec_channel indir_index;
1425 const uint execmask = mach->ExecMask;
1426 unsigned swizzle;
1427 uint i;
1428
1429 index2.i[0] =
1430 index2.i[1] =
1431 index2.i[2] =
1432 index2.i[3] = reg->DimIndirect.Index;
1433
1434 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1435 fetch_src_file_channel(mach,
1436 reg->DimIndirect.File,
1437 swizzle,
1438 &index2,
1439 &ZeroVec,
1440 &indir_index);
1441
1442 index2D.i[0] += indir_index.i[0];
1443 index2D.i[1] += indir_index.i[1];
1444 index2D.i[2] += indir_index.i[2];
1445 index2D.i[3] += indir_index.i[3];
1446
1447 /* for disabled execution channels, zero-out the index to
1448 * avoid using a potential garbage value.
1449 */
1450 for (i = 0; i < QUAD_SIZE; i++) {
1451 if ((execmask & (1 << i)) == 0) {
1452 index2D.i[i] = 0;
1453 }
1454 }
1455 }
1456
1457 /* If by any chance there was a need for a 3D array of register
1458 * files, we would have to check whether Dimension is followed
1459 * by a dimension register and continue the saga.
1460 */
1461 } else {
1462 index2D.i[0] =
1463 index2D.i[1] =
1464 index2D.i[2] =
1465 index2D.i[3] = 0;
1466 }
1467
1468 switch (reg->Register.File) {
1469 case TGSI_FILE_NULL:
1470 dst = &null;
1471 break;
1472
1473 case TGSI_FILE_OUTPUT:
1474 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1475 + reg->Register.Index;
1476 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1477 #if 0
1478 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1479 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1480 for (i = 0; i < QUAD_SIZE; i++)
1481 if (execmask & (1 << i))
1482 fprintf(stderr, "%f, ", chan->f[i]);
1483 fprintf(stderr, ")\n");
1484 }
1485 #endif
1486 break;
1487
1488 case TGSI_FILE_TEMPORARY:
1489 index = reg->Register.Index;
1490 assert( index < TGSI_EXEC_NUM_TEMPS );
1491 dst = &mach->Temps[offset + index].xyzw[chan_index];
1492 break;
1493
1494 case TGSI_FILE_TEMPORARY_ARRAY:
1495 index = reg->Register.Index;
1496 assert( index < TGSI_EXEC_NUM_TEMPS );
1497 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1498 /* XXX we use index2D.i[0] here but somehow we might
1499 * end up with someone trying to store indirectly in
1500 * different buffers */
1501 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1502 break;
1503
1504 case TGSI_FILE_ADDRESS:
1505 index = reg->Register.Index;
1506 dst = &mach->Addrs[index].xyzw[chan_index];
1507 break;
1508
1509 case TGSI_FILE_PREDICATE:
1510 index = reg->Register.Index;
1511 assert(index < TGSI_EXEC_NUM_PREDS);
1512 dst = &mach->Predicates[index].xyzw[chan_index];
1513 break;
1514
1515 default:
1516 assert( 0 );
1517 return;
1518 }
1519
1520 if (inst->Instruction.Predicate) {
1521 uint swizzle;
1522 union tgsi_exec_channel *pred;
1523
1524 switch (chan_index) {
1525 case CHAN_X:
1526 swizzle = inst->Predicate.SwizzleX;
1527 break;
1528 case CHAN_Y:
1529 swizzle = inst->Predicate.SwizzleY;
1530 break;
1531 case CHAN_Z:
1532 swizzle = inst->Predicate.SwizzleZ;
1533 break;
1534 case CHAN_W:
1535 swizzle = inst->Predicate.SwizzleW;
1536 break;
1537 default:
1538 assert(0);
1539 return;
1540 }
1541
1542 assert(inst->Predicate.Index == 0);
1543
1544 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1545
1546 if (inst->Predicate.Negate) {
1547 for (i = 0; i < QUAD_SIZE; i++) {
1548 if (pred->u[i]) {
1549 execmask &= ~(1 << i);
1550 }
1551 }
1552 } else {
1553 for (i = 0; i < QUAD_SIZE; i++) {
1554 if (!pred->u[i]) {
1555 execmask &= ~(1 << i);
1556 }
1557 }
1558 }
1559 }
1560
1561 switch (inst->Instruction.Saturate) {
1562 case TGSI_SAT_NONE:
1563 for (i = 0; i < QUAD_SIZE; i++)
1564 if (execmask & (1 << i))
1565 dst->i[i] = chan->i[i];
1566 break;
1567
1568 case TGSI_SAT_ZERO_ONE:
1569 for (i = 0; i < QUAD_SIZE; i++)
1570 if (execmask & (1 << i)) {
1571 if (chan->f[i] < 0.0f)
1572 dst->f[i] = 0.0f;
1573 else if (chan->f[i] > 1.0f)
1574 dst->f[i] = 1.0f;
1575 else
1576 dst->i[i] = chan->i[i];
1577 }
1578 break;
1579
1580 case TGSI_SAT_MINUS_PLUS_ONE:
1581 for (i = 0; i < QUAD_SIZE; i++)
1582 if (execmask & (1 << i)) {
1583 if (chan->f[i] < -1.0f)
1584 dst->f[i] = -1.0f;
1585 else if (chan->f[i] > 1.0f)
1586 dst->f[i] = 1.0f;
1587 else
1588 dst->i[i] = chan->i[i];
1589 }
1590 break;
1591
1592 default:
1593 assert( 0 );
1594 }
1595 }
1596
1597 #define FETCH(VAL,INDEX,CHAN)\
1598 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1599
1600 #define IFETCH(VAL,INDEX,CHAN)\
1601 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1602
1603
1604 /**
1605 * Execute ARB-style KIL which is predicated by a src register.
1606 * Kill fragment if any of the four values is less than zero.
1607 */
1608 static void
1609 exec_kil(struct tgsi_exec_machine *mach,
1610 const struct tgsi_full_instruction *inst)
1611 {
1612 uint uniquemask;
1613 uint chan_index;
1614 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1615 union tgsi_exec_channel r[1];
1616
1617 /* This mask stores component bits that were already tested. */
1618 uniquemask = 0;
1619
1620 for (chan_index = 0; chan_index < 4; chan_index++)
1621 {
1622 uint swizzle;
1623 uint i;
1624
1625 /* unswizzle channel */
1626 swizzle = tgsi_util_get_full_src_register_swizzle (
1627 &inst->Src[0],
1628 chan_index);
1629
1630 /* check if the component has not been already tested */
1631 if (uniquemask & (1 << swizzle))
1632 continue;
1633 uniquemask |= 1 << swizzle;
1634
1635 FETCH(&r[0], 0, chan_index);
1636 for (i = 0; i < 4; i++)
1637 if (r[0].f[i] < 0.0f)
1638 kilmask |= 1 << i;
1639 }
1640
1641 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1642 }
1643
1644 /**
1645 * Execute NVIDIA-style KIL which is predicated by a condition code.
1646 * Kill fragment if the condition code is TRUE.
1647 */
1648 static void
1649 exec_kilp(struct tgsi_exec_machine *mach,
1650 const struct tgsi_full_instruction *inst)
1651 {
1652 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1653
1654 /* "unconditional" kil */
1655 kilmask = mach->ExecMask;
1656 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1657 }
1658
1659 static void
1660 emit_vertex(struct tgsi_exec_machine *mach)
1661 {
1662 /* FIXME: check for exec mask correctly
1663 unsigned i;
1664 for (i = 0; i < QUAD_SIZE; ++i) {
1665 if ((mach->ExecMask & (1 << i)))
1666 */
1667 if (mach->ExecMask) {
1668 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1669 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1670 }
1671 }
1672
1673 static void
1674 emit_primitive(struct tgsi_exec_machine *mach)
1675 {
1676 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1677 /* FIXME: check for exec mask correctly
1678 unsigned i;
1679 for (i = 0; i < QUAD_SIZE; ++i) {
1680 if ((mach->ExecMask & (1 << i)))
1681 */
1682 if (mach->ExecMask) {
1683 ++(*prim_count);
1684 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1685 mach->Primitives[*prim_count] = 0;
1686 }
1687 }
1688
1689 static void
1690 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1691 {
1692 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1693 int emitted_verts =
1694 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1695 if (emitted_verts) {
1696 emit_primitive(mach);
1697 }
1698 }
1699 }
1700
1701
1702 /*
1703 * Fetch four texture samples using STR texture coordinates.
1704 */
1705 static void
1706 fetch_texel( struct tgsi_sampler *sampler,
1707 const union tgsi_exec_channel *s,
1708 const union tgsi_exec_channel *t,
1709 const union tgsi_exec_channel *p,
1710 const union tgsi_exec_channel *c0,
1711 enum tgsi_sampler_control control,
1712 union tgsi_exec_channel *r,
1713 union tgsi_exec_channel *g,
1714 union tgsi_exec_channel *b,
1715 union tgsi_exec_channel *a )
1716 {
1717 uint j;
1718 float rgba[NUM_CHANNELS][QUAD_SIZE];
1719
1720 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1721
1722 for (j = 0; j < 4; j++) {
1723 r->f[j] = rgba[0][j];
1724 g->f[j] = rgba[1][j];
1725 b->f[j] = rgba[2][j];
1726 a->f[j] = rgba[3][j];
1727 }
1728 }
1729
1730
1731 #define TEX_MODIFIER_NONE 0
1732 #define TEX_MODIFIER_PROJECTED 1
1733 #define TEX_MODIFIER_LOD_BIAS 2
1734 #define TEX_MODIFIER_EXPLICIT_LOD 3
1735
1736
1737 static void
1738 exec_tex(struct tgsi_exec_machine *mach,
1739 const struct tgsi_full_instruction *inst,
1740 uint modifier)
1741 {
1742 const uint unit = inst->Src[1].Register.Index;
1743 union tgsi_exec_channel r[4];
1744 const union tgsi_exec_channel *lod = &ZeroVec;
1745 enum tgsi_sampler_control control;
1746 uint chan;
1747
1748 if (modifier != TEX_MODIFIER_NONE) {
1749 FETCH(&r[3], 0, CHAN_W);
1750 if (modifier != TEX_MODIFIER_PROJECTED) {
1751 lod = &r[3];
1752 }
1753 }
1754
1755 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1756 control = tgsi_sampler_lod_explicit;
1757 } else {
1758 control = tgsi_sampler_lod_bias;
1759 }
1760
1761 switch (inst->Texture.Texture) {
1762 case TGSI_TEXTURE_1D:
1763 case TGSI_TEXTURE_SHADOW1D:
1764 FETCH(&r[0], 0, CHAN_X);
1765
1766 if (modifier == TEX_MODIFIER_PROJECTED) {
1767 micro_div(&r[0], &r[0], &r[3]);
1768 }
1769
1770 fetch_texel(mach->Samplers[unit],
1771 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1772 control,
1773 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1774 break;
1775
1776 case TGSI_TEXTURE_2D:
1777 case TGSI_TEXTURE_RECT:
1778 case TGSI_TEXTURE_SHADOW2D:
1779 case TGSI_TEXTURE_SHADOWRECT:
1780 FETCH(&r[0], 0, CHAN_X);
1781 FETCH(&r[1], 0, CHAN_Y);
1782 FETCH(&r[2], 0, CHAN_Z);
1783
1784 if (modifier == TEX_MODIFIER_PROJECTED) {
1785 micro_div(&r[0], &r[0], &r[3]);
1786 micro_div(&r[1], &r[1], &r[3]);
1787 micro_div(&r[2], &r[2], &r[3]);
1788 }
1789
1790 fetch_texel(mach->Samplers[unit],
1791 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1792 control,
1793 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1794 break;
1795
1796 case TGSI_TEXTURE_1D_ARRAY:
1797 FETCH(&r[0], 0, CHAN_X);
1798 FETCH(&r[1], 0, CHAN_Y);
1799
1800 if (modifier == TEX_MODIFIER_PROJECTED) {
1801 micro_div(&r[0], &r[0], &r[3]);
1802 }
1803
1804 fetch_texel(mach->Samplers[unit],
1805 &r[0], &r[1], &ZeroVec, lod, /* S, T, P, LOD */
1806 control,
1807 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1808 break;
1809 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1810 FETCH(&r[0], 0, CHAN_X);
1811 FETCH(&r[1], 0, CHAN_Y);
1812 FETCH(&r[2], 0, CHAN_Z);
1813
1814 if (modifier == TEX_MODIFIER_PROJECTED) {
1815 micro_div(&r[0], &r[0], &r[3]);
1816 }
1817
1818 fetch_texel(mach->Samplers[unit],
1819 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1820 control,
1821 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1822 break;
1823
1824 case TGSI_TEXTURE_2D_ARRAY:
1825 FETCH(&r[0], 0, CHAN_X);
1826 FETCH(&r[1], 0, CHAN_Y);
1827 FETCH(&r[2], 0, CHAN_Z);
1828
1829 if (modifier == TEX_MODIFIER_PROJECTED) {
1830 micro_div(&r[0], &r[0], &r[3]);
1831 micro_div(&r[1], &r[1], &r[3]);
1832 }
1833
1834 fetch_texel(mach->Samplers[unit],
1835 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1836 control,
1837 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1838 break;
1839 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1840 FETCH(&r[0], 0, CHAN_X);
1841 FETCH(&r[1], 0, CHAN_Y);
1842 FETCH(&r[2], 0, CHAN_Z);
1843 FETCH(&r[3], 0, CHAN_W);
1844
1845 fetch_texel(mach->Samplers[unit],
1846 &r[0], &r[1], &r[2], &r[3], /* S, T, P, LOD */
1847 control,
1848 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1849 break;
1850 case TGSI_TEXTURE_3D:
1851 case TGSI_TEXTURE_CUBE:
1852 FETCH(&r[0], 0, CHAN_X);
1853 FETCH(&r[1], 0, CHAN_Y);
1854 FETCH(&r[2], 0, CHAN_Z);
1855
1856 if (modifier == TEX_MODIFIER_PROJECTED) {
1857 micro_div(&r[0], &r[0], &r[3]);
1858 micro_div(&r[1], &r[1], &r[3]);
1859 micro_div(&r[2], &r[2], &r[3]);
1860 }
1861
1862 fetch_texel(mach->Samplers[unit],
1863 &r[0], &r[1], &r[2], lod,
1864 control,
1865 &r[0], &r[1], &r[2], &r[3]);
1866 break;
1867
1868 default:
1869 assert(0);
1870 }
1871
1872 #if 0
1873 debug_printf("fetch r: %g %g %g %g\n",
1874 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1875 debug_printf("fetch g: %g %g %g %g\n",
1876 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1877 debug_printf("fetch b: %g %g %g %g\n",
1878 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1879 debug_printf("fetch a: %g %g %g %g\n",
1880 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1881 #endif
1882
1883 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1884 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1885 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1886 }
1887 }
1888 }
1889
1890 static void
1891 exec_txd(struct tgsi_exec_machine *mach,
1892 const struct tgsi_full_instruction *inst)
1893 {
1894 const uint unit = inst->Src[3].Register.Index;
1895 union tgsi_exec_channel r[4];
1896 uint chan;
1897
1898 /*
1899 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1900 */
1901
1902 switch (inst->Texture.Texture) {
1903 case TGSI_TEXTURE_1D:
1904 case TGSI_TEXTURE_SHADOW1D:
1905
1906 FETCH(&r[0], 0, CHAN_X);
1907
1908 fetch_texel(mach->Samplers[unit],
1909 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1910 tgsi_sampler_lod_bias,
1911 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1912 break;
1913
1914 case TGSI_TEXTURE_1D_ARRAY:
1915 case TGSI_TEXTURE_2D:
1916 case TGSI_TEXTURE_RECT:
1917 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1918 case TGSI_TEXTURE_SHADOW2D:
1919 case TGSI_TEXTURE_SHADOWRECT:
1920
1921 FETCH(&r[0], 0, CHAN_X);
1922 FETCH(&r[1], 0, CHAN_Y);
1923 FETCH(&r[2], 0, CHAN_Z);
1924
1925 fetch_texel(mach->Samplers[unit],
1926 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1927 tgsi_sampler_lod_bias,
1928 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1929 break;
1930
1931 case TGSI_TEXTURE_2D_ARRAY:
1932 case TGSI_TEXTURE_3D:
1933 case TGSI_TEXTURE_CUBE:
1934
1935 FETCH(&r[0], 0, CHAN_X);
1936 FETCH(&r[1], 0, CHAN_Y);
1937 FETCH(&r[2], 0, CHAN_Z);
1938
1939 fetch_texel(mach->Samplers[unit],
1940 &r[0], &r[1], &r[2], &ZeroVec,
1941 tgsi_sampler_lod_bias,
1942 &r[0], &r[1], &r[2], &r[3]);
1943 break;
1944
1945 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1946
1947 FETCH(&r[0], 0, CHAN_X);
1948 FETCH(&r[1], 0, CHAN_Y);
1949 FETCH(&r[2], 0, CHAN_Z);
1950 FETCH(&r[3], 0, CHAN_W);
1951
1952 fetch_texel(mach->Samplers[unit],
1953 &r[0], &r[1], &r[2], &r[3],
1954 tgsi_sampler_lod_bias,
1955 &r[0], &r[1], &r[2], &r[3]);
1956 break;
1957
1958 default:
1959 assert(0);
1960 }
1961
1962 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1963 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1964 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1965 }
1966 }
1967 }
1968
1969
1970 static void
1971 exec_txf(struct tgsi_exec_machine *mach,
1972 const struct tgsi_full_instruction *inst)
1973 {
1974 struct tgsi_sampler *sampler;
1975 const uint unit = inst->Src[2].Register.Index;
1976 union tgsi_exec_channel r[4];
1977 union tgsi_exec_channel offset[3];
1978 uint chan;
1979 float rgba[NUM_CHANNELS][QUAD_SIZE];
1980 int j;
1981 int8_t offsets[3];
1982
1983 if (inst->Texture.NumOffsets == 1) {
1984 union tgsi_exec_channel index;
1985 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1986 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1987 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1988 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1989 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1990 fetch_src_file_channel(mach, inst->TexOffsets[0].File,
1991 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1992 offsets[0] = offset[0].i[0];
1993 offsets[1] = offset[1].i[0];
1994 offsets[2] = offset[2].i[0];
1995 } else
1996 offsets[0] = offsets[1] = offsets[2] = 0;
1997
1998 IFETCH(&r[3], 0, CHAN_W);
1999
2000 switch(inst->Texture.Texture) {
2001 case TGSI_TEXTURE_3D:
2002 case TGSI_TEXTURE_2D_ARRAY:
2003 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2004 IFETCH(&r[2], 0, CHAN_Z);
2005 /* fallthrough */
2006 case TGSI_TEXTURE_2D:
2007 case TGSI_TEXTURE_RECT:
2008 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2009 case TGSI_TEXTURE_SHADOW2D:
2010 case TGSI_TEXTURE_SHADOWRECT:
2011 case TGSI_TEXTURE_1D_ARRAY:
2012 IFETCH(&r[1], 0, CHAN_Y);
2013 /* fallthrough */
2014 case TGSI_TEXTURE_1D:
2015 case TGSI_TEXTURE_SHADOW1D:
2016 IFETCH(&r[0], 0, CHAN_X);
2017 break;
2018 default:
2019 assert(0);
2020 break;
2021 }
2022
2023 sampler = mach->Samplers[unit];
2024 sampler->get_texel(sampler, r[0].i, r[1].i, r[2].i, r[3].i,
2025 offsets, rgba);
2026
2027 for (j = 0; j < QUAD_SIZE; j++) {
2028 r[0].f[j] = rgba[0][j];
2029 r[1].f[j] = rgba[1][j];
2030 r[2].f[j] = rgba[2][j];
2031 r[3].f[j] = rgba[3][j];
2032 }
2033
2034 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2035 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2036 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2037 }
2038 }
2039 }
2040
2041 static void
2042 exec_txq(struct tgsi_exec_machine *mach,
2043 const struct tgsi_full_instruction *inst)
2044 {
2045 struct tgsi_sampler *sampler;
2046 const uint unit = inst->Src[1].Register.Index;
2047 int result[4];
2048 union tgsi_exec_channel r[4], src;
2049 uint chan;
2050 int i,j;
2051
2052 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_INT);
2053 sampler = mach->Samplers[unit];
2054
2055 sampler->get_dims(sampler, src.i[0], result);
2056
2057 for (i = 0; i < QUAD_SIZE; i++) {
2058 for (j = 0; j < 4; j++) {
2059 r[j].i[i] = result[j];
2060 }
2061 }
2062
2063 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2064 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2065 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2066 TGSI_EXEC_DATA_INT);
2067 }
2068 }
2069 }
2070
2071 static void
2072 exec_sample(struct tgsi_exec_machine *mach,
2073 const struct tgsi_full_instruction *inst,
2074 uint modifier)
2075 {
2076 const uint resource_unit = inst->Src[1].Register.Index;
2077 const uint sampler_unit = inst->Src[2].Register.Index;
2078 union tgsi_exec_channel r[4];
2079 const union tgsi_exec_channel *lod = &ZeroVec;
2080 enum tgsi_sampler_control control;
2081 uint chan;
2082
2083 if (modifier != TEX_MODIFIER_NONE) {
2084 if (modifier == TEX_MODIFIER_LOD_BIAS)
2085 FETCH(&r[3], 3, CHAN_X);
2086 else /*TEX_MODIFIER_LOD*/
2087 FETCH(&r[3], 0, CHAN_W);
2088
2089 if (modifier != TEX_MODIFIER_PROJECTED) {
2090 lod = &r[3];
2091 }
2092 }
2093
2094 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2095 control = tgsi_sampler_lod_explicit;
2096 } else {
2097 control = tgsi_sampler_lod_bias;
2098 }
2099
2100 switch (mach->Resources[resource_unit].Resource) {
2101 case TGSI_TEXTURE_1D:
2102 case TGSI_TEXTURE_SHADOW1D:
2103 FETCH(&r[0], 0, CHAN_X);
2104
2105 if (modifier == TEX_MODIFIER_PROJECTED) {
2106 micro_div(&r[0], &r[0], &r[3]);
2107 }
2108
2109 fetch_texel(mach->Samplers[sampler_unit],
2110 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
2111 control,
2112 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2113 break;
2114
2115 case TGSI_TEXTURE_1D_ARRAY:
2116 case TGSI_TEXTURE_2D:
2117 case TGSI_TEXTURE_RECT:
2118 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2119 case TGSI_TEXTURE_SHADOW2D:
2120 case TGSI_TEXTURE_SHADOWRECT:
2121 FETCH(&r[0], 0, CHAN_X);
2122 FETCH(&r[1], 0, CHAN_Y);
2123 FETCH(&r[2], 0, CHAN_Z);
2124
2125 if (modifier == TEX_MODIFIER_PROJECTED) {
2126 micro_div(&r[0], &r[0], &r[3]);
2127 micro_div(&r[1], &r[1], &r[3]);
2128 micro_div(&r[2], &r[2], &r[3]);
2129 }
2130
2131 fetch_texel(mach->Samplers[sampler_unit],
2132 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
2133 control,
2134 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2135 break;
2136
2137 case TGSI_TEXTURE_2D_ARRAY:
2138 case TGSI_TEXTURE_3D:
2139 case TGSI_TEXTURE_CUBE:
2140 FETCH(&r[0], 0, CHAN_X);
2141 FETCH(&r[1], 0, CHAN_Y);
2142 FETCH(&r[2], 0, CHAN_Z);
2143
2144 if (modifier == TEX_MODIFIER_PROJECTED) {
2145 micro_div(&r[0], &r[0], &r[3]);
2146 micro_div(&r[1], &r[1], &r[3]);
2147 micro_div(&r[2], &r[2], &r[3]);
2148 }
2149
2150 fetch_texel(mach->Samplers[sampler_unit],
2151 &r[0], &r[1], &r[2], lod,
2152 control,
2153 &r[0], &r[1], &r[2], &r[3]);
2154 break;
2155
2156 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2157 FETCH(&r[0], 0, CHAN_X);
2158 FETCH(&r[1], 0, CHAN_Y);
2159 FETCH(&r[2], 0, CHAN_Z);
2160 FETCH(&r[3], 0, CHAN_W);
2161
2162 assert(modifier != TEX_MODIFIER_PROJECTED);
2163
2164 fetch_texel(mach->Samplers[sampler_unit],
2165 &r[0], &r[1], &r[2], &r[3],
2166 control,
2167 &r[0], &r[1], &r[2], &r[3]);
2168 break;
2169
2170 default:
2171 assert(0);
2172 }
2173
2174 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2175 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2176 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2177 }
2178 }
2179 }
2180
2181 static void
2182 exec_sample_d(struct tgsi_exec_machine *mach,
2183 const struct tgsi_full_instruction *inst)
2184 {
2185 const uint resource_unit = inst->Src[1].Register.Index;
2186 const uint sampler_unit = inst->Src[2].Register.Index;
2187 union tgsi_exec_channel r[4];
2188 uint chan;
2189 /*
2190 * XXX: This is fake SAMPLE_D -- the derivatives are not taken into account, yet.
2191 */
2192
2193 switch (mach->Resources[resource_unit].Resource) {
2194 case TGSI_TEXTURE_1D:
2195 case TGSI_TEXTURE_SHADOW1D:
2196
2197 FETCH(&r[0], 0, CHAN_X);
2198
2199 fetch_texel(mach->Samplers[sampler_unit],
2200 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
2201 tgsi_sampler_lod_bias,
2202 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2203 break;
2204
2205 case TGSI_TEXTURE_2D:
2206 case TGSI_TEXTURE_RECT:
2207 case TGSI_TEXTURE_SHADOW2D:
2208 case TGSI_TEXTURE_SHADOWRECT:
2209
2210 FETCH(&r[0], 0, CHAN_X);
2211 FETCH(&r[1], 0, CHAN_Y);
2212 FETCH(&r[2], 0, CHAN_Z);
2213
2214 fetch_texel(mach->Samplers[sampler_unit],
2215 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
2216 tgsi_sampler_lod_bias,
2217 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2218 break;
2219
2220 case TGSI_TEXTURE_3D:
2221 case TGSI_TEXTURE_CUBE:
2222
2223 FETCH(&r[0], 0, CHAN_X);
2224 FETCH(&r[1], 0, CHAN_Y);
2225 FETCH(&r[2], 0, CHAN_Z);
2226
2227 fetch_texel(mach->Samplers[sampler_unit],
2228 &r[0], &r[1], &r[2], &ZeroVec,
2229 tgsi_sampler_lod_bias,
2230 &r[0], &r[1], &r[2], &r[3]);
2231 break;
2232
2233 default:
2234 assert(0);
2235 }
2236
2237 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2238 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2239 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2240 }
2241 }
2242 }
2243
2244
2245 /**
2246 * Evaluate a constant-valued coefficient at the position of the
2247 * current quad.
2248 */
2249 static void
2250 eval_constant_coef(
2251 struct tgsi_exec_machine *mach,
2252 unsigned attrib,
2253 unsigned chan )
2254 {
2255 unsigned i;
2256
2257 for( i = 0; i < QUAD_SIZE; i++ ) {
2258 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2259 }
2260 }
2261
2262 /**
2263 * Evaluate a linear-valued coefficient at the position of the
2264 * current quad.
2265 */
2266 static void
2267 eval_linear_coef(
2268 struct tgsi_exec_machine *mach,
2269 unsigned attrib,
2270 unsigned chan )
2271 {
2272 const float x = mach->QuadPos.xyzw[0].f[0];
2273 const float y = mach->QuadPos.xyzw[1].f[0];
2274 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2275 const float dady = mach->InterpCoefs[attrib].dady[chan];
2276 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2277 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2278 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2279 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2280 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2281 }
2282
2283 /**
2284 * Evaluate a perspective-valued coefficient at the position of the
2285 * current quad.
2286 */
2287 static void
2288 eval_perspective_coef(
2289 struct tgsi_exec_machine *mach,
2290 unsigned attrib,
2291 unsigned chan )
2292 {
2293 const float x = mach->QuadPos.xyzw[0].f[0];
2294 const float y = mach->QuadPos.xyzw[1].f[0];
2295 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2296 const float dady = mach->InterpCoefs[attrib].dady[chan];
2297 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2298 const float *w = mach->QuadPos.xyzw[3].f;
2299 /* divide by W here */
2300 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2301 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2302 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2303 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2304 }
2305
2306
2307 typedef void (* eval_coef_func)(
2308 struct tgsi_exec_machine *mach,
2309 unsigned attrib,
2310 unsigned chan );
2311
2312 static void
2313 exec_declaration(struct tgsi_exec_machine *mach,
2314 const struct tgsi_full_declaration *decl)
2315 {
2316 if (decl->Declaration.File == TGSI_FILE_RESOURCE) {
2317 mach->Resources[decl->Range.First] = decl->Resource;
2318 return;
2319 }
2320
2321 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2322 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2323 uint first, last, mask;
2324
2325 first = decl->Range.First;
2326 last = decl->Range.Last;
2327 mask = decl->Declaration.UsageMask;
2328
2329 /* XXX we could remove this special-case code since
2330 * mach->InterpCoefs[first].a0 should already have the
2331 * front/back-face value. But we should first update the
2332 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2333 * Then, we could remove the tgsi_exec_machine::Face field.
2334 */
2335 /* XXX make FACE a system value */
2336 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2337 uint i;
2338
2339 assert(decl->Semantic.Index == 0);
2340 assert(first == last);
2341
2342 for (i = 0; i < QUAD_SIZE; i++) {
2343 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2344 }
2345 } else {
2346 eval_coef_func eval;
2347 uint i, j;
2348
2349 switch (decl->Declaration.Interpolate) {
2350 case TGSI_INTERPOLATE_CONSTANT:
2351 eval = eval_constant_coef;
2352 break;
2353
2354 case TGSI_INTERPOLATE_LINEAR:
2355 eval = eval_linear_coef;
2356 break;
2357
2358 case TGSI_INTERPOLATE_PERSPECTIVE:
2359 eval = eval_perspective_coef;
2360 break;
2361
2362 default:
2363 assert(0);
2364 return;
2365 }
2366
2367 for (j = 0; j < NUM_CHANNELS; j++) {
2368 if (mask & (1 << j)) {
2369 for (i = first; i <= last; i++) {
2370 eval(mach, i, j);
2371 }
2372 }
2373 }
2374 }
2375 }
2376 }
2377
2378 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2379 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2380 }
2381 }
2382
2383
2384 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2385
2386 static void
2387 exec_vector(struct tgsi_exec_machine *mach,
2388 const struct tgsi_full_instruction *inst,
2389 micro_op op,
2390 enum tgsi_exec_datatype dst_datatype)
2391 {
2392 unsigned int chan;
2393
2394 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2395 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2396 union tgsi_exec_channel dst;
2397
2398 op(&dst);
2399 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2400 }
2401 }
2402 }
2403
2404 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2405 const union tgsi_exec_channel *src);
2406
2407 static void
2408 exec_scalar_unary(struct tgsi_exec_machine *mach,
2409 const struct tgsi_full_instruction *inst,
2410 micro_unary_op op,
2411 enum tgsi_exec_datatype dst_datatype,
2412 enum tgsi_exec_datatype src_datatype)
2413 {
2414 unsigned int chan;
2415 union tgsi_exec_channel src;
2416 union tgsi_exec_channel dst;
2417
2418 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
2419 op(&dst, &src);
2420 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2421 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2422 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2423 }
2424 }
2425 }
2426
2427 static void
2428 exec_vector_unary(struct tgsi_exec_machine *mach,
2429 const struct tgsi_full_instruction *inst,
2430 micro_unary_op op,
2431 enum tgsi_exec_datatype dst_datatype,
2432 enum tgsi_exec_datatype src_datatype)
2433 {
2434 unsigned int chan;
2435 struct tgsi_exec_vector dst;
2436
2437 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2438 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2439 union tgsi_exec_channel src;
2440
2441 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2442 op(&dst.xyzw[chan], &src);
2443 }
2444 }
2445 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2446 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2447 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2448 }
2449 }
2450 }
2451
2452 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2453 const union tgsi_exec_channel *src0,
2454 const union tgsi_exec_channel *src1);
2455
2456 static void
2457 exec_scalar_binary(struct tgsi_exec_machine *mach,
2458 const struct tgsi_full_instruction *inst,
2459 micro_binary_op op,
2460 enum tgsi_exec_datatype dst_datatype,
2461 enum tgsi_exec_datatype src_datatype)
2462 {
2463 unsigned int chan;
2464 union tgsi_exec_channel src[2];
2465 union tgsi_exec_channel dst;
2466
2467 fetch_source(mach, &src[0], &inst->Src[0], CHAN_X, src_datatype);
2468 fetch_source(mach, &src[1], &inst->Src[1], CHAN_Y, src_datatype);
2469 op(&dst, &src[0], &src[1]);
2470 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2471 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2472 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2473 }
2474 }
2475 }
2476
2477 static void
2478 exec_vector_binary(struct tgsi_exec_machine *mach,
2479 const struct tgsi_full_instruction *inst,
2480 micro_binary_op op,
2481 enum tgsi_exec_datatype dst_datatype,
2482 enum tgsi_exec_datatype src_datatype)
2483 {
2484 unsigned int chan;
2485 struct tgsi_exec_vector dst;
2486
2487 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2488 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2489 union tgsi_exec_channel src[2];
2490
2491 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2492 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2493 op(&dst.xyzw[chan], &src[0], &src[1]);
2494 }
2495 }
2496 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2497 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2498 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2499 }
2500 }
2501 }
2502
2503 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2504 const union tgsi_exec_channel *src0,
2505 const union tgsi_exec_channel *src1,
2506 const union tgsi_exec_channel *src2);
2507
2508 static void
2509 exec_vector_trinary(struct tgsi_exec_machine *mach,
2510 const struct tgsi_full_instruction *inst,
2511 micro_trinary_op op,
2512 enum tgsi_exec_datatype dst_datatype,
2513 enum tgsi_exec_datatype src_datatype)
2514 {
2515 unsigned int chan;
2516 struct tgsi_exec_vector dst;
2517
2518 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2519 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2520 union tgsi_exec_channel src[3];
2521
2522 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2523 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2524 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2525 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2526 }
2527 }
2528 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2529 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2530 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2531 }
2532 }
2533 }
2534
2535 static void
2536 exec_dp3(struct tgsi_exec_machine *mach,
2537 const struct tgsi_full_instruction *inst)
2538 {
2539 unsigned int chan;
2540 union tgsi_exec_channel arg[3];
2541
2542 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2543 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2544 micro_mul(&arg[2], &arg[0], &arg[1]);
2545
2546 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2547 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2548 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2549 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2550 }
2551
2552 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2553 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2554 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2555 }
2556 }
2557 }
2558
2559 static void
2560 exec_dp4(struct tgsi_exec_machine *mach,
2561 const struct tgsi_full_instruction *inst)
2562 {
2563 unsigned int chan;
2564 union tgsi_exec_channel arg[3];
2565
2566 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2567 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2568 micro_mul(&arg[2], &arg[0], &arg[1]);
2569
2570 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2571 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2572 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2573 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2574 }
2575
2576 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2577 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2578 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2579 }
2580 }
2581 }
2582
2583 static void
2584 exec_dp2a(struct tgsi_exec_machine *mach,
2585 const struct tgsi_full_instruction *inst)
2586 {
2587 unsigned int chan;
2588 union tgsi_exec_channel arg[3];
2589
2590 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2591 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2592 micro_mul(&arg[2], &arg[0], &arg[1]);
2593
2594 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2595 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2596 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2597
2598 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2599 micro_add(&arg[0], &arg[0], &arg[1]);
2600
2601 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2602 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2603 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2604 }
2605 }
2606 }
2607
2608 static void
2609 exec_dph(struct tgsi_exec_machine *mach,
2610 const struct tgsi_full_instruction *inst)
2611 {
2612 unsigned int chan;
2613 union tgsi_exec_channel arg[3];
2614
2615 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2616 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2617 micro_mul(&arg[2], &arg[0], &arg[1]);
2618
2619 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2620 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2621 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2622
2623 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2624 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2625 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2626
2627 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2628 micro_add(&arg[0], &arg[0], &arg[1]);
2629
2630 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2631 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2632 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2633 }
2634 }
2635 }
2636
2637 static void
2638 exec_dp2(struct tgsi_exec_machine *mach,
2639 const struct tgsi_full_instruction *inst)
2640 {
2641 unsigned int chan;
2642 union tgsi_exec_channel arg[3];
2643
2644 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2645 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2646 micro_mul(&arg[2], &arg[0], &arg[1]);
2647
2648 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2649 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2650 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2651
2652 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2653 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2654 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2655 }
2656 }
2657 }
2658
2659 static void
2660 exec_nrm4(struct tgsi_exec_machine *mach,
2661 const struct tgsi_full_instruction *inst)
2662 {
2663 unsigned int chan;
2664 union tgsi_exec_channel arg[4];
2665 union tgsi_exec_channel scale;
2666
2667 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2668 micro_mul(&scale, &arg[0], &arg[0]);
2669
2670 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2671 union tgsi_exec_channel product;
2672
2673 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2674 micro_mul(&product, &arg[chan], &arg[chan]);
2675 micro_add(&scale, &scale, &product);
2676 }
2677
2678 micro_rsq(&scale, &scale);
2679
2680 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2681 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2682 micro_mul(&arg[chan], &arg[chan], &scale);
2683 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2684 }
2685 }
2686 }
2687
2688 static void
2689 exec_nrm3(struct tgsi_exec_machine *mach,
2690 const struct tgsi_full_instruction *inst)
2691 {
2692 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2693 unsigned int chan;
2694 union tgsi_exec_channel arg[3];
2695 union tgsi_exec_channel scale;
2696
2697 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2698 micro_mul(&scale, &arg[0], &arg[0]);
2699
2700 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2701 union tgsi_exec_channel product;
2702
2703 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2704 micro_mul(&product, &arg[chan], &arg[chan]);
2705 micro_add(&scale, &scale, &product);
2706 }
2707
2708 micro_rsq(&scale, &scale);
2709
2710 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2711 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2712 micro_mul(&arg[chan], &arg[chan], &scale);
2713 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2714 }
2715 }
2716 }
2717
2718 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2719 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2720 }
2721 }
2722
2723 static void
2724 exec_scs(struct tgsi_exec_machine *mach,
2725 const struct tgsi_full_instruction *inst)
2726 {
2727 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2728 union tgsi_exec_channel arg;
2729 union tgsi_exec_channel result;
2730
2731 fetch_source(mach, &arg, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2732
2733 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2734 micro_cos(&result, &arg);
2735 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2736 }
2737 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2738 micro_sin(&result, &arg);
2739 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2740 }
2741 }
2742 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2743 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2744 }
2745 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2746 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2747 }
2748 }
2749
2750 static void
2751 exec_x2d(struct tgsi_exec_machine *mach,
2752 const struct tgsi_full_instruction *inst)
2753 {
2754 union tgsi_exec_channel r[4];
2755 union tgsi_exec_channel d[2];
2756
2757 fetch_source(mach, &r[0], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2758 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2759 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2760 fetch_source(mach, &r[2], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2761 micro_mul(&r[2], &r[2], &r[0]);
2762 fetch_source(mach, &r[3], &inst->Src[2], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2763 micro_mul(&r[3], &r[3], &r[1]);
2764 micro_add(&r[2], &r[2], &r[3]);
2765 fetch_source(mach, &r[3], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2766 micro_add(&d[0], &r[2], &r[3]);
2767 }
2768 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2769 fetch_source(mach, &r[2], &inst->Src[2], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2770 micro_mul(&r[2], &r[2], &r[0]);
2771 fetch_source(mach, &r[3], &inst->Src[2], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2772 micro_mul(&r[3], &r[3], &r[1]);
2773 micro_add(&r[2], &r[2], &r[3]);
2774 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2775 micro_add(&d[1], &r[2], &r[3]);
2776 }
2777 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2778 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2779 }
2780 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2781 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2782 }
2783 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2784 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2785 }
2786 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2787 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2788 }
2789 }
2790
2791 static void
2792 exec_rfl(struct tgsi_exec_machine *mach,
2793 const struct tgsi_full_instruction *inst)
2794 {
2795 union tgsi_exec_channel r[9];
2796
2797 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2798 /* r0 = dp3(src0, src0) */
2799 fetch_source(mach, &r[2], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2800 micro_mul(&r[0], &r[2], &r[2]);
2801 fetch_source(mach, &r[4], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2802 micro_mul(&r[8], &r[4], &r[4]);
2803 micro_add(&r[0], &r[0], &r[8]);
2804 fetch_source(mach, &r[6], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2805 micro_mul(&r[8], &r[6], &r[6]);
2806 micro_add(&r[0], &r[0], &r[8]);
2807
2808 /* r1 = dp3(src0, src1) */
2809 fetch_source(mach, &r[3], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2810 micro_mul(&r[1], &r[2], &r[3]);
2811 fetch_source(mach, &r[5], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2812 micro_mul(&r[8], &r[4], &r[5]);
2813 micro_add(&r[1], &r[1], &r[8]);
2814 fetch_source(mach, &r[7], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2815 micro_mul(&r[8], &r[6], &r[7]);
2816 micro_add(&r[1], &r[1], &r[8]);
2817
2818 /* r1 = 2 * r1 / r0 */
2819 micro_add(&r[1], &r[1], &r[1]);
2820 micro_div(&r[1], &r[1], &r[0]);
2821
2822 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2823 micro_mul(&r[2], &r[2], &r[1]);
2824 micro_sub(&r[2], &r[2], &r[3]);
2825 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2826 }
2827 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2828 micro_mul(&r[4], &r[4], &r[1]);
2829 micro_sub(&r[4], &r[4], &r[5]);
2830 store_dest(mach, &r[4], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2831 }
2832 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2833 micro_mul(&r[6], &r[6], &r[1]);
2834 micro_sub(&r[6], &r[6], &r[7]);
2835 store_dest(mach, &r[6], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2836 }
2837 }
2838 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2839 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2840 }
2841 }
2842
2843 static void
2844 exec_xpd(struct tgsi_exec_machine *mach,
2845 const struct tgsi_full_instruction *inst)
2846 {
2847 union tgsi_exec_channel r[6];
2848 union tgsi_exec_channel d[3];
2849
2850 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2851 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2852
2853 micro_mul(&r[2], &r[0], &r[1]);
2854
2855 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2856 fetch_source(mach, &r[4], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2857
2858 micro_mul(&r[5], &r[3], &r[4] );
2859 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2860
2861 fetch_source(mach, &r[2], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2862
2863 micro_mul(&r[3], &r[3], &r[2]);
2864
2865 fetch_source(mach, &r[5], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2866
2867 micro_mul(&r[1], &r[1], &r[5]);
2868 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2869
2870 micro_mul(&r[5], &r[5], &r[4]);
2871 micro_mul(&r[0], &r[0], &r[2]);
2872 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2873
2874 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2875 store_dest(mach, &d[CHAN_X], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2876 }
2877 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2878 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2879 }
2880 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2881 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2882 }
2883 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2884 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2885 }
2886 }
2887
2888 static void
2889 exec_dst(struct tgsi_exec_machine *mach,
2890 const struct tgsi_full_instruction *inst)
2891 {
2892 union tgsi_exec_channel r[2];
2893 union tgsi_exec_channel d[4];
2894
2895 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2896 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2897 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2898 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2899 }
2900 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2901 fetch_source(mach, &d[CHAN_Z], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2902 }
2903 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2904 fetch_source(mach, &d[CHAN_W], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2905 }
2906
2907 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2908 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2909 }
2910 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2911 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2912 }
2913 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2914 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2915 }
2916 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2917 store_dest(mach, &d[CHAN_W], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2918 }
2919 }
2920
2921 static void
2922 exec_log(struct tgsi_exec_machine *mach,
2923 const struct tgsi_full_instruction *inst)
2924 {
2925 union tgsi_exec_channel r[3];
2926
2927 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2928 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2929 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2930 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2931 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2932 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2933 }
2934 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2935 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2936 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2937 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2938 }
2939 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2940 store_dest(mach, &r[1], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2941 }
2942 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2943 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2944 }
2945 }
2946
2947 static void
2948 exec_exp(struct tgsi_exec_machine *mach,
2949 const struct tgsi_full_instruction *inst)
2950 {
2951 union tgsi_exec_channel r[3];
2952
2953 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2954 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2955 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2956 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2957 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2958 }
2959 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2960 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2961 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2962 }
2963 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2964 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2965 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2966 }
2967 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2968 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2969 }
2970 }
2971
2972 static void
2973 exec_lit(struct tgsi_exec_machine *mach,
2974 const struct tgsi_full_instruction *inst)
2975 {
2976 union tgsi_exec_channel r[3];
2977 union tgsi_exec_channel d[3];
2978
2979 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2980 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2981 }
2982 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2983 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2984 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2985 micro_max(&d[CHAN_Y], &r[0], &ZeroVec);
2986 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2987 }
2988
2989 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2990 fetch_source(mach, &r[1], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2991 micro_max(&r[1], &r[1], &ZeroVec);
2992
2993 fetch_source(mach, &r[2], &inst->Src[0], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2994 micro_min(&r[2], &r[2], &P128Vec);
2995 micro_max(&r[2], &r[2], &M128Vec);
2996 micro_pow(&r[1], &r[1], &r[2]);
2997 micro_lt(&d[CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
2998 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2999 }
3000 }
3001 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3002 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
3003 }
3004 }
3005
3006 static void
3007 exec_break(struct tgsi_exec_machine *mach)
3008 {
3009 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3010 /* turn off loop channels for each enabled exec channel */
3011 mach->LoopMask &= ~mach->ExecMask;
3012 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3013 UPDATE_EXEC_MASK(mach);
3014 } else {
3015 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3016
3017 mach->Switch.mask = 0x0;
3018
3019 UPDATE_EXEC_MASK(mach);
3020 }
3021 }
3022
3023 static void
3024 exec_switch(struct tgsi_exec_machine *mach,
3025 const struct tgsi_full_instruction *inst)
3026 {
3027 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3028 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3029
3030 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3031 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
3032 mach->Switch.mask = 0x0;
3033 mach->Switch.defaultMask = 0x0;
3034
3035 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3036 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3037
3038 UPDATE_EXEC_MASK(mach);
3039 }
3040
3041 static void
3042 exec_case(struct tgsi_exec_machine *mach,
3043 const struct tgsi_full_instruction *inst)
3044 {
3045 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3046 union tgsi_exec_channel src;
3047 uint mask = 0;
3048
3049 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
3050
3051 if (mach->Switch.selector.u[0] == src.u[0]) {
3052 mask |= 0x1;
3053 }
3054 if (mach->Switch.selector.u[1] == src.u[1]) {
3055 mask |= 0x2;
3056 }
3057 if (mach->Switch.selector.u[2] == src.u[2]) {
3058 mask |= 0x4;
3059 }
3060 if (mach->Switch.selector.u[3] == src.u[3]) {
3061 mask |= 0x8;
3062 }
3063
3064 mach->Switch.defaultMask |= mask;
3065
3066 mach->Switch.mask |= mask & prevMask;
3067
3068 UPDATE_EXEC_MASK(mach);
3069 }
3070
3071 static void
3072 exec_default(struct tgsi_exec_machine *mach)
3073 {
3074 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3075
3076 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3077
3078 UPDATE_EXEC_MASK(mach);
3079 }
3080
3081 static void
3082 exec_endswitch(struct tgsi_exec_machine *mach)
3083 {
3084 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3085 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3086
3087 UPDATE_EXEC_MASK(mach);
3088 }
3089
3090 static void
3091 micro_i2f(union tgsi_exec_channel *dst,
3092 const union tgsi_exec_channel *src)
3093 {
3094 dst->f[0] = (float)src->i[0];
3095 dst->f[1] = (float)src->i[1];
3096 dst->f[2] = (float)src->i[2];
3097 dst->f[3] = (float)src->i[3];
3098 }
3099
3100 static void
3101 micro_not(union tgsi_exec_channel *dst,
3102 const union tgsi_exec_channel *src)
3103 {
3104 dst->u[0] = ~src->u[0];
3105 dst->u[1] = ~src->u[1];
3106 dst->u[2] = ~src->u[2];
3107 dst->u[3] = ~src->u[3];
3108 }
3109
3110 static void
3111 micro_shl(union tgsi_exec_channel *dst,
3112 const union tgsi_exec_channel *src0,
3113 const union tgsi_exec_channel *src1)
3114 {
3115 dst->u[0] = src0->u[0] << src1->u[0];
3116 dst->u[1] = src0->u[1] << src1->u[1];
3117 dst->u[2] = src0->u[2] << src1->u[2];
3118 dst->u[3] = src0->u[3] << src1->u[3];
3119 }
3120
3121 static void
3122 micro_and(union tgsi_exec_channel *dst,
3123 const union tgsi_exec_channel *src0,
3124 const union tgsi_exec_channel *src1)
3125 {
3126 dst->u[0] = src0->u[0] & src1->u[0];
3127 dst->u[1] = src0->u[1] & src1->u[1];
3128 dst->u[2] = src0->u[2] & src1->u[2];
3129 dst->u[3] = src0->u[3] & src1->u[3];
3130 }
3131
3132 static void
3133 micro_or(union tgsi_exec_channel *dst,
3134 const union tgsi_exec_channel *src0,
3135 const union tgsi_exec_channel *src1)
3136 {
3137 dst->u[0] = src0->u[0] | src1->u[0];
3138 dst->u[1] = src0->u[1] | src1->u[1];
3139 dst->u[2] = src0->u[2] | src1->u[2];
3140 dst->u[3] = src0->u[3] | src1->u[3];
3141 }
3142
3143 static void
3144 micro_xor(union tgsi_exec_channel *dst,
3145 const union tgsi_exec_channel *src0,
3146 const union tgsi_exec_channel *src1)
3147 {
3148 dst->u[0] = src0->u[0] ^ src1->u[0];
3149 dst->u[1] = src0->u[1] ^ src1->u[1];
3150 dst->u[2] = src0->u[2] ^ src1->u[2];
3151 dst->u[3] = src0->u[3] ^ src1->u[3];
3152 }
3153
3154 static void
3155 micro_mod(union tgsi_exec_channel *dst,
3156 const union tgsi_exec_channel *src0,
3157 const union tgsi_exec_channel *src1)
3158 {
3159 dst->i[0] = src0->i[0] % src1->i[0];
3160 dst->i[1] = src0->i[1] % src1->i[1];
3161 dst->i[2] = src0->i[2] % src1->i[2];
3162 dst->i[3] = src0->i[3] % src1->i[3];
3163 }
3164
3165 static void
3166 micro_f2i(union tgsi_exec_channel *dst,
3167 const union tgsi_exec_channel *src)
3168 {
3169 dst->i[0] = (int)src->f[0];
3170 dst->i[1] = (int)src->f[1];
3171 dst->i[2] = (int)src->f[2];
3172 dst->i[3] = (int)src->f[3];
3173 }
3174
3175 static void
3176 micro_idiv(union tgsi_exec_channel *dst,
3177 const union tgsi_exec_channel *src0,
3178 const union tgsi_exec_channel *src1)
3179 {
3180 dst->i[0] = src0->i[0] / src1->i[0];
3181 dst->i[1] = src0->i[1] / src1->i[1];
3182 dst->i[2] = src0->i[2] / src1->i[2];
3183 dst->i[3] = src0->i[3] / src1->i[3];
3184 }
3185
3186 static void
3187 micro_imax(union tgsi_exec_channel *dst,
3188 const union tgsi_exec_channel *src0,
3189 const union tgsi_exec_channel *src1)
3190 {
3191 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3192 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3193 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3194 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3195 }
3196
3197 static void
3198 micro_imin(union tgsi_exec_channel *dst,
3199 const union tgsi_exec_channel *src0,
3200 const union tgsi_exec_channel *src1)
3201 {
3202 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3203 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3204 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3205 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3206 }
3207
3208 static void
3209 micro_isge(union tgsi_exec_channel *dst,
3210 const union tgsi_exec_channel *src0,
3211 const union tgsi_exec_channel *src1)
3212 {
3213 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3214 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3215 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3216 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3217 }
3218
3219 static void
3220 micro_ishr(union tgsi_exec_channel *dst,
3221 const union tgsi_exec_channel *src0,
3222 const union tgsi_exec_channel *src1)
3223 {
3224 dst->i[0] = src0->i[0] >> src1->i[0];
3225 dst->i[1] = src0->i[1] >> src1->i[1];
3226 dst->i[2] = src0->i[2] >> src1->i[2];
3227 dst->i[3] = src0->i[3] >> src1->i[3];
3228 }
3229
3230 static void
3231 micro_islt(union tgsi_exec_channel *dst,
3232 const union tgsi_exec_channel *src0,
3233 const union tgsi_exec_channel *src1)
3234 {
3235 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3236 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3237 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3238 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3239 }
3240
3241 static void
3242 micro_f2u(union tgsi_exec_channel *dst,
3243 const union tgsi_exec_channel *src)
3244 {
3245 dst->u[0] = (uint)src->f[0];
3246 dst->u[1] = (uint)src->f[1];
3247 dst->u[2] = (uint)src->f[2];
3248 dst->u[3] = (uint)src->f[3];
3249 }
3250
3251 static void
3252 micro_u2f(union tgsi_exec_channel *dst,
3253 const union tgsi_exec_channel *src)
3254 {
3255 dst->f[0] = (float)src->u[0];
3256 dst->f[1] = (float)src->u[1];
3257 dst->f[2] = (float)src->u[2];
3258 dst->f[3] = (float)src->u[3];
3259 }
3260
3261 static void
3262 micro_uadd(union tgsi_exec_channel *dst,
3263 const union tgsi_exec_channel *src0,
3264 const union tgsi_exec_channel *src1)
3265 {
3266 dst->u[0] = src0->u[0] + src1->u[0];
3267 dst->u[1] = src0->u[1] + src1->u[1];
3268 dst->u[2] = src0->u[2] + src1->u[2];
3269 dst->u[3] = src0->u[3] + src1->u[3];
3270 }
3271
3272 static void
3273 micro_udiv(union tgsi_exec_channel *dst,
3274 const union tgsi_exec_channel *src0,
3275 const union tgsi_exec_channel *src1)
3276 {
3277 dst->u[0] = src0->u[0] / src1->u[0];
3278 dst->u[1] = src0->u[1] / src1->u[1];
3279 dst->u[2] = src0->u[2] / src1->u[2];
3280 dst->u[3] = src0->u[3] / src1->u[3];
3281 }
3282
3283 static void
3284 micro_umad(union tgsi_exec_channel *dst,
3285 const union tgsi_exec_channel *src0,
3286 const union tgsi_exec_channel *src1,
3287 const union tgsi_exec_channel *src2)
3288 {
3289 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3290 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3291 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3292 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3293 }
3294
3295 static void
3296 micro_umax(union tgsi_exec_channel *dst,
3297 const union tgsi_exec_channel *src0,
3298 const union tgsi_exec_channel *src1)
3299 {
3300 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3301 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3302 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3303 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3304 }
3305
3306 static void
3307 micro_umin(union tgsi_exec_channel *dst,
3308 const union tgsi_exec_channel *src0,
3309 const union tgsi_exec_channel *src1)
3310 {
3311 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3312 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3313 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3314 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3315 }
3316
3317 static void
3318 micro_umod(union tgsi_exec_channel *dst,
3319 const union tgsi_exec_channel *src0,
3320 const union tgsi_exec_channel *src1)
3321 {
3322 dst->u[0] = src0->u[0] % src1->u[0];
3323 dst->u[1] = src0->u[1] % src1->u[1];
3324 dst->u[2] = src0->u[2] % src1->u[2];
3325 dst->u[3] = src0->u[3] % src1->u[3];
3326 }
3327
3328 static void
3329 micro_umul(union tgsi_exec_channel *dst,
3330 const union tgsi_exec_channel *src0,
3331 const union tgsi_exec_channel *src1)
3332 {
3333 dst->u[0] = src0->u[0] * src1->u[0];
3334 dst->u[1] = src0->u[1] * src1->u[1];
3335 dst->u[2] = src0->u[2] * src1->u[2];
3336 dst->u[3] = src0->u[3] * src1->u[3];
3337 }
3338
3339 static void
3340 micro_useq(union tgsi_exec_channel *dst,
3341 const union tgsi_exec_channel *src0,
3342 const union tgsi_exec_channel *src1)
3343 {
3344 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3345 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3346 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3347 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3348 }
3349
3350 static void
3351 micro_usge(union tgsi_exec_channel *dst,
3352 const union tgsi_exec_channel *src0,
3353 const union tgsi_exec_channel *src1)
3354 {
3355 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3356 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3357 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3358 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3359 }
3360
3361 static void
3362 micro_ushr(union tgsi_exec_channel *dst,
3363 const union tgsi_exec_channel *src0,
3364 const union tgsi_exec_channel *src1)
3365 {
3366 dst->u[0] = src0->u[0] >> src1->u[0];
3367 dst->u[1] = src0->u[1] >> src1->u[1];
3368 dst->u[2] = src0->u[2] >> src1->u[2];
3369 dst->u[3] = src0->u[3] >> src1->u[3];
3370 }
3371
3372 static void
3373 micro_uslt(union tgsi_exec_channel *dst,
3374 const union tgsi_exec_channel *src0,
3375 const union tgsi_exec_channel *src1)
3376 {
3377 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3378 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3379 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3380 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3381 }
3382
3383 static void
3384 micro_usne(union tgsi_exec_channel *dst,
3385 const union tgsi_exec_channel *src0,
3386 const union tgsi_exec_channel *src1)
3387 {
3388 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3389 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3390 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3391 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3392 }
3393
3394 static void
3395 micro_uarl(union tgsi_exec_channel *dst,
3396 const union tgsi_exec_channel *src)
3397 {
3398 dst->i[0] = src->u[0];
3399 dst->i[1] = src->u[1];
3400 dst->i[2] = src->u[2];
3401 dst->i[3] = src->u[3];
3402 }
3403
3404 static void
3405 micro_ucmp(union tgsi_exec_channel *dst,
3406 const union tgsi_exec_channel *src0,
3407 const union tgsi_exec_channel *src1,
3408 const union tgsi_exec_channel *src2)
3409 {
3410 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3411 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3412 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3413 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3414 }
3415
3416 static void
3417 exec_instruction(
3418 struct tgsi_exec_machine *mach,
3419 const struct tgsi_full_instruction *inst,
3420 int *pc )
3421 {
3422 union tgsi_exec_channel r[10];
3423
3424 (*pc)++;
3425
3426 switch (inst->Instruction.Opcode) {
3427 case TGSI_OPCODE_ARL:
3428 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3429 break;
3430
3431 case TGSI_OPCODE_MOV:
3432 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3433 break;
3434
3435 case TGSI_OPCODE_LIT:
3436 exec_lit(mach, inst);
3437 break;
3438
3439 case TGSI_OPCODE_RCP:
3440 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3441 break;
3442
3443 case TGSI_OPCODE_RSQ:
3444 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3445 break;
3446
3447 case TGSI_OPCODE_EXP:
3448 exec_exp(mach, inst);
3449 break;
3450
3451 case TGSI_OPCODE_LOG:
3452 exec_log(mach, inst);
3453 break;
3454
3455 case TGSI_OPCODE_MUL:
3456 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3457 break;
3458
3459 case TGSI_OPCODE_ADD:
3460 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3461 break;
3462
3463 case TGSI_OPCODE_DP3:
3464 exec_dp3(mach, inst);
3465 break;
3466
3467 case TGSI_OPCODE_DP4:
3468 exec_dp4(mach, inst);
3469 break;
3470
3471 case TGSI_OPCODE_DST:
3472 exec_dst(mach, inst);
3473 break;
3474
3475 case TGSI_OPCODE_MIN:
3476 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3477 break;
3478
3479 case TGSI_OPCODE_MAX:
3480 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3481 break;
3482
3483 case TGSI_OPCODE_SLT:
3484 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3485 break;
3486
3487 case TGSI_OPCODE_SGE:
3488 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3489 break;
3490
3491 case TGSI_OPCODE_MAD:
3492 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3493 break;
3494
3495 case TGSI_OPCODE_SUB:
3496 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3497 break;
3498
3499 case TGSI_OPCODE_LRP:
3500 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3501 break;
3502
3503 case TGSI_OPCODE_CND:
3504 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3505 break;
3506
3507 case TGSI_OPCODE_DP2A:
3508 exec_dp2a(mach, inst);
3509 break;
3510
3511 case TGSI_OPCODE_FRC:
3512 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3513 break;
3514
3515 case TGSI_OPCODE_CLAMP:
3516 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3517 break;
3518
3519 case TGSI_OPCODE_FLR:
3520 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3521 break;
3522
3523 case TGSI_OPCODE_ROUND:
3524 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3525 break;
3526
3527 case TGSI_OPCODE_EX2:
3528 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3529 break;
3530
3531 case TGSI_OPCODE_LG2:
3532 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3533 break;
3534
3535 case TGSI_OPCODE_POW:
3536 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3537 break;
3538
3539 case TGSI_OPCODE_XPD:
3540 exec_xpd(mach, inst);
3541 break;
3542
3543 case TGSI_OPCODE_ABS:
3544 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3545 break;
3546
3547 case TGSI_OPCODE_RCC:
3548 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3549 break;
3550
3551 case TGSI_OPCODE_DPH:
3552 exec_dph(mach, inst);
3553 break;
3554
3555 case TGSI_OPCODE_COS:
3556 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3557 break;
3558
3559 case TGSI_OPCODE_DDX:
3560 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3561 break;
3562
3563 case TGSI_OPCODE_DDY:
3564 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3565 break;
3566
3567 case TGSI_OPCODE_KILP:
3568 exec_kilp (mach, inst);
3569 break;
3570
3571 case TGSI_OPCODE_KIL:
3572 exec_kil (mach, inst);
3573 break;
3574
3575 case TGSI_OPCODE_PK2H:
3576 assert (0);
3577 break;
3578
3579 case TGSI_OPCODE_PK2US:
3580 assert (0);
3581 break;
3582
3583 case TGSI_OPCODE_PK4B:
3584 assert (0);
3585 break;
3586
3587 case TGSI_OPCODE_PK4UB:
3588 assert (0);
3589 break;
3590
3591 case TGSI_OPCODE_RFL:
3592 exec_rfl(mach, inst);
3593 break;
3594
3595 case TGSI_OPCODE_SEQ:
3596 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3597 break;
3598
3599 case TGSI_OPCODE_SFL:
3600 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3601 break;
3602
3603 case TGSI_OPCODE_SGT:
3604 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3605 break;
3606
3607 case TGSI_OPCODE_SIN:
3608 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3609 break;
3610
3611 case TGSI_OPCODE_SLE:
3612 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3613 break;
3614
3615 case TGSI_OPCODE_SNE:
3616 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3617 break;
3618
3619 case TGSI_OPCODE_STR:
3620 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3621 break;
3622
3623 case TGSI_OPCODE_TEX:
3624 /* simple texture lookup */
3625 /* src[0] = texcoord */
3626 /* src[1] = sampler unit */
3627 exec_tex(mach, inst, TEX_MODIFIER_NONE);
3628 break;
3629
3630 case TGSI_OPCODE_TXB:
3631 /* Texture lookup with lod bias */
3632 /* src[0] = texcoord (src[0].w = LOD bias) */
3633 /* src[1] = sampler unit */
3634 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
3635 break;
3636
3637 case TGSI_OPCODE_TXD:
3638 /* Texture lookup with explict partial derivatives */
3639 /* src[0] = texcoord */
3640 /* src[1] = d[strq]/dx */
3641 /* src[2] = d[strq]/dy */
3642 /* src[3] = sampler unit */
3643 exec_txd(mach, inst);
3644 break;
3645
3646 case TGSI_OPCODE_TXL:
3647 /* Texture lookup with explit LOD */
3648 /* src[0] = texcoord (src[0].w = LOD) */
3649 /* src[1] = sampler unit */
3650 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3651 break;
3652
3653 case TGSI_OPCODE_TXP:
3654 /* Texture lookup with projection */
3655 /* src[0] = texcoord (src[0].w = projection) */
3656 /* src[1] = sampler unit */
3657 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
3658 break;
3659
3660 case TGSI_OPCODE_UP2H:
3661 assert (0);
3662 break;
3663
3664 case TGSI_OPCODE_UP2US:
3665 assert (0);
3666 break;
3667
3668 case TGSI_OPCODE_UP4B:
3669 assert (0);
3670 break;
3671
3672 case TGSI_OPCODE_UP4UB:
3673 assert (0);
3674 break;
3675
3676 case TGSI_OPCODE_X2D:
3677 exec_x2d(mach, inst);
3678 break;
3679
3680 case TGSI_OPCODE_ARA:
3681 assert (0);
3682 break;
3683
3684 case TGSI_OPCODE_ARR:
3685 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3686 break;
3687
3688 case TGSI_OPCODE_BRA:
3689 assert (0);
3690 break;
3691
3692 case TGSI_OPCODE_CAL:
3693 /* skip the call if no execution channels are enabled */
3694 if (mach->ExecMask) {
3695 /* do the call */
3696
3697 /* First, record the depths of the execution stacks.
3698 * This is important for deeply nested/looped return statements.
3699 * We have to unwind the stacks by the correct amount. For a
3700 * real code generator, we could determine the number of entries
3701 * to pop off each stack with simple static analysis and avoid
3702 * implementing this data structure at run time.
3703 */
3704 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3705 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3706 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3707 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3708 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3709 /* note that PC was already incremented above */
3710 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3711
3712 mach->CallStackTop++;
3713
3714 /* Second, push the Cond, Loop, Cont, Func stacks */
3715 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3716 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3717 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3718 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3719 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3720 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3721
3722 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3723 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3724 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3725 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3726 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3727 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3728
3729 /* Finally, jump to the subroutine */
3730 *pc = inst->Label.Label;
3731 }
3732 break;
3733
3734 case TGSI_OPCODE_RET:
3735 mach->FuncMask &= ~mach->ExecMask;
3736 UPDATE_EXEC_MASK(mach);
3737
3738 if (mach->FuncMask == 0x0) {
3739 /* really return now (otherwise, keep executing */
3740
3741 if (mach->CallStackTop == 0) {
3742 /* returning from main() */
3743 mach->CondStackTop = 0;
3744 mach->LoopStackTop = 0;
3745 *pc = -1;
3746 return;
3747 }
3748
3749 assert(mach->CallStackTop > 0);
3750 mach->CallStackTop--;
3751
3752 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3753 mach->CondMask = mach->CondStack[mach->CondStackTop];
3754
3755 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3756 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3757
3758 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3759 mach->ContMask = mach->ContStack[mach->ContStackTop];
3760
3761 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3762 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3763
3764 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3765 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3766
3767 assert(mach->FuncStackTop > 0);
3768 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3769
3770 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3771
3772 UPDATE_EXEC_MASK(mach);
3773 }
3774 break;
3775
3776 case TGSI_OPCODE_SSG:
3777 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3778 break;
3779
3780 case TGSI_OPCODE_CMP:
3781 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3782 break;
3783
3784 case TGSI_OPCODE_SCS:
3785 exec_scs(mach, inst);
3786 break;
3787
3788 case TGSI_OPCODE_NRM:
3789 exec_nrm3(mach, inst);
3790 break;
3791
3792 case TGSI_OPCODE_NRM4:
3793 exec_nrm4(mach, inst);
3794 break;
3795
3796 case TGSI_OPCODE_DIV:
3797 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3798 break;
3799
3800 case TGSI_OPCODE_DP2:
3801 exec_dp2(mach, inst);
3802 break;
3803
3804 case TGSI_OPCODE_IF:
3805 /* push CondMask */
3806 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3807 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3808 FETCH( &r[0], 0, CHAN_X );
3809 /* update CondMask */
3810 if( ! r[0].u[0] ) {
3811 mach->CondMask &= ~0x1;
3812 }
3813 if( ! r[0].u[1] ) {
3814 mach->CondMask &= ~0x2;
3815 }
3816 if( ! r[0].u[2] ) {
3817 mach->CondMask &= ~0x4;
3818 }
3819 if( ! r[0].u[3] ) {
3820 mach->CondMask &= ~0x8;
3821 }
3822 UPDATE_EXEC_MASK(mach);
3823 /* Todo: If CondMask==0, jump to ELSE */
3824 break;
3825
3826 case TGSI_OPCODE_ELSE:
3827 /* invert CondMask wrt previous mask */
3828 {
3829 uint prevMask;
3830 assert(mach->CondStackTop > 0);
3831 prevMask = mach->CondStack[mach->CondStackTop - 1];
3832 mach->CondMask = ~mach->CondMask & prevMask;
3833 UPDATE_EXEC_MASK(mach);
3834 /* Todo: If CondMask==0, jump to ENDIF */
3835 }
3836 break;
3837
3838 case TGSI_OPCODE_ENDIF:
3839 /* pop CondMask */
3840 assert(mach->CondStackTop > 0);
3841 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3842 UPDATE_EXEC_MASK(mach);
3843 break;
3844
3845 case TGSI_OPCODE_END:
3846 /* make sure we end primitives which haven't
3847 * been explicitly emitted */
3848 conditional_emit_primitive(mach);
3849 /* halt execution */
3850 *pc = -1;
3851 break;
3852
3853 case TGSI_OPCODE_PUSHA:
3854 assert (0);
3855 break;
3856
3857 case TGSI_OPCODE_POPA:
3858 assert (0);
3859 break;
3860
3861 case TGSI_OPCODE_CEIL:
3862 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3863 break;
3864
3865 case TGSI_OPCODE_I2F:
3866 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3867 break;
3868
3869 case TGSI_OPCODE_NOT:
3870 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3871 break;
3872
3873 case TGSI_OPCODE_TRUNC:
3874 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3875 break;
3876
3877 case TGSI_OPCODE_SHL:
3878 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3879 break;
3880
3881 case TGSI_OPCODE_AND:
3882 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3883 break;
3884
3885 case TGSI_OPCODE_OR:
3886 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3887 break;
3888
3889 case TGSI_OPCODE_MOD:
3890 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3891 break;
3892
3893 case TGSI_OPCODE_XOR:
3894 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3895 break;
3896
3897 case TGSI_OPCODE_SAD:
3898 assert (0);
3899 break;
3900
3901 case TGSI_OPCODE_TXF:
3902 exec_txf(mach, inst);
3903 break;
3904
3905 case TGSI_OPCODE_TXQ:
3906 exec_txq(mach, inst);
3907 break;
3908
3909 case TGSI_OPCODE_EMIT:
3910 emit_vertex(mach);
3911 break;
3912
3913 case TGSI_OPCODE_ENDPRIM:
3914 emit_primitive(mach);
3915 break;
3916
3917 case TGSI_OPCODE_BGNLOOP:
3918 /* push LoopMask and ContMasks */
3919 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3920 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3921 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3922 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3923
3924 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3925 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3926 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3927 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3928 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3929 break;
3930
3931 case TGSI_OPCODE_ENDLOOP:
3932 /* Restore ContMask, but don't pop */
3933 assert(mach->ContStackTop > 0);
3934 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3935 UPDATE_EXEC_MASK(mach);
3936 if (mach->ExecMask) {
3937 /* repeat loop: jump to instruction just past BGNLOOP */
3938 assert(mach->LoopLabelStackTop > 0);
3939 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3940 }
3941 else {
3942 /* exit loop: pop LoopMask */
3943 assert(mach->LoopStackTop > 0);
3944 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3945 /* pop ContMask */
3946 assert(mach->ContStackTop > 0);
3947 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3948 assert(mach->LoopLabelStackTop > 0);
3949 --mach->LoopLabelStackTop;
3950
3951 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3952 }
3953 UPDATE_EXEC_MASK(mach);
3954 break;
3955
3956 case TGSI_OPCODE_BRK:
3957 exec_break(mach);
3958 break;
3959
3960 case TGSI_OPCODE_CONT:
3961 /* turn off cont channels for each enabled exec channel */
3962 mach->ContMask &= ~mach->ExecMask;
3963 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3964 UPDATE_EXEC_MASK(mach);
3965 break;
3966
3967 case TGSI_OPCODE_BGNSUB:
3968 /* no-op */
3969 break;
3970
3971 case TGSI_OPCODE_ENDSUB:
3972 /*
3973 * XXX: This really should be a no-op. We should never reach this opcode.
3974 */
3975
3976 assert(mach->CallStackTop > 0);
3977 mach->CallStackTop--;
3978
3979 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3980 mach->CondMask = mach->CondStack[mach->CondStackTop];
3981
3982 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3983 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3984
3985 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3986 mach->ContMask = mach->ContStack[mach->ContStackTop];
3987
3988 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3989 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3990
3991 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3992 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3993
3994 assert(mach->FuncStackTop > 0);
3995 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3996
3997 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3998
3999 UPDATE_EXEC_MASK(mach);
4000 break;
4001
4002 case TGSI_OPCODE_NOP:
4003 break;
4004
4005 case TGSI_OPCODE_BREAKC:
4006 FETCH(&r[0], 0, CHAN_X);
4007 /* update CondMask */
4008 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4009 mach->LoopMask &= ~0x1;
4010 }
4011 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4012 mach->LoopMask &= ~0x2;
4013 }
4014 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4015 mach->LoopMask &= ~0x4;
4016 }
4017 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4018 mach->LoopMask &= ~0x8;
4019 }
4020 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4021 UPDATE_EXEC_MASK(mach);
4022 break;
4023
4024 case TGSI_OPCODE_F2I:
4025 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4026 break;
4027
4028 case TGSI_OPCODE_IDIV:
4029 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4030 break;
4031
4032 case TGSI_OPCODE_IMAX:
4033 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4034 break;
4035
4036 case TGSI_OPCODE_IMIN:
4037 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4038 break;
4039
4040 case TGSI_OPCODE_INEG:
4041 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4042 break;
4043
4044 case TGSI_OPCODE_ISGE:
4045 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4046 break;
4047
4048 case TGSI_OPCODE_ISHR:
4049 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4050 break;
4051
4052 case TGSI_OPCODE_ISLT:
4053 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4054 break;
4055
4056 case TGSI_OPCODE_F2U:
4057 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4058 break;
4059
4060 case TGSI_OPCODE_U2F:
4061 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4062 break;
4063
4064 case TGSI_OPCODE_UADD:
4065 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4066 break;
4067
4068 case TGSI_OPCODE_UDIV:
4069 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4070 break;
4071
4072 case TGSI_OPCODE_UMAD:
4073 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4074 break;
4075
4076 case TGSI_OPCODE_UMAX:
4077 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4078 break;
4079
4080 case TGSI_OPCODE_UMIN:
4081 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4082 break;
4083
4084 case TGSI_OPCODE_UMOD:
4085 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4086 break;
4087
4088 case TGSI_OPCODE_UMUL:
4089 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4090 break;
4091
4092 case TGSI_OPCODE_USEQ:
4093 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4094 break;
4095
4096 case TGSI_OPCODE_USGE:
4097 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4098 break;
4099
4100 case TGSI_OPCODE_USHR:
4101 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4102 break;
4103
4104 case TGSI_OPCODE_USLT:
4105 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4106 break;
4107
4108 case TGSI_OPCODE_USNE:
4109 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4110 break;
4111
4112 case TGSI_OPCODE_SWITCH:
4113 exec_switch(mach, inst);
4114 break;
4115
4116 case TGSI_OPCODE_CASE:
4117 exec_case(mach, inst);
4118 break;
4119
4120 case TGSI_OPCODE_DEFAULT:
4121 exec_default(mach);
4122 break;
4123
4124 case TGSI_OPCODE_ENDSWITCH:
4125 exec_endswitch(mach);
4126 break;
4127
4128 case TGSI_OPCODE_LOAD:
4129 assert(0);
4130 break;
4131
4132 case TGSI_OPCODE_LOAD_MS:
4133 assert(0);
4134 break;
4135
4136 case TGSI_OPCODE_SAMPLE:
4137 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4138 break;
4139
4140 case TGSI_OPCODE_SAMPLE_B:
4141 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4142 break;
4143
4144 case TGSI_OPCODE_SAMPLE_C:
4145 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4146 break;
4147
4148 case TGSI_OPCODE_SAMPLE_C_LZ:
4149 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4150 break;
4151
4152 case TGSI_OPCODE_SAMPLE_D:
4153 exec_sample_d(mach, inst);
4154 break;
4155
4156 case TGSI_OPCODE_SAMPLE_L:
4157 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
4158 break;
4159
4160 case TGSI_OPCODE_GATHER4:
4161 assert(0);
4162 break;
4163
4164 case TGSI_OPCODE_RESINFO:
4165 assert(0);
4166 break;
4167
4168 case TGSI_OPCODE_SAMPLE_POS:
4169 assert(0);
4170 break;
4171
4172 case TGSI_OPCODE_SAMPLE_INFO:
4173 assert(0);
4174 break;
4175
4176 case TGSI_OPCODE_UARL:
4177 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4178 break;
4179
4180 case TGSI_OPCODE_UCMP:
4181 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4182 break;
4183
4184 default:
4185 assert( 0 );
4186 }
4187 }
4188
4189
4190 #define DEBUG_EXECUTION 0
4191
4192
4193 /**
4194 * Run TGSI interpreter.
4195 * \return bitmask of "alive" quad components
4196 */
4197 uint
4198 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4199 {
4200 uint i;
4201 int pc = 0;
4202
4203 mach->CondMask = 0xf;
4204 mach->LoopMask = 0xf;
4205 mach->ContMask = 0xf;
4206 mach->FuncMask = 0xf;
4207 mach->ExecMask = 0xf;
4208
4209 mach->Switch.mask = 0xf;
4210
4211 assert(mach->CondStackTop == 0);
4212 assert(mach->LoopStackTop == 0);
4213 assert(mach->ContStackTop == 0);
4214 assert(mach->SwitchStackTop == 0);
4215 assert(mach->BreakStackTop == 0);
4216 assert(mach->CallStackTop == 0);
4217
4218 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4219 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4220
4221 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4222 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4223 mach->Primitives[0] = 0;
4224 }
4225
4226 /* execute declarations (interpolants) */
4227 for (i = 0; i < mach->NumDeclarations; i++) {
4228 exec_declaration( mach, mach->Declarations+i );
4229 }
4230
4231 {
4232 #if DEBUG_EXECUTION
4233 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4234 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4235 uint inst = 1;
4236
4237 memcpy(temps, mach->Temps, sizeof(temps));
4238 memcpy(outputs, mach->Outputs, sizeof(outputs));
4239 #endif
4240
4241 /* execute instructions, until pc is set to -1 */
4242 while (pc != -1) {
4243
4244 #if DEBUG_EXECUTION
4245 uint i;
4246
4247 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4248 #endif
4249
4250 assert(pc < (int) mach->NumInstructions);
4251 exec_instruction(mach, mach->Instructions + pc, &pc);
4252
4253 #if DEBUG_EXECUTION
4254 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4255 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4256 uint j;
4257
4258 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4259 debug_printf("TEMP[%2u] = ", i);
4260 for (j = 0; j < 4; j++) {
4261 if (j > 0) {
4262 debug_printf(" ");
4263 }
4264 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4265 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4266 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4267 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4268 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4269 }
4270 }
4271 }
4272 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4273 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4274 uint j;
4275
4276 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4277 debug_printf("OUT[%2u] = ", i);
4278 for (j = 0; j < 4; j++) {
4279 if (j > 0) {
4280 debug_printf(" ");
4281 }
4282 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4283 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4284 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4285 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4286 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4287 }
4288 }
4289 }
4290 #endif
4291 }
4292 }
4293
4294 #if 0
4295 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4296 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4297 /*
4298 * Scale back depth component.
4299 */
4300 for (i = 0; i < 4; i++)
4301 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4302 }
4303 #endif
4304
4305 /* Strictly speaking, these assertions aren't really needed but they
4306 * can potentially catch some bugs in the control flow code.
4307 */
4308 assert(mach->CondStackTop == 0);
4309 assert(mach->LoopStackTop == 0);
4310 assert(mach->ContStackTop == 0);
4311 assert(mach->SwitchStackTop == 0);
4312 assert(mach->BreakStackTop == 0);
4313 assert(mach->CallStackTop == 0);
4314
4315 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4316 }