1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_cmp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
142 micro_cos(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src
)
145 dst
->f
[0] = cosf(src
->f
[0]);
146 dst
->f
[1] = cosf(src
->f
[1]);
147 dst
->f
[2] = cosf(src
->f
[2]);
148 dst
->f
[3] = cosf(src
->f
[3]);
152 micro_d2f(union tgsi_exec_channel
*dst
,
153 const union tgsi_double_channel
*src
)
155 dst
->f
[0] = (float)src
->d
[0];
156 dst
->f
[1] = (float)src
->d
[1];
157 dst
->f
[2] = (float)src
->d
[2];
158 dst
->f
[3] = (float)src
->d
[3];
162 micro_d2i(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->i
[0] = (int)src
->d
[0];
166 dst
->i
[1] = (int)src
->d
[1];
167 dst
->i
[2] = (int)src
->d
[2];
168 dst
->i
[3] = (int)src
->d
[3];
172 micro_d2u(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->u
[0] = (unsigned)src
->d
[0];
176 dst
->u
[1] = (unsigned)src
->d
[1];
177 dst
->u
[2] = (unsigned)src
->d
[2];
178 dst
->u
[3] = (unsigned)src
->d
[3];
181 micro_dabs(union tgsi_double_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
185 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
186 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
187 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
191 micro_dadd(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
195 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
196 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
197 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
201 micro_ddiv(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] / src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] / src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] / src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] / src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddy(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
231 micro_dmul(union tgsi_double_channel
*dst
,
232 const union tgsi_double_channel
*src
)
234 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
235 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
236 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
237 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
241 micro_dmax(union tgsi_double_channel
*dst
,
242 const union tgsi_double_channel
*src
)
244 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
245 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
246 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
247 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
251 micro_dmin(union tgsi_double_channel
*dst
,
252 const union tgsi_double_channel
*src
)
254 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
255 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
256 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
257 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
261 micro_dneg(union tgsi_double_channel
*dst
,
262 const union tgsi_double_channel
*src
)
264 dst
->d
[0] = -src
->d
[0];
265 dst
->d
[1] = -src
->d
[1];
266 dst
->d
[2] = -src
->d
[2];
267 dst
->d
[3] = -src
->d
[3];
271 micro_dslt(union tgsi_double_channel
*dst
,
272 const union tgsi_double_channel
*src
)
274 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
275 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
276 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
277 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
281 micro_dsne(union tgsi_double_channel
*dst
,
282 const union tgsi_double_channel
*src
)
284 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
285 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
286 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
287 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
291 micro_dsge(union tgsi_double_channel
*dst
,
292 const union tgsi_double_channel
*src
)
294 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
295 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
296 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
297 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
301 micro_dseq(union tgsi_double_channel
*dst
,
302 const union tgsi_double_channel
*src
)
304 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
305 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
306 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
307 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
311 micro_drcp(union tgsi_double_channel
*dst
,
312 const union tgsi_double_channel
*src
)
314 dst
->d
[0] = 1.0 / src
->d
[0];
315 dst
->d
[1] = 1.0 / src
->d
[1];
316 dst
->d
[2] = 1.0 / src
->d
[2];
317 dst
->d
[3] = 1.0 / src
->d
[3];
321 micro_dsqrt(union tgsi_double_channel
*dst
,
322 const union tgsi_double_channel
*src
)
324 dst
->d
[0] = sqrt(src
->d
[0]);
325 dst
->d
[1] = sqrt(src
->d
[1]);
326 dst
->d
[2] = sqrt(src
->d
[2]);
327 dst
->d
[3] = sqrt(src
->d
[3]);
331 micro_drsq(union tgsi_double_channel
*dst
,
332 const union tgsi_double_channel
*src
)
334 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
335 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
336 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
337 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
341 micro_dmad(union tgsi_double_channel
*dst
,
342 const union tgsi_double_channel
*src
)
344 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
345 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
346 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
347 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
351 micro_dfrac(union tgsi_double_channel
*dst
,
352 const union tgsi_double_channel
*src
)
354 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
355 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
356 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
357 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
361 micro_dldexp(union tgsi_double_channel
*dst
,
362 const union tgsi_double_channel
*src0
,
363 union tgsi_exec_channel
*src1
)
365 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
366 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
367 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
368 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
372 micro_dfracexp(union tgsi_double_channel
*dst
,
373 union tgsi_exec_channel
*dst_exp
,
374 const union tgsi_double_channel
*src
)
376 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
377 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
378 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
379 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
383 micro_exp2(union tgsi_exec_channel
*dst
,
384 const union tgsi_exec_channel
*src
)
387 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
388 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
389 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
390 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
395 union tgsi_exec_channel clamped
;
397 for (i
= 0; i
< 4; i
++) {
398 if (src
->f
[i
] > 127.99999f
) {
399 clamped
.f
[i
] = 127.99999f
;
400 } else if (src
->f
[i
] < -126.99999f
) {
401 clamped
.f
[i
] = -126.99999f
;
403 clamped
.f
[i
] = src
->f
[i
];
409 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
410 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
411 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
412 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
413 #endif /* FAST_MATH */
417 micro_f2d(union tgsi_double_channel
*dst
,
418 const union tgsi_exec_channel
*src
)
420 dst
->d
[0] = (double)src
->f
[0];
421 dst
->d
[1] = (double)src
->f
[1];
422 dst
->d
[2] = (double)src
->f
[2];
423 dst
->d
[3] = (double)src
->f
[3];
427 micro_flr(union tgsi_exec_channel
*dst
,
428 const union tgsi_exec_channel
*src
)
430 dst
->f
[0] = floorf(src
->f
[0]);
431 dst
->f
[1] = floorf(src
->f
[1]);
432 dst
->f
[2] = floorf(src
->f
[2]);
433 dst
->f
[3] = floorf(src
->f
[3]);
437 micro_frc(union tgsi_exec_channel
*dst
,
438 const union tgsi_exec_channel
*src
)
440 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
441 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
442 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
443 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
447 micro_i2d(union tgsi_double_channel
*dst
,
448 const union tgsi_exec_channel
*src
)
450 dst
->d
[0] = (double)src
->i
[0];
451 dst
->d
[1] = (double)src
->i
[1];
452 dst
->d
[2] = (double)src
->i
[2];
453 dst
->d
[3] = (double)src
->i
[3];
457 micro_iabs(union tgsi_exec_channel
*dst
,
458 const union tgsi_exec_channel
*src
)
460 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
461 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
462 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
463 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
467 micro_ineg(union tgsi_exec_channel
*dst
,
468 const union tgsi_exec_channel
*src
)
470 dst
->i
[0] = -src
->i
[0];
471 dst
->i
[1] = -src
->i
[1];
472 dst
->i
[2] = -src
->i
[2];
473 dst
->i
[3] = -src
->i
[3];
477 micro_lg2(union tgsi_exec_channel
*dst
,
478 const union tgsi_exec_channel
*src
)
481 dst
->f
[0] = util_fast_log2(src
->f
[0]);
482 dst
->f
[1] = util_fast_log2(src
->f
[1]);
483 dst
->f
[2] = util_fast_log2(src
->f
[2]);
484 dst
->f
[3] = util_fast_log2(src
->f
[3]);
486 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
487 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
488 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
489 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
494 micro_lrp(union tgsi_exec_channel
*dst
,
495 const union tgsi_exec_channel
*src0
,
496 const union tgsi_exec_channel
*src1
,
497 const union tgsi_exec_channel
*src2
)
499 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
500 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
501 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
502 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
506 micro_mad(union tgsi_exec_channel
*dst
,
507 const union tgsi_exec_channel
*src0
,
508 const union tgsi_exec_channel
*src1
,
509 const union tgsi_exec_channel
*src2
)
511 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
512 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
513 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
514 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
518 micro_mov(union tgsi_exec_channel
*dst
,
519 const union tgsi_exec_channel
*src
)
521 dst
->u
[0] = src
->u
[0];
522 dst
->u
[1] = src
->u
[1];
523 dst
->u
[2] = src
->u
[2];
524 dst
->u
[3] = src
->u
[3];
528 micro_rcp(union tgsi_exec_channel
*dst
,
529 const union tgsi_exec_channel
*src
)
531 #if 0 /* for debugging */
532 assert(src
->f
[0] != 0.0f
);
533 assert(src
->f
[1] != 0.0f
);
534 assert(src
->f
[2] != 0.0f
);
535 assert(src
->f
[3] != 0.0f
);
537 dst
->f
[0] = 1.0f
/ src
->f
[0];
538 dst
->f
[1] = 1.0f
/ src
->f
[1];
539 dst
->f
[2] = 1.0f
/ src
->f
[2];
540 dst
->f
[3] = 1.0f
/ src
->f
[3];
544 micro_rnd(union tgsi_exec_channel
*dst
,
545 const union tgsi_exec_channel
*src
)
547 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
548 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
549 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
550 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
554 micro_rsq(union tgsi_exec_channel
*dst
,
555 const union tgsi_exec_channel
*src
)
557 #if 0 /* for debugging */
558 assert(src
->f
[0] != 0.0f
);
559 assert(src
->f
[1] != 0.0f
);
560 assert(src
->f
[2] != 0.0f
);
561 assert(src
->f
[3] != 0.0f
);
563 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
564 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
565 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
566 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
570 micro_sqrt(union tgsi_exec_channel
*dst
,
571 const union tgsi_exec_channel
*src
)
573 dst
->f
[0] = sqrtf(src
->f
[0]);
574 dst
->f
[1] = sqrtf(src
->f
[1]);
575 dst
->f
[2] = sqrtf(src
->f
[2]);
576 dst
->f
[3] = sqrtf(src
->f
[3]);
580 micro_seq(union tgsi_exec_channel
*dst
,
581 const union tgsi_exec_channel
*src0
,
582 const union tgsi_exec_channel
*src1
)
584 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
585 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
586 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
587 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
591 micro_sge(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src0
,
593 const union tgsi_exec_channel
*src1
)
595 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
596 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
597 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
598 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
602 micro_sgn(union tgsi_exec_channel
*dst
,
603 const union tgsi_exec_channel
*src
)
605 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
608 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
612 micro_isgn(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src
)
615 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
616 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
617 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
618 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
622 micro_sgt(union tgsi_exec_channel
*dst
,
623 const union tgsi_exec_channel
*src0
,
624 const union tgsi_exec_channel
*src1
)
626 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
627 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
628 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
629 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
633 micro_sin(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->f
[0] = sinf(src
->f
[0]);
637 dst
->f
[1] = sinf(src
->f
[1]);
638 dst
->f
[2] = sinf(src
->f
[2]);
639 dst
->f
[3] = sinf(src
->f
[3]);
643 micro_sle(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_slt(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src0
,
656 const union tgsi_exec_channel
*src1
)
658 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
659 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
660 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
661 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
665 micro_sne(union tgsi_exec_channel
*dst
,
666 const union tgsi_exec_channel
*src0
,
667 const union tgsi_exec_channel
*src1
)
669 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
670 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
671 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
672 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
676 micro_trunc(union tgsi_exec_channel
*dst
,
677 const union tgsi_exec_channel
*src
)
679 dst
->f
[0] = truncf(src
->f
[0]);
680 dst
->f
[1] = truncf(src
->f
[1]);
681 dst
->f
[2] = truncf(src
->f
[2]);
682 dst
->f
[3] = truncf(src
->f
[3]);
686 micro_u2d(union tgsi_double_channel
*dst
,
687 const union tgsi_exec_channel
*src
)
689 dst
->d
[0] = (double)src
->u
[0];
690 dst
->d
[1] = (double)src
->u
[1];
691 dst
->d
[2] = (double)src
->u
[2];
692 dst
->d
[3] = (double)src
->u
[3];
696 micro_i64abs(union tgsi_double_channel
*dst
,
697 const union tgsi_double_channel
*src
)
699 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
700 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
701 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
702 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
706 micro_i64sgn(union tgsi_double_channel
*dst
,
707 const union tgsi_double_channel
*src
)
709 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
710 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
711 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
712 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
716 micro_i64neg(union tgsi_double_channel
*dst
,
717 const union tgsi_double_channel
*src
)
719 dst
->i64
[0] = -src
->i64
[0];
720 dst
->i64
[1] = -src
->i64
[1];
721 dst
->i64
[2] = -src
->i64
[2];
722 dst
->i64
[3] = -src
->i64
[3];
726 micro_u64seq(union tgsi_double_channel
*dst
,
727 const union tgsi_double_channel
*src
)
729 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
730 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
731 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
732 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
736 micro_u64sne(union tgsi_double_channel
*dst
,
737 const union tgsi_double_channel
*src
)
739 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
740 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
741 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
742 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
746 micro_i64slt(union tgsi_double_channel
*dst
,
747 const union tgsi_double_channel
*src
)
749 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
750 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
751 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
752 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
756 micro_u64slt(union tgsi_double_channel
*dst
,
757 const union tgsi_double_channel
*src
)
759 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
760 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
761 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
762 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
766 micro_i64sge(union tgsi_double_channel
*dst
,
767 const union tgsi_double_channel
*src
)
769 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
770 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
771 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
772 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
776 micro_u64sge(union tgsi_double_channel
*dst
,
777 const union tgsi_double_channel
*src
)
779 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
780 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
781 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
782 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
786 micro_u64max(union tgsi_double_channel
*dst
,
787 const union tgsi_double_channel
*src
)
789 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
790 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
791 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
792 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
796 micro_i64max(union tgsi_double_channel
*dst
,
797 const union tgsi_double_channel
*src
)
799 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
800 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
801 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
802 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
806 micro_u64min(union tgsi_double_channel
*dst
,
807 const union tgsi_double_channel
*src
)
809 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
810 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
811 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
812 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
816 micro_i64min(union tgsi_double_channel
*dst
,
817 const union tgsi_double_channel
*src
)
819 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
820 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
821 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
822 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
826 micro_u64add(union tgsi_double_channel
*dst
,
827 const union tgsi_double_channel
*src
)
829 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
830 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
831 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
832 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
836 micro_u64mul(union tgsi_double_channel
*dst
,
837 const union tgsi_double_channel
*src
)
839 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
840 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
841 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
842 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
846 micro_u64div(union tgsi_double_channel
*dst
,
847 const union tgsi_double_channel
*src
)
849 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] / src
[1].u64
[0] : ~0ull;
850 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] / src
[1].u64
[1] : ~0ull;
851 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] / src
[1].u64
[2] : ~0ull;
852 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] / src
[1].u64
[3] : ~0ull;
856 micro_i64div(union tgsi_double_channel
*dst
,
857 const union tgsi_double_channel
*src
)
859 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] / src
[1].i64
[0] : 0;
860 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] / src
[1].i64
[1] : 0;
861 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] / src
[1].i64
[2] : 0;
862 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] / src
[1].i64
[3] : 0;
866 micro_u64mod(union tgsi_double_channel
*dst
,
867 const union tgsi_double_channel
*src
)
869 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] % src
[1].u64
[0] : ~0ull;
870 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] % src
[1].u64
[1] : ~0ull;
871 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] % src
[1].u64
[2] : ~0ull;
872 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] % src
[1].u64
[3] : ~0ull;
876 micro_i64mod(union tgsi_double_channel
*dst
,
877 const union tgsi_double_channel
*src
)
879 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] % src
[1].i64
[0] : ~0ll;
880 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] % src
[1].i64
[1] : ~0ll;
881 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] % src
[1].i64
[2] : ~0ll;
882 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] % src
[1].i64
[3] : ~0ll;
886 micro_u64shl(union tgsi_double_channel
*dst
,
887 const union tgsi_double_channel
*src0
,
888 union tgsi_exec_channel
*src1
)
890 unsigned masked_count
;
891 masked_count
= src1
->u
[0] & 0x3f;
892 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
893 masked_count
= src1
->u
[1] & 0x3f;
894 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
895 masked_count
= src1
->u
[2] & 0x3f;
896 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
897 masked_count
= src1
->u
[3] & 0x3f;
898 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
902 micro_i64shr(union tgsi_double_channel
*dst
,
903 const union tgsi_double_channel
*src0
,
904 union tgsi_exec_channel
*src1
)
906 unsigned masked_count
;
907 masked_count
= src1
->u
[0] & 0x3f;
908 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
909 masked_count
= src1
->u
[1] & 0x3f;
910 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
911 masked_count
= src1
->u
[2] & 0x3f;
912 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
913 masked_count
= src1
->u
[3] & 0x3f;
914 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
918 micro_u64shr(union tgsi_double_channel
*dst
,
919 const union tgsi_double_channel
*src0
,
920 union tgsi_exec_channel
*src1
)
922 unsigned masked_count
;
923 masked_count
= src1
->u
[0] & 0x3f;
924 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
925 masked_count
= src1
->u
[1] & 0x3f;
926 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
927 masked_count
= src1
->u
[2] & 0x3f;
928 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
929 masked_count
= src1
->u
[3] & 0x3f;
930 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
933 enum tgsi_exec_datatype
{
934 TGSI_EXEC_DATA_FLOAT
,
937 TGSI_EXEC_DATA_DOUBLE
,
938 TGSI_EXEC_DATA_INT64
,
939 TGSI_EXEC_DATA_UINT64
,
943 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
945 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
946 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
947 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
948 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
949 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
950 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
953 /** The execution mask depends on the conditional mask and the loop mask */
954 #define UPDATE_EXEC_MASK(MACH) \
955 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
958 static const union tgsi_exec_channel ZeroVec
=
959 { { 0.0, 0.0, 0.0, 0.0 } };
961 static const union tgsi_exec_channel OneVec
= {
962 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
965 static const union tgsi_exec_channel P128Vec
= {
966 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
969 static const union tgsi_exec_channel M128Vec
= {
970 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
975 * Assert that none of the float values in 'chan' are infinite or NaN.
976 * NaN and Inf may occur normally during program execution and should
977 * not lead to crashes, etc. But when debugging, it's helpful to catch
981 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
983 assert(!util_is_inf_or_nan((chan
)->f
[0]));
984 assert(!util_is_inf_or_nan((chan
)->f
[1]));
985 assert(!util_is_inf_or_nan((chan
)->f
[2]));
986 assert(!util_is_inf_or_nan((chan
)->f
[3]));
992 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
994 debug_printf("%s = {%f, %f, %f, %f}\n",
995 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1002 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1004 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1006 debug_printf("Temp[%u] =\n", index
);
1007 for (i
= 0; i
< 4; i
++) {
1008 debug_printf(" %c: { %f, %f, %f, %f }\n",
1020 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1023 const unsigned *buf_sizes
)
1027 for (i
= 0; i
< num_bufs
; i
++) {
1028 mach
->Consts
[i
] = bufs
[i
];
1029 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1035 * Check if there's a potential src/dst register data dependency when
1036 * using SOA execution.
1039 * This would expand into:
1044 * The second instruction will have the wrong value for t0 if executed as-is.
1047 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
1051 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
1052 if (writemask
== TGSI_WRITEMASK_X
||
1053 writemask
== TGSI_WRITEMASK_Y
||
1054 writemask
== TGSI_WRITEMASK_Z
||
1055 writemask
== TGSI_WRITEMASK_W
||
1056 writemask
== TGSI_WRITEMASK_NONE
) {
1057 /* no chance of data dependency */
1061 /* loop over src regs */
1062 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1063 if ((inst
->Src
[i
].Register
.File
==
1064 inst
->Dst
[0].Register
.File
) &&
1065 ((inst
->Src
[i
].Register
.Index
==
1066 inst
->Dst
[0].Register
.Index
) ||
1067 inst
->Src
[i
].Register
.Indirect
||
1068 inst
->Dst
[0].Register
.Indirect
)) {
1069 /* loop over dest channels */
1070 uint channelsWritten
= 0x0;
1071 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1072 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1073 /* check if we're reading a channel that's been written */
1074 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
1075 if (channelsWritten
& (1 << swizzle
)) {
1079 channelsWritten
|= (1 << chan
);
1089 * Initialize machine state by expanding tokens to full instructions,
1090 * allocating temporary storage, setting up constants, etc.
1091 * After this, we can call tgsi_exec_machine_run() many times.
1094 tgsi_exec_machine_bind_shader(
1095 struct tgsi_exec_machine
*mach
,
1096 const struct tgsi_token
*tokens
,
1097 struct tgsi_sampler
*sampler
,
1098 struct tgsi_image
*image
,
1099 struct tgsi_buffer
*buffer
)
1102 struct tgsi_parse_context parse
;
1103 struct tgsi_full_instruction
*instructions
;
1104 struct tgsi_full_declaration
*declarations
;
1105 uint maxInstructions
= 10, numInstructions
= 0;
1106 uint maxDeclarations
= 10, numDeclarations
= 0;
1109 tgsi_dump(tokens
, 0);
1115 mach
->Tokens
= tokens
;
1116 mach
->Sampler
= sampler
;
1117 mach
->Image
= image
;
1118 mach
->Buffer
= buffer
;
1121 /* unbind and free all */
1122 FREE(mach
->Declarations
);
1123 mach
->Declarations
= NULL
;
1124 mach
->NumDeclarations
= 0;
1126 FREE(mach
->Instructions
);
1127 mach
->Instructions
= NULL
;
1128 mach
->NumInstructions
= 0;
1133 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1134 if (k
!= TGSI_PARSE_OK
) {
1135 debug_printf( "Problem parsing!\n" );
1140 mach
->NumOutputs
= 0;
1142 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1143 mach
->SysSemanticToIndex
[k
] = -1;
1145 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1146 !mach
->UsedGeometryShader
) {
1147 struct tgsi_exec_vector
*inputs
;
1148 struct tgsi_exec_vector
*outputs
;
1150 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1151 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1157 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1158 TGSI_MAX_TOTAL_VERTICES
, 16);
1165 align_free(mach
->Inputs
);
1166 align_free(mach
->Outputs
);
1168 mach
->Inputs
= inputs
;
1169 mach
->Outputs
= outputs
;
1170 mach
->UsedGeometryShader
= TRUE
;
1173 declarations
= (struct tgsi_full_declaration
*)
1174 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1176 if (!declarations
) {
1180 instructions
= (struct tgsi_full_instruction
*)
1181 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1183 if (!instructions
) {
1184 FREE( declarations
);
1188 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1191 tgsi_parse_token( &parse
);
1192 switch( parse
.FullToken
.Token
.Type
) {
1193 case TGSI_TOKEN_TYPE_DECLARATION
:
1194 /* save expanded declaration */
1195 if (numDeclarations
== maxDeclarations
) {
1196 declarations
= REALLOC(declarations
,
1198 * sizeof(struct tgsi_full_declaration
),
1199 (maxDeclarations
+ 10)
1200 * sizeof(struct tgsi_full_declaration
));
1201 maxDeclarations
+= 10;
1203 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1205 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1206 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1211 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1212 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1213 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1216 memcpy(declarations
+ numDeclarations
,
1217 &parse
.FullToken
.FullDeclaration
,
1218 sizeof(declarations
[0]));
1222 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1224 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1225 assert( size
<= 4 );
1226 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
1228 for( i
= 0; i
< size
; i
++ ) {
1229 mach
->Imms
[mach
->ImmLimit
][i
] =
1230 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1232 mach
->ImmLimit
+= 1;
1236 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1238 /* save expanded instruction */
1239 if (numInstructions
== maxInstructions
) {
1240 instructions
= REALLOC(instructions
,
1242 * sizeof(struct tgsi_full_instruction
),
1243 (maxInstructions
+ 10)
1244 * sizeof(struct tgsi_full_instruction
));
1245 maxInstructions
+= 10;
1248 memcpy(instructions
+ numInstructions
,
1249 &parse
.FullToken
.FullInstruction
,
1250 sizeof(instructions
[0]));
1255 case TGSI_TOKEN_TYPE_PROPERTY
:
1256 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1257 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1258 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1267 tgsi_parse_free (&parse
);
1269 FREE(mach
->Declarations
);
1270 mach
->Declarations
= declarations
;
1271 mach
->NumDeclarations
= numDeclarations
;
1273 FREE(mach
->Instructions
);
1274 mach
->Instructions
= instructions
;
1275 mach
->NumInstructions
= numInstructions
;
1279 struct tgsi_exec_machine
*
1280 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1282 struct tgsi_exec_machine
*mach
;
1285 mach
= align_malloc( sizeof *mach
, 16 );
1289 memset(mach
, 0, sizeof(*mach
));
1291 mach
->ShaderType
= shader_type
;
1292 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1293 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1295 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1296 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1297 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1298 if (!mach
->Inputs
|| !mach
->Outputs
)
1302 /* Setup constants needed by the SSE2 executor. */
1303 for( i
= 0; i
< 4; i
++ ) {
1304 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1305 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1306 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1307 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1308 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1309 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1310 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1311 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1312 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1313 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1317 /* silence warnings */
1326 align_free(mach
->Inputs
);
1327 align_free(mach
->Outputs
);
1335 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1338 FREE(mach
->Instructions
);
1339 FREE(mach
->Declarations
);
1341 align_free(mach
->Inputs
);
1342 align_free(mach
->Outputs
);
1349 micro_add(union tgsi_exec_channel
*dst
,
1350 const union tgsi_exec_channel
*src0
,
1351 const union tgsi_exec_channel
*src1
)
1353 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1354 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1355 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1356 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1361 union tgsi_exec_channel
*dst
,
1362 const union tgsi_exec_channel
*src0
,
1363 const union tgsi_exec_channel
*src1
)
1365 if (src1
->f
[0] != 0) {
1366 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1368 if (src1
->f
[1] != 0) {
1369 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1371 if (src1
->f
[2] != 0) {
1372 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1374 if (src1
->f
[3] != 0) {
1375 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1381 union tgsi_exec_channel
*dst
,
1382 const union tgsi_exec_channel
*src0
,
1383 const union tgsi_exec_channel
*src1
,
1384 const union tgsi_exec_channel
*src2
,
1385 const union tgsi_exec_channel
*src3
)
1387 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1388 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1389 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1390 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1394 micro_max(union tgsi_exec_channel
*dst
,
1395 const union tgsi_exec_channel
*src0
,
1396 const union tgsi_exec_channel
*src1
)
1398 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1399 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1400 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1401 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1405 micro_min(union tgsi_exec_channel
*dst
,
1406 const union tgsi_exec_channel
*src0
,
1407 const union tgsi_exec_channel
*src1
)
1409 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1410 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1411 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1412 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1416 micro_mul(union tgsi_exec_channel
*dst
,
1417 const union tgsi_exec_channel
*src0
,
1418 const union tgsi_exec_channel
*src1
)
1420 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1421 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1422 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1423 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1428 union tgsi_exec_channel
*dst
,
1429 const union tgsi_exec_channel
*src
)
1431 dst
->f
[0] = -src
->f
[0];
1432 dst
->f
[1] = -src
->f
[1];
1433 dst
->f
[2] = -src
->f
[2];
1434 dst
->f
[3] = -src
->f
[3];
1439 union tgsi_exec_channel
*dst
,
1440 const union tgsi_exec_channel
*src0
,
1441 const union tgsi_exec_channel
*src1
)
1444 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1445 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1446 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1447 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1449 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1450 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1451 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1452 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1457 micro_ldexp(union tgsi_exec_channel
*dst
,
1458 const union tgsi_exec_channel
*src0
,
1459 const union tgsi_exec_channel
*src1
)
1461 dst
->f
[0] = ldexpf(src0
->f
[0], src1
->i
[0]);
1462 dst
->f
[1] = ldexpf(src0
->f
[1], src1
->i
[1]);
1463 dst
->f
[2] = ldexpf(src0
->f
[2], src1
->i
[2]);
1464 dst
->f
[3] = ldexpf(src0
->f
[3], src1
->i
[3]);
1468 micro_sub(union tgsi_exec_channel
*dst
,
1469 const union tgsi_exec_channel
*src0
,
1470 const union tgsi_exec_channel
*src1
)
1472 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1473 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1474 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1475 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1479 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1482 const union tgsi_exec_channel
*index
,
1483 const union tgsi_exec_channel
*index2D
,
1484 union tgsi_exec_channel
*chan
)
1488 assert(swizzle
< 4);
1491 case TGSI_FILE_CONSTANT
:
1492 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1493 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1494 assert(mach
->Consts
[index2D
->i
[i
]]);
1496 if (index
->i
[i
] < 0) {
1499 /* NOTE: copying the const value as a uint instead of float */
1500 const uint constbuf
= index2D
->i
[i
];
1501 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1502 const int pos
= index
->i
[i
] * 4 + swizzle
;
1503 /* const buffer bounds check */
1504 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1506 /* Debug: print warning */
1507 static int count
= 0;
1509 debug_printf("TGSI Exec: const buffer index %d"
1510 " out of bounds\n", pos
);
1515 chan
->u
[i
] = buf
[pos
];
1520 case TGSI_FILE_INPUT
:
1521 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1523 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1524 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1525 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1526 index2D->i[i], index->i[i]);
1528 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1530 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1531 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1535 case TGSI_FILE_SYSTEM_VALUE
:
1536 /* XXX no swizzling at this point. Will be needed if we put
1537 * gl_FragCoord, for example, in a sys value register.
1539 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1540 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1544 case TGSI_FILE_TEMPORARY
:
1545 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1546 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1547 assert(index2D
->i
[i
] == 0);
1549 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1553 case TGSI_FILE_IMMEDIATE
:
1554 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1555 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1556 assert(index2D
->i
[i
] == 0);
1558 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1562 case TGSI_FILE_ADDRESS
:
1563 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1564 assert(index
->i
[i
] >= 0);
1565 assert(index2D
->i
[i
] == 0);
1567 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1571 case TGSI_FILE_OUTPUT
:
1572 /* vertex/fragment output vars can be read too */
1573 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1574 assert(index
->i
[i
] >= 0);
1575 assert(index2D
->i
[i
] == 0);
1577 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1583 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1590 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1591 union tgsi_exec_channel
*chan
,
1592 const struct tgsi_full_src_register
*reg
,
1593 const uint chan_index
)
1595 union tgsi_exec_channel index
;
1596 union tgsi_exec_channel index2D
;
1599 /* We start with a direct index into a register file.
1603 * file = Register.File
1604 * [1] = Register.Index
1609 index
.i
[3] = reg
->Register
.Index
;
1611 /* There is an extra source register that indirectly subscripts
1612 * a register file. The direct index now becomes an offset
1613 * that is being added to the indirect register.
1617 * ind = Indirect.File
1618 * [2] = Indirect.Index
1619 * .x = Indirect.SwizzleX
1621 if (reg
->Register
.Indirect
) {
1622 union tgsi_exec_channel index2
;
1623 union tgsi_exec_channel indir_index
;
1624 const uint execmask
= mach
->ExecMask
;
1627 /* which address register (always zero now) */
1631 index2
.i
[3] = reg
->Indirect
.Index
;
1632 /* get current value of address register[swizzle] */
1633 swizzle
= reg
->Indirect
.Swizzle
;
1634 fetch_src_file_channel(mach
,
1641 /* add value of address register to the offset */
1642 index
.i
[0] += indir_index
.i
[0];
1643 index
.i
[1] += indir_index
.i
[1];
1644 index
.i
[2] += indir_index
.i
[2];
1645 index
.i
[3] += indir_index
.i
[3];
1647 /* for disabled execution channels, zero-out the index to
1648 * avoid using a potential garbage value.
1650 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1651 if ((execmask
& (1 << i
)) == 0)
1656 /* There is an extra source register that is a second
1657 * subscript to a register file. Effectively it means that
1658 * the register file is actually a 2D array of registers.
1662 * [3] = Dimension.Index
1664 if (reg
->Register
.Dimension
) {
1668 index2D
.i
[3] = reg
->Dimension
.Index
;
1670 /* Again, the second subscript index can be addressed indirectly
1671 * identically to the first one.
1672 * Nothing stops us from indirectly addressing the indirect register,
1673 * but there is no need for that, so we won't exercise it.
1675 * file[ind[4].y+3][1],
1677 * ind = DimIndirect.File
1678 * [4] = DimIndirect.Index
1679 * .y = DimIndirect.SwizzleX
1681 if (reg
->Dimension
.Indirect
) {
1682 union tgsi_exec_channel index2
;
1683 union tgsi_exec_channel indir_index
;
1684 const uint execmask
= mach
->ExecMask
;
1690 index2
.i
[3] = reg
->DimIndirect
.Index
;
1692 swizzle
= reg
->DimIndirect
.Swizzle
;
1693 fetch_src_file_channel(mach
,
1694 reg
->DimIndirect
.File
,
1700 index2D
.i
[0] += indir_index
.i
[0];
1701 index2D
.i
[1] += indir_index
.i
[1];
1702 index2D
.i
[2] += indir_index
.i
[2];
1703 index2D
.i
[3] += indir_index
.i
[3];
1705 /* for disabled execution channels, zero-out the index to
1706 * avoid using a potential garbage value.
1708 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1709 if ((execmask
& (1 << i
)) == 0) {
1715 /* If by any chance there was a need for a 3D array of register
1716 * files, we would have to check whether Dimension is followed
1717 * by a dimension register and continue the saga.
1726 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1727 fetch_src_file_channel(mach
,
1736 fetch_source(const struct tgsi_exec_machine
*mach
,
1737 union tgsi_exec_channel
*chan
,
1738 const struct tgsi_full_src_register
*reg
,
1739 const uint chan_index
,
1740 enum tgsi_exec_datatype src_datatype
)
1742 fetch_source_d(mach
, chan
, reg
, chan_index
);
1744 if (reg
->Register
.Absolute
) {
1745 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1746 micro_abs(chan
, chan
);
1748 micro_iabs(chan
, chan
);
1752 if (reg
->Register
.Negate
) {
1753 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1754 micro_neg(chan
, chan
);
1756 micro_ineg(chan
, chan
);
1761 static union tgsi_exec_channel
*
1762 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1763 const union tgsi_exec_channel
*chan
,
1764 const struct tgsi_full_dst_register
*reg
,
1766 enum tgsi_exec_datatype dst_datatype
)
1768 static union tgsi_exec_channel null
;
1769 union tgsi_exec_channel
*dst
;
1770 union tgsi_exec_channel index2D
;
1771 int offset
= 0; /* indirection offset */
1775 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1776 check_inf_or_nan(chan
);
1779 /* There is an extra source register that indirectly subscripts
1780 * a register file. The direct index now becomes an offset
1781 * that is being added to the indirect register.
1785 * ind = Indirect.File
1786 * [2] = Indirect.Index
1787 * .x = Indirect.SwizzleX
1789 if (reg
->Register
.Indirect
) {
1790 union tgsi_exec_channel index
;
1791 union tgsi_exec_channel indir_index
;
1794 /* which address register (always zero for now) */
1798 index
.i
[3] = reg
->Indirect
.Index
;
1800 /* get current value of address register[swizzle] */
1801 swizzle
= reg
->Indirect
.Swizzle
;
1803 /* fetch values from the address/indirection register */
1804 fetch_src_file_channel(mach
,
1811 /* save indirection offset */
1812 offset
= indir_index
.i
[0];
1815 /* There is an extra source register that is a second
1816 * subscript to a register file. Effectively it means that
1817 * the register file is actually a 2D array of registers.
1821 * [3] = Dimension.Index
1823 if (reg
->Register
.Dimension
) {
1827 index2D
.i
[3] = reg
->Dimension
.Index
;
1829 /* Again, the second subscript index can be addressed indirectly
1830 * identically to the first one.
1831 * Nothing stops us from indirectly addressing the indirect register,
1832 * but there is no need for that, so we won't exercise it.
1834 * file[ind[4].y+3][1],
1836 * ind = DimIndirect.File
1837 * [4] = DimIndirect.Index
1838 * .y = DimIndirect.SwizzleX
1840 if (reg
->Dimension
.Indirect
) {
1841 union tgsi_exec_channel index2
;
1842 union tgsi_exec_channel indir_index
;
1843 const uint execmask
= mach
->ExecMask
;
1850 index2
.i
[3] = reg
->DimIndirect
.Index
;
1852 swizzle
= reg
->DimIndirect
.Swizzle
;
1853 fetch_src_file_channel(mach
,
1854 reg
->DimIndirect
.File
,
1860 index2D
.i
[0] += indir_index
.i
[0];
1861 index2D
.i
[1] += indir_index
.i
[1];
1862 index2D
.i
[2] += indir_index
.i
[2];
1863 index2D
.i
[3] += indir_index
.i
[3];
1865 /* for disabled execution channels, zero-out the index to
1866 * avoid using a potential garbage value.
1868 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1869 if ((execmask
& (1 << i
)) == 0) {
1875 /* If by any chance there was a need for a 3D array of register
1876 * files, we would have to check whether Dimension is followed
1877 * by a dimension register and continue the saga.
1886 switch (reg
->Register
.File
) {
1887 case TGSI_FILE_NULL
:
1891 case TGSI_FILE_OUTPUT
:
1892 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1893 + reg
->Register
.Index
;
1894 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1896 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1897 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1898 reg
->Register
.Index
);
1899 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1900 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1901 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1902 if (execmask
& (1 << i
))
1903 debug_printf("%f, ", chan
->f
[i
]);
1904 debug_printf(")\n");
1909 case TGSI_FILE_TEMPORARY
:
1910 index
= reg
->Register
.Index
;
1911 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1912 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1915 case TGSI_FILE_ADDRESS
:
1916 index
= reg
->Register
.Index
;
1917 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1929 store_dest_double(struct tgsi_exec_machine
*mach
,
1930 const union tgsi_exec_channel
*chan
,
1931 const struct tgsi_full_dst_register
*reg
,
1933 enum tgsi_exec_datatype dst_datatype
)
1935 union tgsi_exec_channel
*dst
;
1936 const uint execmask
= mach
->ExecMask
;
1939 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1944 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1945 if (execmask
& (1 << i
))
1946 dst
->i
[i
] = chan
->i
[i
];
1950 store_dest(struct tgsi_exec_machine
*mach
,
1951 const union tgsi_exec_channel
*chan
,
1952 const struct tgsi_full_dst_register
*reg
,
1953 const struct tgsi_full_instruction
*inst
,
1955 enum tgsi_exec_datatype dst_datatype
)
1957 union tgsi_exec_channel
*dst
;
1958 const uint execmask
= mach
->ExecMask
;
1961 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1965 if (!inst
->Instruction
.Saturate
) {
1966 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1967 if (execmask
& (1 << i
))
1968 dst
->i
[i
] = chan
->i
[i
];
1971 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1972 if (execmask
& (1 << i
)) {
1973 if (chan
->f
[i
] < 0.0f
)
1975 else if (chan
->f
[i
] > 1.0f
)
1978 dst
->i
[i
] = chan
->i
[i
];
1983 #define FETCH(VAL,INDEX,CHAN)\
1984 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1986 #define IFETCH(VAL,INDEX,CHAN)\
1987 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1991 * Execute ARB-style KIL which is predicated by a src register.
1992 * Kill fragment if any of the four values is less than zero.
1995 exec_kill_if(struct tgsi_exec_machine
*mach
,
1996 const struct tgsi_full_instruction
*inst
)
2000 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2001 union tgsi_exec_channel r
[1];
2003 /* This mask stores component bits that were already tested. */
2006 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2011 /* unswizzle channel */
2012 swizzle
= tgsi_util_get_full_src_register_swizzle (
2016 /* check if the component has not been already tested */
2017 if (uniquemask
& (1 << swizzle
))
2019 uniquemask
|= 1 << swizzle
;
2021 FETCH(&r
[0], 0, chan_index
);
2022 for (i
= 0; i
< 4; i
++)
2023 if (r
[0].f
[i
] < 0.0f
)
2027 /* restrict to fragments currently executing */
2028 kilmask
&= mach
->ExecMask
;
2030 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2034 * Unconditional fragment kill/discard.
2037 exec_kill(struct tgsi_exec_machine
*mach
)
2039 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2041 /* kill fragment for all fragments currently executing */
2042 kilmask
= mach
->ExecMask
;
2043 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2047 emit_vertex(struct tgsi_exec_machine
*mach
)
2049 /* FIXME: check for exec mask correctly
2051 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2052 if ((mach->ExecMask & (1 << i)))
2054 if (mach
->ExecMask
) {
2055 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
2058 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2059 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
2064 emit_primitive(struct tgsi_exec_machine
*mach
)
2066 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
2067 /* FIXME: check for exec mask correctly
2069 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2070 if ((mach->ExecMask & (1 << i)))
2072 if (mach
->ExecMask
) {
2074 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2075 mach
->Primitives
[*prim_count
] = 0;
2080 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2082 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2084 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
2085 if (emitted_verts
) {
2086 emit_primitive(mach
);
2093 * Fetch four texture samples using STR texture coordinates.
2096 fetch_texel( struct tgsi_sampler
*sampler
,
2097 const unsigned sview_idx
,
2098 const unsigned sampler_idx
,
2099 const union tgsi_exec_channel
*s
,
2100 const union tgsi_exec_channel
*t
,
2101 const union tgsi_exec_channel
*p
,
2102 const union tgsi_exec_channel
*c0
,
2103 const union tgsi_exec_channel
*c1
,
2104 float derivs
[3][2][TGSI_QUAD_SIZE
],
2105 const int8_t offset
[3],
2106 enum tgsi_sampler_control control
,
2107 union tgsi_exec_channel
*r
,
2108 union tgsi_exec_channel
*g
,
2109 union tgsi_exec_channel
*b
,
2110 union tgsi_exec_channel
*a
)
2113 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2115 /* FIXME: handle explicit derivs, offsets */
2116 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2117 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2119 for (j
= 0; j
< 4; j
++) {
2120 r
->f
[j
] = rgba
[0][j
];
2121 g
->f
[j
] = rgba
[1][j
];
2122 b
->f
[j
] = rgba
[2][j
];
2123 a
->f
[j
] = rgba
[3][j
];
2128 #define TEX_MODIFIER_NONE 0
2129 #define TEX_MODIFIER_PROJECTED 1
2130 #define TEX_MODIFIER_LOD_BIAS 2
2131 #define TEX_MODIFIER_EXPLICIT_LOD 3
2132 #define TEX_MODIFIER_LEVEL_ZERO 4
2133 #define TEX_MODIFIER_GATHER 5
2136 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2139 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2140 const struct tgsi_full_instruction
*inst
,
2143 if (inst
->Texture
.NumOffsets
== 1) {
2144 union tgsi_exec_channel index
;
2145 union tgsi_exec_channel offset
[3];
2146 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2147 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2148 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2149 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2150 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2151 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2152 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2153 offsets
[0] = offset
[0].i
[0];
2154 offsets
[1] = offset
[1].i
[0];
2155 offsets
[2] = offset
[2].i
[0];
2157 assert(inst
->Texture
.NumOffsets
== 0);
2158 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2164 * Fetch dx and dy values for one channel (s, t or r).
2165 * Put dx values into one float array, dy values into another.
2168 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2169 const struct tgsi_full_instruction
*inst
,
2172 float derivs
[2][TGSI_QUAD_SIZE
])
2174 union tgsi_exec_channel d
;
2175 FETCH(&d
, regdsrcx
, chan
);
2176 derivs
[0][0] = d
.f
[0];
2177 derivs
[0][1] = d
.f
[1];
2178 derivs
[0][2] = d
.f
[2];
2179 derivs
[0][3] = d
.f
[3];
2180 FETCH(&d
, regdsrcx
+ 1, chan
);
2181 derivs
[1][0] = d
.f
[0];
2182 derivs
[1][1] = d
.f
[1];
2183 derivs
[1][2] = d
.f
[2];
2184 derivs
[1][3] = d
.f
[3];
2188 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2189 const struct tgsi_full_instruction
*inst
,
2194 if (inst
->Src
[sampler
].Register
.Indirect
) {
2195 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2196 union tgsi_exec_channel indir_index
, index2
;
2197 const uint execmask
= mach
->ExecMask
;
2201 index2
.i
[3] = reg
->Indirect
.Index
;
2203 fetch_src_file_channel(mach
,
2205 reg
->Indirect
.Swizzle
,
2209 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2210 if (execmask
& (1 << i
)) {
2211 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2217 unit
= inst
->Src
[sampler
].Register
.Index
;
2223 * execute a texture instruction.
2225 * modifier is used to control the channel routing for the
2226 * instruction variants like proj, lod, and texture with lod bias.
2227 * sampler indicates which src register the sampler is contained in.
2230 exec_tex(struct tgsi_exec_machine
*mach
,
2231 const struct tgsi_full_instruction
*inst
,
2232 uint modifier
, uint sampler
)
2234 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2235 union tgsi_exec_channel r
[5];
2236 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2240 int dim
, shadow_ref
, i
;
2242 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2243 /* always fetch all 3 offsets, overkill but keeps code simple */
2244 fetch_texel_offsets(mach
, inst
, offsets
);
2246 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2247 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2249 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2250 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2253 if (shadow_ref
>= 0)
2254 assert(shadow_ref
>= dim
&& shadow_ref
< ARRAY_SIZE(args
));
2256 /* fetch modifier to the last argument */
2257 if (modifier
!= TEX_MODIFIER_NONE
) {
2258 const int last
= ARRAY_SIZE(args
) - 1;
2260 /* fetch modifier from src0.w or src1.x */
2262 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2263 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2266 assert(shadow_ref
!= 4);
2267 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2270 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2271 args
[last
] = &r
[last
];
2275 args
[last
] = &ZeroVec
;
2278 /* point unused arguments to zero vector */
2279 for (i
= dim
; i
< last
; i
++)
2282 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2283 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2284 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2285 control
= TGSI_SAMPLER_LOD_BIAS
;
2286 else if (modifier
== TEX_MODIFIER_GATHER
)
2287 control
= TGSI_SAMPLER_GATHER
;
2290 for (i
= dim
; i
< ARRAY_SIZE(args
); i
++)
2294 /* fetch coordinates */
2295 for (i
= 0; i
< dim
; i
++) {
2296 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2299 micro_div(&r
[i
], &r
[i
], proj
);
2304 /* fetch reference value */
2305 if (shadow_ref
>= 0) {
2306 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2309 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2311 args
[shadow_ref
] = &r
[shadow_ref
];
2314 fetch_texel(mach
->Sampler
, unit
, unit
,
2315 args
[0], args
[1], args
[2], args
[3], args
[4],
2316 NULL
, offsets
, control
,
2317 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2320 debug_printf("fetch r: %g %g %g %g\n",
2321 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2322 debug_printf("fetch g: %g %g %g %g\n",
2323 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2324 debug_printf("fetch b: %g %g %g %g\n",
2325 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2326 debug_printf("fetch a: %g %g %g %g\n",
2327 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2330 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2331 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2332 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2338 exec_lodq(struct tgsi_exec_machine
*mach
,
2339 const struct tgsi_full_instruction
*inst
)
2341 uint resource_unit
, sampler_unit
;
2344 union tgsi_exec_channel coords
[4];
2345 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2346 union tgsi_exec_channel r
[2];
2348 resource_unit
= fetch_sampler_unit(mach
, inst
, 1);
2349 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2350 uint target
= mach
->SamplerViews
[resource_unit
].Resource
;
2351 dim
= tgsi_util_get_texture_coord_dim(target
);
2352 sampler_unit
= fetch_sampler_unit(mach
, inst
, 2);
2354 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2355 sampler_unit
= resource_unit
;
2357 assert(dim
<= ARRAY_SIZE(coords
));
2358 /* fetch coordinates */
2359 for (i
= 0; i
< dim
; i
++) {
2360 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2361 args
[i
] = &coords
[i
];
2363 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2366 mach
->Sampler
->query_lod(mach
->Sampler
, resource_unit
, sampler_unit
,
2371 TGSI_SAMPLER_LOD_NONE
,
2375 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2376 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2377 TGSI_EXEC_DATA_FLOAT
);
2379 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2380 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2381 TGSI_EXEC_DATA_FLOAT
);
2383 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2384 unsigned char swizzles
[4];
2386 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2387 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2388 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2389 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2391 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2392 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2393 if (swizzles
[chan
] >= 2) {
2394 store_dest(mach
, &ZeroVec
,
2395 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2397 store_dest(mach
, &r
[swizzles
[chan
]],
2398 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2403 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2404 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2405 TGSI_EXEC_DATA_FLOAT
);
2407 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2408 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2409 TGSI_EXEC_DATA_FLOAT
);
2415 exec_txd(struct tgsi_exec_machine
*mach
,
2416 const struct tgsi_full_instruction
*inst
)
2418 union tgsi_exec_channel r
[4];
2419 float derivs
[3][2][TGSI_QUAD_SIZE
];
2424 unit
= fetch_sampler_unit(mach
, inst
, 3);
2425 /* always fetch all 3 offsets, overkill but keeps code simple */
2426 fetch_texel_offsets(mach
, inst
, offsets
);
2428 switch (inst
->Texture
.Texture
) {
2429 case TGSI_TEXTURE_1D
:
2430 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2432 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2434 fetch_texel(mach
->Sampler
, unit
, unit
,
2435 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2436 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2437 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2440 case TGSI_TEXTURE_SHADOW1D
:
2441 case TGSI_TEXTURE_1D_ARRAY
:
2442 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2443 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2444 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2445 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2446 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2448 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2450 fetch_texel(mach
->Sampler
, unit
, unit
,
2451 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2452 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2453 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2456 case TGSI_TEXTURE_2D
:
2457 case TGSI_TEXTURE_RECT
:
2458 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2459 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2461 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2462 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2464 fetch_texel(mach
->Sampler
, unit
, unit
,
2465 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2466 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2467 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2471 case TGSI_TEXTURE_SHADOW2D
:
2472 case TGSI_TEXTURE_SHADOWRECT
:
2473 case TGSI_TEXTURE_2D_ARRAY
:
2474 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2475 /* only SHADOW2D_ARRAY actually needs W */
2476 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2477 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2478 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2479 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2481 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2482 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2484 fetch_texel(mach
->Sampler
, unit
, unit
,
2485 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2486 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2487 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2490 case TGSI_TEXTURE_3D
:
2491 case TGSI_TEXTURE_CUBE
:
2492 case TGSI_TEXTURE_CUBE_ARRAY
:
2493 case TGSI_TEXTURE_SHADOWCUBE
:
2494 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2495 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2496 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2497 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2498 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2500 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2501 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2502 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2504 fetch_texel(mach
->Sampler
, unit
, unit
,
2505 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2506 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2507 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2514 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2515 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2516 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2523 exec_txf(struct tgsi_exec_machine
*mach
,
2524 const struct tgsi_full_instruction
*inst
)
2526 union tgsi_exec_channel r
[4];
2529 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2534 unit
= fetch_sampler_unit(mach
, inst
, 1);
2535 /* always fetch all 3 offsets, overkill but keeps code simple */
2536 fetch_texel_offsets(mach
, inst
, offsets
);
2538 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2540 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2541 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2542 target
= mach
->SamplerViews
[unit
].Resource
;
2545 target
= inst
->Texture
.Texture
;
2548 case TGSI_TEXTURE_3D
:
2549 case TGSI_TEXTURE_2D_ARRAY
:
2550 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2551 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2552 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2554 case TGSI_TEXTURE_2D
:
2555 case TGSI_TEXTURE_RECT
:
2556 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2557 case TGSI_TEXTURE_SHADOW2D
:
2558 case TGSI_TEXTURE_SHADOWRECT
:
2559 case TGSI_TEXTURE_1D_ARRAY
:
2560 case TGSI_TEXTURE_2D_MSAA
:
2561 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2563 case TGSI_TEXTURE_BUFFER
:
2564 case TGSI_TEXTURE_1D
:
2565 case TGSI_TEXTURE_SHADOW1D
:
2566 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2573 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2576 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2577 r
[0].f
[j
] = rgba
[0][j
];
2578 r
[1].f
[j
] = rgba
[1][j
];
2579 r
[2].f
[j
] = rgba
[2][j
];
2580 r
[3].f
[j
] = rgba
[3][j
];
2583 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2584 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2585 unsigned char swizzles
[4];
2586 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2587 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2588 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2589 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2591 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2592 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2593 store_dest(mach
, &r
[swizzles
[chan
]],
2594 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2599 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2600 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2601 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2608 exec_txq(struct tgsi_exec_machine
*mach
,
2609 const struct tgsi_full_instruction
*inst
)
2612 union tgsi_exec_channel r
[4], src
;
2617 unit
= fetch_sampler_unit(mach
, inst
, 1);
2619 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2621 /* XXX: This interface can't return per-pixel values */
2622 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2624 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2625 for (j
= 0; j
< 4; j
++) {
2626 r
[j
].i
[i
] = result
[j
];
2630 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2631 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2632 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2633 TGSI_EXEC_DATA_INT
);
2639 exec_sample(struct tgsi_exec_machine
*mach
,
2640 const struct tgsi_full_instruction
*inst
,
2641 uint modifier
, boolean compare
)
2643 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2644 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2645 union tgsi_exec_channel r
[5], c1
;
2646 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2647 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2649 unsigned char swizzles
[4];
2652 /* always fetch all 3 offsets, overkill but keeps code simple */
2653 fetch_texel_offsets(mach
, inst
, offsets
);
2655 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2657 if (modifier
!= TEX_MODIFIER_NONE
) {
2658 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2659 FETCH(&c1
, 3, TGSI_CHAN_X
);
2661 control
= TGSI_SAMPLER_LOD_BIAS
;
2663 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2664 FETCH(&c1
, 3, TGSI_CHAN_X
);
2666 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2668 else if (modifier
== TEX_MODIFIER_GATHER
) {
2669 control
= TGSI_SAMPLER_GATHER
;
2672 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2673 control
= TGSI_SAMPLER_LOD_ZERO
;
2677 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2679 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2680 case TGSI_TEXTURE_1D
:
2682 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2683 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2684 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2685 NULL
, offsets
, control
,
2686 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2689 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2690 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2691 NULL
, offsets
, control
,
2692 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2696 case TGSI_TEXTURE_1D_ARRAY
:
2697 case TGSI_TEXTURE_2D
:
2698 case TGSI_TEXTURE_RECT
:
2699 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2701 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2702 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2703 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2704 NULL
, offsets
, control
,
2705 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2708 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2709 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2710 NULL
, offsets
, control
,
2711 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2715 case TGSI_TEXTURE_2D_ARRAY
:
2716 case TGSI_TEXTURE_3D
:
2717 case TGSI_TEXTURE_CUBE
:
2718 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2719 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2721 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2722 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2723 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2724 NULL
, offsets
, control
,
2725 &r
[0], &r
[1], &r
[2], &r
[3]);
2728 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2729 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2730 NULL
, offsets
, control
,
2731 &r
[0], &r
[1], &r
[2], &r
[3]);
2735 case TGSI_TEXTURE_CUBE_ARRAY
:
2736 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2737 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2738 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2740 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2741 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2742 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2743 NULL
, offsets
, control
,
2744 &r
[0], &r
[1], &r
[2], &r
[3]);
2747 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2748 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2749 NULL
, offsets
, control
,
2750 &r
[0], &r
[1], &r
[2], &r
[3]);
2759 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2760 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2761 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2762 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2764 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2765 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2766 store_dest(mach
, &r
[swizzles
[chan
]],
2767 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2773 exec_sample_d(struct tgsi_exec_machine
*mach
,
2774 const struct tgsi_full_instruction
*inst
)
2776 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2777 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2778 union tgsi_exec_channel r
[4];
2779 float derivs
[3][2][TGSI_QUAD_SIZE
];
2781 unsigned char swizzles
[4];
2784 /* always fetch all 3 offsets, overkill but keeps code simple */
2785 fetch_texel_offsets(mach
, inst
, offsets
);
2787 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2789 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2790 case TGSI_TEXTURE_1D
:
2791 case TGSI_TEXTURE_1D_ARRAY
:
2792 /* only 1D array actually needs Y */
2793 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2795 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2797 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2798 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2799 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2800 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2803 case TGSI_TEXTURE_2D
:
2804 case TGSI_TEXTURE_RECT
:
2805 case TGSI_TEXTURE_2D_ARRAY
:
2806 /* only 2D array actually needs Z */
2807 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2808 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2810 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2811 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2813 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2814 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2815 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2816 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2819 case TGSI_TEXTURE_3D
:
2820 case TGSI_TEXTURE_CUBE
:
2821 case TGSI_TEXTURE_CUBE_ARRAY
:
2822 /* only cube array actually needs W */
2823 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2824 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2825 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2827 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2828 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2829 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2831 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2832 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2833 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2834 &r
[0], &r
[1], &r
[2], &r
[3]);
2841 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2842 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2843 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2844 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2846 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2847 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2848 store_dest(mach
, &r
[swizzles
[chan
]],
2849 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2856 * Evaluate a constant-valued coefficient at the position of the
2861 struct tgsi_exec_machine
*mach
,
2867 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2868 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2873 * Evaluate a linear-valued coefficient at the position of the
2878 struct tgsi_exec_machine
*mach
,
2882 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2883 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2884 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2885 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2886 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2887 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2888 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2889 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2890 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2894 * Evaluate a perspective-valued coefficient at the position of the
2898 eval_perspective_coef(
2899 struct tgsi_exec_machine
*mach
,
2903 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2904 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2905 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2906 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2907 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2908 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2909 /* divide by W here */
2910 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2911 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2912 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2913 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2917 typedef void (* eval_coef_func
)(
2918 struct tgsi_exec_machine
*mach
,
2923 exec_declaration(struct tgsi_exec_machine
*mach
,
2924 const struct tgsi_full_declaration
*decl
)
2926 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2927 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2931 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2932 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2933 uint first
, last
, mask
;
2935 first
= decl
->Range
.First
;
2936 last
= decl
->Range
.Last
;
2937 mask
= decl
->Declaration
.UsageMask
;
2939 /* XXX we could remove this special-case code since
2940 * mach->InterpCoefs[first].a0 should already have the
2941 * front/back-face value. But we should first update the
2942 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2943 * Then, we could remove the tgsi_exec_machine::Face field.
2945 /* XXX make FACE a system value */
2946 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2949 assert(decl
->Semantic
.Index
== 0);
2950 assert(first
== last
);
2952 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2953 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2956 eval_coef_func eval
;
2959 switch (decl
->Interp
.Interpolate
) {
2960 case TGSI_INTERPOLATE_CONSTANT
:
2961 eval
= eval_constant_coef
;
2964 case TGSI_INTERPOLATE_LINEAR
:
2965 eval
= eval_linear_coef
;
2968 case TGSI_INTERPOLATE_PERSPECTIVE
:
2969 eval
= eval_perspective_coef
;
2972 case TGSI_INTERPOLATE_COLOR
:
2973 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2981 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2982 if (mask
& (1 << j
)) {
2983 for (i
= first
; i
<= last
; i
++) {
2990 if (DEBUG_EXECUTION
) {
2992 for (i
= first
; i
<= last
; ++i
) {
2993 debug_printf("IN[%2u] = ", i
);
2994 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2998 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2999 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
3000 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
3001 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
3002 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
3011 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
3012 const union tgsi_exec_channel
*src
);
3015 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
3016 const struct tgsi_full_instruction
*inst
,
3018 enum tgsi_exec_datatype dst_datatype
,
3019 enum tgsi_exec_datatype src_datatype
)
3022 union tgsi_exec_channel src
;
3023 union tgsi_exec_channel dst
;
3025 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3027 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3028 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3029 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3035 exec_vector_unary(struct tgsi_exec_machine
*mach
,
3036 const struct tgsi_full_instruction
*inst
,
3038 enum tgsi_exec_datatype dst_datatype
,
3039 enum tgsi_exec_datatype src_datatype
)
3042 struct tgsi_exec_vector dst
;
3044 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3045 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3046 union tgsi_exec_channel src
;
3048 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3049 op(&dst
.xyzw
[chan
], &src
);
3052 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3053 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3054 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3059 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3060 const union tgsi_exec_channel
*src0
,
3061 const union tgsi_exec_channel
*src1
);
3064 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3065 const struct tgsi_full_instruction
*inst
,
3067 enum tgsi_exec_datatype dst_datatype
,
3068 enum tgsi_exec_datatype src_datatype
)
3071 union tgsi_exec_channel src
[2];
3072 union tgsi_exec_channel dst
;
3074 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3075 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3076 op(&dst
, &src
[0], &src
[1]);
3077 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3078 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3079 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3085 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3086 const struct tgsi_full_instruction
*inst
,
3088 enum tgsi_exec_datatype dst_datatype
,
3089 enum tgsi_exec_datatype src_datatype
)
3092 struct tgsi_exec_vector dst
;
3094 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3095 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3096 union tgsi_exec_channel src
[2];
3098 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3099 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3100 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3103 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3104 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3105 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3110 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3111 const union tgsi_exec_channel
*src0
,
3112 const union tgsi_exec_channel
*src1
,
3113 const union tgsi_exec_channel
*src2
);
3116 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3117 const struct tgsi_full_instruction
*inst
,
3118 micro_trinary_op op
,
3119 enum tgsi_exec_datatype dst_datatype
,
3120 enum tgsi_exec_datatype src_datatype
)
3123 struct tgsi_exec_vector dst
;
3125 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3126 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3127 union tgsi_exec_channel src
[3];
3129 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3130 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3131 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3132 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3135 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3136 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3137 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3142 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3143 const union tgsi_exec_channel
*src0
,
3144 const union tgsi_exec_channel
*src1
,
3145 const union tgsi_exec_channel
*src2
,
3146 const union tgsi_exec_channel
*src3
);
3149 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3150 const struct tgsi_full_instruction
*inst
,
3151 micro_quaternary_op op
,
3152 enum tgsi_exec_datatype dst_datatype
,
3153 enum tgsi_exec_datatype src_datatype
)
3156 struct tgsi_exec_vector dst
;
3158 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3159 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3160 union tgsi_exec_channel src
[4];
3162 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3163 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3164 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3165 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3166 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3169 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3170 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3171 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3177 exec_dp3(struct tgsi_exec_machine
*mach
,
3178 const struct tgsi_full_instruction
*inst
)
3181 union tgsi_exec_channel arg
[3];
3183 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3184 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3185 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3187 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3188 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3189 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3190 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3193 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3194 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3195 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3201 exec_dp4(struct tgsi_exec_machine
*mach
,
3202 const struct tgsi_full_instruction
*inst
)
3205 union tgsi_exec_channel arg
[3];
3207 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3208 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3209 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3211 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3212 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3213 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3214 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3217 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3218 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3219 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3225 exec_dp2(struct tgsi_exec_machine
*mach
,
3226 const struct tgsi_full_instruction
*inst
)
3229 union tgsi_exec_channel arg
[3];
3231 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3232 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3233 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3235 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3236 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3237 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3239 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3240 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3241 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3247 exec_pk2h(struct tgsi_exec_machine
*mach
,
3248 const struct tgsi_full_instruction
*inst
)
3251 union tgsi_exec_channel arg
[2], dst
;
3253 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3254 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3255 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3256 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3257 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3259 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3260 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3261 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3267 exec_up2h(struct tgsi_exec_machine
*mach
,
3268 const struct tgsi_full_instruction
*inst
)
3271 union tgsi_exec_channel arg
, dst
[2];
3273 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3274 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3275 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3276 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3278 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3279 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3280 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3286 micro_ucmp(union tgsi_exec_channel
*dst
,
3287 const union tgsi_exec_channel
*src0
,
3288 const union tgsi_exec_channel
*src1
,
3289 const union tgsi_exec_channel
*src2
)
3291 dst
->f
[0] = src0
->u
[0] ? src1
->f
[0] : src2
->f
[0];
3292 dst
->f
[1] = src0
->u
[1] ? src1
->f
[1] : src2
->f
[1];
3293 dst
->f
[2] = src0
->u
[2] ? src1
->f
[2] : src2
->f
[2];
3294 dst
->f
[3] = src0
->u
[3] ? src1
->f
[3] : src2
->f
[3];
3298 exec_ucmp(struct tgsi_exec_machine
*mach
,
3299 const struct tgsi_full_instruction
*inst
)
3302 struct tgsi_exec_vector dst
;
3304 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3305 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3306 union tgsi_exec_channel src
[3];
3308 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
,
3309 TGSI_EXEC_DATA_UINT
);
3310 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
,
3311 TGSI_EXEC_DATA_FLOAT
);
3312 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
,
3313 TGSI_EXEC_DATA_FLOAT
);
3314 micro_ucmp(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3317 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3318 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3319 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
,
3320 TGSI_EXEC_DATA_FLOAT
);
3326 exec_dst(struct tgsi_exec_machine
*mach
,
3327 const struct tgsi_full_instruction
*inst
)
3329 union tgsi_exec_channel r
[2];
3330 union tgsi_exec_channel d
[4];
3332 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3333 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3334 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3335 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3337 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3338 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3340 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3341 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3344 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3345 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3347 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3348 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3350 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3351 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3353 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3354 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3359 exec_log(struct tgsi_exec_machine
*mach
,
3360 const struct tgsi_full_instruction
*inst
)
3362 union tgsi_exec_channel r
[3];
3364 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3365 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3366 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3367 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3368 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3369 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3371 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3372 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3373 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3374 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3376 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3377 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3379 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3380 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3385 exec_exp(struct tgsi_exec_machine
*mach
,
3386 const struct tgsi_full_instruction
*inst
)
3388 union tgsi_exec_channel r
[3];
3390 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3391 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3392 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3393 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3394 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3396 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3397 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3398 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3400 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3401 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3402 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3404 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3405 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3410 exec_lit(struct tgsi_exec_machine
*mach
,
3411 const struct tgsi_full_instruction
*inst
)
3413 union tgsi_exec_channel r
[3];
3414 union tgsi_exec_channel d
[3];
3416 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3417 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3418 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3419 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3420 micro_max(&r
[1], &r
[1], &ZeroVec
);
3422 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3423 micro_min(&r
[2], &r
[2], &P128Vec
);
3424 micro_max(&r
[2], &r
[2], &M128Vec
);
3425 micro_pow(&r
[1], &r
[1], &r
[2]);
3426 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3427 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3429 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3430 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3431 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3434 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3435 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3438 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3439 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3444 exec_break(struct tgsi_exec_machine
*mach
)
3446 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3447 /* turn off loop channels for each enabled exec channel */
3448 mach
->LoopMask
&= ~mach
->ExecMask
;
3449 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3450 UPDATE_EXEC_MASK(mach
);
3452 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3454 mach
->Switch
.mask
= 0x0;
3456 UPDATE_EXEC_MASK(mach
);
3461 exec_switch(struct tgsi_exec_machine
*mach
,
3462 const struct tgsi_full_instruction
*inst
)
3464 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3465 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3467 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3468 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3469 mach
->Switch
.mask
= 0x0;
3470 mach
->Switch
.defaultMask
= 0x0;
3472 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3473 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3475 UPDATE_EXEC_MASK(mach
);
3479 exec_case(struct tgsi_exec_machine
*mach
,
3480 const struct tgsi_full_instruction
*inst
)
3482 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3483 union tgsi_exec_channel src
;
3486 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3488 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3491 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3494 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3497 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3501 mach
->Switch
.defaultMask
|= mask
;
3503 mach
->Switch
.mask
|= mask
& prevMask
;
3505 UPDATE_EXEC_MASK(mach
);
3508 /* FIXME: this will only work if default is last */
3510 exec_default(struct tgsi_exec_machine
*mach
)
3512 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3514 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3516 UPDATE_EXEC_MASK(mach
);
3520 exec_endswitch(struct tgsi_exec_machine
*mach
)
3522 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3523 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3525 UPDATE_EXEC_MASK(mach
);
3528 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3529 const union tgsi_double_channel
*src
);
3531 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3532 const union tgsi_double_channel
*src0
,
3533 union tgsi_exec_channel
*src1
);
3535 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3536 const union tgsi_exec_channel
*src
);
3538 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3539 const union tgsi_double_channel
*src
);
3542 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3543 union tgsi_double_channel
*chan
,
3544 const struct tgsi_full_src_register
*reg
,
3548 union tgsi_exec_channel src
[2];
3551 fetch_source_d(mach
, &src
[0], reg
, chan_0
);
3552 fetch_source_d(mach
, &src
[1], reg
, chan_1
);
3554 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3555 chan
->u
[i
][0] = src
[0].u
[i
];
3556 chan
->u
[i
][1] = src
[1].u
[i
];
3558 if (reg
->Register
.Absolute
) {
3559 micro_dabs(chan
, chan
);
3561 if (reg
->Register
.Negate
) {
3562 micro_dneg(chan
, chan
);
3567 store_double_channel(struct tgsi_exec_machine
*mach
,
3568 const union tgsi_double_channel
*chan
,
3569 const struct tgsi_full_dst_register
*reg
,
3570 const struct tgsi_full_instruction
*inst
,
3574 union tgsi_exec_channel dst
[2];
3576 union tgsi_double_channel temp
;
3577 const uint execmask
= mach
->ExecMask
;
3579 if (!inst
->Instruction
.Saturate
) {
3580 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3581 if (execmask
& (1 << i
)) {
3582 dst
[0].u
[i
] = chan
->u
[i
][0];
3583 dst
[1].u
[i
] = chan
->u
[i
][1];
3587 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3588 if (execmask
& (1 << i
)) {
3589 if (chan
->d
[i
] < 0.0)
3591 else if (chan
->d
[i
] > 1.0)
3594 temp
.d
[i
] = chan
->d
[i
];
3596 dst
[0].u
[i
] = temp
.u
[i
][0];
3597 dst
[1].u
[i
] = temp
.u
[i
][1];
3601 store_dest_double(mach
, &dst
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3602 if (chan_1
!= (unsigned)-1)
3603 store_dest_double(mach
, &dst
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3607 exec_double_unary(struct tgsi_exec_machine
*mach
,
3608 const struct tgsi_full_instruction
*inst
,
3611 union tgsi_double_channel src
;
3612 union tgsi_double_channel dst
;
3614 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3615 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3617 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3619 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3620 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3622 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3627 exec_double_binary(struct tgsi_exec_machine
*mach
,
3628 const struct tgsi_full_instruction
*inst
,
3630 enum tgsi_exec_datatype dst_datatype
)
3632 union tgsi_double_channel src
[2];
3633 union tgsi_double_channel dst
;
3634 int first_dest_chan
, second_dest_chan
;
3637 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3638 /* these are & because of the way DSLT etc store their destinations */
3639 if (wmask
& TGSI_WRITEMASK_XY
) {
3640 first_dest_chan
= TGSI_CHAN_X
;
3641 second_dest_chan
= TGSI_CHAN_Y
;
3642 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3643 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3644 second_dest_chan
= -1;
3647 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3648 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3650 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3653 if (wmask
& TGSI_WRITEMASK_ZW
) {
3654 first_dest_chan
= TGSI_CHAN_Z
;
3655 second_dest_chan
= TGSI_CHAN_W
;
3656 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3657 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3658 second_dest_chan
= -1;
3661 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3662 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3664 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3669 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3670 const struct tgsi_full_instruction
*inst
,
3673 union tgsi_double_channel src
[3];
3674 union tgsi_double_channel dst
;
3676 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3677 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3678 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3679 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3681 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3683 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3684 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3685 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3686 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3688 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3693 exec_dldexp(struct tgsi_exec_machine
*mach
,
3694 const struct tgsi_full_instruction
*inst
)
3696 union tgsi_double_channel src0
;
3697 union tgsi_exec_channel src1
;
3698 union tgsi_double_channel dst
;
3701 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3702 if (wmask
& TGSI_WRITEMASK_XY
) {
3703 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3704 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3705 micro_dldexp(&dst
, &src0
, &src1
);
3706 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3709 if (wmask
& TGSI_WRITEMASK_ZW
) {
3710 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3711 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3712 micro_dldexp(&dst
, &src0
, &src1
);
3713 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3718 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3719 const struct tgsi_full_instruction
*inst
)
3721 union tgsi_double_channel src
;
3722 union tgsi_double_channel dst
;
3723 union tgsi_exec_channel dst_exp
;
3725 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3726 micro_dfracexp(&dst
, &dst_exp
, &src
);
3727 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)
3728 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3729 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)
3730 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3731 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3732 if (inst
->Dst
[1].Register
.WriteMask
& (1 << chan
))
3733 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, chan
, TGSI_EXEC_DATA_INT
);
3738 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3739 const struct tgsi_full_instruction
*inst
,
3742 union tgsi_double_channel src0
;
3743 union tgsi_exec_channel src1
;
3744 union tgsi_double_channel dst
;
3747 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3748 if (wmask
& TGSI_WRITEMASK_XY
) {
3749 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3750 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3751 op(&dst
, &src0
, &src1
);
3752 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3755 if (wmask
& TGSI_WRITEMASK_ZW
) {
3756 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3757 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3758 op(&dst
, &src0
, &src1
);
3759 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3764 get_image_coord_dim(unsigned tgsi_tex
)
3768 case TGSI_TEXTURE_BUFFER
:
3769 case TGSI_TEXTURE_1D
:
3772 case TGSI_TEXTURE_2D
:
3773 case TGSI_TEXTURE_RECT
:
3774 case TGSI_TEXTURE_1D_ARRAY
:
3775 case TGSI_TEXTURE_2D_MSAA
:
3778 case TGSI_TEXTURE_3D
:
3779 case TGSI_TEXTURE_CUBE
:
3780 case TGSI_TEXTURE_2D_ARRAY
:
3781 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3782 case TGSI_TEXTURE_CUBE_ARRAY
:
3786 assert(!"unknown texture target");
3795 get_image_coord_sample(unsigned tgsi_tex
)
3799 case TGSI_TEXTURE_2D_MSAA
:
3802 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3812 exec_load_img(struct tgsi_exec_machine
*mach
,
3813 const struct tgsi_full_instruction
*inst
)
3815 union tgsi_exec_channel r
[4], sample_r
;
3821 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3822 struct tgsi_image_params params
;
3823 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3825 unit
= fetch_sampler_unit(mach
, inst
, 0);
3826 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3827 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3830 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3832 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3833 params
.format
= inst
->Memory
.Format
;
3835 for (i
= 0; i
< dim
; i
++) {
3836 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3840 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3842 mach
->Image
->load(mach
->Image
, ¶ms
,
3843 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3845 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3846 r
[0].f
[j
] = rgba
[0][j
];
3847 r
[1].f
[j
] = rgba
[1][j
];
3848 r
[2].f
[j
] = rgba
[2][j
];
3849 r
[3].f
[j
] = rgba
[3][j
];
3851 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3852 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3853 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3859 exec_load_buf(struct tgsi_exec_machine
*mach
,
3860 const struct tgsi_full_instruction
*inst
)
3862 union tgsi_exec_channel r
[4];
3866 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3867 struct tgsi_buffer_params params
;
3868 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3870 unit
= fetch_sampler_unit(mach
, inst
, 0);
3872 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3874 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3876 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3878 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3879 r
[0].f
[j
] = rgba
[0][j
];
3880 r
[1].f
[j
] = rgba
[1][j
];
3881 r
[2].f
[j
] = rgba
[2][j
];
3882 r
[3].f
[j
] = rgba
[3][j
];
3884 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3885 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3886 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3892 exec_load_mem(struct tgsi_exec_machine
*mach
,
3893 const struct tgsi_full_instruction
*inst
)
3895 union tgsi_exec_channel r
[4];
3897 char *ptr
= mach
->LocalMem
;
3901 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3902 if (r
[0].u
[0] >= mach
->LocalMemSize
)
3908 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3909 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3910 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3911 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
3916 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3917 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3918 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3924 exec_load(struct tgsi_exec_machine
*mach
,
3925 const struct tgsi_full_instruction
*inst
)
3927 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
3928 exec_load_img(mach
, inst
);
3929 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
3930 exec_load_buf(mach
, inst
);
3931 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
3932 exec_load_mem(mach
, inst
);
3936 exec_store_img(struct tgsi_exec_machine
*mach
,
3937 const struct tgsi_full_instruction
*inst
)
3939 union tgsi_exec_channel r
[3], sample_r
;
3940 union tgsi_exec_channel value
[4];
3941 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3942 struct tgsi_image_params params
;
3947 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3948 unit
= inst
->Dst
[0].Register
.Index
;
3949 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3950 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3953 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3955 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3956 params
.format
= inst
->Memory
.Format
;
3958 for (i
= 0; i
< dim
; i
++) {
3959 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
3962 for (i
= 0; i
< 4; i
++) {
3963 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3966 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
3968 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3969 rgba
[0][j
] = value
[0].f
[j
];
3970 rgba
[1][j
] = value
[1].f
[j
];
3971 rgba
[2][j
] = value
[2].f
[j
];
3972 rgba
[3][j
] = value
[3].f
[j
];
3975 mach
->Image
->store(mach
->Image
, ¶ms
,
3976 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3981 exec_store_buf(struct tgsi_exec_machine
*mach
,
3982 const struct tgsi_full_instruction
*inst
)
3984 union tgsi_exec_channel r
[3];
3985 union tgsi_exec_channel value
[4];
3986 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3987 struct tgsi_buffer_params params
;
3990 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3992 unit
= inst
->Dst
[0].Register
.Index
;
3994 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3996 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
3998 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
3999 for (i
= 0; i
< 4; i
++) {
4000 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4003 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4004 rgba
[0][j
] = value
[0].f
[j
];
4005 rgba
[1][j
] = value
[1].f
[j
];
4006 rgba
[2][j
] = value
[2].f
[j
];
4007 rgba
[3][j
] = value
[3].f
[j
];
4010 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4016 exec_store_mem(struct tgsi_exec_machine
*mach
,
4017 const struct tgsi_full_instruction
*inst
)
4019 union tgsi_exec_channel r
[3];
4020 union tgsi_exec_channel value
[4];
4022 char *ptr
= mach
->LocalMem
;
4023 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4024 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4026 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4028 for (i
= 0; i
< 4; i
++) {
4029 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4032 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4036 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4037 if (execmask
& (1 << i
)) {
4038 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4039 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4040 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4048 exec_store(struct tgsi_exec_machine
*mach
,
4049 const struct tgsi_full_instruction
*inst
)
4051 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4052 exec_store_img(mach
, inst
);
4053 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4054 exec_store_buf(mach
, inst
);
4055 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4056 exec_store_mem(mach
, inst
);
4060 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4061 const struct tgsi_full_instruction
*inst
)
4063 union tgsi_exec_channel r
[4], sample_r
;
4064 union tgsi_exec_channel value
[4], value2
[4];
4065 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4066 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4067 struct tgsi_image_params params
;
4072 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4073 unit
= fetch_sampler_unit(mach
, inst
, 0);
4074 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4075 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4078 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4080 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4081 params
.format
= inst
->Memory
.Format
;
4083 for (i
= 0; i
< dim
; i
++) {
4084 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4087 for (i
= 0; i
< 4; i
++) {
4088 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4089 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4090 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4093 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4095 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4096 rgba
[0][j
] = value
[0].f
[j
];
4097 rgba
[1][j
] = value
[1].f
[j
];
4098 rgba
[2][j
] = value
[2].f
[j
];
4099 rgba
[3][j
] = value
[3].f
[j
];
4101 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4102 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4103 rgba2
[0][j
] = value2
[0].f
[j
];
4104 rgba2
[1][j
] = value2
[1].f
[j
];
4105 rgba2
[2][j
] = value2
[2].f
[j
];
4106 rgba2
[3][j
] = value2
[3].f
[j
];
4110 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4111 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4114 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4115 r
[0].f
[j
] = rgba
[0][j
];
4116 r
[1].f
[j
] = rgba
[1][j
];
4117 r
[2].f
[j
] = rgba
[2][j
];
4118 r
[3].f
[j
] = rgba
[3][j
];
4120 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4121 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4122 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4128 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4129 const struct tgsi_full_instruction
*inst
)
4131 union tgsi_exec_channel r
[4];
4132 union tgsi_exec_channel value
[4], value2
[4];
4133 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4134 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4135 struct tgsi_buffer_params params
;
4138 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4140 unit
= fetch_sampler_unit(mach
, inst
, 0);
4142 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4144 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4146 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4148 for (i
= 0; i
< 4; i
++) {
4149 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4150 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4151 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4154 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4155 rgba
[0][j
] = value
[0].f
[j
];
4156 rgba
[1][j
] = value
[1].f
[j
];
4157 rgba
[2][j
] = value
[2].f
[j
];
4158 rgba
[3][j
] = value
[3].f
[j
];
4160 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4161 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4162 rgba2
[0][j
] = value2
[0].f
[j
];
4163 rgba2
[1][j
] = value2
[1].f
[j
];
4164 rgba2
[2][j
] = value2
[2].f
[j
];
4165 rgba2
[3][j
] = value2
[3].f
[j
];
4169 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4173 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4174 r
[0].f
[j
] = rgba
[0][j
];
4175 r
[1].f
[j
] = rgba
[1][j
];
4176 r
[2].f
[j
] = rgba
[2][j
];
4177 r
[3].f
[j
] = rgba
[3][j
];
4179 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4180 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4181 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4187 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4188 const struct tgsi_full_instruction
*inst
)
4190 union tgsi_exec_channel r
[4];
4191 union tgsi_exec_channel value
[4], value2
[4];
4192 char *ptr
= mach
->LocalMem
;
4196 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4197 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4198 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4200 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4205 for (i
= 0; i
< 4; i
++) {
4206 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4207 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4208 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4211 memcpy(&r
[0].u
[0], ptr
, 4);
4213 switch (inst
->Instruction
.Opcode
) {
4214 case TGSI_OPCODE_ATOMUADD
:
4215 val
+= value
[0].u
[0];
4217 case TGSI_OPCODE_ATOMXOR
:
4218 val
^= value
[0].u
[0];
4220 case TGSI_OPCODE_ATOMOR
:
4221 val
|= value
[0].u
[0];
4223 case TGSI_OPCODE_ATOMAND
:
4224 val
&= value
[0].u
[0];
4226 case TGSI_OPCODE_ATOMUMIN
:
4227 val
= MIN2(val
, value
[0].u
[0]);
4229 case TGSI_OPCODE_ATOMUMAX
:
4230 val
= MAX2(val
, value
[0].u
[0]);
4232 case TGSI_OPCODE_ATOMIMIN
:
4233 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4235 case TGSI_OPCODE_ATOMIMAX
:
4236 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4238 case TGSI_OPCODE_ATOMXCHG
:
4239 val
= value
[0].i
[0];
4241 case TGSI_OPCODE_ATOMCAS
:
4242 if (val
== value
[0].u
[0])
4243 val
= value2
[0].u
[0];
4248 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4249 if (execmask
& (1 << i
))
4250 memcpy(ptr
, &val
, 4);
4252 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4253 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4254 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4260 exec_atomop(struct tgsi_exec_machine
*mach
,
4261 const struct tgsi_full_instruction
*inst
)
4263 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4264 exec_atomop_img(mach
, inst
);
4265 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4266 exec_atomop_buf(mach
, inst
);
4267 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4268 exec_atomop_mem(mach
, inst
);
4272 exec_resq_img(struct tgsi_exec_machine
*mach
,
4273 const struct tgsi_full_instruction
*inst
)
4276 union tgsi_exec_channel r
[4];
4279 struct tgsi_image_params params
;
4280 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4282 unit
= fetch_sampler_unit(mach
, inst
, 0);
4284 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4286 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4287 params
.format
= inst
->Memory
.Format
;
4289 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4291 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4292 for (j
= 0; j
< 4; j
++) {
4293 r
[j
].i
[i
] = result
[j
];
4297 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4298 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4299 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4300 TGSI_EXEC_DATA_INT
);
4306 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4307 const struct tgsi_full_instruction
*inst
)
4310 union tgsi_exec_channel r
[4];
4313 struct tgsi_buffer_params params
;
4314 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4316 unit
= fetch_sampler_unit(mach
, inst
, 0);
4318 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4321 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4323 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4327 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4328 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4329 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4330 TGSI_EXEC_DATA_INT
);
4336 exec_resq(struct tgsi_exec_machine
*mach
,
4337 const struct tgsi_full_instruction
*inst
)
4339 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4340 exec_resq_img(mach
, inst
);
4342 exec_resq_buf(mach
, inst
);
4346 micro_f2u64(union tgsi_double_channel
*dst
,
4347 const union tgsi_exec_channel
*src
)
4349 dst
->u64
[0] = (uint64_t)src
->f
[0];
4350 dst
->u64
[1] = (uint64_t)src
->f
[1];
4351 dst
->u64
[2] = (uint64_t)src
->f
[2];
4352 dst
->u64
[3] = (uint64_t)src
->f
[3];
4356 micro_f2i64(union tgsi_double_channel
*dst
,
4357 const union tgsi_exec_channel
*src
)
4359 dst
->i64
[0] = (int64_t)src
->f
[0];
4360 dst
->i64
[1] = (int64_t)src
->f
[1];
4361 dst
->i64
[2] = (int64_t)src
->f
[2];
4362 dst
->i64
[3] = (int64_t)src
->f
[3];
4366 micro_u2i64(union tgsi_double_channel
*dst
,
4367 const union tgsi_exec_channel
*src
)
4369 dst
->u64
[0] = (uint64_t)src
->u
[0];
4370 dst
->u64
[1] = (uint64_t)src
->u
[1];
4371 dst
->u64
[2] = (uint64_t)src
->u
[2];
4372 dst
->u64
[3] = (uint64_t)src
->u
[3];
4376 micro_i2i64(union tgsi_double_channel
*dst
,
4377 const union tgsi_exec_channel
*src
)
4379 dst
->i64
[0] = (int64_t)src
->i
[0];
4380 dst
->i64
[1] = (int64_t)src
->i
[1];
4381 dst
->i64
[2] = (int64_t)src
->i
[2];
4382 dst
->i64
[3] = (int64_t)src
->i
[3];
4386 micro_d2u64(union tgsi_double_channel
*dst
,
4387 const union tgsi_double_channel
*src
)
4389 dst
->u64
[0] = (uint64_t)src
->d
[0];
4390 dst
->u64
[1] = (uint64_t)src
->d
[1];
4391 dst
->u64
[2] = (uint64_t)src
->d
[2];
4392 dst
->u64
[3] = (uint64_t)src
->d
[3];
4396 micro_d2i64(union tgsi_double_channel
*dst
,
4397 const union tgsi_double_channel
*src
)
4399 dst
->i64
[0] = (int64_t)src
->d
[0];
4400 dst
->i64
[1] = (int64_t)src
->d
[1];
4401 dst
->i64
[2] = (int64_t)src
->d
[2];
4402 dst
->i64
[3] = (int64_t)src
->d
[3];
4406 micro_u642d(union tgsi_double_channel
*dst
,
4407 const union tgsi_double_channel
*src
)
4409 dst
->d
[0] = (double)src
->u64
[0];
4410 dst
->d
[1] = (double)src
->u64
[1];
4411 dst
->d
[2] = (double)src
->u64
[2];
4412 dst
->d
[3] = (double)src
->u64
[3];
4416 micro_i642d(union tgsi_double_channel
*dst
,
4417 const union tgsi_double_channel
*src
)
4419 dst
->d
[0] = (double)src
->i64
[0];
4420 dst
->d
[1] = (double)src
->i64
[1];
4421 dst
->d
[2] = (double)src
->i64
[2];
4422 dst
->d
[3] = (double)src
->i64
[3];
4426 micro_u642f(union tgsi_exec_channel
*dst
,
4427 const union tgsi_double_channel
*src
)
4429 dst
->f
[0] = (float)src
->u64
[0];
4430 dst
->f
[1] = (float)src
->u64
[1];
4431 dst
->f
[2] = (float)src
->u64
[2];
4432 dst
->f
[3] = (float)src
->u64
[3];
4436 micro_i642f(union tgsi_exec_channel
*dst
,
4437 const union tgsi_double_channel
*src
)
4439 dst
->f
[0] = (float)src
->i64
[0];
4440 dst
->f
[1] = (float)src
->i64
[1];
4441 dst
->f
[2] = (float)src
->i64
[2];
4442 dst
->f
[3] = (float)src
->i64
[3];
4446 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4447 const struct tgsi_full_instruction
*inst
,
4449 enum tgsi_exec_datatype src_datatype
)
4451 union tgsi_exec_channel src
;
4452 union tgsi_double_channel dst
;
4454 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4455 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4457 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4459 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4460 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4462 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4467 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4468 const struct tgsi_full_instruction
*inst
,
4470 enum tgsi_exec_datatype dst_datatype
)
4472 union tgsi_double_channel src
;
4473 union tgsi_exec_channel dst
;
4474 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4477 for (i
= 0; i
< 2; i
++) {
4480 wm
&= ~(1 << (bit
- 1));
4482 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4484 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4486 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4492 micro_i2f(union tgsi_exec_channel
*dst
,
4493 const union tgsi_exec_channel
*src
)
4495 dst
->f
[0] = (float)src
->i
[0];
4496 dst
->f
[1] = (float)src
->i
[1];
4497 dst
->f
[2] = (float)src
->i
[2];
4498 dst
->f
[3] = (float)src
->i
[3];
4502 micro_not(union tgsi_exec_channel
*dst
,
4503 const union tgsi_exec_channel
*src
)
4505 dst
->u
[0] = ~src
->u
[0];
4506 dst
->u
[1] = ~src
->u
[1];
4507 dst
->u
[2] = ~src
->u
[2];
4508 dst
->u
[3] = ~src
->u
[3];
4512 micro_shl(union tgsi_exec_channel
*dst
,
4513 const union tgsi_exec_channel
*src0
,
4514 const union tgsi_exec_channel
*src1
)
4516 unsigned masked_count
;
4517 masked_count
= src1
->u
[0] & 0x1f;
4518 dst
->u
[0] = src0
->u
[0] << masked_count
;
4519 masked_count
= src1
->u
[1] & 0x1f;
4520 dst
->u
[1] = src0
->u
[1] << masked_count
;
4521 masked_count
= src1
->u
[2] & 0x1f;
4522 dst
->u
[2] = src0
->u
[2] << masked_count
;
4523 masked_count
= src1
->u
[3] & 0x1f;
4524 dst
->u
[3] = src0
->u
[3] << masked_count
;
4528 micro_and(union tgsi_exec_channel
*dst
,
4529 const union tgsi_exec_channel
*src0
,
4530 const union tgsi_exec_channel
*src1
)
4532 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4533 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4534 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4535 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4539 micro_or(union tgsi_exec_channel
*dst
,
4540 const union tgsi_exec_channel
*src0
,
4541 const union tgsi_exec_channel
*src1
)
4543 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4544 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4545 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4546 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4550 micro_xor(union tgsi_exec_channel
*dst
,
4551 const union tgsi_exec_channel
*src0
,
4552 const union tgsi_exec_channel
*src1
)
4554 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4555 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4556 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4557 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4561 micro_mod(union tgsi_exec_channel
*dst
,
4562 const union tgsi_exec_channel
*src0
,
4563 const union tgsi_exec_channel
*src1
)
4565 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] % src1
->i
[0] : ~0;
4566 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] % src1
->i
[1] : ~0;
4567 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] % src1
->i
[2] : ~0;
4568 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] % src1
->i
[3] : ~0;
4572 micro_f2i(union tgsi_exec_channel
*dst
,
4573 const union tgsi_exec_channel
*src
)
4575 dst
->i
[0] = (int)src
->f
[0];
4576 dst
->i
[1] = (int)src
->f
[1];
4577 dst
->i
[2] = (int)src
->f
[2];
4578 dst
->i
[3] = (int)src
->f
[3];
4582 micro_fseq(union tgsi_exec_channel
*dst
,
4583 const union tgsi_exec_channel
*src0
,
4584 const union tgsi_exec_channel
*src1
)
4586 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4587 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4588 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4589 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4593 micro_fsge(union tgsi_exec_channel
*dst
,
4594 const union tgsi_exec_channel
*src0
,
4595 const union tgsi_exec_channel
*src1
)
4597 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4598 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4599 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4600 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4604 micro_fslt(union tgsi_exec_channel
*dst
,
4605 const union tgsi_exec_channel
*src0
,
4606 const union tgsi_exec_channel
*src1
)
4608 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4609 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4610 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4611 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4615 micro_fsne(union tgsi_exec_channel
*dst
,
4616 const union tgsi_exec_channel
*src0
,
4617 const union tgsi_exec_channel
*src1
)
4619 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4620 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4621 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4622 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4626 micro_idiv(union tgsi_exec_channel
*dst
,
4627 const union tgsi_exec_channel
*src0
,
4628 const union tgsi_exec_channel
*src1
)
4630 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4631 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4632 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4633 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4637 micro_imax(union tgsi_exec_channel
*dst
,
4638 const union tgsi_exec_channel
*src0
,
4639 const union tgsi_exec_channel
*src1
)
4641 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4642 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4643 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4644 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4648 micro_imin(union tgsi_exec_channel
*dst
,
4649 const union tgsi_exec_channel
*src0
,
4650 const union tgsi_exec_channel
*src1
)
4652 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4653 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4654 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4655 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4659 micro_isge(union tgsi_exec_channel
*dst
,
4660 const union tgsi_exec_channel
*src0
,
4661 const union tgsi_exec_channel
*src1
)
4663 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4664 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4665 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4666 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4670 micro_ishr(union tgsi_exec_channel
*dst
,
4671 const union tgsi_exec_channel
*src0
,
4672 const union tgsi_exec_channel
*src1
)
4674 unsigned masked_count
;
4675 masked_count
= src1
->i
[0] & 0x1f;
4676 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4677 masked_count
= src1
->i
[1] & 0x1f;
4678 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4679 masked_count
= src1
->i
[2] & 0x1f;
4680 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4681 masked_count
= src1
->i
[3] & 0x1f;
4682 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4686 micro_islt(union tgsi_exec_channel
*dst
,
4687 const union tgsi_exec_channel
*src0
,
4688 const union tgsi_exec_channel
*src1
)
4690 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4691 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4692 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4693 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4697 micro_f2u(union tgsi_exec_channel
*dst
,
4698 const union tgsi_exec_channel
*src
)
4700 dst
->u
[0] = (uint
)src
->f
[0];
4701 dst
->u
[1] = (uint
)src
->f
[1];
4702 dst
->u
[2] = (uint
)src
->f
[2];
4703 dst
->u
[3] = (uint
)src
->f
[3];
4707 micro_u2f(union tgsi_exec_channel
*dst
,
4708 const union tgsi_exec_channel
*src
)
4710 dst
->f
[0] = (float)src
->u
[0];
4711 dst
->f
[1] = (float)src
->u
[1];
4712 dst
->f
[2] = (float)src
->u
[2];
4713 dst
->f
[3] = (float)src
->u
[3];
4717 micro_uadd(union tgsi_exec_channel
*dst
,
4718 const union tgsi_exec_channel
*src0
,
4719 const union tgsi_exec_channel
*src1
)
4721 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4722 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4723 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4724 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4728 micro_udiv(union tgsi_exec_channel
*dst
,
4729 const union tgsi_exec_channel
*src0
,
4730 const union tgsi_exec_channel
*src1
)
4732 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4733 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4734 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4735 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4739 micro_umad(union tgsi_exec_channel
*dst
,
4740 const union tgsi_exec_channel
*src0
,
4741 const union tgsi_exec_channel
*src1
,
4742 const union tgsi_exec_channel
*src2
)
4744 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4745 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4746 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4747 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4751 micro_umax(union tgsi_exec_channel
*dst
,
4752 const union tgsi_exec_channel
*src0
,
4753 const union tgsi_exec_channel
*src1
)
4755 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4756 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4757 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4758 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4762 micro_umin(union tgsi_exec_channel
*dst
,
4763 const union tgsi_exec_channel
*src0
,
4764 const union tgsi_exec_channel
*src1
)
4766 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4767 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4768 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4769 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4773 micro_umod(union tgsi_exec_channel
*dst
,
4774 const union tgsi_exec_channel
*src0
,
4775 const union tgsi_exec_channel
*src1
)
4777 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4778 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4779 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4780 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4784 micro_umul(union tgsi_exec_channel
*dst
,
4785 const union tgsi_exec_channel
*src0
,
4786 const union tgsi_exec_channel
*src1
)
4788 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4789 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4790 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4791 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4795 micro_imul_hi(union tgsi_exec_channel
*dst
,
4796 const union tgsi_exec_channel
*src0
,
4797 const union tgsi_exec_channel
*src1
)
4799 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4800 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4801 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4802 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4803 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4808 micro_umul_hi(union tgsi_exec_channel
*dst
,
4809 const union tgsi_exec_channel
*src0
,
4810 const union tgsi_exec_channel
*src1
)
4812 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4813 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4814 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4815 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4816 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4821 micro_useq(union tgsi_exec_channel
*dst
,
4822 const union tgsi_exec_channel
*src0
,
4823 const union tgsi_exec_channel
*src1
)
4825 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4826 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4827 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4828 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4832 micro_usge(union tgsi_exec_channel
*dst
,
4833 const union tgsi_exec_channel
*src0
,
4834 const union tgsi_exec_channel
*src1
)
4836 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4837 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4838 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4839 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4843 micro_ushr(union tgsi_exec_channel
*dst
,
4844 const union tgsi_exec_channel
*src0
,
4845 const union tgsi_exec_channel
*src1
)
4847 unsigned masked_count
;
4848 masked_count
= src1
->u
[0] & 0x1f;
4849 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4850 masked_count
= src1
->u
[1] & 0x1f;
4851 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4852 masked_count
= src1
->u
[2] & 0x1f;
4853 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4854 masked_count
= src1
->u
[3] & 0x1f;
4855 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4859 micro_uslt(union tgsi_exec_channel
*dst
,
4860 const union tgsi_exec_channel
*src0
,
4861 const union tgsi_exec_channel
*src1
)
4863 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4864 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4865 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4866 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4870 micro_usne(union tgsi_exec_channel
*dst
,
4871 const union tgsi_exec_channel
*src0
,
4872 const union tgsi_exec_channel
*src1
)
4874 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4875 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4876 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4877 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4881 micro_uarl(union tgsi_exec_channel
*dst
,
4882 const union tgsi_exec_channel
*src
)
4884 dst
->i
[0] = src
->u
[0];
4885 dst
->i
[1] = src
->u
[1];
4886 dst
->i
[2] = src
->u
[2];
4887 dst
->i
[3] = src
->u
[3];
4891 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4894 micro_ibfe(union tgsi_exec_channel
*dst
,
4895 const union tgsi_exec_channel
*src0
,
4896 const union tgsi_exec_channel
*src1
,
4897 const union tgsi_exec_channel
*src2
)
4900 for (i
= 0; i
< 4; i
++) {
4901 int width
= src2
->i
[i
] & 0x1f;
4902 int offset
= src1
->i
[i
] & 0x1f;
4905 else if (width
+ offset
< 32)
4906 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
4908 dst
->i
[i
] = src0
->i
[i
] >> offset
;
4913 * Unsigned bitfield extract
4916 micro_ubfe(union tgsi_exec_channel
*dst
,
4917 const union tgsi_exec_channel
*src0
,
4918 const union tgsi_exec_channel
*src1
,
4919 const union tgsi_exec_channel
*src2
)
4922 for (i
= 0; i
< 4; i
++) {
4923 int width
= src2
->u
[i
] & 0x1f;
4924 int offset
= src1
->u
[i
] & 0x1f;
4927 else if (width
+ offset
< 32)
4928 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
4930 dst
->u
[i
] = src0
->u
[i
] >> offset
;
4935 * Bitfield insert: copy low bits from src1 into a region of src0.
4938 micro_bfi(union tgsi_exec_channel
*dst
,
4939 const union tgsi_exec_channel
*src0
,
4940 const union tgsi_exec_channel
*src1
,
4941 const union tgsi_exec_channel
*src2
,
4942 const union tgsi_exec_channel
*src3
)
4945 for (i
= 0; i
< 4; i
++) {
4946 int width
= src3
->u
[i
] & 0x1f;
4947 int offset
= src2
->u
[i
] & 0x1f;
4948 int bitmask
= ((1 << width
) - 1) << offset
;
4949 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
4954 micro_brev(union tgsi_exec_channel
*dst
,
4955 const union tgsi_exec_channel
*src
)
4957 dst
->u
[0] = util_bitreverse(src
->u
[0]);
4958 dst
->u
[1] = util_bitreverse(src
->u
[1]);
4959 dst
->u
[2] = util_bitreverse(src
->u
[2]);
4960 dst
->u
[3] = util_bitreverse(src
->u
[3]);
4964 micro_popc(union tgsi_exec_channel
*dst
,
4965 const union tgsi_exec_channel
*src
)
4967 dst
->u
[0] = util_bitcount(src
->u
[0]);
4968 dst
->u
[1] = util_bitcount(src
->u
[1]);
4969 dst
->u
[2] = util_bitcount(src
->u
[2]);
4970 dst
->u
[3] = util_bitcount(src
->u
[3]);
4974 micro_lsb(union tgsi_exec_channel
*dst
,
4975 const union tgsi_exec_channel
*src
)
4977 dst
->i
[0] = ffs(src
->u
[0]) - 1;
4978 dst
->i
[1] = ffs(src
->u
[1]) - 1;
4979 dst
->i
[2] = ffs(src
->u
[2]) - 1;
4980 dst
->i
[3] = ffs(src
->u
[3]) - 1;
4984 micro_imsb(union tgsi_exec_channel
*dst
,
4985 const union tgsi_exec_channel
*src
)
4987 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
4988 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
4989 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
4990 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
4994 micro_umsb(union tgsi_exec_channel
*dst
,
4995 const union tgsi_exec_channel
*src
)
4997 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
4998 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
4999 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5000 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5004 * Execute a TGSI instruction.
5005 * Returns TRUE if a barrier instruction is hit,
5010 struct tgsi_exec_machine
*mach
,
5011 const struct tgsi_full_instruction
*inst
,
5014 union tgsi_exec_channel r
[10];
5018 switch (inst
->Instruction
.Opcode
) {
5019 case TGSI_OPCODE_ARL
:
5020 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5023 case TGSI_OPCODE_MOV
:
5024 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5027 case TGSI_OPCODE_LIT
:
5028 exec_lit(mach
, inst
);
5031 case TGSI_OPCODE_RCP
:
5032 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5035 case TGSI_OPCODE_RSQ
:
5036 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5039 case TGSI_OPCODE_EXP
:
5040 exec_exp(mach
, inst
);
5043 case TGSI_OPCODE_LOG
:
5044 exec_log(mach
, inst
);
5047 case TGSI_OPCODE_MUL
:
5048 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5051 case TGSI_OPCODE_ADD
:
5052 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5055 case TGSI_OPCODE_DP3
:
5056 exec_dp3(mach
, inst
);
5059 case TGSI_OPCODE_DP4
:
5060 exec_dp4(mach
, inst
);
5063 case TGSI_OPCODE_DST
:
5064 exec_dst(mach
, inst
);
5067 case TGSI_OPCODE_MIN
:
5068 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5071 case TGSI_OPCODE_MAX
:
5072 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5075 case TGSI_OPCODE_SLT
:
5076 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5079 case TGSI_OPCODE_SGE
:
5080 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5083 case TGSI_OPCODE_MAD
:
5084 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5087 case TGSI_OPCODE_LRP
:
5088 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5091 case TGSI_OPCODE_SQRT
:
5092 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5095 case TGSI_OPCODE_FRC
:
5096 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5099 case TGSI_OPCODE_FLR
:
5100 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5103 case TGSI_OPCODE_ROUND
:
5104 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5107 case TGSI_OPCODE_EX2
:
5108 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5111 case TGSI_OPCODE_LG2
:
5112 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5115 case TGSI_OPCODE_POW
:
5116 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5119 case TGSI_OPCODE_LDEXP
:
5120 exec_vector_binary(mach
, inst
, micro_ldexp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5123 case TGSI_OPCODE_COS
:
5124 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5127 case TGSI_OPCODE_DDX
:
5128 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5131 case TGSI_OPCODE_DDY
:
5132 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5135 case TGSI_OPCODE_KILL
:
5139 case TGSI_OPCODE_KILL_IF
:
5140 exec_kill_if (mach
, inst
);
5143 case TGSI_OPCODE_PK2H
:
5144 exec_pk2h(mach
, inst
);
5147 case TGSI_OPCODE_PK2US
:
5151 case TGSI_OPCODE_PK4B
:
5155 case TGSI_OPCODE_PK4UB
:
5159 case TGSI_OPCODE_SEQ
:
5160 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5163 case TGSI_OPCODE_SGT
:
5164 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5167 case TGSI_OPCODE_SIN
:
5168 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5171 case TGSI_OPCODE_SLE
:
5172 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5175 case TGSI_OPCODE_SNE
:
5176 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5179 case TGSI_OPCODE_TEX
:
5180 /* simple texture lookup */
5181 /* src[0] = texcoord */
5182 /* src[1] = sampler unit */
5183 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5186 case TGSI_OPCODE_TXB
:
5187 /* Texture lookup with lod bias */
5188 /* src[0] = texcoord (src[0].w = LOD bias) */
5189 /* src[1] = sampler unit */
5190 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5193 case TGSI_OPCODE_TXD
:
5194 /* Texture lookup with explict partial derivatives */
5195 /* src[0] = texcoord */
5196 /* src[1] = d[strq]/dx */
5197 /* src[2] = d[strq]/dy */
5198 /* src[3] = sampler unit */
5199 exec_txd(mach
, inst
);
5202 case TGSI_OPCODE_TXL
:
5203 /* Texture lookup with explit LOD */
5204 /* src[0] = texcoord (src[0].w = LOD) */
5205 /* src[1] = sampler unit */
5206 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5209 case TGSI_OPCODE_TXP
:
5210 /* Texture lookup with projection */
5211 /* src[0] = texcoord (src[0].w = projection) */
5212 /* src[1] = sampler unit */
5213 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5216 case TGSI_OPCODE_TG4
:
5217 /* src[0] = texcoord */
5218 /* src[1] = component */
5219 /* src[2] = sampler unit */
5220 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5223 case TGSI_OPCODE_LODQ
:
5224 /* src[0] = texcoord */
5225 /* src[1] = sampler unit */
5226 exec_lodq(mach
, inst
);
5229 case TGSI_OPCODE_UP2H
:
5230 exec_up2h(mach
, inst
);
5233 case TGSI_OPCODE_UP2US
:
5237 case TGSI_OPCODE_UP4B
:
5241 case TGSI_OPCODE_UP4UB
:
5245 case TGSI_OPCODE_ARR
:
5246 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5249 case TGSI_OPCODE_CAL
:
5250 /* skip the call if no execution channels are enabled */
5251 if (mach
->ExecMask
) {
5254 /* First, record the depths of the execution stacks.
5255 * This is important for deeply nested/looped return statements.
5256 * We have to unwind the stacks by the correct amount. For a
5257 * real code generator, we could determine the number of entries
5258 * to pop off each stack with simple static analysis and avoid
5259 * implementing this data structure at run time.
5261 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5262 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5263 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5264 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5265 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5266 /* note that PC was already incremented above */
5267 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5269 mach
->CallStackTop
++;
5271 /* Second, push the Cond, Loop, Cont, Func stacks */
5272 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5273 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5274 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5275 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5276 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5277 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5279 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5280 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5281 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5282 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5283 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5284 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5286 /* Finally, jump to the subroutine. The label is a pointer
5287 * (an instruction number) to the BGNSUB instruction.
5289 *pc
= inst
->Label
.Label
;
5290 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5291 == TGSI_OPCODE_BGNSUB
);
5295 case TGSI_OPCODE_RET
:
5296 mach
->FuncMask
&= ~mach
->ExecMask
;
5297 UPDATE_EXEC_MASK(mach
);
5299 if (mach
->FuncMask
== 0x0) {
5300 /* really return now (otherwise, keep executing */
5302 if (mach
->CallStackTop
== 0) {
5303 /* returning from main() */
5304 mach
->CondStackTop
= 0;
5305 mach
->LoopStackTop
= 0;
5306 mach
->ContStackTop
= 0;
5307 mach
->LoopLabelStackTop
= 0;
5308 mach
->SwitchStackTop
= 0;
5309 mach
->BreakStackTop
= 0;
5314 assert(mach
->CallStackTop
> 0);
5315 mach
->CallStackTop
--;
5317 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5318 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5320 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5321 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5323 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5324 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5326 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5327 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5329 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5330 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5332 assert(mach
->FuncStackTop
> 0);
5333 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5335 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5337 UPDATE_EXEC_MASK(mach
);
5341 case TGSI_OPCODE_SSG
:
5342 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5345 case TGSI_OPCODE_CMP
:
5346 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5349 case TGSI_OPCODE_DIV
:
5350 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5353 case TGSI_OPCODE_DP2
:
5354 exec_dp2(mach
, inst
);
5357 case TGSI_OPCODE_IF
:
5359 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5360 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5361 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5362 /* update CondMask */
5364 mach
->CondMask
&= ~0x1;
5367 mach
->CondMask
&= ~0x2;
5370 mach
->CondMask
&= ~0x4;
5373 mach
->CondMask
&= ~0x8;
5375 UPDATE_EXEC_MASK(mach
);
5376 /* Todo: If CondMask==0, jump to ELSE */
5379 case TGSI_OPCODE_UIF
:
5381 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5382 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5383 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5384 /* update CondMask */
5386 mach
->CondMask
&= ~0x1;
5389 mach
->CondMask
&= ~0x2;
5392 mach
->CondMask
&= ~0x4;
5395 mach
->CondMask
&= ~0x8;
5397 UPDATE_EXEC_MASK(mach
);
5398 /* Todo: If CondMask==0, jump to ELSE */
5401 case TGSI_OPCODE_ELSE
:
5402 /* invert CondMask wrt previous mask */
5405 assert(mach
->CondStackTop
> 0);
5406 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5407 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5408 UPDATE_EXEC_MASK(mach
);
5409 /* Todo: If CondMask==0, jump to ENDIF */
5413 case TGSI_OPCODE_ENDIF
:
5415 assert(mach
->CondStackTop
> 0);
5416 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5417 UPDATE_EXEC_MASK(mach
);
5420 case TGSI_OPCODE_END
:
5421 /* make sure we end primitives which haven't
5422 * been explicitly emitted */
5423 conditional_emit_primitive(mach
);
5424 /* halt execution */
5428 case TGSI_OPCODE_CEIL
:
5429 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5432 case TGSI_OPCODE_I2F
:
5433 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5436 case TGSI_OPCODE_NOT
:
5437 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5440 case TGSI_OPCODE_TRUNC
:
5441 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5444 case TGSI_OPCODE_SHL
:
5445 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5448 case TGSI_OPCODE_AND
:
5449 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5452 case TGSI_OPCODE_OR
:
5453 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5456 case TGSI_OPCODE_MOD
:
5457 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5460 case TGSI_OPCODE_XOR
:
5461 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5464 case TGSI_OPCODE_TXF
:
5465 exec_txf(mach
, inst
);
5468 case TGSI_OPCODE_TXQ
:
5469 exec_txq(mach
, inst
);
5472 case TGSI_OPCODE_EMIT
:
5476 case TGSI_OPCODE_ENDPRIM
:
5477 emit_primitive(mach
);
5480 case TGSI_OPCODE_BGNLOOP
:
5481 /* push LoopMask and ContMasks */
5482 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5483 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5484 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5485 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5487 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5488 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5489 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5490 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5491 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5494 case TGSI_OPCODE_ENDLOOP
:
5495 /* Restore ContMask, but don't pop */
5496 assert(mach
->ContStackTop
> 0);
5497 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5498 UPDATE_EXEC_MASK(mach
);
5499 if (mach
->ExecMask
) {
5500 /* repeat loop: jump to instruction just past BGNLOOP */
5501 assert(mach
->LoopLabelStackTop
> 0);
5502 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5505 /* exit loop: pop LoopMask */
5506 assert(mach
->LoopStackTop
> 0);
5507 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5509 assert(mach
->ContStackTop
> 0);
5510 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5511 assert(mach
->LoopLabelStackTop
> 0);
5512 --mach
->LoopLabelStackTop
;
5514 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5516 UPDATE_EXEC_MASK(mach
);
5519 case TGSI_OPCODE_BRK
:
5523 case TGSI_OPCODE_CONT
:
5524 /* turn off cont channels for each enabled exec channel */
5525 mach
->ContMask
&= ~mach
->ExecMask
;
5526 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5527 UPDATE_EXEC_MASK(mach
);
5530 case TGSI_OPCODE_BGNSUB
:
5534 case TGSI_OPCODE_ENDSUB
:
5536 * XXX: This really should be a no-op. We should never reach this opcode.
5539 assert(mach
->CallStackTop
> 0);
5540 mach
->CallStackTop
--;
5542 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5543 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5545 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5546 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5548 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5549 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5551 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5552 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5554 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5555 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5557 assert(mach
->FuncStackTop
> 0);
5558 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5560 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5562 UPDATE_EXEC_MASK(mach
);
5565 case TGSI_OPCODE_NOP
:
5568 case TGSI_OPCODE_F2I
:
5569 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5572 case TGSI_OPCODE_FSEQ
:
5573 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5576 case TGSI_OPCODE_FSGE
:
5577 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5580 case TGSI_OPCODE_FSLT
:
5581 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5584 case TGSI_OPCODE_FSNE
:
5585 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5588 case TGSI_OPCODE_IDIV
:
5589 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5592 case TGSI_OPCODE_IMAX
:
5593 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5596 case TGSI_OPCODE_IMIN
:
5597 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5600 case TGSI_OPCODE_INEG
:
5601 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5604 case TGSI_OPCODE_ISGE
:
5605 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5608 case TGSI_OPCODE_ISHR
:
5609 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5612 case TGSI_OPCODE_ISLT
:
5613 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5616 case TGSI_OPCODE_F2U
:
5617 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5620 case TGSI_OPCODE_U2F
:
5621 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5624 case TGSI_OPCODE_UADD
:
5625 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5628 case TGSI_OPCODE_UDIV
:
5629 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5632 case TGSI_OPCODE_UMAD
:
5633 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5636 case TGSI_OPCODE_UMAX
:
5637 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5640 case TGSI_OPCODE_UMIN
:
5641 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5644 case TGSI_OPCODE_UMOD
:
5645 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5648 case TGSI_OPCODE_UMUL
:
5649 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5652 case TGSI_OPCODE_IMUL_HI
:
5653 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5656 case TGSI_OPCODE_UMUL_HI
:
5657 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5660 case TGSI_OPCODE_USEQ
:
5661 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5664 case TGSI_OPCODE_USGE
:
5665 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5668 case TGSI_OPCODE_USHR
:
5669 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5672 case TGSI_OPCODE_USLT
:
5673 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5676 case TGSI_OPCODE_USNE
:
5677 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5680 case TGSI_OPCODE_SWITCH
:
5681 exec_switch(mach
, inst
);
5684 case TGSI_OPCODE_CASE
:
5685 exec_case(mach
, inst
);
5688 case TGSI_OPCODE_DEFAULT
:
5692 case TGSI_OPCODE_ENDSWITCH
:
5693 exec_endswitch(mach
);
5696 case TGSI_OPCODE_SAMPLE_I
:
5697 exec_txf(mach
, inst
);
5700 case TGSI_OPCODE_SAMPLE_I_MS
:
5701 exec_txf(mach
, inst
);
5704 case TGSI_OPCODE_SAMPLE
:
5705 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5708 case TGSI_OPCODE_SAMPLE_B
:
5709 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5712 case TGSI_OPCODE_SAMPLE_C
:
5713 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5716 case TGSI_OPCODE_SAMPLE_C_LZ
:
5717 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5720 case TGSI_OPCODE_SAMPLE_D
:
5721 exec_sample_d(mach
, inst
);
5724 case TGSI_OPCODE_SAMPLE_L
:
5725 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5728 case TGSI_OPCODE_GATHER4
:
5729 exec_sample(mach
, inst
, TEX_MODIFIER_GATHER
, FALSE
);
5732 case TGSI_OPCODE_SVIEWINFO
:
5733 exec_txq(mach
, inst
);
5736 case TGSI_OPCODE_SAMPLE_POS
:
5740 case TGSI_OPCODE_SAMPLE_INFO
:
5744 case TGSI_OPCODE_LOD
:
5745 exec_lodq(mach
, inst
);
5748 case TGSI_OPCODE_UARL
:
5749 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5752 case TGSI_OPCODE_UCMP
:
5753 exec_ucmp(mach
, inst
);
5756 case TGSI_OPCODE_IABS
:
5757 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5760 case TGSI_OPCODE_ISSG
:
5761 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5764 case TGSI_OPCODE_TEX2
:
5765 /* simple texture lookup */
5766 /* src[0] = texcoord */
5767 /* src[1] = compare */
5768 /* src[2] = sampler unit */
5769 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5771 case TGSI_OPCODE_TXB2
:
5772 /* simple texture lookup */
5773 /* src[0] = texcoord */
5775 /* src[2] = sampler unit */
5776 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5778 case TGSI_OPCODE_TXL2
:
5779 /* simple texture lookup */
5780 /* src[0] = texcoord */
5782 /* src[2] = sampler unit */
5783 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5786 case TGSI_OPCODE_IBFE
:
5787 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5789 case TGSI_OPCODE_UBFE
:
5790 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5792 case TGSI_OPCODE_BFI
:
5793 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5795 case TGSI_OPCODE_BREV
:
5796 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5798 case TGSI_OPCODE_POPC
:
5799 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5801 case TGSI_OPCODE_LSB
:
5802 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5804 case TGSI_OPCODE_IMSB
:
5805 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5807 case TGSI_OPCODE_UMSB
:
5808 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5811 case TGSI_OPCODE_F2D
:
5812 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
5815 case TGSI_OPCODE_D2F
:
5816 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
5819 case TGSI_OPCODE_DABS
:
5820 exec_double_unary(mach
, inst
, micro_dabs
);
5823 case TGSI_OPCODE_DNEG
:
5824 exec_double_unary(mach
, inst
, micro_dneg
);
5827 case TGSI_OPCODE_DADD
:
5828 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5831 case TGSI_OPCODE_DDIV
:
5832 exec_double_binary(mach
, inst
, micro_ddiv
, TGSI_EXEC_DATA_DOUBLE
);
5835 case TGSI_OPCODE_DMUL
:
5836 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
5839 case TGSI_OPCODE_DMAX
:
5840 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
5843 case TGSI_OPCODE_DMIN
:
5844 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
5847 case TGSI_OPCODE_DSLT
:
5848 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
5851 case TGSI_OPCODE_DSGE
:
5852 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
5855 case TGSI_OPCODE_DSEQ
:
5856 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
5859 case TGSI_OPCODE_DSNE
:
5860 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
5863 case TGSI_OPCODE_DRCP
:
5864 exec_double_unary(mach
, inst
, micro_drcp
);
5867 case TGSI_OPCODE_DSQRT
:
5868 exec_double_unary(mach
, inst
, micro_dsqrt
);
5871 case TGSI_OPCODE_DRSQ
:
5872 exec_double_unary(mach
, inst
, micro_drsq
);
5875 case TGSI_OPCODE_DMAD
:
5876 exec_double_trinary(mach
, inst
, micro_dmad
);
5879 case TGSI_OPCODE_DFRAC
:
5880 exec_double_unary(mach
, inst
, micro_dfrac
);
5883 case TGSI_OPCODE_DLDEXP
:
5884 exec_dldexp(mach
, inst
);
5887 case TGSI_OPCODE_DFRACEXP
:
5888 exec_dfracexp(mach
, inst
);
5891 case TGSI_OPCODE_I2D
:
5892 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
5895 case TGSI_OPCODE_D2I
:
5896 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
5899 case TGSI_OPCODE_U2D
:
5900 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
5903 case TGSI_OPCODE_D2U
:
5904 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
5907 case TGSI_OPCODE_LOAD
:
5908 exec_load(mach
, inst
);
5911 case TGSI_OPCODE_STORE
:
5912 exec_store(mach
, inst
);
5915 case TGSI_OPCODE_ATOMUADD
:
5916 case TGSI_OPCODE_ATOMXCHG
:
5917 case TGSI_OPCODE_ATOMCAS
:
5918 case TGSI_OPCODE_ATOMAND
:
5919 case TGSI_OPCODE_ATOMOR
:
5920 case TGSI_OPCODE_ATOMXOR
:
5921 case TGSI_OPCODE_ATOMUMIN
:
5922 case TGSI_OPCODE_ATOMUMAX
:
5923 case TGSI_OPCODE_ATOMIMIN
:
5924 case TGSI_OPCODE_ATOMIMAX
:
5925 exec_atomop(mach
, inst
);
5928 case TGSI_OPCODE_RESQ
:
5929 exec_resq(mach
, inst
);
5931 case TGSI_OPCODE_BARRIER
:
5932 case TGSI_OPCODE_MEMBAR
:
5936 case TGSI_OPCODE_I64ABS
:
5937 exec_double_unary(mach
, inst
, micro_i64abs
);
5940 case TGSI_OPCODE_I64SSG
:
5941 exec_double_unary(mach
, inst
, micro_i64sgn
);
5944 case TGSI_OPCODE_I64NEG
:
5945 exec_double_unary(mach
, inst
, micro_i64neg
);
5948 case TGSI_OPCODE_U64SEQ
:
5949 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
5952 case TGSI_OPCODE_U64SNE
:
5953 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
5956 case TGSI_OPCODE_I64SLT
:
5957 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
5959 case TGSI_OPCODE_U64SLT
:
5960 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
5963 case TGSI_OPCODE_I64SGE
:
5964 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
5966 case TGSI_OPCODE_U64SGE
:
5967 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
5970 case TGSI_OPCODE_I64MIN
:
5971 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
5973 case TGSI_OPCODE_U64MIN
:
5974 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
5976 case TGSI_OPCODE_I64MAX
:
5977 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
5979 case TGSI_OPCODE_U64MAX
:
5980 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
5982 case TGSI_OPCODE_U64ADD
:
5983 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
5985 case TGSI_OPCODE_U64MUL
:
5986 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
5988 case TGSI_OPCODE_U64SHL
:
5989 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
5991 case TGSI_OPCODE_I64SHR
:
5992 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
5994 case TGSI_OPCODE_U64SHR
:
5995 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
5997 case TGSI_OPCODE_U64DIV
:
5998 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6000 case TGSI_OPCODE_I64DIV
:
6001 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6003 case TGSI_OPCODE_U64MOD
:
6004 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6006 case TGSI_OPCODE_I64MOD
:
6007 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6010 case TGSI_OPCODE_F2U64
:
6011 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6014 case TGSI_OPCODE_F2I64
:
6015 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6018 case TGSI_OPCODE_U2I64
:
6019 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6021 case TGSI_OPCODE_I2I64
:
6022 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6025 case TGSI_OPCODE_D2U64
:
6026 exec_double_unary(mach
, inst
, micro_d2u64
);
6029 case TGSI_OPCODE_D2I64
:
6030 exec_double_unary(mach
, inst
, micro_d2i64
);
6033 case TGSI_OPCODE_U642F
:
6034 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6036 case TGSI_OPCODE_I642F
:
6037 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6040 case TGSI_OPCODE_U642D
:
6041 exec_double_unary(mach
, inst
, micro_u642d
);
6043 case TGSI_OPCODE_I642D
:
6044 exec_double_unary(mach
, inst
, micro_i642d
);
6054 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6056 uint default_mask
= 0xf;
6058 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6059 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6061 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6062 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
6063 mach
->Primitives
[0] = 0;
6064 /* GS runs on a single primitive for now */
6068 if (mach
->NonHelperMask
== 0)
6069 mach
->NonHelperMask
= default_mask
;
6070 mach
->CondMask
= default_mask
;
6071 mach
->LoopMask
= default_mask
;
6072 mach
->ContMask
= default_mask
;
6073 mach
->FuncMask
= default_mask
;
6074 mach
->ExecMask
= default_mask
;
6076 mach
->Switch
.mask
= default_mask
;
6078 assert(mach
->CondStackTop
== 0);
6079 assert(mach
->LoopStackTop
== 0);
6080 assert(mach
->ContStackTop
== 0);
6081 assert(mach
->SwitchStackTop
== 0);
6082 assert(mach
->BreakStackTop
== 0);
6083 assert(mach
->CallStackTop
== 0);
6087 * Run TGSI interpreter.
6088 * \return bitmask of "alive" quad components
6091 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6095 mach
->pc
= start_pc
;
6098 tgsi_exec_machine_setup_masks(mach
);
6100 /* execute declarations (interpolants) */
6101 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6102 exec_declaration( mach
, mach
->Declarations
+i
);
6108 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6109 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6113 memset(mach
->Temps
, 0, sizeof(temps
));
6115 memset(mach
->Outputs
, 0, sizeof(outputs
));
6116 memset(temps
, 0, sizeof(temps
));
6117 memset(outputs
, 0, sizeof(outputs
));
6121 /* execute instructions, until pc is set to -1 */
6122 while (mach
->pc
!= -1) {
6123 boolean barrier_hit
;
6127 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6130 assert(mach
->pc
< (int) mach
->NumInstructions
);
6131 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6133 /* for compute shaders if we hit a barrier return now for later rescheduling */
6134 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6138 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6139 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6142 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6143 debug_printf("TEMP[%2u] = ", i
);
6144 for (j
= 0; j
< 4; j
++) {
6148 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6149 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6150 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6151 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6152 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6156 if (mach
->Outputs
) {
6157 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6158 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6161 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6162 debug_printf("OUT[%2u] = ", i
);
6163 for (j
= 0; j
< 4; j
++) {
6167 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6168 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6169 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6170 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6171 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6181 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6182 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6184 * Scale back depth component.
6186 for (i
= 0; i
< 4; i
++)
6187 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6191 /* Strictly speaking, these assertions aren't really needed but they
6192 * can potentially catch some bugs in the control flow code.
6194 assert(mach
->CondStackTop
== 0);
6195 assert(mach
->LoopStackTop
== 0);
6196 assert(mach
->ContStackTop
== 0);
6197 assert(mach
->SwitchStackTop
== 0);
6198 assert(mach
->BreakStackTop
== 0);
6199 assert(mach
->CallStackTop
== 0);
6201 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];