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gallium: remove TGSI_OPCODE_CLAMP
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
65
66
67 #define DEBUG_EXECUTION 0
68
69
70 #define FAST_MATH 0
71
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
76
77 union tgsi_double_channel {
78 double d[TGSI_QUAD_SIZE];
79 unsigned u[TGSI_QUAD_SIZE][2];
80 uint64_t u64[TGSI_QUAD_SIZE];
81 int64_t i64[TGSI_QUAD_SIZE];
82 };
83
84 struct tgsi_double_vector {
85 union tgsi_double_channel xy;
86 union tgsi_double_channel zw;
87 };
88
89 static void
90 micro_abs(union tgsi_exec_channel *dst,
91 const union tgsi_exec_channel *src)
92 {
93 dst->f[0] = fabsf(src->f[0]);
94 dst->f[1] = fabsf(src->f[1]);
95 dst->f[2] = fabsf(src->f[2]);
96 dst->f[3] = fabsf(src->f[3]);
97 }
98
99 static void
100 micro_arl(union tgsi_exec_channel *dst,
101 const union tgsi_exec_channel *src)
102 {
103 dst->i[0] = (int)floorf(src->f[0]);
104 dst->i[1] = (int)floorf(src->f[1]);
105 dst->i[2] = (int)floorf(src->f[2]);
106 dst->i[3] = (int)floorf(src->f[3]);
107 }
108
109 static void
110 micro_arr(union tgsi_exec_channel *dst,
111 const union tgsi_exec_channel *src)
112 {
113 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
114 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
115 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
116 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
117 }
118
119 static void
120 micro_ceil(union tgsi_exec_channel *dst,
121 const union tgsi_exec_channel *src)
122 {
123 dst->f[0] = ceilf(src->f[0]);
124 dst->f[1] = ceilf(src->f[1]);
125 dst->f[2] = ceilf(src->f[2]);
126 dst->f[3] = ceilf(src->f[3]);
127 }
128
129 static void
130 micro_cmp(union tgsi_exec_channel *dst,
131 const union tgsi_exec_channel *src0,
132 const union tgsi_exec_channel *src1,
133 const union tgsi_exec_channel *src2)
134 {
135 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
136 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
137 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
138 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
139 }
140
141 static void
142 micro_cos(union tgsi_exec_channel *dst,
143 const union tgsi_exec_channel *src)
144 {
145 dst->f[0] = cosf(src->f[0]);
146 dst->f[1] = cosf(src->f[1]);
147 dst->f[2] = cosf(src->f[2]);
148 dst->f[3] = cosf(src->f[3]);
149 }
150
151 static void
152 micro_d2f(union tgsi_exec_channel *dst,
153 const union tgsi_double_channel *src)
154 {
155 dst->f[0] = (float)src->d[0];
156 dst->f[1] = (float)src->d[1];
157 dst->f[2] = (float)src->d[2];
158 dst->f[3] = (float)src->d[3];
159 }
160
161 static void
162 micro_d2i(union tgsi_exec_channel *dst,
163 const union tgsi_double_channel *src)
164 {
165 dst->i[0] = (int)src->d[0];
166 dst->i[1] = (int)src->d[1];
167 dst->i[2] = (int)src->d[2];
168 dst->i[3] = (int)src->d[3];
169 }
170
171 static void
172 micro_d2u(union tgsi_exec_channel *dst,
173 const union tgsi_double_channel *src)
174 {
175 dst->u[0] = (unsigned)src->d[0];
176 dst->u[1] = (unsigned)src->d[1];
177 dst->u[2] = (unsigned)src->d[2];
178 dst->u[3] = (unsigned)src->d[3];
179 }
180 static void
181 micro_dabs(union tgsi_double_channel *dst,
182 const union tgsi_double_channel *src)
183 {
184 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
185 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
186 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
187 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
188 }
189
190 static void
191 micro_dadd(union tgsi_double_channel *dst,
192 const union tgsi_double_channel *src)
193 {
194 dst->d[0] = src[0].d[0] + src[1].d[0];
195 dst->d[1] = src[0].d[1] + src[1].d[1];
196 dst->d[2] = src[0].d[2] + src[1].d[2];
197 dst->d[3] = src[0].d[3] + src[1].d[3];
198 }
199
200 static void
201 micro_ddiv(union tgsi_double_channel *dst,
202 const union tgsi_double_channel *src)
203 {
204 dst->d[0] = src[0].d[0] / src[1].d[0];
205 dst->d[1] = src[0].d[1] / src[1].d[1];
206 dst->d[2] = src[0].d[2] / src[1].d[2];
207 dst->d[3] = src[0].d[3] / src[1].d[3];
208 }
209
210 static void
211 micro_ddx(union tgsi_exec_channel *dst,
212 const union tgsi_exec_channel *src)
213 {
214 dst->f[0] =
215 dst->f[1] =
216 dst->f[2] =
217 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
218 }
219
220 static void
221 micro_ddy(union tgsi_exec_channel *dst,
222 const union tgsi_exec_channel *src)
223 {
224 dst->f[0] =
225 dst->f[1] =
226 dst->f[2] =
227 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
228 }
229
230 static void
231 micro_dmul(union tgsi_double_channel *dst,
232 const union tgsi_double_channel *src)
233 {
234 dst->d[0] = src[0].d[0] * src[1].d[0];
235 dst->d[1] = src[0].d[1] * src[1].d[1];
236 dst->d[2] = src[0].d[2] * src[1].d[2];
237 dst->d[3] = src[0].d[3] * src[1].d[3];
238 }
239
240 static void
241 micro_dmax(union tgsi_double_channel *dst,
242 const union tgsi_double_channel *src)
243 {
244 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
245 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
246 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
247 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
248 }
249
250 static void
251 micro_dmin(union tgsi_double_channel *dst,
252 const union tgsi_double_channel *src)
253 {
254 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
255 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
256 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
257 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
258 }
259
260 static void
261 micro_dneg(union tgsi_double_channel *dst,
262 const union tgsi_double_channel *src)
263 {
264 dst->d[0] = -src->d[0];
265 dst->d[1] = -src->d[1];
266 dst->d[2] = -src->d[2];
267 dst->d[3] = -src->d[3];
268 }
269
270 static void
271 micro_dslt(union tgsi_double_channel *dst,
272 const union tgsi_double_channel *src)
273 {
274 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
275 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
276 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
277 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
278 }
279
280 static void
281 micro_dsne(union tgsi_double_channel *dst,
282 const union tgsi_double_channel *src)
283 {
284 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
285 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
286 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
287 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
288 }
289
290 static void
291 micro_dsge(union tgsi_double_channel *dst,
292 const union tgsi_double_channel *src)
293 {
294 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
295 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
296 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
297 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
298 }
299
300 static void
301 micro_dseq(union tgsi_double_channel *dst,
302 const union tgsi_double_channel *src)
303 {
304 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
305 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
306 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
307 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
308 }
309
310 static void
311 micro_drcp(union tgsi_double_channel *dst,
312 const union tgsi_double_channel *src)
313 {
314 dst->d[0] = 1.0 / src->d[0];
315 dst->d[1] = 1.0 / src->d[1];
316 dst->d[2] = 1.0 / src->d[2];
317 dst->d[3] = 1.0 / src->d[3];
318 }
319
320 static void
321 micro_dsqrt(union tgsi_double_channel *dst,
322 const union tgsi_double_channel *src)
323 {
324 dst->d[0] = sqrt(src->d[0]);
325 dst->d[1] = sqrt(src->d[1]);
326 dst->d[2] = sqrt(src->d[2]);
327 dst->d[3] = sqrt(src->d[3]);
328 }
329
330 static void
331 micro_drsq(union tgsi_double_channel *dst,
332 const union tgsi_double_channel *src)
333 {
334 dst->d[0] = 1.0 / sqrt(src->d[0]);
335 dst->d[1] = 1.0 / sqrt(src->d[1]);
336 dst->d[2] = 1.0 / sqrt(src->d[2]);
337 dst->d[3] = 1.0 / sqrt(src->d[3]);
338 }
339
340 static void
341 micro_dmad(union tgsi_double_channel *dst,
342 const union tgsi_double_channel *src)
343 {
344 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
345 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
346 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
347 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
348 }
349
350 static void
351 micro_dfrac(union tgsi_double_channel *dst,
352 const union tgsi_double_channel *src)
353 {
354 dst->d[0] = src->d[0] - floor(src->d[0]);
355 dst->d[1] = src->d[1] - floor(src->d[1]);
356 dst->d[2] = src->d[2] - floor(src->d[2]);
357 dst->d[3] = src->d[3] - floor(src->d[3]);
358 }
359
360 static void
361 micro_dldexp(union tgsi_double_channel *dst,
362 const union tgsi_double_channel *src0,
363 union tgsi_exec_channel *src1)
364 {
365 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
366 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
367 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
368 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
369 }
370
371 static void
372 micro_dfracexp(union tgsi_double_channel *dst,
373 union tgsi_exec_channel *dst_exp,
374 const union tgsi_double_channel *src)
375 {
376 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
377 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
378 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
379 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
380 }
381
382 static void
383 micro_exp2(union tgsi_exec_channel *dst,
384 const union tgsi_exec_channel *src)
385 {
386 #if FAST_MATH
387 dst->f[0] = util_fast_exp2(src->f[0]);
388 dst->f[1] = util_fast_exp2(src->f[1]);
389 dst->f[2] = util_fast_exp2(src->f[2]);
390 dst->f[3] = util_fast_exp2(src->f[3]);
391 #else
392 #if DEBUG
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
394 uint i;
395 union tgsi_exec_channel clamped;
396
397 for (i = 0; i < 4; i++) {
398 if (src->f[i] > 127.99999f) {
399 clamped.f[i] = 127.99999f;
400 } else if (src->f[i] < -126.99999f) {
401 clamped.f[i] = -126.99999f;
402 } else {
403 clamped.f[i] = src->f[i];
404 }
405 }
406 src = &clamped;
407 #endif /* DEBUG */
408
409 dst->f[0] = powf(2.0f, src->f[0]);
410 dst->f[1] = powf(2.0f, src->f[1]);
411 dst->f[2] = powf(2.0f, src->f[2]);
412 dst->f[3] = powf(2.0f, src->f[3]);
413 #endif /* FAST_MATH */
414 }
415
416 static void
417 micro_f2d(union tgsi_double_channel *dst,
418 const union tgsi_exec_channel *src)
419 {
420 dst->d[0] = (double)src->f[0];
421 dst->d[1] = (double)src->f[1];
422 dst->d[2] = (double)src->f[2];
423 dst->d[3] = (double)src->f[3];
424 }
425
426 static void
427 micro_flr(union tgsi_exec_channel *dst,
428 const union tgsi_exec_channel *src)
429 {
430 dst->f[0] = floorf(src->f[0]);
431 dst->f[1] = floorf(src->f[1]);
432 dst->f[2] = floorf(src->f[2]);
433 dst->f[3] = floorf(src->f[3]);
434 }
435
436 static void
437 micro_frc(union tgsi_exec_channel *dst,
438 const union tgsi_exec_channel *src)
439 {
440 dst->f[0] = src->f[0] - floorf(src->f[0]);
441 dst->f[1] = src->f[1] - floorf(src->f[1]);
442 dst->f[2] = src->f[2] - floorf(src->f[2]);
443 dst->f[3] = src->f[3] - floorf(src->f[3]);
444 }
445
446 static void
447 micro_i2d(union tgsi_double_channel *dst,
448 const union tgsi_exec_channel *src)
449 {
450 dst->d[0] = (double)src->i[0];
451 dst->d[1] = (double)src->i[1];
452 dst->d[2] = (double)src->i[2];
453 dst->d[3] = (double)src->i[3];
454 }
455
456 static void
457 micro_iabs(union tgsi_exec_channel *dst,
458 const union tgsi_exec_channel *src)
459 {
460 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
461 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
462 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
463 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
464 }
465
466 static void
467 micro_ineg(union tgsi_exec_channel *dst,
468 const union tgsi_exec_channel *src)
469 {
470 dst->i[0] = -src->i[0];
471 dst->i[1] = -src->i[1];
472 dst->i[2] = -src->i[2];
473 dst->i[3] = -src->i[3];
474 }
475
476 static void
477 micro_lg2(union tgsi_exec_channel *dst,
478 const union tgsi_exec_channel *src)
479 {
480 #if FAST_MATH
481 dst->f[0] = util_fast_log2(src->f[0]);
482 dst->f[1] = util_fast_log2(src->f[1]);
483 dst->f[2] = util_fast_log2(src->f[2]);
484 dst->f[3] = util_fast_log2(src->f[3]);
485 #else
486 dst->f[0] = logf(src->f[0]) * 1.442695f;
487 dst->f[1] = logf(src->f[1]) * 1.442695f;
488 dst->f[2] = logf(src->f[2]) * 1.442695f;
489 dst->f[3] = logf(src->f[3]) * 1.442695f;
490 #endif
491 }
492
493 static void
494 micro_lrp(union tgsi_exec_channel *dst,
495 const union tgsi_exec_channel *src0,
496 const union tgsi_exec_channel *src1,
497 const union tgsi_exec_channel *src2)
498 {
499 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
500 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
501 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
502 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
503 }
504
505 static void
506 micro_mad(union tgsi_exec_channel *dst,
507 const union tgsi_exec_channel *src0,
508 const union tgsi_exec_channel *src1,
509 const union tgsi_exec_channel *src2)
510 {
511 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
512 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
513 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
514 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
515 }
516
517 static void
518 micro_mov(union tgsi_exec_channel *dst,
519 const union tgsi_exec_channel *src)
520 {
521 dst->u[0] = src->u[0];
522 dst->u[1] = src->u[1];
523 dst->u[2] = src->u[2];
524 dst->u[3] = src->u[3];
525 }
526
527 static void
528 micro_rcp(union tgsi_exec_channel *dst,
529 const union tgsi_exec_channel *src)
530 {
531 #if 0 /* for debugging */
532 assert(src->f[0] != 0.0f);
533 assert(src->f[1] != 0.0f);
534 assert(src->f[2] != 0.0f);
535 assert(src->f[3] != 0.0f);
536 #endif
537 dst->f[0] = 1.0f / src->f[0];
538 dst->f[1] = 1.0f / src->f[1];
539 dst->f[2] = 1.0f / src->f[2];
540 dst->f[3] = 1.0f / src->f[3];
541 }
542
543 static void
544 micro_rnd(union tgsi_exec_channel *dst,
545 const union tgsi_exec_channel *src)
546 {
547 dst->f[0] = _mesa_roundevenf(src->f[0]);
548 dst->f[1] = _mesa_roundevenf(src->f[1]);
549 dst->f[2] = _mesa_roundevenf(src->f[2]);
550 dst->f[3] = _mesa_roundevenf(src->f[3]);
551 }
552
553 static void
554 micro_rsq(union tgsi_exec_channel *dst,
555 const union tgsi_exec_channel *src)
556 {
557 #if 0 /* for debugging */
558 assert(src->f[0] != 0.0f);
559 assert(src->f[1] != 0.0f);
560 assert(src->f[2] != 0.0f);
561 assert(src->f[3] != 0.0f);
562 #endif
563 dst->f[0] = 1.0f / sqrtf(src->f[0]);
564 dst->f[1] = 1.0f / sqrtf(src->f[1]);
565 dst->f[2] = 1.0f / sqrtf(src->f[2]);
566 dst->f[3] = 1.0f / sqrtf(src->f[3]);
567 }
568
569 static void
570 micro_sqrt(union tgsi_exec_channel *dst,
571 const union tgsi_exec_channel *src)
572 {
573 dst->f[0] = sqrtf(src->f[0]);
574 dst->f[1] = sqrtf(src->f[1]);
575 dst->f[2] = sqrtf(src->f[2]);
576 dst->f[3] = sqrtf(src->f[3]);
577 }
578
579 static void
580 micro_seq(union tgsi_exec_channel *dst,
581 const union tgsi_exec_channel *src0,
582 const union tgsi_exec_channel *src1)
583 {
584 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
585 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
586 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
587 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
588 }
589
590 static void
591 micro_sge(union tgsi_exec_channel *dst,
592 const union tgsi_exec_channel *src0,
593 const union tgsi_exec_channel *src1)
594 {
595 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
596 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
597 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
598 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
599 }
600
601 static void
602 micro_sgn(union tgsi_exec_channel *dst,
603 const union tgsi_exec_channel *src)
604 {
605 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
606 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
607 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
608 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
609 }
610
611 static void
612 micro_isgn(union tgsi_exec_channel *dst,
613 const union tgsi_exec_channel *src)
614 {
615 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
616 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
617 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
618 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
619 }
620
621 static void
622 micro_sgt(union tgsi_exec_channel *dst,
623 const union tgsi_exec_channel *src0,
624 const union tgsi_exec_channel *src1)
625 {
626 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
627 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
628 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
629 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
630 }
631
632 static void
633 micro_sin(union tgsi_exec_channel *dst,
634 const union tgsi_exec_channel *src)
635 {
636 dst->f[0] = sinf(src->f[0]);
637 dst->f[1] = sinf(src->f[1]);
638 dst->f[2] = sinf(src->f[2]);
639 dst->f[3] = sinf(src->f[3]);
640 }
641
642 static void
643 micro_sle(union tgsi_exec_channel *dst,
644 const union tgsi_exec_channel *src0,
645 const union tgsi_exec_channel *src1)
646 {
647 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
648 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
649 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
650 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
651 }
652
653 static void
654 micro_slt(union tgsi_exec_channel *dst,
655 const union tgsi_exec_channel *src0,
656 const union tgsi_exec_channel *src1)
657 {
658 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
659 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
660 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
661 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
662 }
663
664 static void
665 micro_sne(union tgsi_exec_channel *dst,
666 const union tgsi_exec_channel *src0,
667 const union tgsi_exec_channel *src1)
668 {
669 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
670 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
671 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
672 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
673 }
674
675 static void
676 micro_trunc(union tgsi_exec_channel *dst,
677 const union tgsi_exec_channel *src)
678 {
679 dst->f[0] = truncf(src->f[0]);
680 dst->f[1] = truncf(src->f[1]);
681 dst->f[2] = truncf(src->f[2]);
682 dst->f[3] = truncf(src->f[3]);
683 }
684
685 static void
686 micro_u2d(union tgsi_double_channel *dst,
687 const union tgsi_exec_channel *src)
688 {
689 dst->d[0] = (double)src->u[0];
690 dst->d[1] = (double)src->u[1];
691 dst->d[2] = (double)src->u[2];
692 dst->d[3] = (double)src->u[3];
693 }
694
695 static void
696 micro_i64abs(union tgsi_double_channel *dst,
697 const union tgsi_double_channel *src)
698 {
699 dst->i64[0] = src->i64[0] >= 0.0 ? src->i64[0] : -src->i64[0];
700 dst->i64[1] = src->i64[1] >= 0.0 ? src->i64[1] : -src->i64[1];
701 dst->i64[2] = src->i64[2] >= 0.0 ? src->i64[2] : -src->i64[2];
702 dst->i64[3] = src->i64[3] >= 0.0 ? src->i64[3] : -src->i64[3];
703 }
704
705 static void
706 micro_i64sgn(union tgsi_double_channel *dst,
707 const union tgsi_double_channel *src)
708 {
709 dst->i64[0] = src->i64[0] < 0 ? -1 : src->i64[0] > 0 ? 1 : 0;
710 dst->i64[1] = src->i64[1] < 0 ? -1 : src->i64[1] > 0 ? 1 : 0;
711 dst->i64[2] = src->i64[2] < 0 ? -1 : src->i64[2] > 0 ? 1 : 0;
712 dst->i64[3] = src->i64[3] < 0 ? -1 : src->i64[3] > 0 ? 1 : 0;
713 }
714
715 static void
716 micro_i64neg(union tgsi_double_channel *dst,
717 const union tgsi_double_channel *src)
718 {
719 dst->i64[0] = -src->i64[0];
720 dst->i64[1] = -src->i64[1];
721 dst->i64[2] = -src->i64[2];
722 dst->i64[3] = -src->i64[3];
723 }
724
725 static void
726 micro_u64seq(union tgsi_double_channel *dst,
727 const union tgsi_double_channel *src)
728 {
729 dst->u[0][0] = src[0].u64[0] == src[1].u64[0] ? ~0U : 0U;
730 dst->u[1][0] = src[0].u64[1] == src[1].u64[1] ? ~0U : 0U;
731 dst->u[2][0] = src[0].u64[2] == src[1].u64[2] ? ~0U : 0U;
732 dst->u[3][0] = src[0].u64[3] == src[1].u64[3] ? ~0U : 0U;
733 }
734
735 static void
736 micro_u64sne(union tgsi_double_channel *dst,
737 const union tgsi_double_channel *src)
738 {
739 dst->u[0][0] = src[0].u64[0] != src[1].u64[0] ? ~0U : 0U;
740 dst->u[1][0] = src[0].u64[1] != src[1].u64[1] ? ~0U : 0U;
741 dst->u[2][0] = src[0].u64[2] != src[1].u64[2] ? ~0U : 0U;
742 dst->u[3][0] = src[0].u64[3] != src[1].u64[3] ? ~0U : 0U;
743 }
744
745 static void
746 micro_i64slt(union tgsi_double_channel *dst,
747 const union tgsi_double_channel *src)
748 {
749 dst->u[0][0] = src[0].i64[0] < src[1].i64[0] ? ~0U : 0U;
750 dst->u[1][0] = src[0].i64[1] < src[1].i64[1] ? ~0U : 0U;
751 dst->u[2][0] = src[0].i64[2] < src[1].i64[2] ? ~0U : 0U;
752 dst->u[3][0] = src[0].i64[3] < src[1].i64[3] ? ~0U : 0U;
753 }
754
755 static void
756 micro_u64slt(union tgsi_double_channel *dst,
757 const union tgsi_double_channel *src)
758 {
759 dst->u[0][0] = src[0].u64[0] < src[1].u64[0] ? ~0U : 0U;
760 dst->u[1][0] = src[0].u64[1] < src[1].u64[1] ? ~0U : 0U;
761 dst->u[2][0] = src[0].u64[2] < src[1].u64[2] ? ~0U : 0U;
762 dst->u[3][0] = src[0].u64[3] < src[1].u64[3] ? ~0U : 0U;
763 }
764
765 static void
766 micro_i64sge(union tgsi_double_channel *dst,
767 const union tgsi_double_channel *src)
768 {
769 dst->u[0][0] = src[0].i64[0] >= src[1].i64[0] ? ~0U : 0U;
770 dst->u[1][0] = src[0].i64[1] >= src[1].i64[1] ? ~0U : 0U;
771 dst->u[2][0] = src[0].i64[2] >= src[1].i64[2] ? ~0U : 0U;
772 dst->u[3][0] = src[0].i64[3] >= src[1].i64[3] ? ~0U : 0U;
773 }
774
775 static void
776 micro_u64sge(union tgsi_double_channel *dst,
777 const union tgsi_double_channel *src)
778 {
779 dst->u[0][0] = src[0].u64[0] >= src[1].u64[0] ? ~0U : 0U;
780 dst->u[1][0] = src[0].u64[1] >= src[1].u64[1] ? ~0U : 0U;
781 dst->u[2][0] = src[0].u64[2] >= src[1].u64[2] ? ~0U : 0U;
782 dst->u[3][0] = src[0].u64[3] >= src[1].u64[3] ? ~0U : 0U;
783 }
784
785 static void
786 micro_u64max(union tgsi_double_channel *dst,
787 const union tgsi_double_channel *src)
788 {
789 dst->u64[0] = src[0].u64[0] > src[1].u64[0] ? src[0].u64[0] : src[1].u64[0];
790 dst->u64[1] = src[0].u64[1] > src[1].u64[1] ? src[0].u64[1] : src[1].u64[1];
791 dst->u64[2] = src[0].u64[2] > src[1].u64[2] ? src[0].u64[2] : src[1].u64[2];
792 dst->u64[3] = src[0].u64[3] > src[1].u64[3] ? src[0].u64[3] : src[1].u64[3];
793 }
794
795 static void
796 micro_i64max(union tgsi_double_channel *dst,
797 const union tgsi_double_channel *src)
798 {
799 dst->i64[0] = src[0].i64[0] > src[1].i64[0] ? src[0].i64[0] : src[1].i64[0];
800 dst->i64[1] = src[0].i64[1] > src[1].i64[1] ? src[0].i64[1] : src[1].i64[1];
801 dst->i64[2] = src[0].i64[2] > src[1].i64[2] ? src[0].i64[2] : src[1].i64[2];
802 dst->i64[3] = src[0].i64[3] > src[1].i64[3] ? src[0].i64[3] : src[1].i64[3];
803 }
804
805 static void
806 micro_u64min(union tgsi_double_channel *dst,
807 const union tgsi_double_channel *src)
808 {
809 dst->u64[0] = src[0].u64[0] < src[1].u64[0] ? src[0].u64[0] : src[1].u64[0];
810 dst->u64[1] = src[0].u64[1] < src[1].u64[1] ? src[0].u64[1] : src[1].u64[1];
811 dst->u64[2] = src[0].u64[2] < src[1].u64[2] ? src[0].u64[2] : src[1].u64[2];
812 dst->u64[3] = src[0].u64[3] < src[1].u64[3] ? src[0].u64[3] : src[1].u64[3];
813 }
814
815 static void
816 micro_i64min(union tgsi_double_channel *dst,
817 const union tgsi_double_channel *src)
818 {
819 dst->i64[0] = src[0].i64[0] < src[1].i64[0] ? src[0].i64[0] : src[1].i64[0];
820 dst->i64[1] = src[0].i64[1] < src[1].i64[1] ? src[0].i64[1] : src[1].i64[1];
821 dst->i64[2] = src[0].i64[2] < src[1].i64[2] ? src[0].i64[2] : src[1].i64[2];
822 dst->i64[3] = src[0].i64[3] < src[1].i64[3] ? src[0].i64[3] : src[1].i64[3];
823 }
824
825 static void
826 micro_u64add(union tgsi_double_channel *dst,
827 const union tgsi_double_channel *src)
828 {
829 dst->u64[0] = src[0].u64[0] + src[1].u64[0];
830 dst->u64[1] = src[0].u64[1] + src[1].u64[1];
831 dst->u64[2] = src[0].u64[2] + src[1].u64[2];
832 dst->u64[3] = src[0].u64[3] + src[1].u64[3];
833 }
834
835 static void
836 micro_u64mul(union tgsi_double_channel *dst,
837 const union tgsi_double_channel *src)
838 {
839 dst->u64[0] = src[0].u64[0] * src[1].u64[0];
840 dst->u64[1] = src[0].u64[1] * src[1].u64[1];
841 dst->u64[2] = src[0].u64[2] * src[1].u64[2];
842 dst->u64[3] = src[0].u64[3] * src[1].u64[3];
843 }
844
845 static void
846 micro_u64div(union tgsi_double_channel *dst,
847 const union tgsi_double_channel *src)
848 {
849 dst->u64[0] = src[0].u64[0] / src[1].u64[0];
850 dst->u64[1] = src[0].u64[1] / src[1].u64[1];
851 dst->u64[2] = src[0].u64[2] / src[1].u64[2];
852 dst->u64[3] = src[0].u64[3] / src[1].u64[3];
853 }
854
855 static void
856 micro_i64div(union tgsi_double_channel *dst,
857 const union tgsi_double_channel *src)
858 {
859 dst->i64[0] = src[0].i64[0] / src[1].i64[0];
860 dst->i64[1] = src[0].i64[1] / src[1].i64[1];
861 dst->i64[2] = src[0].i64[2] / src[1].i64[2];
862 dst->i64[3] = src[0].i64[3] / src[1].i64[3];
863 }
864
865 static void
866 micro_u64mod(union tgsi_double_channel *dst,
867 const union tgsi_double_channel *src)
868 {
869 dst->u64[0] = src[0].u64[0] % src[1].u64[0];
870 dst->u64[1] = src[0].u64[1] % src[1].u64[1];
871 dst->u64[2] = src[0].u64[2] % src[1].u64[2];
872 dst->u64[3] = src[0].u64[3] % src[1].u64[3];
873 }
874
875 static void
876 micro_i64mod(union tgsi_double_channel *dst,
877 const union tgsi_double_channel *src)
878 {
879 dst->i64[0] = src[0].i64[0] % src[1].i64[0];
880 dst->i64[1] = src[0].i64[1] % src[1].i64[1];
881 dst->i64[2] = src[0].i64[2] % src[1].i64[2];
882 dst->i64[3] = src[0].i64[3] % src[1].i64[3];
883 }
884
885 static void
886 micro_u64shl(union tgsi_double_channel *dst,
887 const union tgsi_double_channel *src0,
888 union tgsi_exec_channel *src1)
889 {
890 unsigned masked_count;
891 masked_count = src1->u[0] & 0x3f;
892 dst->u64[0] = src0->u64[0] << masked_count;
893 masked_count = src1->u[1] & 0x3f;
894 dst->u64[1] = src0->u64[1] << masked_count;
895 masked_count = src1->u[2] & 0x3f;
896 dst->u64[2] = src0->u64[2] << masked_count;
897 masked_count = src1->u[3] & 0x3f;
898 dst->u64[3] = src0->u64[3] << masked_count;
899 }
900
901 static void
902 micro_i64shr(union tgsi_double_channel *dst,
903 const union tgsi_double_channel *src0,
904 union tgsi_exec_channel *src1)
905 {
906 unsigned masked_count;
907 masked_count = src1->u[0] & 0x3f;
908 dst->i64[0] = src0->i64[0] >> masked_count;
909 masked_count = src1->u[1] & 0x3f;
910 dst->i64[1] = src0->i64[1] >> masked_count;
911 masked_count = src1->u[2] & 0x3f;
912 dst->i64[2] = src0->i64[2] >> masked_count;
913 masked_count = src1->u[3] & 0x3f;
914 dst->i64[3] = src0->i64[3] >> masked_count;
915 }
916
917 static void
918 micro_u64shr(union tgsi_double_channel *dst,
919 const union tgsi_double_channel *src0,
920 union tgsi_exec_channel *src1)
921 {
922 unsigned masked_count;
923 masked_count = src1->u[0] & 0x3f;
924 dst->u64[0] = src0->u64[0] >> masked_count;
925 masked_count = src1->u[1] & 0x3f;
926 dst->u64[1] = src0->u64[1] >> masked_count;
927 masked_count = src1->u[2] & 0x3f;
928 dst->u64[2] = src0->u64[2] >> masked_count;
929 masked_count = src1->u[3] & 0x3f;
930 dst->u64[3] = src0->u64[3] >> masked_count;
931 }
932
933 enum tgsi_exec_datatype {
934 TGSI_EXEC_DATA_FLOAT,
935 TGSI_EXEC_DATA_INT,
936 TGSI_EXEC_DATA_UINT,
937 TGSI_EXEC_DATA_DOUBLE,
938 TGSI_EXEC_DATA_INT64,
939 TGSI_EXEC_DATA_UINT64,
940 };
941
942 /*
943 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
944 */
945 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
946 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
947 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
948 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
949 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
950 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
951
952
953 /** The execution mask depends on the conditional mask and the loop mask */
954 #define UPDATE_EXEC_MASK(MACH) \
955 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
956
957
958 static const union tgsi_exec_channel ZeroVec =
959 { { 0.0, 0.0, 0.0, 0.0 } };
960
961 static const union tgsi_exec_channel OneVec = {
962 {1.0f, 1.0f, 1.0f, 1.0f}
963 };
964
965 static const union tgsi_exec_channel P128Vec = {
966 {128.0f, 128.0f, 128.0f, 128.0f}
967 };
968
969 static const union tgsi_exec_channel M128Vec = {
970 {-128.0f, -128.0f, -128.0f, -128.0f}
971 };
972
973
974 /**
975 * Assert that none of the float values in 'chan' are infinite or NaN.
976 * NaN and Inf may occur normally during program execution and should
977 * not lead to crashes, etc. But when debugging, it's helpful to catch
978 * them.
979 */
980 static inline void
981 check_inf_or_nan(const union tgsi_exec_channel *chan)
982 {
983 assert(!util_is_inf_or_nan((chan)->f[0]));
984 assert(!util_is_inf_or_nan((chan)->f[1]));
985 assert(!util_is_inf_or_nan((chan)->f[2]));
986 assert(!util_is_inf_or_nan((chan)->f[3]));
987 }
988
989
990 #ifdef DEBUG
991 static void
992 print_chan(const char *msg, const union tgsi_exec_channel *chan)
993 {
994 debug_printf("%s = {%f, %f, %f, %f}\n",
995 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
996 }
997 #endif
998
999
1000 #ifdef DEBUG
1001 static void
1002 print_temp(const struct tgsi_exec_machine *mach, uint index)
1003 {
1004 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
1005 int i;
1006 debug_printf("Temp[%u] =\n", index);
1007 for (i = 0; i < 4; i++) {
1008 debug_printf(" %c: { %f, %f, %f, %f }\n",
1009 "XYZW"[i],
1010 tmp->xyzw[i].f[0],
1011 tmp->xyzw[i].f[1],
1012 tmp->xyzw[i].f[2],
1013 tmp->xyzw[i].f[3]);
1014 }
1015 }
1016 #endif
1017
1018
1019 void
1020 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
1021 unsigned num_bufs,
1022 const void **bufs,
1023 const unsigned *buf_sizes)
1024 {
1025 unsigned i;
1026
1027 for (i = 0; i < num_bufs; i++) {
1028 mach->Consts[i] = bufs[i];
1029 mach->ConstsSize[i] = buf_sizes[i];
1030 }
1031 }
1032
1033
1034 /**
1035 * Check if there's a potential src/dst register data dependency when
1036 * using SOA execution.
1037 * Example:
1038 * MOV T, T.yxwz;
1039 * This would expand into:
1040 * MOV t0, t1;
1041 * MOV t1, t0;
1042 * MOV t2, t3;
1043 * MOV t3, t2;
1044 * The second instruction will have the wrong value for t0 if executed as-is.
1045 */
1046 boolean
1047 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
1048 {
1049 uint i, chan;
1050
1051 uint writemask = inst->Dst[0].Register.WriteMask;
1052 if (writemask == TGSI_WRITEMASK_X ||
1053 writemask == TGSI_WRITEMASK_Y ||
1054 writemask == TGSI_WRITEMASK_Z ||
1055 writemask == TGSI_WRITEMASK_W ||
1056 writemask == TGSI_WRITEMASK_NONE) {
1057 /* no chance of data dependency */
1058 return FALSE;
1059 }
1060
1061 /* loop over src regs */
1062 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1063 if ((inst->Src[i].Register.File ==
1064 inst->Dst[0].Register.File) &&
1065 ((inst->Src[i].Register.Index ==
1066 inst->Dst[0].Register.Index) ||
1067 inst->Src[i].Register.Indirect ||
1068 inst->Dst[0].Register.Indirect)) {
1069 /* loop over dest channels */
1070 uint channelsWritten = 0x0;
1071 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1072 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1073 /* check if we're reading a channel that's been written */
1074 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
1075 if (channelsWritten & (1 << swizzle)) {
1076 return TRUE;
1077 }
1078
1079 channelsWritten |= (1 << chan);
1080 }
1081 }
1082 }
1083 }
1084 return FALSE;
1085 }
1086
1087
1088 /**
1089 * Initialize machine state by expanding tokens to full instructions,
1090 * allocating temporary storage, setting up constants, etc.
1091 * After this, we can call tgsi_exec_machine_run() many times.
1092 */
1093 void
1094 tgsi_exec_machine_bind_shader(
1095 struct tgsi_exec_machine *mach,
1096 const struct tgsi_token *tokens,
1097 struct tgsi_sampler *sampler,
1098 struct tgsi_image *image,
1099 struct tgsi_buffer *buffer)
1100 {
1101 uint k;
1102 struct tgsi_parse_context parse;
1103 struct tgsi_full_instruction *instructions;
1104 struct tgsi_full_declaration *declarations;
1105 uint maxInstructions = 10, numInstructions = 0;
1106 uint maxDeclarations = 10, numDeclarations = 0;
1107
1108 #if 0
1109 tgsi_dump(tokens, 0);
1110 #endif
1111
1112 util_init_math();
1113
1114
1115 mach->Tokens = tokens;
1116 mach->Sampler = sampler;
1117 mach->Image = image;
1118 mach->Buffer = buffer;
1119
1120 if (!tokens) {
1121 /* unbind and free all */
1122 FREE(mach->Declarations);
1123 mach->Declarations = NULL;
1124 mach->NumDeclarations = 0;
1125
1126 FREE(mach->Instructions);
1127 mach->Instructions = NULL;
1128 mach->NumInstructions = 0;
1129
1130 return;
1131 }
1132
1133 k = tgsi_parse_init (&parse, mach->Tokens);
1134 if (k != TGSI_PARSE_OK) {
1135 debug_printf( "Problem parsing!\n" );
1136 return;
1137 }
1138
1139 mach->ImmLimit = 0;
1140 mach->NumOutputs = 0;
1141
1142 for (k = 0; k < TGSI_SEMANTIC_COUNT; k++)
1143 mach->SysSemanticToIndex[k] = -1;
1144
1145 if (mach->ShaderType == PIPE_SHADER_GEOMETRY &&
1146 !mach->UsedGeometryShader) {
1147 struct tgsi_exec_vector *inputs;
1148 struct tgsi_exec_vector *outputs;
1149
1150 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
1151 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
1152 16);
1153
1154 if (!inputs)
1155 return;
1156
1157 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
1158 TGSI_MAX_TOTAL_VERTICES, 16);
1159
1160 if (!outputs) {
1161 align_free(inputs);
1162 return;
1163 }
1164
1165 align_free(mach->Inputs);
1166 align_free(mach->Outputs);
1167
1168 mach->Inputs = inputs;
1169 mach->Outputs = outputs;
1170 mach->UsedGeometryShader = TRUE;
1171 }
1172
1173 declarations = (struct tgsi_full_declaration *)
1174 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
1175
1176 if (!declarations) {
1177 return;
1178 }
1179
1180 instructions = (struct tgsi_full_instruction *)
1181 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
1182
1183 if (!instructions) {
1184 FREE( declarations );
1185 return;
1186 }
1187
1188 while( !tgsi_parse_end_of_tokens( &parse ) ) {
1189 uint i;
1190
1191 tgsi_parse_token( &parse );
1192 switch( parse.FullToken.Token.Type ) {
1193 case TGSI_TOKEN_TYPE_DECLARATION:
1194 /* save expanded declaration */
1195 if (numDeclarations == maxDeclarations) {
1196 declarations = REALLOC(declarations,
1197 maxDeclarations
1198 * sizeof(struct tgsi_full_declaration),
1199 (maxDeclarations + 10)
1200 * sizeof(struct tgsi_full_declaration));
1201 maxDeclarations += 10;
1202 }
1203 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
1204 unsigned reg;
1205 for (reg = parse.FullToken.FullDeclaration.Range.First;
1206 reg <= parse.FullToken.FullDeclaration.Range.Last;
1207 ++reg) {
1208 ++mach->NumOutputs;
1209 }
1210 }
1211 else if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1212 const struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
1213 mach->SysSemanticToIndex[decl->Semantic.Name] = decl->Range.First;
1214 }
1215
1216 memcpy(declarations + numDeclarations,
1217 &parse.FullToken.FullDeclaration,
1218 sizeof(declarations[0]));
1219 numDeclarations++;
1220 break;
1221
1222 case TGSI_TOKEN_TYPE_IMMEDIATE:
1223 {
1224 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
1225 assert( size <= 4 );
1226 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
1227
1228 for( i = 0; i < size; i++ ) {
1229 mach->Imms[mach->ImmLimit][i] =
1230 parse.FullToken.FullImmediate.u[i].Float;
1231 }
1232 mach->ImmLimit += 1;
1233 }
1234 break;
1235
1236 case TGSI_TOKEN_TYPE_INSTRUCTION:
1237
1238 /* save expanded instruction */
1239 if (numInstructions == maxInstructions) {
1240 instructions = REALLOC(instructions,
1241 maxInstructions
1242 * sizeof(struct tgsi_full_instruction),
1243 (maxInstructions + 10)
1244 * sizeof(struct tgsi_full_instruction));
1245 maxInstructions += 10;
1246 }
1247
1248 memcpy(instructions + numInstructions,
1249 &parse.FullToken.FullInstruction,
1250 sizeof(instructions[0]));
1251
1252 numInstructions++;
1253 break;
1254
1255 case TGSI_TOKEN_TYPE_PROPERTY:
1256 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
1257 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1258 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1259 }
1260 }
1261 break;
1262
1263 default:
1264 assert( 0 );
1265 }
1266 }
1267 tgsi_parse_free (&parse);
1268
1269 FREE(mach->Declarations);
1270 mach->Declarations = declarations;
1271 mach->NumDeclarations = numDeclarations;
1272
1273 FREE(mach->Instructions);
1274 mach->Instructions = instructions;
1275 mach->NumInstructions = numInstructions;
1276 }
1277
1278
1279 struct tgsi_exec_machine *
1280 tgsi_exec_machine_create(enum pipe_shader_type shader_type)
1281 {
1282 struct tgsi_exec_machine *mach;
1283 uint i;
1284
1285 mach = align_malloc( sizeof *mach, 16 );
1286 if (!mach)
1287 goto fail;
1288
1289 memset(mach, 0, sizeof(*mach));
1290
1291 mach->ShaderType = shader_type;
1292 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1293 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1294 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1295
1296 if (shader_type != PIPE_SHADER_COMPUTE) {
1297 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1298 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1299 if (!mach->Inputs || !mach->Outputs)
1300 goto fail;
1301 }
1302
1303 /* Setup constants needed by the SSE2 executor. */
1304 for( i = 0; i < 4; i++ ) {
1305 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1306 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1307 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1308 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1309 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1310 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1311 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1312 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1313 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1314 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1315 }
1316
1317 #ifdef DEBUG
1318 /* silence warnings */
1319 (void) print_chan;
1320 (void) print_temp;
1321 #endif
1322
1323 return mach;
1324
1325 fail:
1326 if (mach) {
1327 align_free(mach->Inputs);
1328 align_free(mach->Outputs);
1329 align_free(mach);
1330 }
1331 return NULL;
1332 }
1333
1334
1335 void
1336 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1337 {
1338 if (mach) {
1339 FREE(mach->Instructions);
1340 FREE(mach->Declarations);
1341
1342 align_free(mach->Inputs);
1343 align_free(mach->Outputs);
1344
1345 align_free(mach);
1346 }
1347 }
1348
1349 static void
1350 micro_add(union tgsi_exec_channel *dst,
1351 const union tgsi_exec_channel *src0,
1352 const union tgsi_exec_channel *src1)
1353 {
1354 dst->f[0] = src0->f[0] + src1->f[0];
1355 dst->f[1] = src0->f[1] + src1->f[1];
1356 dst->f[2] = src0->f[2] + src1->f[2];
1357 dst->f[3] = src0->f[3] + src1->f[3];
1358 }
1359
1360 static void
1361 micro_div(
1362 union tgsi_exec_channel *dst,
1363 const union tgsi_exec_channel *src0,
1364 const union tgsi_exec_channel *src1 )
1365 {
1366 if (src1->f[0] != 0) {
1367 dst->f[0] = src0->f[0] / src1->f[0];
1368 }
1369 if (src1->f[1] != 0) {
1370 dst->f[1] = src0->f[1] / src1->f[1];
1371 }
1372 if (src1->f[2] != 0) {
1373 dst->f[2] = src0->f[2] / src1->f[2];
1374 }
1375 if (src1->f[3] != 0) {
1376 dst->f[3] = src0->f[3] / src1->f[3];
1377 }
1378 }
1379
1380 static void
1381 micro_lt(
1382 union tgsi_exec_channel *dst,
1383 const union tgsi_exec_channel *src0,
1384 const union tgsi_exec_channel *src1,
1385 const union tgsi_exec_channel *src2,
1386 const union tgsi_exec_channel *src3 )
1387 {
1388 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1389 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1390 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1391 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1392 }
1393
1394 static void
1395 micro_max(union tgsi_exec_channel *dst,
1396 const union tgsi_exec_channel *src0,
1397 const union tgsi_exec_channel *src1)
1398 {
1399 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1400 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1401 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1402 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1403 }
1404
1405 static void
1406 micro_min(union tgsi_exec_channel *dst,
1407 const union tgsi_exec_channel *src0,
1408 const union tgsi_exec_channel *src1)
1409 {
1410 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1411 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1412 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1413 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1414 }
1415
1416 static void
1417 micro_mul(union tgsi_exec_channel *dst,
1418 const union tgsi_exec_channel *src0,
1419 const union tgsi_exec_channel *src1)
1420 {
1421 dst->f[0] = src0->f[0] * src1->f[0];
1422 dst->f[1] = src0->f[1] * src1->f[1];
1423 dst->f[2] = src0->f[2] * src1->f[2];
1424 dst->f[3] = src0->f[3] * src1->f[3];
1425 }
1426
1427 static void
1428 micro_neg(
1429 union tgsi_exec_channel *dst,
1430 const union tgsi_exec_channel *src )
1431 {
1432 dst->f[0] = -src->f[0];
1433 dst->f[1] = -src->f[1];
1434 dst->f[2] = -src->f[2];
1435 dst->f[3] = -src->f[3];
1436 }
1437
1438 static void
1439 micro_pow(
1440 union tgsi_exec_channel *dst,
1441 const union tgsi_exec_channel *src0,
1442 const union tgsi_exec_channel *src1 )
1443 {
1444 #if FAST_MATH
1445 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1446 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1447 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1448 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1449 #else
1450 dst->f[0] = powf( src0->f[0], src1->f[0] );
1451 dst->f[1] = powf( src0->f[1], src1->f[1] );
1452 dst->f[2] = powf( src0->f[2], src1->f[2] );
1453 dst->f[3] = powf( src0->f[3], src1->f[3] );
1454 #endif
1455 }
1456
1457 static void
1458 micro_sub(union tgsi_exec_channel *dst,
1459 const union tgsi_exec_channel *src0,
1460 const union tgsi_exec_channel *src1)
1461 {
1462 dst->f[0] = src0->f[0] - src1->f[0];
1463 dst->f[1] = src0->f[1] - src1->f[1];
1464 dst->f[2] = src0->f[2] - src1->f[2];
1465 dst->f[3] = src0->f[3] - src1->f[3];
1466 }
1467
1468 static void
1469 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1470 const uint chan_index,
1471 const uint file,
1472 const uint swizzle,
1473 const union tgsi_exec_channel *index,
1474 const union tgsi_exec_channel *index2D,
1475 union tgsi_exec_channel *chan)
1476 {
1477 uint i;
1478
1479 assert(swizzle < 4);
1480
1481 switch (file) {
1482 case TGSI_FILE_CONSTANT:
1483 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1484 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1485 assert(mach->Consts[index2D->i[i]]);
1486
1487 if (index->i[i] < 0) {
1488 chan->u[i] = 0;
1489 } else {
1490 /* NOTE: copying the const value as a uint instead of float */
1491 const uint constbuf = index2D->i[i];
1492 const uint *buf = (const uint *)mach->Consts[constbuf];
1493 const int pos = index->i[i] * 4 + swizzle;
1494 /* const buffer bounds check */
1495 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1496 if (0) {
1497 /* Debug: print warning */
1498 static int count = 0;
1499 if (count++ < 100)
1500 debug_printf("TGSI Exec: const buffer index %d"
1501 " out of bounds\n", pos);
1502 }
1503 chan->u[i] = 0;
1504 }
1505 else
1506 chan->u[i] = buf[pos];
1507 }
1508 }
1509 break;
1510
1511 case TGSI_FILE_INPUT:
1512 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1513 /*
1514 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1515 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1516 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1517 index2D->i[i], index->i[i]);
1518 }*/
1519 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1520 assert(pos >= 0);
1521 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1522 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1523 }
1524 break;
1525
1526 case TGSI_FILE_SYSTEM_VALUE:
1527 /* XXX no swizzling at this point. Will be needed if we put
1528 * gl_FragCoord, for example, in a sys value register.
1529 */
1530 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1531 chan->u[i] = mach->SystemValue[index->i[i]].xyzw[swizzle].u[i];
1532 }
1533 break;
1534
1535 case TGSI_FILE_TEMPORARY:
1536 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1537 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1538 assert(index2D->i[i] == 0);
1539
1540 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1541 }
1542 break;
1543
1544 case TGSI_FILE_IMMEDIATE:
1545 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1546 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1547 assert(index2D->i[i] == 0);
1548
1549 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1550 }
1551 break;
1552
1553 case TGSI_FILE_ADDRESS:
1554 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1555 assert(index->i[i] >= 0);
1556 assert(index2D->i[i] == 0);
1557
1558 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1559 }
1560 break;
1561
1562 case TGSI_FILE_PREDICATE:
1563 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1564 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1565 assert(index2D->i[i] == 0);
1566
1567 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1568 }
1569 break;
1570
1571 case TGSI_FILE_OUTPUT:
1572 /* vertex/fragment output vars can be read too */
1573 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1574 assert(index->i[i] >= 0);
1575 assert(index2D->i[i] == 0);
1576
1577 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1578 }
1579 break;
1580
1581 default:
1582 assert(0);
1583 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1584 chan->u[i] = 0;
1585 }
1586 }
1587 }
1588
1589 static void
1590 fetch_source_d(const struct tgsi_exec_machine *mach,
1591 union tgsi_exec_channel *chan,
1592 const struct tgsi_full_src_register *reg,
1593 const uint chan_index,
1594 enum tgsi_exec_datatype src_datatype)
1595 {
1596 union tgsi_exec_channel index;
1597 union tgsi_exec_channel index2D;
1598 uint swizzle;
1599
1600 /* We start with a direct index into a register file.
1601 *
1602 * file[1],
1603 * where:
1604 * file = Register.File
1605 * [1] = Register.Index
1606 */
1607 index.i[0] =
1608 index.i[1] =
1609 index.i[2] =
1610 index.i[3] = reg->Register.Index;
1611
1612 /* There is an extra source register that indirectly subscripts
1613 * a register file. The direct index now becomes an offset
1614 * that is being added to the indirect register.
1615 *
1616 * file[ind[2].x+1],
1617 * where:
1618 * ind = Indirect.File
1619 * [2] = Indirect.Index
1620 * .x = Indirect.SwizzleX
1621 */
1622 if (reg->Register.Indirect) {
1623 union tgsi_exec_channel index2;
1624 union tgsi_exec_channel indir_index;
1625 const uint execmask = mach->ExecMask;
1626 uint i;
1627
1628 /* which address register (always zero now) */
1629 index2.i[0] =
1630 index2.i[1] =
1631 index2.i[2] =
1632 index2.i[3] = reg->Indirect.Index;
1633 /* get current value of address register[swizzle] */
1634 swizzle = reg->Indirect.Swizzle;
1635 fetch_src_file_channel(mach,
1636 chan_index,
1637 reg->Indirect.File,
1638 swizzle,
1639 &index2,
1640 &ZeroVec,
1641 &indir_index);
1642
1643 /* add value of address register to the offset */
1644 index.i[0] += indir_index.i[0];
1645 index.i[1] += indir_index.i[1];
1646 index.i[2] += indir_index.i[2];
1647 index.i[3] += indir_index.i[3];
1648
1649 /* for disabled execution channels, zero-out the index to
1650 * avoid using a potential garbage value.
1651 */
1652 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1653 if ((execmask & (1 << i)) == 0)
1654 index.i[i] = 0;
1655 }
1656 }
1657
1658 /* There is an extra source register that is a second
1659 * subscript to a register file. Effectively it means that
1660 * the register file is actually a 2D array of registers.
1661 *
1662 * file[3][1],
1663 * where:
1664 * [3] = Dimension.Index
1665 */
1666 if (reg->Register.Dimension) {
1667 index2D.i[0] =
1668 index2D.i[1] =
1669 index2D.i[2] =
1670 index2D.i[3] = reg->Dimension.Index;
1671
1672 /* Again, the second subscript index can be addressed indirectly
1673 * identically to the first one.
1674 * Nothing stops us from indirectly addressing the indirect register,
1675 * but there is no need for that, so we won't exercise it.
1676 *
1677 * file[ind[4].y+3][1],
1678 * where:
1679 * ind = DimIndirect.File
1680 * [4] = DimIndirect.Index
1681 * .y = DimIndirect.SwizzleX
1682 */
1683 if (reg->Dimension.Indirect) {
1684 union tgsi_exec_channel index2;
1685 union tgsi_exec_channel indir_index;
1686 const uint execmask = mach->ExecMask;
1687 uint i;
1688
1689 index2.i[0] =
1690 index2.i[1] =
1691 index2.i[2] =
1692 index2.i[3] = reg->DimIndirect.Index;
1693
1694 swizzle = reg->DimIndirect.Swizzle;
1695 fetch_src_file_channel(mach,
1696 chan_index,
1697 reg->DimIndirect.File,
1698 swizzle,
1699 &index2,
1700 &ZeroVec,
1701 &indir_index);
1702
1703 index2D.i[0] += indir_index.i[0];
1704 index2D.i[1] += indir_index.i[1];
1705 index2D.i[2] += indir_index.i[2];
1706 index2D.i[3] += indir_index.i[3];
1707
1708 /* for disabled execution channels, zero-out the index to
1709 * avoid using a potential garbage value.
1710 */
1711 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1712 if ((execmask & (1 << i)) == 0) {
1713 index2D.i[i] = 0;
1714 }
1715 }
1716 }
1717
1718 /* If by any chance there was a need for a 3D array of register
1719 * files, we would have to check whether Dimension is followed
1720 * by a dimension register and continue the saga.
1721 */
1722 } else {
1723 index2D.i[0] =
1724 index2D.i[1] =
1725 index2D.i[2] =
1726 index2D.i[3] = 0;
1727 }
1728
1729 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1730 fetch_src_file_channel(mach,
1731 chan_index,
1732 reg->Register.File,
1733 swizzle,
1734 &index,
1735 &index2D,
1736 chan);
1737 }
1738
1739 static void
1740 fetch_source(const struct tgsi_exec_machine *mach,
1741 union tgsi_exec_channel *chan,
1742 const struct tgsi_full_src_register *reg,
1743 const uint chan_index,
1744 enum tgsi_exec_datatype src_datatype)
1745 {
1746 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1747
1748 if (reg->Register.Absolute) {
1749 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1750 micro_abs(chan, chan);
1751 } else {
1752 micro_iabs(chan, chan);
1753 }
1754 }
1755
1756 if (reg->Register.Negate) {
1757 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1758 micro_neg(chan, chan);
1759 } else {
1760 micro_ineg(chan, chan);
1761 }
1762 }
1763 }
1764
1765 static union tgsi_exec_channel *
1766 store_dest_dstret(struct tgsi_exec_machine *mach,
1767 const union tgsi_exec_channel *chan,
1768 const struct tgsi_full_dst_register *reg,
1769 const struct tgsi_full_instruction *inst,
1770 uint chan_index,
1771 enum tgsi_exec_datatype dst_datatype)
1772 {
1773 uint i;
1774 static union tgsi_exec_channel null;
1775 union tgsi_exec_channel *dst;
1776 union tgsi_exec_channel index2D;
1777 uint execmask = mach->ExecMask;
1778 int offset = 0; /* indirection offset */
1779 int index;
1780
1781 /* for debugging */
1782 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1783 check_inf_or_nan(chan);
1784 }
1785
1786 /* There is an extra source register that indirectly subscripts
1787 * a register file. The direct index now becomes an offset
1788 * that is being added to the indirect register.
1789 *
1790 * file[ind[2].x+1],
1791 * where:
1792 * ind = Indirect.File
1793 * [2] = Indirect.Index
1794 * .x = Indirect.SwizzleX
1795 */
1796 if (reg->Register.Indirect) {
1797 union tgsi_exec_channel index;
1798 union tgsi_exec_channel indir_index;
1799 uint swizzle;
1800
1801 /* which address register (always zero for now) */
1802 index.i[0] =
1803 index.i[1] =
1804 index.i[2] =
1805 index.i[3] = reg->Indirect.Index;
1806
1807 /* get current value of address register[swizzle] */
1808 swizzle = reg->Indirect.Swizzle;
1809
1810 /* fetch values from the address/indirection register */
1811 fetch_src_file_channel(mach,
1812 chan_index,
1813 reg->Indirect.File,
1814 swizzle,
1815 &index,
1816 &ZeroVec,
1817 &indir_index);
1818
1819 /* save indirection offset */
1820 offset = indir_index.i[0];
1821 }
1822
1823 /* There is an extra source register that is a second
1824 * subscript to a register file. Effectively it means that
1825 * the register file is actually a 2D array of registers.
1826 *
1827 * file[3][1],
1828 * where:
1829 * [3] = Dimension.Index
1830 */
1831 if (reg->Register.Dimension) {
1832 index2D.i[0] =
1833 index2D.i[1] =
1834 index2D.i[2] =
1835 index2D.i[3] = reg->Dimension.Index;
1836
1837 /* Again, the second subscript index can be addressed indirectly
1838 * identically to the first one.
1839 * Nothing stops us from indirectly addressing the indirect register,
1840 * but there is no need for that, so we won't exercise it.
1841 *
1842 * file[ind[4].y+3][1],
1843 * where:
1844 * ind = DimIndirect.File
1845 * [4] = DimIndirect.Index
1846 * .y = DimIndirect.SwizzleX
1847 */
1848 if (reg->Dimension.Indirect) {
1849 union tgsi_exec_channel index2;
1850 union tgsi_exec_channel indir_index;
1851 const uint execmask = mach->ExecMask;
1852 unsigned swizzle;
1853 uint i;
1854
1855 index2.i[0] =
1856 index2.i[1] =
1857 index2.i[2] =
1858 index2.i[3] = reg->DimIndirect.Index;
1859
1860 swizzle = reg->DimIndirect.Swizzle;
1861 fetch_src_file_channel(mach,
1862 chan_index,
1863 reg->DimIndirect.File,
1864 swizzle,
1865 &index2,
1866 &ZeroVec,
1867 &indir_index);
1868
1869 index2D.i[0] += indir_index.i[0];
1870 index2D.i[1] += indir_index.i[1];
1871 index2D.i[2] += indir_index.i[2];
1872 index2D.i[3] += indir_index.i[3];
1873
1874 /* for disabled execution channels, zero-out the index to
1875 * avoid using a potential garbage value.
1876 */
1877 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1878 if ((execmask & (1 << i)) == 0) {
1879 index2D.i[i] = 0;
1880 }
1881 }
1882 }
1883
1884 /* If by any chance there was a need for a 3D array of register
1885 * files, we would have to check whether Dimension is followed
1886 * by a dimension register and continue the saga.
1887 */
1888 } else {
1889 index2D.i[0] =
1890 index2D.i[1] =
1891 index2D.i[2] =
1892 index2D.i[3] = 0;
1893 }
1894
1895 switch (reg->Register.File) {
1896 case TGSI_FILE_NULL:
1897 dst = &null;
1898 break;
1899
1900 case TGSI_FILE_OUTPUT:
1901 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1902 + reg->Register.Index;
1903 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1904 #if 0
1905 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1906 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1907 reg->Register.Index);
1908 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1909 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1910 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1911 if (execmask & (1 << i))
1912 debug_printf("%f, ", chan->f[i]);
1913 debug_printf(")\n");
1914 }
1915 #endif
1916 break;
1917
1918 case TGSI_FILE_TEMPORARY:
1919 index = reg->Register.Index;
1920 assert( index < TGSI_EXEC_NUM_TEMPS );
1921 dst = &mach->Temps[offset + index].xyzw[chan_index];
1922 break;
1923
1924 case TGSI_FILE_ADDRESS:
1925 index = reg->Register.Index;
1926 dst = &mach->Addrs[index].xyzw[chan_index];
1927 break;
1928
1929 case TGSI_FILE_PREDICATE:
1930 index = reg->Register.Index;
1931 assert(index < TGSI_EXEC_NUM_PREDS);
1932 dst = &mach->Predicates[index].xyzw[chan_index];
1933 break;
1934
1935 default:
1936 assert( 0 );
1937 return NULL;
1938 }
1939
1940 if (inst->Instruction.Predicate) {
1941 uint swizzle;
1942 union tgsi_exec_channel *pred;
1943
1944 switch (chan_index) {
1945 case TGSI_CHAN_X:
1946 swizzle = inst->Predicate.SwizzleX;
1947 break;
1948 case TGSI_CHAN_Y:
1949 swizzle = inst->Predicate.SwizzleY;
1950 break;
1951 case TGSI_CHAN_Z:
1952 swizzle = inst->Predicate.SwizzleZ;
1953 break;
1954 case TGSI_CHAN_W:
1955 swizzle = inst->Predicate.SwizzleW;
1956 break;
1957 default:
1958 assert(0);
1959 return NULL;
1960 }
1961
1962 assert(inst->Predicate.Index == 0);
1963
1964 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1965
1966 if (inst->Predicate.Negate) {
1967 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1968 if (pred->u[i]) {
1969 execmask &= ~(1 << i);
1970 }
1971 }
1972 } else {
1973 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1974 if (!pred->u[i]) {
1975 execmask &= ~(1 << i);
1976 }
1977 }
1978 }
1979 }
1980
1981 return dst;
1982 }
1983
1984 static void
1985 store_dest_double(struct tgsi_exec_machine *mach,
1986 const union tgsi_exec_channel *chan,
1987 const struct tgsi_full_dst_register *reg,
1988 const struct tgsi_full_instruction *inst,
1989 uint chan_index,
1990 enum tgsi_exec_datatype dst_datatype)
1991 {
1992 union tgsi_exec_channel *dst;
1993 const uint execmask = mach->ExecMask;
1994 int i;
1995
1996 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1997 dst_datatype);
1998 if (!dst)
1999 return;
2000
2001 /* doubles path */
2002 for (i = 0; i < TGSI_QUAD_SIZE; i++)
2003 if (execmask & (1 << i))
2004 dst->i[i] = chan->i[i];
2005 }
2006
2007 static void
2008 store_dest(struct tgsi_exec_machine *mach,
2009 const union tgsi_exec_channel *chan,
2010 const struct tgsi_full_dst_register *reg,
2011 const struct tgsi_full_instruction *inst,
2012 uint chan_index,
2013 enum tgsi_exec_datatype dst_datatype)
2014 {
2015 union tgsi_exec_channel *dst;
2016 const uint execmask = mach->ExecMask;
2017 int i;
2018
2019 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
2020 dst_datatype);
2021 if (!dst)
2022 return;
2023
2024 if (!inst->Instruction.Saturate) {
2025 for (i = 0; i < TGSI_QUAD_SIZE; i++)
2026 if (execmask & (1 << i))
2027 dst->i[i] = chan->i[i];
2028 }
2029 else {
2030 for (i = 0; i < TGSI_QUAD_SIZE; i++)
2031 if (execmask & (1 << i)) {
2032 if (chan->f[i] < 0.0f)
2033 dst->f[i] = 0.0f;
2034 else if (chan->f[i] > 1.0f)
2035 dst->f[i] = 1.0f;
2036 else
2037 dst->i[i] = chan->i[i];
2038 }
2039 }
2040 }
2041
2042 #define FETCH(VAL,INDEX,CHAN)\
2043 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
2044
2045 #define IFETCH(VAL,INDEX,CHAN)\
2046 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
2047
2048
2049 /**
2050 * Execute ARB-style KIL which is predicated by a src register.
2051 * Kill fragment if any of the four values is less than zero.
2052 */
2053 static void
2054 exec_kill_if(struct tgsi_exec_machine *mach,
2055 const struct tgsi_full_instruction *inst)
2056 {
2057 uint uniquemask;
2058 uint chan_index;
2059 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2060 union tgsi_exec_channel r[1];
2061
2062 /* This mask stores component bits that were already tested. */
2063 uniquemask = 0;
2064
2065 for (chan_index = 0; chan_index < 4; chan_index++)
2066 {
2067 uint swizzle;
2068 uint i;
2069
2070 /* unswizzle channel */
2071 swizzle = tgsi_util_get_full_src_register_swizzle (
2072 &inst->Src[0],
2073 chan_index);
2074
2075 /* check if the component has not been already tested */
2076 if (uniquemask & (1 << swizzle))
2077 continue;
2078 uniquemask |= 1 << swizzle;
2079
2080 FETCH(&r[0], 0, chan_index);
2081 for (i = 0; i < 4; i++)
2082 if (r[0].f[i] < 0.0f)
2083 kilmask |= 1 << i;
2084 }
2085
2086 /* restrict to fragments currently executing */
2087 kilmask &= mach->ExecMask;
2088
2089 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
2090 }
2091
2092 /**
2093 * Unconditional fragment kill/discard.
2094 */
2095 static void
2096 exec_kill(struct tgsi_exec_machine *mach,
2097 const struct tgsi_full_instruction *inst)
2098 {
2099 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2100
2101 /* kill fragment for all fragments currently executing */
2102 kilmask = mach->ExecMask;
2103 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
2104 }
2105
2106 static void
2107 emit_vertex(struct tgsi_exec_machine *mach)
2108 {
2109 /* FIXME: check for exec mask correctly
2110 unsigned i;
2111 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2112 if ((mach->ExecMask & (1 << i)))
2113 */
2114 if (mach->ExecMask) {
2115 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
2116 return;
2117
2118 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
2119 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
2120 }
2121 }
2122
2123 static void
2124 emit_primitive(struct tgsi_exec_machine *mach)
2125 {
2126 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
2127 /* FIXME: check for exec mask correctly
2128 unsigned i;
2129 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2130 if ((mach->ExecMask & (1 << i)))
2131 */
2132 if (mach->ExecMask) {
2133 ++(*prim_count);
2134 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
2135 mach->Primitives[*prim_count] = 0;
2136 }
2137 }
2138
2139 static void
2140 conditional_emit_primitive(struct tgsi_exec_machine *mach)
2141 {
2142 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
2143 int emitted_verts =
2144 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
2145 if (emitted_verts) {
2146 emit_primitive(mach);
2147 }
2148 }
2149 }
2150
2151
2152 /*
2153 * Fetch four texture samples using STR texture coordinates.
2154 */
2155 static void
2156 fetch_texel( struct tgsi_sampler *sampler,
2157 const unsigned sview_idx,
2158 const unsigned sampler_idx,
2159 const union tgsi_exec_channel *s,
2160 const union tgsi_exec_channel *t,
2161 const union tgsi_exec_channel *p,
2162 const union tgsi_exec_channel *c0,
2163 const union tgsi_exec_channel *c1,
2164 float derivs[3][2][TGSI_QUAD_SIZE],
2165 const int8_t offset[3],
2166 enum tgsi_sampler_control control,
2167 union tgsi_exec_channel *r,
2168 union tgsi_exec_channel *g,
2169 union tgsi_exec_channel *b,
2170 union tgsi_exec_channel *a )
2171 {
2172 uint j;
2173 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2174
2175 /* FIXME: handle explicit derivs, offsets */
2176 sampler->get_samples(sampler, sview_idx, sampler_idx,
2177 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
2178
2179 for (j = 0; j < 4; j++) {
2180 r->f[j] = rgba[0][j];
2181 g->f[j] = rgba[1][j];
2182 b->f[j] = rgba[2][j];
2183 a->f[j] = rgba[3][j];
2184 }
2185 }
2186
2187
2188 #define TEX_MODIFIER_NONE 0
2189 #define TEX_MODIFIER_PROJECTED 1
2190 #define TEX_MODIFIER_LOD_BIAS 2
2191 #define TEX_MODIFIER_EXPLICIT_LOD 3
2192 #define TEX_MODIFIER_LEVEL_ZERO 4
2193 #define TEX_MODIFIER_GATHER 5
2194
2195 /*
2196 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2197 */
2198 static void
2199 fetch_texel_offsets(struct tgsi_exec_machine *mach,
2200 const struct tgsi_full_instruction *inst,
2201 int8_t offsets[3])
2202 {
2203 if (inst->Texture.NumOffsets == 1) {
2204 union tgsi_exec_channel index;
2205 union tgsi_exec_channel offset[3];
2206 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
2207 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2208 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
2209 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2210 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
2211 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2212 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
2213 offsets[0] = offset[0].i[0];
2214 offsets[1] = offset[1].i[0];
2215 offsets[2] = offset[2].i[0];
2216 } else {
2217 assert(inst->Texture.NumOffsets == 0);
2218 offsets[0] = offsets[1] = offsets[2] = 0;
2219 }
2220 }
2221
2222
2223 /*
2224 * Fetch dx and dy values for one channel (s, t or r).
2225 * Put dx values into one float array, dy values into another.
2226 */
2227 static void
2228 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
2229 const struct tgsi_full_instruction *inst,
2230 unsigned regdsrcx,
2231 unsigned chan,
2232 float derivs[2][TGSI_QUAD_SIZE])
2233 {
2234 union tgsi_exec_channel d;
2235 FETCH(&d, regdsrcx, chan);
2236 derivs[0][0] = d.f[0];
2237 derivs[0][1] = d.f[1];
2238 derivs[0][2] = d.f[2];
2239 derivs[0][3] = d.f[3];
2240 FETCH(&d, regdsrcx + 1, chan);
2241 derivs[1][0] = d.f[0];
2242 derivs[1][1] = d.f[1];
2243 derivs[1][2] = d.f[2];
2244 derivs[1][3] = d.f[3];
2245 }
2246
2247 static uint
2248 fetch_sampler_unit(struct tgsi_exec_machine *mach,
2249 const struct tgsi_full_instruction *inst,
2250 uint sampler)
2251 {
2252 uint unit = 0;
2253 int i;
2254 if (inst->Src[sampler].Register.Indirect) {
2255 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2256 union tgsi_exec_channel indir_index, index2;
2257 const uint execmask = mach->ExecMask;
2258 index2.i[0] =
2259 index2.i[1] =
2260 index2.i[2] =
2261 index2.i[3] = reg->Indirect.Index;
2262
2263 fetch_src_file_channel(mach,
2264 0,
2265 reg->Indirect.File,
2266 reg->Indirect.Swizzle,
2267 &index2,
2268 &ZeroVec,
2269 &indir_index);
2270 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2271 if (execmask & (1 << i)) {
2272 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2273 break;
2274 }
2275 }
2276
2277 } else {
2278 unit = inst->Src[sampler].Register.Index;
2279 }
2280 return unit;
2281 }
2282
2283 /*
2284 * execute a texture instruction.
2285 *
2286 * modifier is used to control the channel routing for the
2287 * instruction variants like proj, lod, and texture with lod bias.
2288 * sampler indicates which src register the sampler is contained in.
2289 */
2290 static void
2291 exec_tex(struct tgsi_exec_machine *mach,
2292 const struct tgsi_full_instruction *inst,
2293 uint modifier, uint sampler)
2294 {
2295 const union tgsi_exec_channel *args[5], *proj = NULL;
2296 union tgsi_exec_channel r[5];
2297 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2298 uint chan;
2299 uint unit;
2300 int8_t offsets[3];
2301 int dim, shadow_ref, i;
2302
2303 unit = fetch_sampler_unit(mach, inst, sampler);
2304 /* always fetch all 3 offsets, overkill but keeps code simple */
2305 fetch_texel_offsets(mach, inst, offsets);
2306
2307 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2308 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2309
2310 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2311 shadow_ref = tgsi_util_get_shadow_ref_src_index(inst->Texture.Texture);
2312
2313 assert(dim <= 4);
2314 if (shadow_ref >= 0)
2315 assert(shadow_ref >= dim && shadow_ref < ARRAY_SIZE(args));
2316
2317 /* fetch modifier to the last argument */
2318 if (modifier != TEX_MODIFIER_NONE) {
2319 const int last = ARRAY_SIZE(args) - 1;
2320
2321 /* fetch modifier from src0.w or src1.x */
2322 if (sampler == 1) {
2323 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2324 FETCH(&r[last], 0, TGSI_CHAN_W);
2325 }
2326 else {
2327 assert(shadow_ref != 4);
2328 FETCH(&r[last], 1, TGSI_CHAN_X);
2329 }
2330
2331 if (modifier != TEX_MODIFIER_PROJECTED) {
2332 args[last] = &r[last];
2333 }
2334 else {
2335 proj = &r[last];
2336 args[last] = &ZeroVec;
2337 }
2338
2339 /* point unused arguments to zero vector */
2340 for (i = dim; i < last; i++)
2341 args[i] = &ZeroVec;
2342
2343 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2344 control = TGSI_SAMPLER_LOD_EXPLICIT;
2345 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2346 control = TGSI_SAMPLER_LOD_BIAS;
2347 else if (modifier == TEX_MODIFIER_GATHER)
2348 control = TGSI_SAMPLER_GATHER;
2349 }
2350 else {
2351 for (i = dim; i < ARRAY_SIZE(args); i++)
2352 args[i] = &ZeroVec;
2353 }
2354
2355 /* fetch coordinates */
2356 for (i = 0; i < dim; i++) {
2357 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2358
2359 if (proj)
2360 micro_div(&r[i], &r[i], proj);
2361
2362 args[i] = &r[i];
2363 }
2364
2365 /* fetch reference value */
2366 if (shadow_ref >= 0) {
2367 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2368
2369 if (proj)
2370 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2371
2372 args[shadow_ref] = &r[shadow_ref];
2373 }
2374
2375 fetch_texel(mach->Sampler, unit, unit,
2376 args[0], args[1], args[2], args[3], args[4],
2377 NULL, offsets, control,
2378 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2379
2380 #if 0
2381 debug_printf("fetch r: %g %g %g %g\n",
2382 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2383 debug_printf("fetch g: %g %g %g %g\n",
2384 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2385 debug_printf("fetch b: %g %g %g %g\n",
2386 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2387 debug_printf("fetch a: %g %g %g %g\n",
2388 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2389 #endif
2390
2391 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2392 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2393 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2394 }
2395 }
2396 }
2397
2398 static void
2399 exec_lodq(struct tgsi_exec_machine *mach,
2400 const struct tgsi_full_instruction *inst)
2401 {
2402 uint unit;
2403 int dim;
2404 int i;
2405 union tgsi_exec_channel coords[4];
2406 const union tgsi_exec_channel *args[ARRAY_SIZE(coords)];
2407 union tgsi_exec_channel r[2];
2408
2409 unit = fetch_sampler_unit(mach, inst, 1);
2410 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2411 assert(dim <= ARRAY_SIZE(coords));
2412 /* fetch coordinates */
2413 for (i = 0; i < dim; i++) {
2414 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2415 args[i] = &coords[i];
2416 }
2417 for (i = dim; i < ARRAY_SIZE(coords); i++) {
2418 args[i] = &ZeroVec;
2419 }
2420 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2421 args[0]->f,
2422 args[1]->f,
2423 args[2]->f,
2424 args[3]->f,
2425 TGSI_SAMPLER_LOD_NONE,
2426 r[0].f,
2427 r[1].f);
2428
2429 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2430 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2431 TGSI_EXEC_DATA_FLOAT);
2432 }
2433 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2434 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2435 TGSI_EXEC_DATA_FLOAT);
2436 }
2437 }
2438
2439 static void
2440 exec_txd(struct tgsi_exec_machine *mach,
2441 const struct tgsi_full_instruction *inst)
2442 {
2443 union tgsi_exec_channel r[4];
2444 float derivs[3][2][TGSI_QUAD_SIZE];
2445 uint chan;
2446 uint unit;
2447 int8_t offsets[3];
2448
2449 unit = fetch_sampler_unit(mach, inst, 3);
2450 /* always fetch all 3 offsets, overkill but keeps code simple */
2451 fetch_texel_offsets(mach, inst, offsets);
2452
2453 switch (inst->Texture.Texture) {
2454 case TGSI_TEXTURE_1D:
2455 FETCH(&r[0], 0, TGSI_CHAN_X);
2456
2457 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2458
2459 fetch_texel(mach->Sampler, unit, unit,
2460 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2461 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2462 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2463 break;
2464
2465 case TGSI_TEXTURE_SHADOW1D:
2466 case TGSI_TEXTURE_1D_ARRAY:
2467 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2468 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2469 FETCH(&r[0], 0, TGSI_CHAN_X);
2470 FETCH(&r[1], 0, TGSI_CHAN_Y);
2471 FETCH(&r[2], 0, TGSI_CHAN_Z);
2472
2473 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2474
2475 fetch_texel(mach->Sampler, unit, unit,
2476 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2477 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2478 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2479 break;
2480
2481 case TGSI_TEXTURE_2D:
2482 case TGSI_TEXTURE_RECT:
2483 FETCH(&r[0], 0, TGSI_CHAN_X);
2484 FETCH(&r[1], 0, TGSI_CHAN_Y);
2485
2486 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2487 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2488
2489 fetch_texel(mach->Sampler, unit, unit,
2490 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2491 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2492 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2493 break;
2494
2495
2496 case TGSI_TEXTURE_SHADOW2D:
2497 case TGSI_TEXTURE_SHADOWRECT:
2498 case TGSI_TEXTURE_2D_ARRAY:
2499 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2500 /* only SHADOW2D_ARRAY actually needs W */
2501 FETCH(&r[0], 0, TGSI_CHAN_X);
2502 FETCH(&r[1], 0, TGSI_CHAN_Y);
2503 FETCH(&r[2], 0, TGSI_CHAN_Z);
2504 FETCH(&r[3], 0, TGSI_CHAN_W);
2505
2506 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2507 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2508
2509 fetch_texel(mach->Sampler, unit, unit,
2510 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2511 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2512 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2513 break;
2514
2515 case TGSI_TEXTURE_3D:
2516 case TGSI_TEXTURE_CUBE:
2517 case TGSI_TEXTURE_CUBE_ARRAY:
2518 case TGSI_TEXTURE_SHADOWCUBE:
2519 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2520 FETCH(&r[0], 0, TGSI_CHAN_X);
2521 FETCH(&r[1], 0, TGSI_CHAN_Y);
2522 FETCH(&r[2], 0, TGSI_CHAN_Z);
2523 FETCH(&r[3], 0, TGSI_CHAN_W);
2524
2525 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2526 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2527 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2528
2529 fetch_texel(mach->Sampler, unit, unit,
2530 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2531 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2532 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2533 break;
2534
2535 default:
2536 assert(0);
2537 }
2538
2539 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2540 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2541 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2542 }
2543 }
2544 }
2545
2546
2547 static void
2548 exec_txf(struct tgsi_exec_machine *mach,
2549 const struct tgsi_full_instruction *inst)
2550 {
2551 union tgsi_exec_channel r[4];
2552 uint chan;
2553 uint unit;
2554 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2555 int j;
2556 int8_t offsets[3];
2557 unsigned target;
2558
2559 unit = fetch_sampler_unit(mach, inst, 1);
2560 /* always fetch all 3 offsets, overkill but keeps code simple */
2561 fetch_texel_offsets(mach, inst, offsets);
2562
2563 IFETCH(&r[3], 0, TGSI_CHAN_W);
2564
2565 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2566 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2567 target = mach->SamplerViews[unit].Resource;
2568 }
2569 else {
2570 target = inst->Texture.Texture;
2571 }
2572 switch(target) {
2573 case TGSI_TEXTURE_3D:
2574 case TGSI_TEXTURE_2D_ARRAY:
2575 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2576 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2577 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2578 /* fallthrough */
2579 case TGSI_TEXTURE_2D:
2580 case TGSI_TEXTURE_RECT:
2581 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2582 case TGSI_TEXTURE_SHADOW2D:
2583 case TGSI_TEXTURE_SHADOWRECT:
2584 case TGSI_TEXTURE_1D_ARRAY:
2585 case TGSI_TEXTURE_2D_MSAA:
2586 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2587 /* fallthrough */
2588 case TGSI_TEXTURE_BUFFER:
2589 case TGSI_TEXTURE_1D:
2590 case TGSI_TEXTURE_SHADOW1D:
2591 IFETCH(&r[0], 0, TGSI_CHAN_X);
2592 break;
2593 default:
2594 assert(0);
2595 break;
2596 }
2597
2598 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2599 offsets, rgba);
2600
2601 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2602 r[0].f[j] = rgba[0][j];
2603 r[1].f[j] = rgba[1][j];
2604 r[2].f[j] = rgba[2][j];
2605 r[3].f[j] = rgba[3][j];
2606 }
2607
2608 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2609 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2610 unsigned char swizzles[4];
2611 swizzles[0] = inst->Src[1].Register.SwizzleX;
2612 swizzles[1] = inst->Src[1].Register.SwizzleY;
2613 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2614 swizzles[3] = inst->Src[1].Register.SwizzleW;
2615
2616 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2617 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2618 store_dest(mach, &r[swizzles[chan]],
2619 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2620 }
2621 }
2622 }
2623 else {
2624 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2625 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2626 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2627 }
2628 }
2629 }
2630 }
2631
2632 static void
2633 exec_txq(struct tgsi_exec_machine *mach,
2634 const struct tgsi_full_instruction *inst)
2635 {
2636 int result[4];
2637 union tgsi_exec_channel r[4], src;
2638 uint chan;
2639 uint unit;
2640 int i,j;
2641
2642 unit = fetch_sampler_unit(mach, inst, 1);
2643
2644 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2645
2646 /* XXX: This interface can't return per-pixel values */
2647 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2648
2649 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2650 for (j = 0; j < 4; j++) {
2651 r[j].i[i] = result[j];
2652 }
2653 }
2654
2655 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2656 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2657 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2658 TGSI_EXEC_DATA_INT);
2659 }
2660 }
2661 }
2662
2663 static void
2664 exec_sample(struct tgsi_exec_machine *mach,
2665 const struct tgsi_full_instruction *inst,
2666 uint modifier, boolean compare)
2667 {
2668 const uint resource_unit = inst->Src[1].Register.Index;
2669 const uint sampler_unit = inst->Src[2].Register.Index;
2670 union tgsi_exec_channel r[5], c1;
2671 const union tgsi_exec_channel *lod = &ZeroVec;
2672 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2673 uint chan;
2674 unsigned char swizzles[4];
2675 int8_t offsets[3];
2676
2677 /* always fetch all 3 offsets, overkill but keeps code simple */
2678 fetch_texel_offsets(mach, inst, offsets);
2679
2680 assert(modifier != TEX_MODIFIER_PROJECTED);
2681
2682 if (modifier != TEX_MODIFIER_NONE) {
2683 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2684 FETCH(&c1, 3, TGSI_CHAN_X);
2685 lod = &c1;
2686 control = TGSI_SAMPLER_LOD_BIAS;
2687 }
2688 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2689 FETCH(&c1, 3, TGSI_CHAN_X);
2690 lod = &c1;
2691 control = TGSI_SAMPLER_LOD_EXPLICIT;
2692 }
2693 else {
2694 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2695 control = TGSI_SAMPLER_LOD_ZERO;
2696 }
2697 }
2698
2699 FETCH(&r[0], 0, TGSI_CHAN_X);
2700
2701 switch (mach->SamplerViews[resource_unit].Resource) {
2702 case TGSI_TEXTURE_1D:
2703 if (compare) {
2704 FETCH(&r[2], 3, TGSI_CHAN_X);
2705 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2706 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2707 NULL, offsets, control,
2708 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2709 }
2710 else {
2711 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2712 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2713 NULL, offsets, control,
2714 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2715 }
2716 break;
2717
2718 case TGSI_TEXTURE_1D_ARRAY:
2719 case TGSI_TEXTURE_2D:
2720 case TGSI_TEXTURE_RECT:
2721 FETCH(&r[1], 0, TGSI_CHAN_Y);
2722 if (compare) {
2723 FETCH(&r[2], 3, TGSI_CHAN_X);
2724 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2725 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2726 NULL, offsets, control,
2727 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2728 }
2729 else {
2730 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2731 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2732 NULL, offsets, control,
2733 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2734 }
2735 break;
2736
2737 case TGSI_TEXTURE_2D_ARRAY:
2738 case TGSI_TEXTURE_3D:
2739 case TGSI_TEXTURE_CUBE:
2740 FETCH(&r[1], 0, TGSI_CHAN_Y);
2741 FETCH(&r[2], 0, TGSI_CHAN_Z);
2742 if(compare) {
2743 FETCH(&r[3], 3, TGSI_CHAN_X);
2744 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2745 &r[0], &r[1], &r[2], &r[3], lod,
2746 NULL, offsets, control,
2747 &r[0], &r[1], &r[2], &r[3]);
2748 }
2749 else {
2750 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2751 &r[0], &r[1], &r[2], &ZeroVec, lod,
2752 NULL, offsets, control,
2753 &r[0], &r[1], &r[2], &r[3]);
2754 }
2755 break;
2756
2757 case TGSI_TEXTURE_CUBE_ARRAY:
2758 FETCH(&r[1], 0, TGSI_CHAN_Y);
2759 FETCH(&r[2], 0, TGSI_CHAN_Z);
2760 FETCH(&r[3], 0, TGSI_CHAN_W);
2761 if(compare) {
2762 FETCH(&r[4], 3, TGSI_CHAN_X);
2763 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2764 &r[0], &r[1], &r[2], &r[3], &r[4],
2765 NULL, offsets, control,
2766 &r[0], &r[1], &r[2], &r[3]);
2767 }
2768 else {
2769 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2770 &r[0], &r[1], &r[2], &r[3], lod,
2771 NULL, offsets, control,
2772 &r[0], &r[1], &r[2], &r[3]);
2773 }
2774 break;
2775
2776
2777 default:
2778 assert(0);
2779 }
2780
2781 swizzles[0] = inst->Src[1].Register.SwizzleX;
2782 swizzles[1] = inst->Src[1].Register.SwizzleY;
2783 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2784 swizzles[3] = inst->Src[1].Register.SwizzleW;
2785
2786 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2787 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2788 store_dest(mach, &r[swizzles[chan]],
2789 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2790 }
2791 }
2792 }
2793
2794 static void
2795 exec_sample_d(struct tgsi_exec_machine *mach,
2796 const struct tgsi_full_instruction *inst)
2797 {
2798 const uint resource_unit = inst->Src[1].Register.Index;
2799 const uint sampler_unit = inst->Src[2].Register.Index;
2800 union tgsi_exec_channel r[4];
2801 float derivs[3][2][TGSI_QUAD_SIZE];
2802 uint chan;
2803 unsigned char swizzles[4];
2804 int8_t offsets[3];
2805
2806 /* always fetch all 3 offsets, overkill but keeps code simple */
2807 fetch_texel_offsets(mach, inst, offsets);
2808
2809 FETCH(&r[0], 0, TGSI_CHAN_X);
2810
2811 switch (mach->SamplerViews[resource_unit].Resource) {
2812 case TGSI_TEXTURE_1D:
2813 case TGSI_TEXTURE_1D_ARRAY:
2814 /* only 1D array actually needs Y */
2815 FETCH(&r[1], 0, TGSI_CHAN_Y);
2816
2817 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2818
2819 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2820 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2821 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2822 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2823 break;
2824
2825 case TGSI_TEXTURE_2D:
2826 case TGSI_TEXTURE_RECT:
2827 case TGSI_TEXTURE_2D_ARRAY:
2828 /* only 2D array actually needs Z */
2829 FETCH(&r[1], 0, TGSI_CHAN_Y);
2830 FETCH(&r[2], 0, TGSI_CHAN_Z);
2831
2832 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2833 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2834
2835 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2836 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2837 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2838 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2839 break;
2840
2841 case TGSI_TEXTURE_3D:
2842 case TGSI_TEXTURE_CUBE:
2843 case TGSI_TEXTURE_CUBE_ARRAY:
2844 /* only cube array actually needs W */
2845 FETCH(&r[1], 0, TGSI_CHAN_Y);
2846 FETCH(&r[2], 0, TGSI_CHAN_Z);
2847 FETCH(&r[3], 0, TGSI_CHAN_W);
2848
2849 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2850 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2851 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2852
2853 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2854 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2855 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2856 &r[0], &r[1], &r[2], &r[3]);
2857 break;
2858
2859 default:
2860 assert(0);
2861 }
2862
2863 swizzles[0] = inst->Src[1].Register.SwizzleX;
2864 swizzles[1] = inst->Src[1].Register.SwizzleY;
2865 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2866 swizzles[3] = inst->Src[1].Register.SwizzleW;
2867
2868 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2869 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2870 store_dest(mach, &r[swizzles[chan]],
2871 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2872 }
2873 }
2874 }
2875
2876
2877 /**
2878 * Evaluate a constant-valued coefficient at the position of the
2879 * current quad.
2880 */
2881 static void
2882 eval_constant_coef(
2883 struct tgsi_exec_machine *mach,
2884 unsigned attrib,
2885 unsigned chan )
2886 {
2887 unsigned i;
2888
2889 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2890 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2891 }
2892 }
2893
2894 /**
2895 * Evaluate a linear-valued coefficient at the position of the
2896 * current quad.
2897 */
2898 static void
2899 eval_linear_coef(
2900 struct tgsi_exec_machine *mach,
2901 unsigned attrib,
2902 unsigned chan )
2903 {
2904 const float x = mach->QuadPos.xyzw[0].f[0];
2905 const float y = mach->QuadPos.xyzw[1].f[0];
2906 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2907 const float dady = mach->InterpCoefs[attrib].dady[chan];
2908 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2909 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2910 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2911 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2912 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2913 }
2914
2915 /**
2916 * Evaluate a perspective-valued coefficient at the position of the
2917 * current quad.
2918 */
2919 static void
2920 eval_perspective_coef(
2921 struct tgsi_exec_machine *mach,
2922 unsigned attrib,
2923 unsigned chan )
2924 {
2925 const float x = mach->QuadPos.xyzw[0].f[0];
2926 const float y = mach->QuadPos.xyzw[1].f[0];
2927 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2928 const float dady = mach->InterpCoefs[attrib].dady[chan];
2929 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2930 const float *w = mach->QuadPos.xyzw[3].f;
2931 /* divide by W here */
2932 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2933 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2934 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2935 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2936 }
2937
2938
2939 typedef void (* eval_coef_func)(
2940 struct tgsi_exec_machine *mach,
2941 unsigned attrib,
2942 unsigned chan );
2943
2944 static void
2945 exec_declaration(struct tgsi_exec_machine *mach,
2946 const struct tgsi_full_declaration *decl)
2947 {
2948 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2949 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2950 return;
2951 }
2952
2953 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
2954 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2955 uint first, last, mask;
2956
2957 first = decl->Range.First;
2958 last = decl->Range.Last;
2959 mask = decl->Declaration.UsageMask;
2960
2961 /* XXX we could remove this special-case code since
2962 * mach->InterpCoefs[first].a0 should already have the
2963 * front/back-face value. But we should first update the
2964 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2965 * Then, we could remove the tgsi_exec_machine::Face field.
2966 */
2967 /* XXX make FACE a system value */
2968 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2969 uint i;
2970
2971 assert(decl->Semantic.Index == 0);
2972 assert(first == last);
2973
2974 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2975 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2976 }
2977 } else {
2978 eval_coef_func eval;
2979 uint i, j;
2980
2981 switch (decl->Interp.Interpolate) {
2982 case TGSI_INTERPOLATE_CONSTANT:
2983 eval = eval_constant_coef;
2984 break;
2985
2986 case TGSI_INTERPOLATE_LINEAR:
2987 eval = eval_linear_coef;
2988 break;
2989
2990 case TGSI_INTERPOLATE_PERSPECTIVE:
2991 eval = eval_perspective_coef;
2992 break;
2993
2994 case TGSI_INTERPOLATE_COLOR:
2995 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2996 break;
2997
2998 default:
2999 assert(0);
3000 return;
3001 }
3002
3003 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
3004 if (mask & (1 << j)) {
3005 for (i = first; i <= last; i++) {
3006 eval(mach, i, j);
3007 }
3008 }
3009 }
3010 }
3011
3012 if (DEBUG_EXECUTION) {
3013 uint i, j;
3014 for (i = first; i <= last; ++i) {
3015 debug_printf("IN[%2u] = ", i);
3016 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
3017 if (j > 0) {
3018 debug_printf(" ");
3019 }
3020 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3021 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
3022 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
3023 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
3024 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
3025 }
3026 }
3027 }
3028 }
3029 }
3030
3031 }
3032
3033 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
3034 const union tgsi_exec_channel *src);
3035
3036 static void
3037 exec_scalar_unary(struct tgsi_exec_machine *mach,
3038 const struct tgsi_full_instruction *inst,
3039 micro_unary_op op,
3040 enum tgsi_exec_datatype dst_datatype,
3041 enum tgsi_exec_datatype src_datatype)
3042 {
3043 unsigned int chan;
3044 union tgsi_exec_channel src;
3045 union tgsi_exec_channel dst;
3046
3047 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
3048 op(&dst, &src);
3049 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3050 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3051 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
3052 }
3053 }
3054 }
3055
3056 static void
3057 exec_vector_unary(struct tgsi_exec_machine *mach,
3058 const struct tgsi_full_instruction *inst,
3059 micro_unary_op op,
3060 enum tgsi_exec_datatype dst_datatype,
3061 enum tgsi_exec_datatype src_datatype)
3062 {
3063 unsigned int chan;
3064 struct tgsi_exec_vector dst;
3065
3066 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3067 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3068 union tgsi_exec_channel src;
3069
3070 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
3071 op(&dst.xyzw[chan], &src);
3072 }
3073 }
3074 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3075 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3076 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3077 }
3078 }
3079 }
3080
3081 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
3082 const union tgsi_exec_channel *src0,
3083 const union tgsi_exec_channel *src1);
3084
3085 static void
3086 exec_scalar_binary(struct tgsi_exec_machine *mach,
3087 const struct tgsi_full_instruction *inst,
3088 micro_binary_op op,
3089 enum tgsi_exec_datatype dst_datatype,
3090 enum tgsi_exec_datatype src_datatype)
3091 {
3092 unsigned int chan;
3093 union tgsi_exec_channel src[2];
3094 union tgsi_exec_channel dst;
3095
3096 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
3097 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
3098 op(&dst, &src[0], &src[1]);
3099 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3100 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3101 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
3102 }
3103 }
3104 }
3105
3106 static void
3107 exec_vector_binary(struct tgsi_exec_machine *mach,
3108 const struct tgsi_full_instruction *inst,
3109 micro_binary_op op,
3110 enum tgsi_exec_datatype dst_datatype,
3111 enum tgsi_exec_datatype src_datatype)
3112 {
3113 unsigned int chan;
3114 struct tgsi_exec_vector dst;
3115
3116 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3117 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3118 union tgsi_exec_channel src[2];
3119
3120 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3121 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3122 op(&dst.xyzw[chan], &src[0], &src[1]);
3123 }
3124 }
3125 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3126 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3127 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3128 }
3129 }
3130 }
3131
3132 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
3133 const union tgsi_exec_channel *src0,
3134 const union tgsi_exec_channel *src1,
3135 const union tgsi_exec_channel *src2);
3136
3137 static void
3138 exec_vector_trinary(struct tgsi_exec_machine *mach,
3139 const struct tgsi_full_instruction *inst,
3140 micro_trinary_op op,
3141 enum tgsi_exec_datatype dst_datatype,
3142 enum tgsi_exec_datatype src_datatype)
3143 {
3144 unsigned int chan;
3145 struct tgsi_exec_vector dst;
3146
3147 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3148 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3149 union tgsi_exec_channel src[3];
3150
3151 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3152 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3153 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
3154 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
3155 }
3156 }
3157 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3158 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3159 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3160 }
3161 }
3162 }
3163
3164 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
3165 const union tgsi_exec_channel *src0,
3166 const union tgsi_exec_channel *src1,
3167 const union tgsi_exec_channel *src2,
3168 const union tgsi_exec_channel *src3);
3169
3170 static void
3171 exec_vector_quaternary(struct tgsi_exec_machine *mach,
3172 const struct tgsi_full_instruction *inst,
3173 micro_quaternary_op op,
3174 enum tgsi_exec_datatype dst_datatype,
3175 enum tgsi_exec_datatype src_datatype)
3176 {
3177 unsigned int chan;
3178 struct tgsi_exec_vector dst;
3179
3180 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3181 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3182 union tgsi_exec_channel src[4];
3183
3184 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3185 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3186 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
3187 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
3188 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
3189 }
3190 }
3191 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3192 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3193 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3194 }
3195 }
3196 }
3197
3198 static void
3199 exec_dp3(struct tgsi_exec_machine *mach,
3200 const struct tgsi_full_instruction *inst)
3201 {
3202 unsigned int chan;
3203 union tgsi_exec_channel arg[3];
3204
3205 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3206 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3207 micro_mul(&arg[2], &arg[0], &arg[1]);
3208
3209 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
3210 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
3211 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
3212 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3213 }
3214
3215 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3216 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3217 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3218 }
3219 }
3220 }
3221
3222 static void
3223 exec_dp4(struct tgsi_exec_machine *mach,
3224 const struct tgsi_full_instruction *inst)
3225 {
3226 unsigned int chan;
3227 union tgsi_exec_channel arg[3];
3228
3229 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3230 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3231 micro_mul(&arg[2], &arg[0], &arg[1]);
3232
3233 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
3234 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
3235 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
3236 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3237 }
3238
3239 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3240 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3241 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3242 }
3243 }
3244 }
3245
3246 static void
3247 exec_dp2a(struct tgsi_exec_machine *mach,
3248 const struct tgsi_full_instruction *inst)
3249 {
3250 unsigned int chan;
3251 union tgsi_exec_channel arg[3];
3252
3253 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3254 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3255 micro_mul(&arg[2], &arg[0], &arg[1]);
3256
3257 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3258 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3259 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3260
3261 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3262 micro_add(&arg[0], &arg[0], &arg[1]);
3263
3264 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3265 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3266 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3267 }
3268 }
3269 }
3270
3271 static void
3272 exec_dph(struct tgsi_exec_machine *mach,
3273 const struct tgsi_full_instruction *inst)
3274 {
3275 unsigned int chan;
3276 union tgsi_exec_channel arg[3];
3277
3278 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3279 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3280 micro_mul(&arg[2], &arg[0], &arg[1]);
3281
3282 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3283 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3284 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3285
3286 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3287 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3288 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3289
3290 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3291 micro_add(&arg[0], &arg[0], &arg[1]);
3292
3293 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3294 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3295 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3296 }
3297 }
3298 }
3299
3300 static void
3301 exec_dp2(struct tgsi_exec_machine *mach,
3302 const struct tgsi_full_instruction *inst)
3303 {
3304 unsigned int chan;
3305 union tgsi_exec_channel arg[3];
3306
3307 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3308 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3309 micro_mul(&arg[2], &arg[0], &arg[1]);
3310
3311 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3312 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3313 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3314
3315 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3316 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3317 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3318 }
3319 }
3320 }
3321
3322 static void
3323 exec_pk2h(struct tgsi_exec_machine *mach,
3324 const struct tgsi_full_instruction *inst)
3325 {
3326 unsigned chan;
3327 union tgsi_exec_channel arg[2], dst;
3328
3329 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3330 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3331 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3332 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3333 (util_float_to_half(arg[1].f[chan]) << 16);
3334 }
3335 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3336 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3337 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3338 }
3339 }
3340 }
3341
3342 static void
3343 exec_up2h(struct tgsi_exec_machine *mach,
3344 const struct tgsi_full_instruction *inst)
3345 {
3346 unsigned chan;
3347 union tgsi_exec_channel arg, dst[2];
3348
3349 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3350 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3351 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3352 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3353 }
3354 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3355 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3356 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3357 }
3358 }
3359 }
3360
3361 static void
3362 exec_scs(struct tgsi_exec_machine *mach,
3363 const struct tgsi_full_instruction *inst)
3364 {
3365 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3366 union tgsi_exec_channel arg;
3367 union tgsi_exec_channel result;
3368
3369 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3370
3371 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3372 micro_cos(&result, &arg);
3373 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3374 }
3375 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3376 micro_sin(&result, &arg);
3377 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3378 }
3379 }
3380 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3381 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3382 }
3383 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3384 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3385 }
3386 }
3387
3388 static void
3389 exec_xpd(struct tgsi_exec_machine *mach,
3390 const struct tgsi_full_instruction *inst)
3391 {
3392 union tgsi_exec_channel r[6];
3393 union tgsi_exec_channel d[3];
3394
3395 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3396 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3397
3398 micro_mul(&r[2], &r[0], &r[1]);
3399
3400 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3401 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3402
3403 micro_mul(&r[5], &r[3], &r[4] );
3404 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3405
3406 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3407
3408 micro_mul(&r[3], &r[3], &r[2]);
3409
3410 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3411
3412 micro_mul(&r[1], &r[1], &r[5]);
3413 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3414
3415 micro_mul(&r[5], &r[5], &r[4]);
3416 micro_mul(&r[0], &r[0], &r[2]);
3417 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3418
3419 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3420 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3421 }
3422 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3423 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3424 }
3425 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3426 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3427 }
3428 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3429 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3430 }
3431 }
3432
3433 static void
3434 exec_dst(struct tgsi_exec_machine *mach,
3435 const struct tgsi_full_instruction *inst)
3436 {
3437 union tgsi_exec_channel r[2];
3438 union tgsi_exec_channel d[4];
3439
3440 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3441 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3442 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3443 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3444 }
3445 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3446 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3447 }
3448 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3449 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3450 }
3451
3452 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3453 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3454 }
3455 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3456 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3457 }
3458 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3459 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3460 }
3461 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3462 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3463 }
3464 }
3465
3466 static void
3467 exec_log(struct tgsi_exec_machine *mach,
3468 const struct tgsi_full_instruction *inst)
3469 {
3470 union tgsi_exec_channel r[3];
3471
3472 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3473 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3474 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3475 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3476 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3477 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3478 }
3479 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3480 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3481 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3482 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3483 }
3484 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3485 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3486 }
3487 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3488 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3489 }
3490 }
3491
3492 static void
3493 exec_exp(struct tgsi_exec_machine *mach,
3494 const struct tgsi_full_instruction *inst)
3495 {
3496 union tgsi_exec_channel r[3];
3497
3498 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3499 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3500 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3501 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3502 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3503 }
3504 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3505 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3506 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3507 }
3508 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3509 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3510 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3511 }
3512 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3513 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3514 }
3515 }
3516
3517 static void
3518 exec_lit(struct tgsi_exec_machine *mach,
3519 const struct tgsi_full_instruction *inst)
3520 {
3521 union tgsi_exec_channel r[3];
3522 union tgsi_exec_channel d[3];
3523
3524 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3525 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3526 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3527 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3528 micro_max(&r[1], &r[1], &ZeroVec);
3529
3530 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3531 micro_min(&r[2], &r[2], &P128Vec);
3532 micro_max(&r[2], &r[2], &M128Vec);
3533 micro_pow(&r[1], &r[1], &r[2]);
3534 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3535 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3536 }
3537 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3538 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3539 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3540 }
3541 }
3542 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3543 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3544 }
3545
3546 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3547 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3548 }
3549 }
3550
3551 static void
3552 exec_break(struct tgsi_exec_machine *mach)
3553 {
3554 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3555 /* turn off loop channels for each enabled exec channel */
3556 mach->LoopMask &= ~mach->ExecMask;
3557 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3558 UPDATE_EXEC_MASK(mach);
3559 } else {
3560 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3561
3562 mach->Switch.mask = 0x0;
3563
3564 UPDATE_EXEC_MASK(mach);
3565 }
3566 }
3567
3568 static void
3569 exec_switch(struct tgsi_exec_machine *mach,
3570 const struct tgsi_full_instruction *inst)
3571 {
3572 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3573 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3574
3575 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3576 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3577 mach->Switch.mask = 0x0;
3578 mach->Switch.defaultMask = 0x0;
3579
3580 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3581 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3582
3583 UPDATE_EXEC_MASK(mach);
3584 }
3585
3586 static void
3587 exec_case(struct tgsi_exec_machine *mach,
3588 const struct tgsi_full_instruction *inst)
3589 {
3590 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3591 union tgsi_exec_channel src;
3592 uint mask = 0;
3593
3594 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3595
3596 if (mach->Switch.selector.u[0] == src.u[0]) {
3597 mask |= 0x1;
3598 }
3599 if (mach->Switch.selector.u[1] == src.u[1]) {
3600 mask |= 0x2;
3601 }
3602 if (mach->Switch.selector.u[2] == src.u[2]) {
3603 mask |= 0x4;
3604 }
3605 if (mach->Switch.selector.u[3] == src.u[3]) {
3606 mask |= 0x8;
3607 }
3608
3609 mach->Switch.defaultMask |= mask;
3610
3611 mach->Switch.mask |= mask & prevMask;
3612
3613 UPDATE_EXEC_MASK(mach);
3614 }
3615
3616 /* FIXME: this will only work if default is last */
3617 static void
3618 exec_default(struct tgsi_exec_machine *mach)
3619 {
3620 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3621
3622 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3623
3624 UPDATE_EXEC_MASK(mach);
3625 }
3626
3627 static void
3628 exec_endswitch(struct tgsi_exec_machine *mach)
3629 {
3630 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3631 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3632
3633 UPDATE_EXEC_MASK(mach);
3634 }
3635
3636 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3637 const union tgsi_double_channel *src);
3638
3639 typedef void (* micro_dop_sop)(union tgsi_double_channel *dst,
3640 const union tgsi_double_channel *src0,
3641 union tgsi_exec_channel *src1);
3642
3643 typedef void (* micro_dop_s)(union tgsi_double_channel *dst,
3644 const union tgsi_exec_channel *src);
3645
3646 typedef void (* micro_sop_d)(union tgsi_exec_channel *dst,
3647 const union tgsi_double_channel *src);
3648
3649 static void
3650 fetch_double_channel(struct tgsi_exec_machine *mach,
3651 union tgsi_double_channel *chan,
3652 const struct tgsi_full_src_register *reg,
3653 uint chan_0,
3654 uint chan_1)
3655 {
3656 union tgsi_exec_channel src[2];
3657 uint i;
3658
3659 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3660 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3661
3662 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3663 chan->u[i][0] = src[0].u[i];
3664 chan->u[i][1] = src[1].u[i];
3665 }
3666 if (reg->Register.Absolute) {
3667 micro_dabs(chan, chan);
3668 }
3669 if (reg->Register.Negate) {
3670 micro_dneg(chan, chan);
3671 }
3672 }
3673
3674 static void
3675 store_double_channel(struct tgsi_exec_machine *mach,
3676 const union tgsi_double_channel *chan,
3677 const struct tgsi_full_dst_register *reg,
3678 const struct tgsi_full_instruction *inst,
3679 uint chan_0,
3680 uint chan_1)
3681 {
3682 union tgsi_exec_channel dst[2];
3683 uint i;
3684 union tgsi_double_channel temp;
3685 const uint execmask = mach->ExecMask;
3686
3687 if (!inst->Instruction.Saturate) {
3688 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3689 if (execmask & (1 << i)) {
3690 dst[0].u[i] = chan->u[i][0];
3691 dst[1].u[i] = chan->u[i][1];
3692 }
3693 }
3694 else {
3695 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3696 if (execmask & (1 << i)) {
3697 if (chan->d[i] < 0.0)
3698 temp.d[i] = 0.0;
3699 else if (chan->d[i] > 1.0)
3700 temp.d[i] = 1.0;
3701 else
3702 temp.d[i] = chan->d[i];
3703
3704 dst[0].u[i] = temp.u[i][0];
3705 dst[1].u[i] = temp.u[i][1];
3706 }
3707 }
3708
3709 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3710 if (chan_1 != -1)
3711 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3712 }
3713
3714 static void
3715 exec_double_unary(struct tgsi_exec_machine *mach,
3716 const struct tgsi_full_instruction *inst,
3717 micro_dop op)
3718 {
3719 union tgsi_double_channel src;
3720 union tgsi_double_channel dst;
3721
3722 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3723 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3724 op(&dst, &src);
3725 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3726 }
3727 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3728 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3729 op(&dst, &src);
3730 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3731 }
3732 }
3733
3734 static void
3735 exec_double_binary(struct tgsi_exec_machine *mach,
3736 const struct tgsi_full_instruction *inst,
3737 micro_dop op,
3738 enum tgsi_exec_datatype dst_datatype)
3739 {
3740 union tgsi_double_channel src[2];
3741 union tgsi_double_channel dst;
3742 int first_dest_chan, second_dest_chan;
3743 int wmask;
3744
3745 wmask = inst->Dst[0].Register.WriteMask;
3746 /* these are & because of the way DSLT etc store their destinations */
3747 if (wmask & TGSI_WRITEMASK_XY) {
3748 first_dest_chan = TGSI_CHAN_X;
3749 second_dest_chan = TGSI_CHAN_Y;
3750 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3751 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3752 second_dest_chan = -1;
3753 }
3754
3755 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3756 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3757 op(&dst, src);
3758 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3759 }
3760
3761 if (wmask & TGSI_WRITEMASK_ZW) {
3762 first_dest_chan = TGSI_CHAN_Z;
3763 second_dest_chan = TGSI_CHAN_W;
3764 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3765 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3766 second_dest_chan = -1;
3767 }
3768
3769 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3770 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3771 op(&dst, src);
3772 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3773 }
3774 }
3775
3776 static void
3777 exec_double_trinary(struct tgsi_exec_machine *mach,
3778 const struct tgsi_full_instruction *inst,
3779 micro_dop op)
3780 {
3781 union tgsi_double_channel src[3];
3782 union tgsi_double_channel dst;
3783
3784 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3785 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3786 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3787 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3788 op(&dst, src);
3789 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3790 }
3791 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3792 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3793 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3794 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3795 op(&dst, src);
3796 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3797 }
3798 }
3799
3800 static void
3801 exec_dldexp(struct tgsi_exec_machine *mach,
3802 const struct tgsi_full_instruction *inst)
3803 {
3804 union tgsi_double_channel src0;
3805 union tgsi_exec_channel src1;
3806 union tgsi_double_channel dst;
3807 int wmask;
3808
3809 wmask = inst->Dst[0].Register.WriteMask;
3810 if (wmask & TGSI_WRITEMASK_XY) {
3811 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3812 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3813 micro_dldexp(&dst, &src0, &src1);
3814 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3815 }
3816
3817 if (wmask & TGSI_WRITEMASK_ZW) {
3818 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3819 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3820 micro_dldexp(&dst, &src0, &src1);
3821 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3822 }
3823 }
3824
3825 static void
3826 exec_dfracexp(struct tgsi_exec_machine *mach,
3827 const struct tgsi_full_instruction *inst)
3828 {
3829 union tgsi_double_channel src;
3830 union tgsi_double_channel dst;
3831 union tgsi_exec_channel dst_exp;
3832
3833 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3834 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3835 micro_dfracexp(&dst, &dst_exp, &src);
3836 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3837 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3838 }
3839 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3840 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3841 micro_dfracexp(&dst, &dst_exp, &src);
3842 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3843 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3844 }
3845 }
3846
3847 static void
3848 exec_arg0_64_arg1_32(struct tgsi_exec_machine *mach,
3849 const struct tgsi_full_instruction *inst,
3850 micro_dop_sop op)
3851 {
3852 union tgsi_double_channel src0;
3853 union tgsi_exec_channel src1;
3854 union tgsi_double_channel dst;
3855 int wmask;
3856
3857 wmask = inst->Dst[0].Register.WriteMask;
3858 if (wmask & TGSI_WRITEMASK_XY) {
3859 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3860 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3861 op(&dst, &src0, &src1);
3862 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3863 }
3864
3865 if (wmask & TGSI_WRITEMASK_ZW) {
3866 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3867 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3868 op(&dst, &src0, &src1);
3869 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3870 }
3871 }
3872
3873 static int
3874 get_image_coord_dim(unsigned tgsi_tex)
3875 {
3876 int dim;
3877 switch (tgsi_tex) {
3878 case TGSI_TEXTURE_BUFFER:
3879 case TGSI_TEXTURE_1D:
3880 dim = 1;
3881 break;
3882 case TGSI_TEXTURE_2D:
3883 case TGSI_TEXTURE_RECT:
3884 case TGSI_TEXTURE_1D_ARRAY:
3885 case TGSI_TEXTURE_2D_MSAA:
3886 dim = 2;
3887 break;
3888 case TGSI_TEXTURE_3D:
3889 case TGSI_TEXTURE_CUBE:
3890 case TGSI_TEXTURE_2D_ARRAY:
3891 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3892 case TGSI_TEXTURE_CUBE_ARRAY:
3893 dim = 3;
3894 break;
3895 default:
3896 assert(!"unknown texture target");
3897 dim = 0;
3898 break;
3899 }
3900
3901 return dim;
3902 }
3903
3904 static int
3905 get_image_coord_sample(unsigned tgsi_tex)
3906 {
3907 int sample = 0;
3908 switch (tgsi_tex) {
3909 case TGSI_TEXTURE_2D_MSAA:
3910 sample = 3;
3911 break;
3912 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3913 sample = 4;
3914 break;
3915 default:
3916 break;
3917 }
3918 return sample;
3919 }
3920
3921 static void
3922 exec_load_img(struct tgsi_exec_machine *mach,
3923 const struct tgsi_full_instruction *inst)
3924 {
3925 union tgsi_exec_channel r[4], sample_r;
3926 uint unit;
3927 int sample;
3928 int i, j;
3929 int dim;
3930 uint chan;
3931 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3932 struct tgsi_image_params params;
3933 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3934
3935 unit = fetch_sampler_unit(mach, inst, 0);
3936 dim = get_image_coord_dim(inst->Memory.Texture);
3937 sample = get_image_coord_sample(inst->Memory.Texture);
3938 assert(dim <= 3);
3939
3940 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3941 params.unit = unit;
3942 params.tgsi_tex_instr = inst->Memory.Texture;
3943 params.format = inst->Memory.Format;
3944
3945 for (i = 0; i < dim; i++) {
3946 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3947 }
3948
3949 if (sample)
3950 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3951
3952 mach->Image->load(mach->Image, &params,
3953 r[0].i, r[1].i, r[2].i, sample_r.i,
3954 rgba);
3955 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3956 r[0].f[j] = rgba[0][j];
3957 r[1].f[j] = rgba[1][j];
3958 r[2].f[j] = rgba[2][j];
3959 r[3].f[j] = rgba[3][j];
3960 }
3961 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3962 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3963 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3964 }
3965 }
3966 }
3967
3968 static void
3969 exec_load_buf(struct tgsi_exec_machine *mach,
3970 const struct tgsi_full_instruction *inst)
3971 {
3972 union tgsi_exec_channel r[4];
3973 uint unit;
3974 int j;
3975 uint chan;
3976 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3977 struct tgsi_buffer_params params;
3978 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3979
3980 unit = fetch_sampler_unit(mach, inst, 0);
3981
3982 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3983 params.unit = unit;
3984 IFETCH(&r[0], 1, TGSI_CHAN_X);
3985
3986 mach->Buffer->load(mach->Buffer, &params,
3987 r[0].i, rgba);
3988 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3989 r[0].f[j] = rgba[0][j];
3990 r[1].f[j] = rgba[1][j];
3991 r[2].f[j] = rgba[2][j];
3992 r[3].f[j] = rgba[3][j];
3993 }
3994 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3995 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3996 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3997 }
3998 }
3999 }
4000
4001 static void
4002 exec_load_mem(struct tgsi_exec_machine *mach,
4003 const struct tgsi_full_instruction *inst)
4004 {
4005 union tgsi_exec_channel r[4];
4006 uint chan;
4007 char *ptr = mach->LocalMem;
4008 uint32_t offset;
4009 int j;
4010
4011 IFETCH(&r[0], 1, TGSI_CHAN_X);
4012 if (r[0].u[0] >= mach->LocalMemSize)
4013 return;
4014
4015 offset = r[0].u[0];
4016 ptr += offset;
4017
4018 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4019 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4020 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4021 memcpy(&r[chan].u[j], ptr + (4 * chan), 4);
4022 }
4023 }
4024 }
4025
4026 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4027 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4028 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4029 }
4030 }
4031 }
4032
4033 static void
4034 exec_load(struct tgsi_exec_machine *mach,
4035 const struct tgsi_full_instruction *inst)
4036 {
4037 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4038 exec_load_img(mach, inst);
4039 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
4040 exec_load_buf(mach, inst);
4041 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
4042 exec_load_mem(mach, inst);
4043 }
4044
4045 static void
4046 exec_store_img(struct tgsi_exec_machine *mach,
4047 const struct tgsi_full_instruction *inst)
4048 {
4049 union tgsi_exec_channel r[3], sample_r;
4050 union tgsi_exec_channel value[4];
4051 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4052 struct tgsi_image_params params;
4053 int dim;
4054 int sample;
4055 int i, j;
4056 uint unit;
4057 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4058 unit = inst->Dst[0].Register.Index;
4059 dim = get_image_coord_dim(inst->Memory.Texture);
4060 sample = get_image_coord_sample(inst->Memory.Texture);
4061 assert(dim <= 3);
4062
4063 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4064 params.unit = unit;
4065 params.tgsi_tex_instr = inst->Memory.Texture;
4066 params.format = inst->Memory.Format;
4067
4068 for (i = 0; i < dim; i++) {
4069 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
4070 }
4071
4072 for (i = 0; i < 4; i++) {
4073 FETCH(&value[i], 1, TGSI_CHAN_X + i);
4074 }
4075 if (sample)
4076 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
4077
4078 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4079 rgba[0][j] = value[0].f[j];
4080 rgba[1][j] = value[1].f[j];
4081 rgba[2][j] = value[2].f[j];
4082 rgba[3][j] = value[3].f[j];
4083 }
4084
4085 mach->Image->store(mach->Image, &params,
4086 r[0].i, r[1].i, r[2].i, sample_r.i,
4087 rgba);
4088 }
4089
4090 static void
4091 exec_store_buf(struct tgsi_exec_machine *mach,
4092 const struct tgsi_full_instruction *inst)
4093 {
4094 union tgsi_exec_channel r[3];
4095 union tgsi_exec_channel value[4];
4096 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4097 struct tgsi_buffer_params params;
4098 int i, j;
4099 uint unit;
4100 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4101
4102 unit = inst->Dst[0].Register.Index;
4103
4104 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4105 params.unit = unit;
4106 params.writemask = inst->Dst[0].Register.WriteMask;
4107
4108 IFETCH(&r[0], 0, TGSI_CHAN_X);
4109 for (i = 0; i < 4; i++) {
4110 FETCH(&value[i], 1, TGSI_CHAN_X + i);
4111 }
4112
4113 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4114 rgba[0][j] = value[0].f[j];
4115 rgba[1][j] = value[1].f[j];
4116 rgba[2][j] = value[2].f[j];
4117 rgba[3][j] = value[3].f[j];
4118 }
4119
4120 mach->Buffer->store(mach->Buffer, &params,
4121 r[0].i,
4122 rgba);
4123 }
4124
4125 static void
4126 exec_store_mem(struct tgsi_exec_machine *mach,
4127 const struct tgsi_full_instruction *inst)
4128 {
4129 union tgsi_exec_channel r[3];
4130 union tgsi_exec_channel value[4];
4131 uint i, chan;
4132 char *ptr = mach->LocalMem;
4133 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4134 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4135
4136 IFETCH(&r[0], 0, TGSI_CHAN_X);
4137
4138 for (i = 0; i < 4; i++) {
4139 FETCH(&value[i], 1, TGSI_CHAN_X + i);
4140 }
4141
4142 if (r[0].u[0] >= mach->LocalMemSize)
4143 return;
4144 ptr += r[0].u[0];
4145
4146 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4147 if (execmask & (1 << i)) {
4148 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4149 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4150 memcpy(ptr + (chan * 4), &value[chan].u[0], 4);
4151 }
4152 }
4153 }
4154 }
4155 }
4156
4157 static void
4158 exec_store(struct tgsi_exec_machine *mach,
4159 const struct tgsi_full_instruction *inst)
4160 {
4161 if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE)
4162 exec_store_img(mach, inst);
4163 else if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
4164 exec_store_buf(mach, inst);
4165 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
4166 exec_store_mem(mach, inst);
4167 }
4168
4169 static void
4170 exec_atomop_img(struct tgsi_exec_machine *mach,
4171 const struct tgsi_full_instruction *inst)
4172 {
4173 union tgsi_exec_channel r[4], sample_r;
4174 union tgsi_exec_channel value[4], value2[4];
4175 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4176 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4177 struct tgsi_image_params params;
4178 int dim;
4179 int sample;
4180 int i, j;
4181 uint unit, chan;
4182 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4183 unit = fetch_sampler_unit(mach, inst, 0);
4184 dim = get_image_coord_dim(inst->Memory.Texture);
4185 sample = get_image_coord_sample(inst->Memory.Texture);
4186 assert(dim <= 3);
4187
4188 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4189 params.unit = unit;
4190 params.tgsi_tex_instr = inst->Memory.Texture;
4191 params.format = inst->Memory.Format;
4192
4193 for (i = 0; i < dim; i++) {
4194 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
4195 }
4196
4197 for (i = 0; i < 4; i++) {
4198 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4199 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4200 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4201 }
4202 if (sample)
4203 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
4204
4205 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4206 rgba[0][j] = value[0].f[j];
4207 rgba[1][j] = value[1].f[j];
4208 rgba[2][j] = value[2].f[j];
4209 rgba[3][j] = value[3].f[j];
4210 }
4211 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4212 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4213 rgba2[0][j] = value2[0].f[j];
4214 rgba2[1][j] = value2[1].f[j];
4215 rgba2[2][j] = value2[2].f[j];
4216 rgba2[3][j] = value2[3].f[j];
4217 }
4218 }
4219
4220 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
4221 r[0].i, r[1].i, r[2].i, sample_r.i,
4222 rgba, rgba2);
4223
4224 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4225 r[0].f[j] = rgba[0][j];
4226 r[1].f[j] = rgba[1][j];
4227 r[2].f[j] = rgba[2][j];
4228 r[3].f[j] = rgba[3][j];
4229 }
4230 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4231 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4232 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4233 }
4234 }
4235 }
4236
4237 static void
4238 exec_atomop_buf(struct tgsi_exec_machine *mach,
4239 const struct tgsi_full_instruction *inst)
4240 {
4241 union tgsi_exec_channel r[4];
4242 union tgsi_exec_channel value[4], value2[4];
4243 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4244 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4245 struct tgsi_buffer_params params;
4246 int i, j;
4247 uint unit, chan;
4248 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4249
4250 unit = fetch_sampler_unit(mach, inst, 0);
4251
4252 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4253 params.unit = unit;
4254 params.writemask = inst->Dst[0].Register.WriteMask;
4255
4256 IFETCH(&r[0], 1, TGSI_CHAN_X);
4257
4258 for (i = 0; i < 4; i++) {
4259 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4260 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4261 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4262 }
4263
4264 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4265 rgba[0][j] = value[0].f[j];
4266 rgba[1][j] = value[1].f[j];
4267 rgba[2][j] = value[2].f[j];
4268 rgba[3][j] = value[3].f[j];
4269 }
4270 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4271 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4272 rgba2[0][j] = value2[0].f[j];
4273 rgba2[1][j] = value2[1].f[j];
4274 rgba2[2][j] = value2[2].f[j];
4275 rgba2[3][j] = value2[3].f[j];
4276 }
4277 }
4278
4279 mach->Buffer->op(mach->Buffer, &params, inst->Instruction.Opcode,
4280 r[0].i,
4281 rgba, rgba2);
4282
4283 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4284 r[0].f[j] = rgba[0][j];
4285 r[1].f[j] = rgba[1][j];
4286 r[2].f[j] = rgba[2][j];
4287 r[3].f[j] = rgba[3][j];
4288 }
4289 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4290 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4291 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4292 }
4293 }
4294 }
4295
4296 static void
4297 exec_atomop_mem(struct tgsi_exec_machine *mach,
4298 const struct tgsi_full_instruction *inst)
4299 {
4300 union tgsi_exec_channel r[4];
4301 union tgsi_exec_channel value[4], value2[4];
4302 char *ptr = mach->LocalMem;
4303 uint32_t val;
4304 uint chan, i;
4305 uint32_t offset;
4306 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4307 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4308 IFETCH(&r[0], 1, TGSI_CHAN_X);
4309
4310 if (r[0].u[0] >= mach->LocalMemSize)
4311 return;
4312
4313 offset = r[0].u[0];
4314 ptr += offset;
4315 for (i = 0; i < 4; i++) {
4316 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4317 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4318 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4319 }
4320
4321 memcpy(&r[0].u[0], ptr, 4);
4322 val = r[0].u[0];
4323 switch (inst->Instruction.Opcode) {
4324 case TGSI_OPCODE_ATOMUADD:
4325 val += value[0].u[0];
4326 break;
4327 case TGSI_OPCODE_ATOMXOR:
4328 val ^= value[0].u[0];
4329 break;
4330 case TGSI_OPCODE_ATOMOR:
4331 val |= value[0].u[0];
4332 break;
4333 case TGSI_OPCODE_ATOMAND:
4334 val &= value[0].u[0];
4335 break;
4336 case TGSI_OPCODE_ATOMUMIN:
4337 val = MIN2(val, value[0].u[0]);
4338 break;
4339 case TGSI_OPCODE_ATOMUMAX:
4340 val = MAX2(val, value[0].u[0]);
4341 break;
4342 case TGSI_OPCODE_ATOMIMIN:
4343 val = MIN2(r[0].i[0], value[0].i[0]);
4344 break;
4345 case TGSI_OPCODE_ATOMIMAX:
4346 val = MAX2(r[0].i[0], value[0].i[0]);
4347 break;
4348 case TGSI_OPCODE_ATOMXCHG:
4349 val = value[0].i[0];
4350 break;
4351 case TGSI_OPCODE_ATOMCAS:
4352 if (val == value[0].u[0])
4353 val = value2[0].u[0];
4354 break;
4355 default:
4356 break;
4357 }
4358 for (i = 0; i < TGSI_QUAD_SIZE; i++)
4359 if (execmask & (1 << i))
4360 memcpy(ptr, &val, 4);
4361
4362 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4363 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4364 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4365 }
4366 }
4367 }
4368
4369 static void
4370 exec_atomop(struct tgsi_exec_machine *mach,
4371 const struct tgsi_full_instruction *inst)
4372 {
4373 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4374 exec_atomop_img(mach, inst);
4375 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
4376 exec_atomop_buf(mach, inst);
4377 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
4378 exec_atomop_mem(mach, inst);
4379 }
4380
4381 static void
4382 exec_resq_img(struct tgsi_exec_machine *mach,
4383 const struct tgsi_full_instruction *inst)
4384 {
4385 int result[4];
4386 union tgsi_exec_channel r[4];
4387 uint unit;
4388 int i, chan, j;
4389 struct tgsi_image_params params;
4390 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4391
4392 unit = fetch_sampler_unit(mach, inst, 0);
4393
4394 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4395 params.unit = unit;
4396 params.tgsi_tex_instr = inst->Memory.Texture;
4397 params.format = inst->Memory.Format;
4398
4399 mach->Image->get_dims(mach->Image, &params, result);
4400
4401 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4402 for (j = 0; j < 4; j++) {
4403 r[j].i[i] = result[j];
4404 }
4405 }
4406
4407 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4408 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4409 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4410 TGSI_EXEC_DATA_INT);
4411 }
4412 }
4413 }
4414
4415 static void
4416 exec_resq_buf(struct tgsi_exec_machine *mach,
4417 const struct tgsi_full_instruction *inst)
4418 {
4419 int result;
4420 union tgsi_exec_channel r[4];
4421 uint unit;
4422 int i, chan;
4423 struct tgsi_buffer_params params;
4424 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4425
4426 unit = fetch_sampler_unit(mach, inst, 0);
4427
4428 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4429 params.unit = unit;
4430
4431 mach->Buffer->get_dims(mach->Buffer, &params, &result);
4432
4433 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4434 r[0].i[i] = result;
4435 }
4436
4437 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4438 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4439 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4440 TGSI_EXEC_DATA_INT);
4441 }
4442 }
4443 }
4444
4445 static void
4446 exec_resq(struct tgsi_exec_machine *mach,
4447 const struct tgsi_full_instruction *inst)
4448 {
4449 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4450 exec_resq_img(mach, inst);
4451 else
4452 exec_resq_buf(mach, inst);
4453 }
4454
4455 static void
4456 micro_f2u64(union tgsi_double_channel *dst,
4457 const union tgsi_exec_channel *src)
4458 {
4459 dst->u64[0] = (uint64_t)src->f[0];
4460 dst->u64[1] = (uint64_t)src->f[1];
4461 dst->u64[2] = (uint64_t)src->f[2];
4462 dst->u64[3] = (uint64_t)src->f[3];
4463 }
4464
4465 static void
4466 micro_f2i64(union tgsi_double_channel *dst,
4467 const union tgsi_exec_channel *src)
4468 {
4469 dst->i64[0] = (int64_t)src->f[0];
4470 dst->i64[1] = (int64_t)src->f[1];
4471 dst->i64[2] = (int64_t)src->f[2];
4472 dst->i64[3] = (int64_t)src->f[3];
4473 }
4474
4475 static void
4476 micro_u2i64(union tgsi_double_channel *dst,
4477 const union tgsi_exec_channel *src)
4478 {
4479 dst->u64[0] = (uint64_t)src->u[0];
4480 dst->u64[1] = (uint64_t)src->u[1];
4481 dst->u64[2] = (uint64_t)src->u[2];
4482 dst->u64[3] = (uint64_t)src->u[3];
4483 }
4484
4485 static void
4486 micro_i2i64(union tgsi_double_channel *dst,
4487 const union tgsi_exec_channel *src)
4488 {
4489 dst->i64[0] = (int64_t)src->i[0];
4490 dst->i64[1] = (int64_t)src->i[1];
4491 dst->i64[2] = (int64_t)src->i[2];
4492 dst->i64[3] = (int64_t)src->i[3];
4493 }
4494
4495 static void
4496 micro_d2u64(union tgsi_double_channel *dst,
4497 const union tgsi_double_channel *src)
4498 {
4499 dst->u64[0] = (uint64_t)src->d[0];
4500 dst->u64[1] = (uint64_t)src->d[1];
4501 dst->u64[2] = (uint64_t)src->d[2];
4502 dst->u64[3] = (uint64_t)src->d[3];
4503 }
4504
4505 static void
4506 micro_d2i64(union tgsi_double_channel *dst,
4507 const union tgsi_double_channel *src)
4508 {
4509 dst->i64[0] = (int64_t)src->d[0];
4510 dst->i64[1] = (int64_t)src->d[1];
4511 dst->i64[2] = (int64_t)src->d[2];
4512 dst->i64[3] = (int64_t)src->d[3];
4513 }
4514
4515 static void
4516 micro_u642d(union tgsi_double_channel *dst,
4517 const union tgsi_double_channel *src)
4518 {
4519 dst->d[0] = (double)src->u64[0];
4520 dst->d[1] = (double)src->u64[1];
4521 dst->d[2] = (double)src->u64[2];
4522 dst->d[3] = (double)src->u64[3];
4523 }
4524
4525 static void
4526 micro_i642d(union tgsi_double_channel *dst,
4527 const union tgsi_double_channel *src)
4528 {
4529 dst->d[0] = (double)src->i64[0];
4530 dst->d[1] = (double)src->i64[1];
4531 dst->d[2] = (double)src->i64[2];
4532 dst->d[3] = (double)src->i64[3];
4533 }
4534
4535 static void
4536 micro_u642f(union tgsi_exec_channel *dst,
4537 const union tgsi_double_channel *src)
4538 {
4539 dst->f[0] = (float)src->u64[0];
4540 dst->f[1] = (float)src->u64[1];
4541 dst->f[2] = (float)src->u64[2];
4542 dst->f[3] = (float)src->u64[3];
4543 }
4544
4545 static void
4546 micro_i642f(union tgsi_exec_channel *dst,
4547 const union tgsi_double_channel *src)
4548 {
4549 dst->f[0] = (float)src->i64[0];
4550 dst->f[1] = (float)src->i64[1];
4551 dst->f[2] = (float)src->i64[2];
4552 dst->f[3] = (float)src->i64[3];
4553 }
4554
4555 static void
4556 exec_t_2_64(struct tgsi_exec_machine *mach,
4557 const struct tgsi_full_instruction *inst,
4558 micro_dop_s op,
4559 enum tgsi_exec_datatype src_datatype)
4560 {
4561 union tgsi_exec_channel src;
4562 union tgsi_double_channel dst;
4563
4564 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
4565 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
4566 op(&dst, &src);
4567 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
4568 }
4569 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
4570 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, src_datatype);
4571 op(&dst, &src);
4572 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
4573 }
4574 }
4575
4576 static void
4577 exec_64_2_t(struct tgsi_exec_machine *mach,
4578 const struct tgsi_full_instruction *inst,
4579 micro_sop_d op,
4580 enum tgsi_exec_datatype dst_datatype)
4581 {
4582 union tgsi_double_channel src;
4583 union tgsi_exec_channel dst;
4584 int wm = inst->Dst[0].Register.WriteMask;
4585 int i;
4586 int bit;
4587 for (i = 0; i < 2; i++) {
4588 bit = ffs(wm);
4589 if (bit) {
4590 wm &= ~(1 << (bit - 1));
4591 if (i == 0)
4592 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
4593 else
4594 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
4595 op(&dst, &src);
4596 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, dst_datatype);
4597 }
4598 }
4599 }
4600
4601 static void
4602 micro_i2f(union tgsi_exec_channel *dst,
4603 const union tgsi_exec_channel *src)
4604 {
4605 dst->f[0] = (float)src->i[0];
4606 dst->f[1] = (float)src->i[1];
4607 dst->f[2] = (float)src->i[2];
4608 dst->f[3] = (float)src->i[3];
4609 }
4610
4611 static void
4612 micro_not(union tgsi_exec_channel *dst,
4613 const union tgsi_exec_channel *src)
4614 {
4615 dst->u[0] = ~src->u[0];
4616 dst->u[1] = ~src->u[1];
4617 dst->u[2] = ~src->u[2];
4618 dst->u[3] = ~src->u[3];
4619 }
4620
4621 static void
4622 micro_shl(union tgsi_exec_channel *dst,
4623 const union tgsi_exec_channel *src0,
4624 const union tgsi_exec_channel *src1)
4625 {
4626 unsigned masked_count;
4627 masked_count = src1->u[0] & 0x1f;
4628 dst->u[0] = src0->u[0] << masked_count;
4629 masked_count = src1->u[1] & 0x1f;
4630 dst->u[1] = src0->u[1] << masked_count;
4631 masked_count = src1->u[2] & 0x1f;
4632 dst->u[2] = src0->u[2] << masked_count;
4633 masked_count = src1->u[3] & 0x1f;
4634 dst->u[3] = src0->u[3] << masked_count;
4635 }
4636
4637 static void
4638 micro_and(union tgsi_exec_channel *dst,
4639 const union tgsi_exec_channel *src0,
4640 const union tgsi_exec_channel *src1)
4641 {
4642 dst->u[0] = src0->u[0] & src1->u[0];
4643 dst->u[1] = src0->u[1] & src1->u[1];
4644 dst->u[2] = src0->u[2] & src1->u[2];
4645 dst->u[3] = src0->u[3] & src1->u[3];
4646 }
4647
4648 static void
4649 micro_or(union tgsi_exec_channel *dst,
4650 const union tgsi_exec_channel *src0,
4651 const union tgsi_exec_channel *src1)
4652 {
4653 dst->u[0] = src0->u[0] | src1->u[0];
4654 dst->u[1] = src0->u[1] | src1->u[1];
4655 dst->u[2] = src0->u[2] | src1->u[2];
4656 dst->u[3] = src0->u[3] | src1->u[3];
4657 }
4658
4659 static void
4660 micro_xor(union tgsi_exec_channel *dst,
4661 const union tgsi_exec_channel *src0,
4662 const union tgsi_exec_channel *src1)
4663 {
4664 dst->u[0] = src0->u[0] ^ src1->u[0];
4665 dst->u[1] = src0->u[1] ^ src1->u[1];
4666 dst->u[2] = src0->u[2] ^ src1->u[2];
4667 dst->u[3] = src0->u[3] ^ src1->u[3];
4668 }
4669
4670 static void
4671 micro_mod(union tgsi_exec_channel *dst,
4672 const union tgsi_exec_channel *src0,
4673 const union tgsi_exec_channel *src1)
4674 {
4675 dst->i[0] = src0->i[0] % src1->i[0];
4676 dst->i[1] = src0->i[1] % src1->i[1];
4677 dst->i[2] = src0->i[2] % src1->i[2];
4678 dst->i[3] = src0->i[3] % src1->i[3];
4679 }
4680
4681 static void
4682 micro_f2i(union tgsi_exec_channel *dst,
4683 const union tgsi_exec_channel *src)
4684 {
4685 dst->i[0] = (int)src->f[0];
4686 dst->i[1] = (int)src->f[1];
4687 dst->i[2] = (int)src->f[2];
4688 dst->i[3] = (int)src->f[3];
4689 }
4690
4691 static void
4692 micro_fseq(union tgsi_exec_channel *dst,
4693 const union tgsi_exec_channel *src0,
4694 const union tgsi_exec_channel *src1)
4695 {
4696 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4697 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4698 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4699 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4700 }
4701
4702 static void
4703 micro_fsge(union tgsi_exec_channel *dst,
4704 const union tgsi_exec_channel *src0,
4705 const union tgsi_exec_channel *src1)
4706 {
4707 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4708 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4709 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4710 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4711 }
4712
4713 static void
4714 micro_fslt(union tgsi_exec_channel *dst,
4715 const union tgsi_exec_channel *src0,
4716 const union tgsi_exec_channel *src1)
4717 {
4718 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4719 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4720 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4721 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4722 }
4723
4724 static void
4725 micro_fsne(union tgsi_exec_channel *dst,
4726 const union tgsi_exec_channel *src0,
4727 const union tgsi_exec_channel *src1)
4728 {
4729 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4730 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4731 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4732 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4733 }
4734
4735 static void
4736 micro_idiv(union tgsi_exec_channel *dst,
4737 const union tgsi_exec_channel *src0,
4738 const union tgsi_exec_channel *src1)
4739 {
4740 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4741 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4742 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4743 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4744 }
4745
4746 static void
4747 micro_imax(union tgsi_exec_channel *dst,
4748 const union tgsi_exec_channel *src0,
4749 const union tgsi_exec_channel *src1)
4750 {
4751 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4752 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4753 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4754 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4755 }
4756
4757 static void
4758 micro_imin(union tgsi_exec_channel *dst,
4759 const union tgsi_exec_channel *src0,
4760 const union tgsi_exec_channel *src1)
4761 {
4762 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4763 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4764 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4765 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4766 }
4767
4768 static void
4769 micro_isge(union tgsi_exec_channel *dst,
4770 const union tgsi_exec_channel *src0,
4771 const union tgsi_exec_channel *src1)
4772 {
4773 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4774 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4775 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4776 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4777 }
4778
4779 static void
4780 micro_ishr(union tgsi_exec_channel *dst,
4781 const union tgsi_exec_channel *src0,
4782 const union tgsi_exec_channel *src1)
4783 {
4784 unsigned masked_count;
4785 masked_count = src1->i[0] & 0x1f;
4786 dst->i[0] = src0->i[0] >> masked_count;
4787 masked_count = src1->i[1] & 0x1f;
4788 dst->i[1] = src0->i[1] >> masked_count;
4789 masked_count = src1->i[2] & 0x1f;
4790 dst->i[2] = src0->i[2] >> masked_count;
4791 masked_count = src1->i[3] & 0x1f;
4792 dst->i[3] = src0->i[3] >> masked_count;
4793 }
4794
4795 static void
4796 micro_islt(union tgsi_exec_channel *dst,
4797 const union tgsi_exec_channel *src0,
4798 const union tgsi_exec_channel *src1)
4799 {
4800 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4801 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4802 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4803 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4804 }
4805
4806 static void
4807 micro_f2u(union tgsi_exec_channel *dst,
4808 const union tgsi_exec_channel *src)
4809 {
4810 dst->u[0] = (uint)src->f[0];
4811 dst->u[1] = (uint)src->f[1];
4812 dst->u[2] = (uint)src->f[2];
4813 dst->u[3] = (uint)src->f[3];
4814 }
4815
4816 static void
4817 micro_u2f(union tgsi_exec_channel *dst,
4818 const union tgsi_exec_channel *src)
4819 {
4820 dst->f[0] = (float)src->u[0];
4821 dst->f[1] = (float)src->u[1];
4822 dst->f[2] = (float)src->u[2];
4823 dst->f[3] = (float)src->u[3];
4824 }
4825
4826 static void
4827 micro_uadd(union tgsi_exec_channel *dst,
4828 const union tgsi_exec_channel *src0,
4829 const union tgsi_exec_channel *src1)
4830 {
4831 dst->u[0] = src0->u[0] + src1->u[0];
4832 dst->u[1] = src0->u[1] + src1->u[1];
4833 dst->u[2] = src0->u[2] + src1->u[2];
4834 dst->u[3] = src0->u[3] + src1->u[3];
4835 }
4836
4837 static void
4838 micro_udiv(union tgsi_exec_channel *dst,
4839 const union tgsi_exec_channel *src0,
4840 const union tgsi_exec_channel *src1)
4841 {
4842 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4843 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4844 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4845 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4846 }
4847
4848 static void
4849 micro_umad(union tgsi_exec_channel *dst,
4850 const union tgsi_exec_channel *src0,
4851 const union tgsi_exec_channel *src1,
4852 const union tgsi_exec_channel *src2)
4853 {
4854 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4855 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4856 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4857 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4858 }
4859
4860 static void
4861 micro_umax(union tgsi_exec_channel *dst,
4862 const union tgsi_exec_channel *src0,
4863 const union tgsi_exec_channel *src1)
4864 {
4865 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4866 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4867 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4868 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4869 }
4870
4871 static void
4872 micro_umin(union tgsi_exec_channel *dst,
4873 const union tgsi_exec_channel *src0,
4874 const union tgsi_exec_channel *src1)
4875 {
4876 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4877 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4878 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4879 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4880 }
4881
4882 static void
4883 micro_umod(union tgsi_exec_channel *dst,
4884 const union tgsi_exec_channel *src0,
4885 const union tgsi_exec_channel *src1)
4886 {
4887 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4888 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4889 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4890 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4891 }
4892
4893 static void
4894 micro_umul(union tgsi_exec_channel *dst,
4895 const union tgsi_exec_channel *src0,
4896 const union tgsi_exec_channel *src1)
4897 {
4898 dst->u[0] = src0->u[0] * src1->u[0];
4899 dst->u[1] = src0->u[1] * src1->u[1];
4900 dst->u[2] = src0->u[2] * src1->u[2];
4901 dst->u[3] = src0->u[3] * src1->u[3];
4902 }
4903
4904 static void
4905 micro_imul_hi(union tgsi_exec_channel *dst,
4906 const union tgsi_exec_channel *src0,
4907 const union tgsi_exec_channel *src1)
4908 {
4909 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4910 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4911 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4912 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4913 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4914 #undef I64M
4915 }
4916
4917 static void
4918 micro_umul_hi(union tgsi_exec_channel *dst,
4919 const union tgsi_exec_channel *src0,
4920 const union tgsi_exec_channel *src1)
4921 {
4922 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4923 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4924 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4925 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4926 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4927 #undef U64M
4928 }
4929
4930 static void
4931 micro_useq(union tgsi_exec_channel *dst,
4932 const union tgsi_exec_channel *src0,
4933 const union tgsi_exec_channel *src1)
4934 {
4935 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4936 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4937 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4938 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4939 }
4940
4941 static void
4942 micro_usge(union tgsi_exec_channel *dst,
4943 const union tgsi_exec_channel *src0,
4944 const union tgsi_exec_channel *src1)
4945 {
4946 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4947 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4948 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4949 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4950 }
4951
4952 static void
4953 micro_ushr(union tgsi_exec_channel *dst,
4954 const union tgsi_exec_channel *src0,
4955 const union tgsi_exec_channel *src1)
4956 {
4957 unsigned masked_count;
4958 masked_count = src1->u[0] & 0x1f;
4959 dst->u[0] = src0->u[0] >> masked_count;
4960 masked_count = src1->u[1] & 0x1f;
4961 dst->u[1] = src0->u[1] >> masked_count;
4962 masked_count = src1->u[2] & 0x1f;
4963 dst->u[2] = src0->u[2] >> masked_count;
4964 masked_count = src1->u[3] & 0x1f;
4965 dst->u[3] = src0->u[3] >> masked_count;
4966 }
4967
4968 static void
4969 micro_uslt(union tgsi_exec_channel *dst,
4970 const union tgsi_exec_channel *src0,
4971 const union tgsi_exec_channel *src1)
4972 {
4973 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4974 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4975 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4976 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4977 }
4978
4979 static void
4980 micro_usne(union tgsi_exec_channel *dst,
4981 const union tgsi_exec_channel *src0,
4982 const union tgsi_exec_channel *src1)
4983 {
4984 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4985 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4986 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4987 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4988 }
4989
4990 static void
4991 micro_uarl(union tgsi_exec_channel *dst,
4992 const union tgsi_exec_channel *src)
4993 {
4994 dst->i[0] = src->u[0];
4995 dst->i[1] = src->u[1];
4996 dst->i[2] = src->u[2];
4997 dst->i[3] = src->u[3];
4998 }
4999
5000 static void
5001 micro_ucmp(union tgsi_exec_channel *dst,
5002 const union tgsi_exec_channel *src0,
5003 const union tgsi_exec_channel *src1,
5004 const union tgsi_exec_channel *src2)
5005 {
5006 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
5007 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
5008 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
5009 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
5010 }
5011
5012 /**
5013 * Signed bitfield extract (i.e. sign-extend the extracted bits)
5014 */
5015 static void
5016 micro_ibfe(union tgsi_exec_channel *dst,
5017 const union tgsi_exec_channel *src0,
5018 const union tgsi_exec_channel *src1,
5019 const union tgsi_exec_channel *src2)
5020 {
5021 int i;
5022 for (i = 0; i < 4; i++) {
5023 int width = src2->i[i] & 0x1f;
5024 int offset = src1->i[i] & 0x1f;
5025 if (width == 0)
5026 dst->i[i] = 0;
5027 else if (width + offset < 32)
5028 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
5029 else
5030 dst->i[i] = src0->i[i] >> offset;
5031 }
5032 }
5033
5034 /**
5035 * Unsigned bitfield extract
5036 */
5037 static void
5038 micro_ubfe(union tgsi_exec_channel *dst,
5039 const union tgsi_exec_channel *src0,
5040 const union tgsi_exec_channel *src1,
5041 const union tgsi_exec_channel *src2)
5042 {
5043 int i;
5044 for (i = 0; i < 4; i++) {
5045 int width = src2->u[i] & 0x1f;
5046 int offset = src1->u[i] & 0x1f;
5047 if (width == 0)
5048 dst->u[i] = 0;
5049 else if (width + offset < 32)
5050 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
5051 else
5052 dst->u[i] = src0->u[i] >> offset;
5053 }
5054 }
5055
5056 /**
5057 * Bitfield insert: copy low bits from src1 into a region of src0.
5058 */
5059 static void
5060 micro_bfi(union tgsi_exec_channel *dst,
5061 const union tgsi_exec_channel *src0,
5062 const union tgsi_exec_channel *src1,
5063 const union tgsi_exec_channel *src2,
5064 const union tgsi_exec_channel *src3)
5065 {
5066 int i;
5067 for (i = 0; i < 4; i++) {
5068 int width = src3->u[i] & 0x1f;
5069 int offset = src2->u[i] & 0x1f;
5070 int bitmask = ((1 << width) - 1) << offset;
5071 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
5072 }
5073 }
5074
5075 static void
5076 micro_brev(union tgsi_exec_channel *dst,
5077 const union tgsi_exec_channel *src)
5078 {
5079 dst->u[0] = util_bitreverse(src->u[0]);
5080 dst->u[1] = util_bitreverse(src->u[1]);
5081 dst->u[2] = util_bitreverse(src->u[2]);
5082 dst->u[3] = util_bitreverse(src->u[3]);
5083 }
5084
5085 static void
5086 micro_popc(union tgsi_exec_channel *dst,
5087 const union tgsi_exec_channel *src)
5088 {
5089 dst->u[0] = util_bitcount(src->u[0]);
5090 dst->u[1] = util_bitcount(src->u[1]);
5091 dst->u[2] = util_bitcount(src->u[2]);
5092 dst->u[3] = util_bitcount(src->u[3]);
5093 }
5094
5095 static void
5096 micro_lsb(union tgsi_exec_channel *dst,
5097 const union tgsi_exec_channel *src)
5098 {
5099 dst->i[0] = ffs(src->u[0]) - 1;
5100 dst->i[1] = ffs(src->u[1]) - 1;
5101 dst->i[2] = ffs(src->u[2]) - 1;
5102 dst->i[3] = ffs(src->u[3]) - 1;
5103 }
5104
5105 static void
5106 micro_imsb(union tgsi_exec_channel *dst,
5107 const union tgsi_exec_channel *src)
5108 {
5109 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
5110 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
5111 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
5112 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
5113 }
5114
5115 static void
5116 micro_umsb(union tgsi_exec_channel *dst,
5117 const union tgsi_exec_channel *src)
5118 {
5119 dst->i[0] = util_last_bit(src->u[0]) - 1;
5120 dst->i[1] = util_last_bit(src->u[1]) - 1;
5121 dst->i[2] = util_last_bit(src->u[2]) - 1;
5122 dst->i[3] = util_last_bit(src->u[3]) - 1;
5123 }
5124
5125 /**
5126 * Execute a TGSI instruction.
5127 * Returns TRUE if a barrier instruction is hit,
5128 * otherwise FALSE.
5129 */
5130 static boolean
5131 exec_instruction(
5132 struct tgsi_exec_machine *mach,
5133 const struct tgsi_full_instruction *inst,
5134 int *pc )
5135 {
5136 union tgsi_exec_channel r[10];
5137
5138 (*pc)++;
5139
5140 switch (inst->Instruction.Opcode) {
5141 case TGSI_OPCODE_ARL:
5142 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5143 break;
5144
5145 case TGSI_OPCODE_MOV:
5146 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5147 break;
5148
5149 case TGSI_OPCODE_LIT:
5150 exec_lit(mach, inst);
5151 break;
5152
5153 case TGSI_OPCODE_RCP:
5154 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5155 break;
5156
5157 case TGSI_OPCODE_RSQ:
5158 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5159 break;
5160
5161 case TGSI_OPCODE_EXP:
5162 exec_exp(mach, inst);
5163 break;
5164
5165 case TGSI_OPCODE_LOG:
5166 exec_log(mach, inst);
5167 break;
5168
5169 case TGSI_OPCODE_MUL:
5170 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5171 break;
5172
5173 case TGSI_OPCODE_ADD:
5174 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5175 break;
5176
5177 case TGSI_OPCODE_DP3:
5178 exec_dp3(mach, inst);
5179 break;
5180
5181 case TGSI_OPCODE_DP4:
5182 exec_dp4(mach, inst);
5183 break;
5184
5185 case TGSI_OPCODE_DST:
5186 exec_dst(mach, inst);
5187 break;
5188
5189 case TGSI_OPCODE_MIN:
5190 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5191 break;
5192
5193 case TGSI_OPCODE_MAX:
5194 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5195 break;
5196
5197 case TGSI_OPCODE_SLT:
5198 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5199 break;
5200
5201 case TGSI_OPCODE_SGE:
5202 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5203 break;
5204
5205 case TGSI_OPCODE_MAD:
5206 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5207 break;
5208
5209 case TGSI_OPCODE_LRP:
5210 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5211 break;
5212
5213 case TGSI_OPCODE_SQRT:
5214 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5215 break;
5216
5217 case TGSI_OPCODE_DP2A:
5218 exec_dp2a(mach, inst);
5219 break;
5220
5221 case TGSI_OPCODE_FRC:
5222 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5223 break;
5224
5225 case TGSI_OPCODE_FLR:
5226 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5227 break;
5228
5229 case TGSI_OPCODE_ROUND:
5230 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5231 break;
5232
5233 case TGSI_OPCODE_EX2:
5234 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5235 break;
5236
5237 case TGSI_OPCODE_LG2:
5238 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5239 break;
5240
5241 case TGSI_OPCODE_POW:
5242 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5243 break;
5244
5245 case TGSI_OPCODE_XPD:
5246 exec_xpd(mach, inst);
5247 break;
5248
5249 case TGSI_OPCODE_DPH:
5250 exec_dph(mach, inst);
5251 break;
5252
5253 case TGSI_OPCODE_COS:
5254 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5255 break;
5256
5257 case TGSI_OPCODE_DDX:
5258 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5259 break;
5260
5261 case TGSI_OPCODE_DDY:
5262 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5263 break;
5264
5265 case TGSI_OPCODE_KILL:
5266 exec_kill (mach, inst);
5267 break;
5268
5269 case TGSI_OPCODE_KILL_IF:
5270 exec_kill_if (mach, inst);
5271 break;
5272
5273 case TGSI_OPCODE_PK2H:
5274 exec_pk2h(mach, inst);
5275 break;
5276
5277 case TGSI_OPCODE_PK2US:
5278 assert (0);
5279 break;
5280
5281 case TGSI_OPCODE_PK4B:
5282 assert (0);
5283 break;
5284
5285 case TGSI_OPCODE_PK4UB:
5286 assert (0);
5287 break;
5288
5289 case TGSI_OPCODE_SEQ:
5290 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5291 break;
5292
5293 case TGSI_OPCODE_SGT:
5294 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5295 break;
5296
5297 case TGSI_OPCODE_SIN:
5298 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5299 break;
5300
5301 case TGSI_OPCODE_SLE:
5302 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5303 break;
5304
5305 case TGSI_OPCODE_SNE:
5306 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5307 break;
5308
5309 case TGSI_OPCODE_TEX:
5310 /* simple texture lookup */
5311 /* src[0] = texcoord */
5312 /* src[1] = sampler unit */
5313 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
5314 break;
5315
5316 case TGSI_OPCODE_TXB:
5317 /* Texture lookup with lod bias */
5318 /* src[0] = texcoord (src[0].w = LOD bias) */
5319 /* src[1] = sampler unit */
5320 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
5321 break;
5322
5323 case TGSI_OPCODE_TXD:
5324 /* Texture lookup with explict partial derivatives */
5325 /* src[0] = texcoord */
5326 /* src[1] = d[strq]/dx */
5327 /* src[2] = d[strq]/dy */
5328 /* src[3] = sampler unit */
5329 exec_txd(mach, inst);
5330 break;
5331
5332 case TGSI_OPCODE_TXL:
5333 /* Texture lookup with explit LOD */
5334 /* src[0] = texcoord (src[0].w = LOD) */
5335 /* src[1] = sampler unit */
5336 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
5337 break;
5338
5339 case TGSI_OPCODE_TXP:
5340 /* Texture lookup with projection */
5341 /* src[0] = texcoord (src[0].w = projection) */
5342 /* src[1] = sampler unit */
5343 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
5344 break;
5345
5346 case TGSI_OPCODE_TG4:
5347 /* src[0] = texcoord */
5348 /* src[1] = component */
5349 /* src[2] = sampler unit */
5350 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
5351 break;
5352
5353 case TGSI_OPCODE_LODQ:
5354 /* src[0] = texcoord */
5355 /* src[1] = sampler unit */
5356 exec_lodq(mach, inst);
5357 break;
5358
5359 case TGSI_OPCODE_UP2H:
5360 exec_up2h(mach, inst);
5361 break;
5362
5363 case TGSI_OPCODE_UP2US:
5364 assert (0);
5365 break;
5366
5367 case TGSI_OPCODE_UP4B:
5368 assert (0);
5369 break;
5370
5371 case TGSI_OPCODE_UP4UB:
5372 assert (0);
5373 break;
5374
5375 case TGSI_OPCODE_ARR:
5376 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5377 break;
5378
5379 case TGSI_OPCODE_CAL:
5380 /* skip the call if no execution channels are enabled */
5381 if (mach->ExecMask) {
5382 /* do the call */
5383
5384 /* First, record the depths of the execution stacks.
5385 * This is important for deeply nested/looped return statements.
5386 * We have to unwind the stacks by the correct amount. For a
5387 * real code generator, we could determine the number of entries
5388 * to pop off each stack with simple static analysis and avoid
5389 * implementing this data structure at run time.
5390 */
5391 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
5392 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
5393 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
5394 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
5395 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
5396 /* note that PC was already incremented above */
5397 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
5398
5399 mach->CallStackTop++;
5400
5401 /* Second, push the Cond, Loop, Cont, Func stacks */
5402 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5403 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5404 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5405 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
5406 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5407 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
5408
5409 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5410 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5411 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5412 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
5413 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5414 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
5415
5416 /* Finally, jump to the subroutine. The label is a pointer
5417 * (an instruction number) to the BGNSUB instruction.
5418 */
5419 *pc = inst->Label.Label;
5420 assert(mach->Instructions[*pc].Instruction.Opcode
5421 == TGSI_OPCODE_BGNSUB);
5422 }
5423 break;
5424
5425 case TGSI_OPCODE_RET:
5426 mach->FuncMask &= ~mach->ExecMask;
5427 UPDATE_EXEC_MASK(mach);
5428
5429 if (mach->FuncMask == 0x0) {
5430 /* really return now (otherwise, keep executing */
5431
5432 if (mach->CallStackTop == 0) {
5433 /* returning from main() */
5434 mach->CondStackTop = 0;
5435 mach->LoopStackTop = 0;
5436 mach->ContStackTop = 0;
5437 mach->LoopLabelStackTop = 0;
5438 mach->SwitchStackTop = 0;
5439 mach->BreakStackTop = 0;
5440 *pc = -1;
5441 return FALSE;
5442 }
5443
5444 assert(mach->CallStackTop > 0);
5445 mach->CallStackTop--;
5446
5447 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5448 mach->CondMask = mach->CondStack[mach->CondStackTop];
5449
5450 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5451 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5452
5453 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5454 mach->ContMask = mach->ContStack[mach->ContStackTop];
5455
5456 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5457 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5458
5459 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5460 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5461
5462 assert(mach->FuncStackTop > 0);
5463 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5464
5465 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5466
5467 UPDATE_EXEC_MASK(mach);
5468 }
5469 break;
5470
5471 case TGSI_OPCODE_SSG:
5472 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5473 break;
5474
5475 case TGSI_OPCODE_CMP:
5476 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5477 break;
5478
5479 case TGSI_OPCODE_SCS:
5480 exec_scs(mach, inst);
5481 break;
5482
5483 case TGSI_OPCODE_DIV:
5484 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5485 break;
5486
5487 case TGSI_OPCODE_DP2:
5488 exec_dp2(mach, inst);
5489 break;
5490
5491 case TGSI_OPCODE_IF:
5492 /* push CondMask */
5493 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5494 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5495 FETCH( &r[0], 0, TGSI_CHAN_X );
5496 /* update CondMask */
5497 if( ! r[0].f[0] ) {
5498 mach->CondMask &= ~0x1;
5499 }
5500 if( ! r[0].f[1] ) {
5501 mach->CondMask &= ~0x2;
5502 }
5503 if( ! r[0].f[2] ) {
5504 mach->CondMask &= ~0x4;
5505 }
5506 if( ! r[0].f[3] ) {
5507 mach->CondMask &= ~0x8;
5508 }
5509 UPDATE_EXEC_MASK(mach);
5510 /* Todo: If CondMask==0, jump to ELSE */
5511 break;
5512
5513 case TGSI_OPCODE_UIF:
5514 /* push CondMask */
5515 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5516 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5517 IFETCH( &r[0], 0, TGSI_CHAN_X );
5518 /* update CondMask */
5519 if( ! r[0].u[0] ) {
5520 mach->CondMask &= ~0x1;
5521 }
5522 if( ! r[0].u[1] ) {
5523 mach->CondMask &= ~0x2;
5524 }
5525 if( ! r[0].u[2] ) {
5526 mach->CondMask &= ~0x4;
5527 }
5528 if( ! r[0].u[3] ) {
5529 mach->CondMask &= ~0x8;
5530 }
5531 UPDATE_EXEC_MASK(mach);
5532 /* Todo: If CondMask==0, jump to ELSE */
5533 break;
5534
5535 case TGSI_OPCODE_ELSE:
5536 /* invert CondMask wrt previous mask */
5537 {
5538 uint prevMask;
5539 assert(mach->CondStackTop > 0);
5540 prevMask = mach->CondStack[mach->CondStackTop - 1];
5541 mach->CondMask = ~mach->CondMask & prevMask;
5542 UPDATE_EXEC_MASK(mach);
5543 /* Todo: If CondMask==0, jump to ENDIF */
5544 }
5545 break;
5546
5547 case TGSI_OPCODE_ENDIF:
5548 /* pop CondMask */
5549 assert(mach->CondStackTop > 0);
5550 mach->CondMask = mach->CondStack[--mach->CondStackTop];
5551 UPDATE_EXEC_MASK(mach);
5552 break;
5553
5554 case TGSI_OPCODE_END:
5555 /* make sure we end primitives which haven't
5556 * been explicitly emitted */
5557 conditional_emit_primitive(mach);
5558 /* halt execution */
5559 *pc = -1;
5560 break;
5561
5562 case TGSI_OPCODE_PUSHA:
5563 assert (0);
5564 break;
5565
5566 case TGSI_OPCODE_POPA:
5567 assert (0);
5568 break;
5569
5570 case TGSI_OPCODE_CEIL:
5571 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5572 break;
5573
5574 case TGSI_OPCODE_I2F:
5575 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5576 break;
5577
5578 case TGSI_OPCODE_NOT:
5579 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5580 break;
5581
5582 case TGSI_OPCODE_TRUNC:
5583 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5584 break;
5585
5586 case TGSI_OPCODE_SHL:
5587 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5588 break;
5589
5590 case TGSI_OPCODE_AND:
5591 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5592 break;
5593
5594 case TGSI_OPCODE_OR:
5595 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5596 break;
5597
5598 case TGSI_OPCODE_MOD:
5599 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5600 break;
5601
5602 case TGSI_OPCODE_XOR:
5603 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5604 break;
5605
5606 case TGSI_OPCODE_SAD:
5607 assert (0);
5608 break;
5609
5610 case TGSI_OPCODE_TXF:
5611 exec_txf(mach, inst);
5612 break;
5613
5614 case TGSI_OPCODE_TXQ:
5615 exec_txq(mach, inst);
5616 break;
5617
5618 case TGSI_OPCODE_EMIT:
5619 emit_vertex(mach);
5620 break;
5621
5622 case TGSI_OPCODE_ENDPRIM:
5623 emit_primitive(mach);
5624 break;
5625
5626 case TGSI_OPCODE_BGNLOOP:
5627 /* push LoopMask and ContMasks */
5628 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5629 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5630 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5631 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5632
5633 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5634 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5635 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
5636 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5637 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
5638 break;
5639
5640 case TGSI_OPCODE_ENDLOOP:
5641 /* Restore ContMask, but don't pop */
5642 assert(mach->ContStackTop > 0);
5643 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
5644 UPDATE_EXEC_MASK(mach);
5645 if (mach->ExecMask) {
5646 /* repeat loop: jump to instruction just past BGNLOOP */
5647 assert(mach->LoopLabelStackTop > 0);
5648 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5649 }
5650 else {
5651 /* exit loop: pop LoopMask */
5652 assert(mach->LoopStackTop > 0);
5653 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5654 /* pop ContMask */
5655 assert(mach->ContStackTop > 0);
5656 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5657 assert(mach->LoopLabelStackTop > 0);
5658 --mach->LoopLabelStackTop;
5659
5660 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5661 }
5662 UPDATE_EXEC_MASK(mach);
5663 break;
5664
5665 case TGSI_OPCODE_BRK:
5666 exec_break(mach);
5667 break;
5668
5669 case TGSI_OPCODE_CONT:
5670 /* turn off cont channels for each enabled exec channel */
5671 mach->ContMask &= ~mach->ExecMask;
5672 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5673 UPDATE_EXEC_MASK(mach);
5674 break;
5675
5676 case TGSI_OPCODE_BGNSUB:
5677 /* no-op */
5678 break;
5679
5680 case TGSI_OPCODE_ENDSUB:
5681 /*
5682 * XXX: This really should be a no-op. We should never reach this opcode.
5683 */
5684
5685 assert(mach->CallStackTop > 0);
5686 mach->CallStackTop--;
5687
5688 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5689 mach->CondMask = mach->CondStack[mach->CondStackTop];
5690
5691 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5692 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5693
5694 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5695 mach->ContMask = mach->ContStack[mach->ContStackTop];
5696
5697 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5698 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5699
5700 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5701 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5702
5703 assert(mach->FuncStackTop > 0);
5704 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5705
5706 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5707
5708 UPDATE_EXEC_MASK(mach);
5709 break;
5710
5711 case TGSI_OPCODE_NOP:
5712 break;
5713
5714 case TGSI_OPCODE_BREAKC:
5715 IFETCH(&r[0], 0, TGSI_CHAN_X);
5716 /* update CondMask */
5717 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
5718 mach->LoopMask &= ~0x1;
5719 }
5720 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
5721 mach->LoopMask &= ~0x2;
5722 }
5723 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
5724 mach->LoopMask &= ~0x4;
5725 }
5726 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
5727 mach->LoopMask &= ~0x8;
5728 }
5729 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5730 UPDATE_EXEC_MASK(mach);
5731 break;
5732
5733 case TGSI_OPCODE_F2I:
5734 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5735 break;
5736
5737 case TGSI_OPCODE_FSEQ:
5738 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5739 break;
5740
5741 case TGSI_OPCODE_FSGE:
5742 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5743 break;
5744
5745 case TGSI_OPCODE_FSLT:
5746 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5747 break;
5748
5749 case TGSI_OPCODE_FSNE:
5750 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5751 break;
5752
5753 case TGSI_OPCODE_IDIV:
5754 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5755 break;
5756
5757 case TGSI_OPCODE_IMAX:
5758 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5759 break;
5760
5761 case TGSI_OPCODE_IMIN:
5762 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5763 break;
5764
5765 case TGSI_OPCODE_INEG:
5766 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5767 break;
5768
5769 case TGSI_OPCODE_ISGE:
5770 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5771 break;
5772
5773 case TGSI_OPCODE_ISHR:
5774 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5775 break;
5776
5777 case TGSI_OPCODE_ISLT:
5778 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5779 break;
5780
5781 case TGSI_OPCODE_F2U:
5782 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5783 break;
5784
5785 case TGSI_OPCODE_U2F:
5786 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5787 break;
5788
5789 case TGSI_OPCODE_UADD:
5790 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5791 break;
5792
5793 case TGSI_OPCODE_UDIV:
5794 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5795 break;
5796
5797 case TGSI_OPCODE_UMAD:
5798 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5799 break;
5800
5801 case TGSI_OPCODE_UMAX:
5802 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5803 break;
5804
5805 case TGSI_OPCODE_UMIN:
5806 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5807 break;
5808
5809 case TGSI_OPCODE_UMOD:
5810 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5811 break;
5812
5813 case TGSI_OPCODE_UMUL:
5814 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5815 break;
5816
5817 case TGSI_OPCODE_IMUL_HI:
5818 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5819 break;
5820
5821 case TGSI_OPCODE_UMUL_HI:
5822 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5823 break;
5824
5825 case TGSI_OPCODE_USEQ:
5826 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5827 break;
5828
5829 case TGSI_OPCODE_USGE:
5830 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5831 break;
5832
5833 case TGSI_OPCODE_USHR:
5834 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5835 break;
5836
5837 case TGSI_OPCODE_USLT:
5838 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5839 break;
5840
5841 case TGSI_OPCODE_USNE:
5842 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5843 break;
5844
5845 case TGSI_OPCODE_SWITCH:
5846 exec_switch(mach, inst);
5847 break;
5848
5849 case TGSI_OPCODE_CASE:
5850 exec_case(mach, inst);
5851 break;
5852
5853 case TGSI_OPCODE_DEFAULT:
5854 exec_default(mach);
5855 break;
5856
5857 case TGSI_OPCODE_ENDSWITCH:
5858 exec_endswitch(mach);
5859 break;
5860
5861 case TGSI_OPCODE_SAMPLE_I:
5862 exec_txf(mach, inst);
5863 break;
5864
5865 case TGSI_OPCODE_SAMPLE_I_MS:
5866 exec_txf(mach, inst);
5867 break;
5868
5869 case TGSI_OPCODE_SAMPLE:
5870 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5871 break;
5872
5873 case TGSI_OPCODE_SAMPLE_B:
5874 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5875 break;
5876
5877 case TGSI_OPCODE_SAMPLE_C:
5878 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5879 break;
5880
5881 case TGSI_OPCODE_SAMPLE_C_LZ:
5882 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5883 break;
5884
5885 case TGSI_OPCODE_SAMPLE_D:
5886 exec_sample_d(mach, inst);
5887 break;
5888
5889 case TGSI_OPCODE_SAMPLE_L:
5890 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5891 break;
5892
5893 case TGSI_OPCODE_GATHER4:
5894 assert(0);
5895 break;
5896
5897 case TGSI_OPCODE_SVIEWINFO:
5898 exec_txq(mach, inst);
5899 break;
5900
5901 case TGSI_OPCODE_SAMPLE_POS:
5902 assert(0);
5903 break;
5904
5905 case TGSI_OPCODE_SAMPLE_INFO:
5906 assert(0);
5907 break;
5908
5909 case TGSI_OPCODE_UARL:
5910 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5911 break;
5912
5913 case TGSI_OPCODE_UCMP:
5914 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5915 break;
5916
5917 case TGSI_OPCODE_IABS:
5918 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5919 break;
5920
5921 case TGSI_OPCODE_ISSG:
5922 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5923 break;
5924
5925 case TGSI_OPCODE_TEX2:
5926 /* simple texture lookup */
5927 /* src[0] = texcoord */
5928 /* src[1] = compare */
5929 /* src[2] = sampler unit */
5930 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5931 break;
5932 case TGSI_OPCODE_TXB2:
5933 /* simple texture lookup */
5934 /* src[0] = texcoord */
5935 /* src[1] = bias */
5936 /* src[2] = sampler unit */
5937 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5938 break;
5939 case TGSI_OPCODE_TXL2:
5940 /* simple texture lookup */
5941 /* src[0] = texcoord */
5942 /* src[1] = lod */
5943 /* src[2] = sampler unit */
5944 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5945 break;
5946
5947 case TGSI_OPCODE_IBFE:
5948 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5949 break;
5950 case TGSI_OPCODE_UBFE:
5951 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5952 break;
5953 case TGSI_OPCODE_BFI:
5954 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5955 break;
5956 case TGSI_OPCODE_BREV:
5957 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5958 break;
5959 case TGSI_OPCODE_POPC:
5960 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5961 break;
5962 case TGSI_OPCODE_LSB:
5963 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5964 break;
5965 case TGSI_OPCODE_IMSB:
5966 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5967 break;
5968 case TGSI_OPCODE_UMSB:
5969 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5970 break;
5971
5972 case TGSI_OPCODE_F2D:
5973 exec_t_2_64(mach, inst, micro_f2d, TGSI_EXEC_DATA_FLOAT);
5974 break;
5975
5976 case TGSI_OPCODE_D2F:
5977 exec_64_2_t(mach, inst, micro_d2f, TGSI_EXEC_DATA_FLOAT);
5978 break;
5979
5980 case TGSI_OPCODE_DABS:
5981 exec_double_unary(mach, inst, micro_dabs);
5982 break;
5983
5984 case TGSI_OPCODE_DNEG:
5985 exec_double_unary(mach, inst, micro_dneg);
5986 break;
5987
5988 case TGSI_OPCODE_DADD:
5989 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5990 break;
5991
5992 case TGSI_OPCODE_DDIV:
5993 exec_double_binary(mach, inst, micro_ddiv, TGSI_EXEC_DATA_DOUBLE);
5994 break;
5995
5996 case TGSI_OPCODE_DMUL:
5997 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5998 break;
5999
6000 case TGSI_OPCODE_DMAX:
6001 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
6002 break;
6003
6004 case TGSI_OPCODE_DMIN:
6005 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
6006 break;
6007
6008 case TGSI_OPCODE_DSLT:
6009 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
6010 break;
6011
6012 case TGSI_OPCODE_DSGE:
6013 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
6014 break;
6015
6016 case TGSI_OPCODE_DSEQ:
6017 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
6018 break;
6019
6020 case TGSI_OPCODE_DSNE:
6021 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
6022 break;
6023
6024 case TGSI_OPCODE_DRCP:
6025 exec_double_unary(mach, inst, micro_drcp);
6026 break;
6027
6028 case TGSI_OPCODE_DSQRT:
6029 exec_double_unary(mach, inst, micro_dsqrt);
6030 break;
6031
6032 case TGSI_OPCODE_DRSQ:
6033 exec_double_unary(mach, inst, micro_drsq);
6034 break;
6035
6036 case TGSI_OPCODE_DMAD:
6037 exec_double_trinary(mach, inst, micro_dmad);
6038 break;
6039
6040 case TGSI_OPCODE_DFRAC:
6041 exec_double_unary(mach, inst, micro_dfrac);
6042 break;
6043
6044 case TGSI_OPCODE_DLDEXP:
6045 exec_dldexp(mach, inst);
6046 break;
6047
6048 case TGSI_OPCODE_DFRACEXP:
6049 exec_dfracexp(mach, inst);
6050 break;
6051
6052 case TGSI_OPCODE_I2D:
6053 exec_t_2_64(mach, inst, micro_i2d, TGSI_EXEC_DATA_INT);
6054 break;
6055
6056 case TGSI_OPCODE_D2I:
6057 exec_64_2_t(mach, inst, micro_d2i, TGSI_EXEC_DATA_INT);
6058 break;
6059
6060 case TGSI_OPCODE_U2D:
6061 exec_t_2_64(mach, inst, micro_u2d, TGSI_EXEC_DATA_UINT);
6062 break;
6063
6064 case TGSI_OPCODE_D2U:
6065 exec_64_2_t(mach, inst, micro_d2u, TGSI_EXEC_DATA_INT);
6066 break;
6067
6068 case TGSI_OPCODE_LOAD:
6069 exec_load(mach, inst);
6070 break;
6071
6072 case TGSI_OPCODE_STORE:
6073 exec_store(mach, inst);
6074 break;
6075
6076 case TGSI_OPCODE_ATOMUADD:
6077 case TGSI_OPCODE_ATOMXCHG:
6078 case TGSI_OPCODE_ATOMCAS:
6079 case TGSI_OPCODE_ATOMAND:
6080 case TGSI_OPCODE_ATOMOR:
6081 case TGSI_OPCODE_ATOMXOR:
6082 case TGSI_OPCODE_ATOMUMIN:
6083 case TGSI_OPCODE_ATOMUMAX:
6084 case TGSI_OPCODE_ATOMIMIN:
6085 case TGSI_OPCODE_ATOMIMAX:
6086 exec_atomop(mach, inst);
6087 break;
6088
6089 case TGSI_OPCODE_RESQ:
6090 exec_resq(mach, inst);
6091 break;
6092 case TGSI_OPCODE_BARRIER:
6093 case TGSI_OPCODE_MEMBAR:
6094 return TRUE;
6095 break;
6096
6097 case TGSI_OPCODE_I64ABS:
6098 exec_double_unary(mach, inst, micro_i64abs);
6099 break;
6100
6101 case TGSI_OPCODE_I64SSG:
6102 exec_double_unary(mach, inst, micro_i64sgn);
6103 break;
6104
6105 case TGSI_OPCODE_I64NEG:
6106 exec_double_unary(mach, inst, micro_i64neg);
6107 break;
6108
6109 case TGSI_OPCODE_U64SEQ:
6110 exec_double_binary(mach, inst, micro_u64seq, TGSI_EXEC_DATA_UINT);
6111 break;
6112
6113 case TGSI_OPCODE_U64SNE:
6114 exec_double_binary(mach, inst, micro_u64sne, TGSI_EXEC_DATA_UINT);
6115 break;
6116
6117 case TGSI_OPCODE_I64SLT:
6118 exec_double_binary(mach, inst, micro_i64slt, TGSI_EXEC_DATA_UINT);
6119 break;
6120 case TGSI_OPCODE_U64SLT:
6121 exec_double_binary(mach, inst, micro_u64slt, TGSI_EXEC_DATA_UINT);
6122 break;
6123
6124 case TGSI_OPCODE_I64SGE:
6125 exec_double_binary(mach, inst, micro_i64sge, TGSI_EXEC_DATA_UINT);
6126 break;
6127 case TGSI_OPCODE_U64SGE:
6128 exec_double_binary(mach, inst, micro_u64sge, TGSI_EXEC_DATA_UINT);
6129 break;
6130
6131 case TGSI_OPCODE_I64MIN:
6132 exec_double_binary(mach, inst, micro_i64min, TGSI_EXEC_DATA_INT64);
6133 break;
6134 case TGSI_OPCODE_U64MIN:
6135 exec_double_binary(mach, inst, micro_u64min, TGSI_EXEC_DATA_UINT64);
6136 break;
6137 case TGSI_OPCODE_I64MAX:
6138 exec_double_binary(mach, inst, micro_i64max, TGSI_EXEC_DATA_INT64);
6139 break;
6140 case TGSI_OPCODE_U64MAX:
6141 exec_double_binary(mach, inst, micro_u64max, TGSI_EXEC_DATA_UINT64);
6142 break;
6143 case TGSI_OPCODE_U64ADD:
6144 exec_double_binary(mach, inst, micro_u64add, TGSI_EXEC_DATA_UINT64);
6145 break;
6146 case TGSI_OPCODE_U64MUL:
6147 exec_double_binary(mach, inst, micro_u64mul, TGSI_EXEC_DATA_UINT64);
6148 break;
6149 case TGSI_OPCODE_U64SHL:
6150 exec_arg0_64_arg1_32(mach, inst, micro_u64shl);
6151 break;
6152 case TGSI_OPCODE_I64SHR:
6153 exec_arg0_64_arg1_32(mach, inst, micro_i64shr);
6154 break;
6155 case TGSI_OPCODE_U64SHR:
6156 exec_arg0_64_arg1_32(mach, inst, micro_u64shr);
6157 break;
6158 case TGSI_OPCODE_U64DIV:
6159 exec_double_binary(mach, inst, micro_u64div, TGSI_EXEC_DATA_UINT64);
6160 break;
6161 case TGSI_OPCODE_I64DIV:
6162 exec_double_binary(mach, inst, micro_i64div, TGSI_EXEC_DATA_INT64);
6163 break;
6164 case TGSI_OPCODE_U64MOD:
6165 exec_double_binary(mach, inst, micro_u64mod, TGSI_EXEC_DATA_UINT64);
6166 break;
6167 case TGSI_OPCODE_I64MOD:
6168 exec_double_binary(mach, inst, micro_i64mod, TGSI_EXEC_DATA_INT64);
6169 break;
6170
6171 case TGSI_OPCODE_F2U64:
6172 exec_t_2_64(mach, inst, micro_f2u64, TGSI_EXEC_DATA_FLOAT);
6173 break;
6174
6175 case TGSI_OPCODE_F2I64:
6176 exec_t_2_64(mach, inst, micro_f2i64, TGSI_EXEC_DATA_FLOAT);
6177 break;
6178
6179 case TGSI_OPCODE_U2I64:
6180 exec_t_2_64(mach, inst, micro_u2i64, TGSI_EXEC_DATA_INT);
6181 break;
6182 case TGSI_OPCODE_I2I64:
6183 exec_t_2_64(mach, inst, micro_i2i64, TGSI_EXEC_DATA_INT);
6184 break;
6185
6186 case TGSI_OPCODE_D2U64:
6187 exec_double_unary(mach, inst, micro_d2u64);
6188 break;
6189
6190 case TGSI_OPCODE_D2I64:
6191 exec_double_unary(mach, inst, micro_d2i64);
6192 break;
6193
6194 case TGSI_OPCODE_U642F:
6195 exec_64_2_t(mach, inst, micro_u642f, TGSI_EXEC_DATA_FLOAT);
6196 break;
6197 case TGSI_OPCODE_I642F:
6198 exec_64_2_t(mach, inst, micro_i642f, TGSI_EXEC_DATA_FLOAT);
6199 break;
6200
6201 case TGSI_OPCODE_U642D:
6202 exec_double_unary(mach, inst, micro_u642d);
6203 break;
6204 case TGSI_OPCODE_I642D:
6205 exec_double_unary(mach, inst, micro_i642d);
6206 break;
6207
6208 default:
6209 assert( 0 );
6210 }
6211 return FALSE;
6212 }
6213
6214 static void
6215 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine *mach)
6216 {
6217 uint default_mask = 0xf;
6218
6219 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
6220 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
6221
6222 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
6223 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
6224 mach->Primitives[0] = 0;
6225 /* GS runs on a single primitive for now */
6226 default_mask = 0x1;
6227 }
6228
6229 if (mach->NonHelperMask == 0)
6230 mach->NonHelperMask = default_mask;
6231 mach->CondMask = default_mask;
6232 mach->LoopMask = default_mask;
6233 mach->ContMask = default_mask;
6234 mach->FuncMask = default_mask;
6235 mach->ExecMask = default_mask;
6236
6237 mach->Switch.mask = default_mask;
6238
6239 assert(mach->CondStackTop == 0);
6240 assert(mach->LoopStackTop == 0);
6241 assert(mach->ContStackTop == 0);
6242 assert(mach->SwitchStackTop == 0);
6243 assert(mach->BreakStackTop == 0);
6244 assert(mach->CallStackTop == 0);
6245 }
6246
6247 /**
6248 * Run TGSI interpreter.
6249 * \return bitmask of "alive" quad components
6250 */
6251 uint
6252 tgsi_exec_machine_run( struct tgsi_exec_machine *mach, int start_pc )
6253 {
6254 uint i;
6255
6256 mach->pc = start_pc;
6257
6258 if (!start_pc) {
6259 tgsi_exec_machine_setup_masks(mach);
6260
6261 /* execute declarations (interpolants) */
6262 for (i = 0; i < mach->NumDeclarations; i++) {
6263 exec_declaration( mach, mach->Declarations+i );
6264 }
6265 }
6266
6267 {
6268 #if DEBUG_EXECUTION
6269 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
6270 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
6271 uint inst = 1;
6272
6273 if (!start_pc) {
6274 memset(mach->Temps, 0, sizeof(temps));
6275 if (mach->Outputs)
6276 memset(mach->Outputs, 0, sizeof(outputs));
6277 memset(temps, 0, sizeof(temps));
6278 memset(outputs, 0, sizeof(outputs));
6279 }
6280 #endif
6281
6282 /* execute instructions, until pc is set to -1 */
6283 while (mach->pc != -1) {
6284 boolean barrier_hit;
6285 #if DEBUG_EXECUTION
6286 uint i;
6287
6288 tgsi_dump_instruction(&mach->Instructions[mach->pc], inst++);
6289 #endif
6290
6291 assert(mach->pc < (int) mach->NumInstructions);
6292 barrier_hit = exec_instruction(mach, mach->Instructions + mach->pc, &mach->pc);
6293
6294 /* for compute shaders if we hit a barrier return now for later rescheduling */
6295 if (barrier_hit && mach->ShaderType == PIPE_SHADER_COMPUTE)
6296 return 0;
6297
6298 #if DEBUG_EXECUTION
6299 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
6300 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
6301 uint j;
6302
6303 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
6304 debug_printf("TEMP[%2u] = ", i);
6305 for (j = 0; j < 4; j++) {
6306 if (j > 0) {
6307 debug_printf(" ");
6308 }
6309 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6310 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
6311 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
6312 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
6313 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
6314 }
6315 }
6316 }
6317 if (mach->Outputs) {
6318 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
6319 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
6320 uint j;
6321
6322 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
6323 debug_printf("OUT[%2u] = ", i);
6324 for (j = 0; j < 4; j++) {
6325 if (j > 0) {
6326 debug_printf(" ");
6327 }
6328 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6329 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
6330 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
6331 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
6332 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
6333 }
6334 }
6335 }
6336 }
6337 #endif
6338 }
6339 }
6340
6341 #if 0
6342 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6343 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
6344 /*
6345 * Scale back depth component.
6346 */
6347 for (i = 0; i < 4; i++)
6348 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
6349 }
6350 #endif
6351
6352 /* Strictly speaking, these assertions aren't really needed but they
6353 * can potentially catch some bugs in the control flow code.
6354 */
6355 assert(mach->CondStackTop == 0);
6356 assert(mach->LoopStackTop == 0);
6357 assert(mach->ContStackTop == 0);
6358 assert(mach->SwitchStackTop == 0);
6359 assert(mach->BreakStackTop == 0);
6360 assert(mach->CallStackTop == 0);
6361
6362 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
6363 }