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tgsi: Allow TXF from buffers.
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 0
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
349 {
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
354 }
355
356 static void
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
360 {
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
365 }
366
367 static void
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
370 {
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_isgn(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src)
380 {
381 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
382 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
383 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
384 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
385 }
386
387 static void
388 micro_sgt(union tgsi_exec_channel *dst,
389 const union tgsi_exec_channel *src0,
390 const union tgsi_exec_channel *src1)
391 {
392 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
393 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
394 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
395 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
396 }
397
398 static void
399 micro_sin(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src)
401 {
402 dst->f[0] = sinf(src->f[0]);
403 dst->f[1] = sinf(src->f[1]);
404 dst->f[2] = sinf(src->f[2]);
405 dst->f[3] = sinf(src->f[3]);
406 }
407
408 static void
409 micro_sle(union tgsi_exec_channel *dst,
410 const union tgsi_exec_channel *src0,
411 const union tgsi_exec_channel *src1)
412 {
413 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
414 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
415 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
416 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
417 }
418
419 static void
420 micro_slt(union tgsi_exec_channel *dst,
421 const union tgsi_exec_channel *src0,
422 const union tgsi_exec_channel *src1)
423 {
424 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
425 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
426 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
427 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
428 }
429
430 static void
431 micro_sne(union tgsi_exec_channel *dst,
432 const union tgsi_exec_channel *src0,
433 const union tgsi_exec_channel *src1)
434 {
435 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
436 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
437 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
438 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
439 }
440
441 static void
442 micro_sfl(union tgsi_exec_channel *dst)
443 {
444 dst->f[0] = 0.0f;
445 dst->f[1] = 0.0f;
446 dst->f[2] = 0.0f;
447 dst->f[3] = 0.0f;
448 }
449
450 static void
451 micro_str(union tgsi_exec_channel *dst)
452 {
453 dst->f[0] = 1.0f;
454 dst->f[1] = 1.0f;
455 dst->f[2] = 1.0f;
456 dst->f[3] = 1.0f;
457 }
458
459 static void
460 micro_trunc(union tgsi_exec_channel *dst,
461 const union tgsi_exec_channel *src)
462 {
463 dst->f[0] = (float)(int)src->f[0];
464 dst->f[1] = (float)(int)src->f[1];
465 dst->f[2] = (float)(int)src->f[2];
466 dst->f[3] = (float)(int)src->f[3];
467 }
468
469
470 enum tgsi_exec_datatype {
471 TGSI_EXEC_DATA_FLOAT,
472 TGSI_EXEC_DATA_INT,
473 TGSI_EXEC_DATA_UINT
474 };
475
476 /*
477 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
478 */
479 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
480 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
481 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
482 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
483 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
484 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
485
486
487 /** The execution mask depends on the conditional mask and the loop mask */
488 #define UPDATE_EXEC_MASK(MACH) \
489 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
490
491
492 static const union tgsi_exec_channel ZeroVec =
493 { { 0.0, 0.0, 0.0, 0.0 } };
494
495 static const union tgsi_exec_channel OneVec = {
496 {1.0f, 1.0f, 1.0f, 1.0f}
497 };
498
499 static const union tgsi_exec_channel P128Vec = {
500 {128.0f, 128.0f, 128.0f, 128.0f}
501 };
502
503 static const union tgsi_exec_channel M128Vec = {
504 {-128.0f, -128.0f, -128.0f, -128.0f}
505 };
506
507
508 /**
509 * Assert that none of the float values in 'chan' are infinite or NaN.
510 * NaN and Inf may occur normally during program execution and should
511 * not lead to crashes, etc. But when debugging, it's helpful to catch
512 * them.
513 */
514 static INLINE void
515 check_inf_or_nan(const union tgsi_exec_channel *chan)
516 {
517 assert(!util_is_inf_or_nan((chan)->f[0]));
518 assert(!util_is_inf_or_nan((chan)->f[1]));
519 assert(!util_is_inf_or_nan((chan)->f[2]));
520 assert(!util_is_inf_or_nan((chan)->f[3]));
521 }
522
523
524 #ifdef DEBUG
525 static void
526 print_chan(const char *msg, const union tgsi_exec_channel *chan)
527 {
528 debug_printf("%s = {%f, %f, %f, %f}\n",
529 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
530 }
531 #endif
532
533
534 #ifdef DEBUG
535 static void
536 print_temp(const struct tgsi_exec_machine *mach, uint index)
537 {
538 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
539 int i;
540 debug_printf("Temp[%u] =\n", index);
541 for (i = 0; i < 4; i++) {
542 debug_printf(" %c: { %f, %f, %f, %f }\n",
543 "XYZW"[i],
544 tmp->xyzw[i].f[0],
545 tmp->xyzw[i].f[1],
546 tmp->xyzw[i].f[2],
547 tmp->xyzw[i].f[3]);
548 }
549 }
550 #endif
551
552
553 void
554 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
555 unsigned num_bufs,
556 const void **bufs,
557 const unsigned *buf_sizes)
558 {
559 unsigned i;
560
561 for (i = 0; i < num_bufs; i++) {
562 mach->Consts[i] = bufs[i];
563 mach->ConstsSize[i] = buf_sizes[i];
564 }
565 }
566
567
568 /**
569 * Check if there's a potential src/dst register data dependency when
570 * using SOA execution.
571 * Example:
572 * MOV T, T.yxwz;
573 * This would expand into:
574 * MOV t0, t1;
575 * MOV t1, t0;
576 * MOV t2, t3;
577 * MOV t3, t2;
578 * The second instruction will have the wrong value for t0 if executed as-is.
579 */
580 boolean
581 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
582 {
583 uint i, chan;
584
585 uint writemask = inst->Dst[0].Register.WriteMask;
586 if (writemask == TGSI_WRITEMASK_X ||
587 writemask == TGSI_WRITEMASK_Y ||
588 writemask == TGSI_WRITEMASK_Z ||
589 writemask == TGSI_WRITEMASK_W ||
590 writemask == TGSI_WRITEMASK_NONE) {
591 /* no chance of data dependency */
592 return FALSE;
593 }
594
595 /* loop over src regs */
596 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
597 if ((inst->Src[i].Register.File ==
598 inst->Dst[0].Register.File) &&
599 ((inst->Src[i].Register.Index ==
600 inst->Dst[0].Register.Index) ||
601 inst->Src[i].Register.Indirect ||
602 inst->Dst[0].Register.Indirect)) {
603 /* loop over dest channels */
604 uint channelsWritten = 0x0;
605 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
607 /* check if we're reading a channel that's been written */
608 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
609 if (channelsWritten & (1 << swizzle)) {
610 return TRUE;
611 }
612
613 channelsWritten |= (1 << chan);
614 }
615 }
616 }
617 }
618 return FALSE;
619 }
620
621
622 /**
623 * Initialize machine state by expanding tokens to full instructions,
624 * allocating temporary storage, setting up constants, etc.
625 * After this, we can call tgsi_exec_machine_run() many times.
626 */
627 void
628 tgsi_exec_machine_bind_shader(
629 struct tgsi_exec_machine *mach,
630 const struct tgsi_token *tokens,
631 uint numSamplers,
632 struct tgsi_sampler **samplers)
633 {
634 uint k;
635 struct tgsi_parse_context parse;
636 struct tgsi_full_instruction *instructions;
637 struct tgsi_full_declaration *declarations;
638 uint maxInstructions = 10, numInstructions = 0;
639 uint maxDeclarations = 10, numDeclarations = 0;
640
641 #if 0
642 tgsi_dump(tokens, 0);
643 #endif
644
645 util_init_math();
646
647 if (numSamplers) {
648 assert(samplers);
649 }
650
651 mach->Tokens = tokens;
652 mach->Samplers = samplers;
653
654 if (!tokens) {
655 /* unbind and free all */
656 FREE(mach->Declarations);
657 mach->Declarations = NULL;
658 mach->NumDeclarations = 0;
659
660 FREE(mach->Instructions);
661 mach->Instructions = NULL;
662 mach->NumInstructions = 0;
663
664 return;
665 }
666
667 k = tgsi_parse_init (&parse, mach->Tokens);
668 if (k != TGSI_PARSE_OK) {
669 debug_printf( "Problem parsing!\n" );
670 return;
671 }
672
673 mach->Processor = parse.FullHeader.Processor.Processor;
674 mach->ImmLimit = 0;
675
676 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
677 !mach->UsedGeometryShader) {
678 struct tgsi_exec_vector *inputs;
679 struct tgsi_exec_vector *outputs;
680
681 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
682 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
683 16);
684
685 if (!inputs)
686 return;
687
688 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
689 TGSI_MAX_TOTAL_VERTICES, 16);
690
691 if (!outputs) {
692 align_free(inputs);
693 return;
694 }
695
696 align_free(mach->Inputs);
697 align_free(mach->Outputs);
698
699 mach->Inputs = inputs;
700 mach->Outputs = outputs;
701 mach->UsedGeometryShader = TRUE;
702 }
703
704 declarations = (struct tgsi_full_declaration *)
705 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
706
707 if (!declarations) {
708 return;
709 }
710
711 instructions = (struct tgsi_full_instruction *)
712 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
713
714 if (!instructions) {
715 FREE( declarations );
716 return;
717 }
718
719 while( !tgsi_parse_end_of_tokens( &parse ) ) {
720 uint i;
721
722 tgsi_parse_token( &parse );
723 switch( parse.FullToken.Token.Type ) {
724 case TGSI_TOKEN_TYPE_DECLARATION:
725 /* save expanded declaration */
726 if (numDeclarations == maxDeclarations) {
727 declarations = REALLOC(declarations,
728 maxDeclarations
729 * sizeof(struct tgsi_full_declaration),
730 (maxDeclarations + 10)
731 * sizeof(struct tgsi_full_declaration));
732 maxDeclarations += 10;
733 }
734 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
735 unsigned reg;
736 for (reg = parse.FullToken.FullDeclaration.Range.First;
737 reg <= parse.FullToken.FullDeclaration.Range.Last;
738 ++reg) {
739 ++mach->NumOutputs;
740 }
741 }
742 if (parse.FullToken.FullDeclaration.Declaration.File ==
743 TGSI_FILE_IMMEDIATE_ARRAY) {
744 unsigned reg;
745 struct tgsi_full_declaration *decl =
746 &parse.FullToken.FullDeclaration;
747 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
748 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
749 for( i = 0; i < 4; i++ ) {
750 int idx = reg * 4 + i;
751 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
752 }
753 }
754 }
755 memcpy(declarations + numDeclarations,
756 &parse.FullToken.FullDeclaration,
757 sizeof(declarations[0]));
758 numDeclarations++;
759 break;
760
761 case TGSI_TOKEN_TYPE_IMMEDIATE:
762 {
763 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
764 assert( size <= 4 );
765 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
766
767 for( i = 0; i < size; i++ ) {
768 mach->Imms[mach->ImmLimit][i] =
769 parse.FullToken.FullImmediate.u[i].Float;
770 }
771 mach->ImmLimit += 1;
772 }
773 break;
774
775 case TGSI_TOKEN_TYPE_INSTRUCTION:
776
777 /* save expanded instruction */
778 if (numInstructions == maxInstructions) {
779 instructions = REALLOC(instructions,
780 maxInstructions
781 * sizeof(struct tgsi_full_instruction),
782 (maxInstructions + 10)
783 * sizeof(struct tgsi_full_instruction));
784 maxInstructions += 10;
785 }
786
787 memcpy(instructions + numInstructions,
788 &parse.FullToken.FullInstruction,
789 sizeof(instructions[0]));
790
791 numInstructions++;
792 break;
793
794 case TGSI_TOKEN_TYPE_PROPERTY:
795 break;
796
797 default:
798 assert( 0 );
799 }
800 }
801 tgsi_parse_free (&parse);
802
803 FREE(mach->Declarations);
804 mach->Declarations = declarations;
805 mach->NumDeclarations = numDeclarations;
806
807 FREE(mach->Instructions);
808 mach->Instructions = instructions;
809 mach->NumInstructions = numInstructions;
810 }
811
812
813 struct tgsi_exec_machine *
814 tgsi_exec_machine_create( void )
815 {
816 struct tgsi_exec_machine *mach;
817 uint i;
818
819 mach = align_malloc( sizeof *mach, 16 );
820 if (!mach)
821 goto fail;
822
823 memset(mach, 0, sizeof(*mach));
824
825 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
826 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
827 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
828
829 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
830 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
831 if (!mach->Inputs || !mach->Outputs)
832 goto fail;
833
834 /* Setup constants needed by the SSE2 executor. */
835 for( i = 0; i < 4; i++ ) {
836 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
837 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
838 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
839 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
840 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
841 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
842 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
843 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
844 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
845 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
846 }
847
848 #ifdef DEBUG
849 /* silence warnings */
850 (void) print_chan;
851 (void) print_temp;
852 #endif
853
854 return mach;
855
856 fail:
857 if (mach) {
858 align_free(mach->Inputs);
859 align_free(mach->Outputs);
860 align_free(mach);
861 }
862 return NULL;
863 }
864
865
866 void
867 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
868 {
869 if (mach) {
870 FREE(mach->Instructions);
871 FREE(mach->Declarations);
872
873 align_free(mach->Inputs);
874 align_free(mach->Outputs);
875
876 align_free(mach);
877 }
878 }
879
880 static void
881 micro_add(union tgsi_exec_channel *dst,
882 const union tgsi_exec_channel *src0,
883 const union tgsi_exec_channel *src1)
884 {
885 dst->f[0] = src0->f[0] + src1->f[0];
886 dst->f[1] = src0->f[1] + src1->f[1];
887 dst->f[2] = src0->f[2] + src1->f[2];
888 dst->f[3] = src0->f[3] + src1->f[3];
889 }
890
891 static void
892 micro_div(
893 union tgsi_exec_channel *dst,
894 const union tgsi_exec_channel *src0,
895 const union tgsi_exec_channel *src1 )
896 {
897 if (src1->f[0] != 0) {
898 dst->f[0] = src0->f[0] / src1->f[0];
899 }
900 if (src1->f[1] != 0) {
901 dst->f[1] = src0->f[1] / src1->f[1];
902 }
903 if (src1->f[2] != 0) {
904 dst->f[2] = src0->f[2] / src1->f[2];
905 }
906 if (src1->f[3] != 0) {
907 dst->f[3] = src0->f[3] / src1->f[3];
908 }
909 }
910
911 static void
912 micro_rcc(union tgsi_exec_channel *dst,
913 const union tgsi_exec_channel *src)
914 {
915 uint i;
916
917 for (i = 0; i < 4; i++) {
918 float recip = 1.0f / src->f[i];
919
920 if (recip > 0.0f) {
921 if (recip > 1.884467e+019f) {
922 dst->f[i] = 1.884467e+019f;
923 }
924 else if (recip < 5.42101e-020f) {
925 dst->f[i] = 5.42101e-020f;
926 }
927 else {
928 dst->f[i] = recip;
929 }
930 }
931 else {
932 if (recip < -1.884467e+019f) {
933 dst->f[i] = -1.884467e+019f;
934 }
935 else if (recip > -5.42101e-020f) {
936 dst->f[i] = -5.42101e-020f;
937 }
938 else {
939 dst->f[i] = recip;
940 }
941 }
942 }
943 }
944
945 static void
946 micro_lt(
947 union tgsi_exec_channel *dst,
948 const union tgsi_exec_channel *src0,
949 const union tgsi_exec_channel *src1,
950 const union tgsi_exec_channel *src2,
951 const union tgsi_exec_channel *src3 )
952 {
953 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
954 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
955 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
956 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
957 }
958
959 static void
960 micro_max(union tgsi_exec_channel *dst,
961 const union tgsi_exec_channel *src0,
962 const union tgsi_exec_channel *src1)
963 {
964 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
965 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
966 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
967 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
968 }
969
970 static void
971 micro_min(union tgsi_exec_channel *dst,
972 const union tgsi_exec_channel *src0,
973 const union tgsi_exec_channel *src1)
974 {
975 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
976 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
977 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
978 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
979 }
980
981 static void
982 micro_mul(union tgsi_exec_channel *dst,
983 const union tgsi_exec_channel *src0,
984 const union tgsi_exec_channel *src1)
985 {
986 dst->f[0] = src0->f[0] * src1->f[0];
987 dst->f[1] = src0->f[1] * src1->f[1];
988 dst->f[2] = src0->f[2] * src1->f[2];
989 dst->f[3] = src0->f[3] * src1->f[3];
990 }
991
992 static void
993 micro_neg(
994 union tgsi_exec_channel *dst,
995 const union tgsi_exec_channel *src )
996 {
997 dst->f[0] = -src->f[0];
998 dst->f[1] = -src->f[1];
999 dst->f[2] = -src->f[2];
1000 dst->f[3] = -src->f[3];
1001 }
1002
1003 static void
1004 micro_pow(
1005 union tgsi_exec_channel *dst,
1006 const union tgsi_exec_channel *src0,
1007 const union tgsi_exec_channel *src1 )
1008 {
1009 #if FAST_MATH
1010 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1011 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1012 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1013 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1014 #else
1015 dst->f[0] = powf( src0->f[0], src1->f[0] );
1016 dst->f[1] = powf( src0->f[1], src1->f[1] );
1017 dst->f[2] = powf( src0->f[2], src1->f[2] );
1018 dst->f[3] = powf( src0->f[3], src1->f[3] );
1019 #endif
1020 }
1021
1022 static void
1023 micro_sub(union tgsi_exec_channel *dst,
1024 const union tgsi_exec_channel *src0,
1025 const union tgsi_exec_channel *src1)
1026 {
1027 dst->f[0] = src0->f[0] - src1->f[0];
1028 dst->f[1] = src0->f[1] - src1->f[1];
1029 dst->f[2] = src0->f[2] - src1->f[2];
1030 dst->f[3] = src0->f[3] - src1->f[3];
1031 }
1032
1033 static void
1034 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1035 const uint chan_index,
1036 const uint file,
1037 const uint swizzle,
1038 const union tgsi_exec_channel *index,
1039 const union tgsi_exec_channel *index2D,
1040 union tgsi_exec_channel *chan)
1041 {
1042 uint i;
1043
1044 assert(swizzle < 4);
1045
1046 switch (file) {
1047 case TGSI_FILE_CONSTANT:
1048 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1049 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1050 assert(mach->Consts[index2D->i[i]]);
1051
1052 if (index->i[i] < 0) {
1053 chan->u[i] = 0;
1054 } else {
1055 /* NOTE: copying the const value as a uint instead of float */
1056 const uint constbuf = index2D->i[i];
1057 const uint *buf = (const uint *)mach->Consts[constbuf];
1058 const int pos = index->i[i] * 4 + swizzle;
1059 /* const buffer bounds check */
1060 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1061 if (0) {
1062 /* Debug: print warning */
1063 static int count = 0;
1064 if (count++ < 100)
1065 debug_printf("TGSI Exec: const buffer index %d"
1066 " out of bounds\n", pos);
1067 }
1068 chan->u[i] = 0;
1069 }
1070 else
1071 chan->u[i] = buf[pos];
1072 }
1073 }
1074 break;
1075
1076 case TGSI_FILE_INPUT:
1077 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1078 /*
1079 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1080 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1081 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1082 index2D->i[i], index->i[i]);
1083 }*/
1084 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1085 assert(pos >= 0);
1086 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1087 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1088 }
1089 break;
1090
1091 case TGSI_FILE_SYSTEM_VALUE:
1092 /* XXX no swizzling at this point. Will be needed if we put
1093 * gl_FragCoord, for example, in a sys value register.
1094 */
1095 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1096 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1097 }
1098 break;
1099
1100 case TGSI_FILE_TEMPORARY:
1101 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1102 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1103 assert(index2D->i[i] == 0);
1104
1105 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1106 }
1107 break;
1108
1109 case TGSI_FILE_TEMPORARY_ARRAY:
1110 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1111 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1112 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1113
1114 chan->u[i] =
1115 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1116 }
1117 break;
1118
1119 case TGSI_FILE_IMMEDIATE:
1120 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1121 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1122 assert(index2D->i[i] == 0);
1123
1124 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1125 }
1126 break;
1127
1128 case TGSI_FILE_IMMEDIATE_ARRAY:
1129 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1130 assert(index2D->i[i] == 0);
1131
1132 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1133 }
1134 break;
1135
1136 case TGSI_FILE_ADDRESS:
1137 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1138 assert(index->i[i] >= 0);
1139 assert(index2D->i[i] == 0);
1140
1141 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1142 }
1143 break;
1144
1145 case TGSI_FILE_PREDICATE:
1146 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1147 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1148 assert(index2D->i[i] == 0);
1149
1150 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1151 }
1152 break;
1153
1154 case TGSI_FILE_OUTPUT:
1155 /* vertex/fragment output vars can be read too */
1156 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1157 assert(index->i[i] >= 0);
1158 assert(index2D->i[i] == 0);
1159
1160 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1161 }
1162 break;
1163
1164 default:
1165 assert(0);
1166 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1167 chan->u[i] = 0;
1168 }
1169 }
1170 }
1171
1172 static void
1173 fetch_source(const struct tgsi_exec_machine *mach,
1174 union tgsi_exec_channel *chan,
1175 const struct tgsi_full_src_register *reg,
1176 const uint chan_index,
1177 enum tgsi_exec_datatype src_datatype)
1178 {
1179 union tgsi_exec_channel index;
1180 union tgsi_exec_channel index2D;
1181 uint swizzle;
1182
1183 /* We start with a direct index into a register file.
1184 *
1185 * file[1],
1186 * where:
1187 * file = Register.File
1188 * [1] = Register.Index
1189 */
1190 index.i[0] =
1191 index.i[1] =
1192 index.i[2] =
1193 index.i[3] = reg->Register.Index;
1194
1195 /* There is an extra source register that indirectly subscripts
1196 * a register file. The direct index now becomes an offset
1197 * that is being added to the indirect register.
1198 *
1199 * file[ind[2].x+1],
1200 * where:
1201 * ind = Indirect.File
1202 * [2] = Indirect.Index
1203 * .x = Indirect.SwizzleX
1204 */
1205 if (reg->Register.Indirect) {
1206 union tgsi_exec_channel index2;
1207 union tgsi_exec_channel indir_index;
1208 const uint execmask = mach->ExecMask;
1209 uint i;
1210
1211 /* which address register (always zero now) */
1212 index2.i[0] =
1213 index2.i[1] =
1214 index2.i[2] =
1215 index2.i[3] = reg->Indirect.Index;
1216 /* get current value of address register[swizzle] */
1217 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, TGSI_CHAN_X );
1218 fetch_src_file_channel(mach,
1219 chan_index,
1220 reg->Indirect.File,
1221 swizzle,
1222 &index2,
1223 &ZeroVec,
1224 &indir_index);
1225
1226 /* add value of address register to the offset */
1227 index.i[0] += indir_index.i[0];
1228 index.i[1] += indir_index.i[1];
1229 index.i[2] += indir_index.i[2];
1230 index.i[3] += indir_index.i[3];
1231
1232 /* for disabled execution channels, zero-out the index to
1233 * avoid using a potential garbage value.
1234 */
1235 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1236 if ((execmask & (1 << i)) == 0)
1237 index.i[i] = 0;
1238 }
1239 }
1240
1241 /* There is an extra source register that is a second
1242 * subscript to a register file. Effectively it means that
1243 * the register file is actually a 2D array of registers.
1244 *
1245 * file[3][1],
1246 * where:
1247 * [3] = Dimension.Index
1248 */
1249 if (reg->Register.Dimension) {
1250 index2D.i[0] =
1251 index2D.i[1] =
1252 index2D.i[2] =
1253 index2D.i[3] = reg->Dimension.Index;
1254
1255 /* Again, the second subscript index can be addressed indirectly
1256 * identically to the first one.
1257 * Nothing stops us from indirectly addressing the indirect register,
1258 * but there is no need for that, so we won't exercise it.
1259 *
1260 * file[ind[4].y+3][1],
1261 * where:
1262 * ind = DimIndirect.File
1263 * [4] = DimIndirect.Index
1264 * .y = DimIndirect.SwizzleX
1265 */
1266 if (reg->Dimension.Indirect) {
1267 union tgsi_exec_channel index2;
1268 union tgsi_exec_channel indir_index;
1269 const uint execmask = mach->ExecMask;
1270 uint i;
1271
1272 index2.i[0] =
1273 index2.i[1] =
1274 index2.i[2] =
1275 index2.i[3] = reg->DimIndirect.Index;
1276
1277 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, TGSI_CHAN_X );
1278 fetch_src_file_channel(mach,
1279 chan_index,
1280 reg->DimIndirect.File,
1281 swizzle,
1282 &index2,
1283 &ZeroVec,
1284 &indir_index);
1285
1286 index2D.i[0] += indir_index.i[0];
1287 index2D.i[1] += indir_index.i[1];
1288 index2D.i[2] += indir_index.i[2];
1289 index2D.i[3] += indir_index.i[3];
1290
1291 /* for disabled execution channels, zero-out the index to
1292 * avoid using a potential garbage value.
1293 */
1294 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1295 if ((execmask & (1 << i)) == 0) {
1296 index2D.i[i] = 0;
1297 }
1298 }
1299 }
1300
1301 /* If by any chance there was a need for a 3D array of register
1302 * files, we would have to check whether Dimension is followed
1303 * by a dimension register and continue the saga.
1304 */
1305 } else {
1306 index2D.i[0] =
1307 index2D.i[1] =
1308 index2D.i[2] =
1309 index2D.i[3] = 0;
1310 }
1311
1312 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1313 fetch_src_file_channel(mach,
1314 chan_index,
1315 reg->Register.File,
1316 swizzle,
1317 &index,
1318 &index2D,
1319 chan);
1320
1321 if (reg->Register.Absolute) {
1322 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1323 micro_abs(chan, chan);
1324 } else {
1325 micro_iabs(chan, chan);
1326 }
1327 }
1328
1329 if (reg->Register.Negate) {
1330 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1331 micro_neg(chan, chan);
1332 } else {
1333 micro_ineg(chan, chan);
1334 }
1335 }
1336 }
1337
1338 static void
1339 store_dest(struct tgsi_exec_machine *mach,
1340 const union tgsi_exec_channel *chan,
1341 const struct tgsi_full_dst_register *reg,
1342 const struct tgsi_full_instruction *inst,
1343 uint chan_index,
1344 enum tgsi_exec_datatype dst_datatype)
1345 {
1346 uint i;
1347 union tgsi_exec_channel null;
1348 union tgsi_exec_channel *dst;
1349 union tgsi_exec_channel index2D;
1350 uint execmask = mach->ExecMask;
1351 int offset = 0; /* indirection offset */
1352 int index;
1353
1354 /* for debugging */
1355 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1356 check_inf_or_nan(chan);
1357 }
1358
1359 /* There is an extra source register that indirectly subscripts
1360 * a register file. The direct index now becomes an offset
1361 * that is being added to the indirect register.
1362 *
1363 * file[ind[2].x+1],
1364 * where:
1365 * ind = Indirect.File
1366 * [2] = Indirect.Index
1367 * .x = Indirect.SwizzleX
1368 */
1369 if (reg->Register.Indirect) {
1370 union tgsi_exec_channel index;
1371 union tgsi_exec_channel indir_index;
1372 uint swizzle;
1373
1374 /* which address register (always zero for now) */
1375 index.i[0] =
1376 index.i[1] =
1377 index.i[2] =
1378 index.i[3] = reg->Indirect.Index;
1379
1380 /* get current value of address register[swizzle] */
1381 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, TGSI_CHAN_X );
1382
1383 /* fetch values from the address/indirection register */
1384 fetch_src_file_channel(mach,
1385 chan_index,
1386 reg->Indirect.File,
1387 swizzle,
1388 &index,
1389 &ZeroVec,
1390 &indir_index);
1391
1392 /* save indirection offset */
1393 offset = indir_index.i[0];
1394 }
1395
1396 /* There is an extra source register that is a second
1397 * subscript to a register file. Effectively it means that
1398 * the register file is actually a 2D array of registers.
1399 *
1400 * file[3][1],
1401 * where:
1402 * [3] = Dimension.Index
1403 */
1404 if (reg->Register.Dimension) {
1405 index2D.i[0] =
1406 index2D.i[1] =
1407 index2D.i[2] =
1408 index2D.i[3] = reg->Dimension.Index;
1409
1410 /* Again, the second subscript index can be addressed indirectly
1411 * identically to the first one.
1412 * Nothing stops us from indirectly addressing the indirect register,
1413 * but there is no need for that, so we won't exercise it.
1414 *
1415 * file[ind[4].y+3][1],
1416 * where:
1417 * ind = DimIndirect.File
1418 * [4] = DimIndirect.Index
1419 * .y = DimIndirect.SwizzleX
1420 */
1421 if (reg->Dimension.Indirect) {
1422 union tgsi_exec_channel index2;
1423 union tgsi_exec_channel indir_index;
1424 const uint execmask = mach->ExecMask;
1425 unsigned swizzle;
1426 uint i;
1427
1428 index2.i[0] =
1429 index2.i[1] =
1430 index2.i[2] =
1431 index2.i[3] = reg->DimIndirect.Index;
1432
1433 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, TGSI_CHAN_X );
1434 fetch_src_file_channel(mach,
1435 chan_index,
1436 reg->DimIndirect.File,
1437 swizzle,
1438 &index2,
1439 &ZeroVec,
1440 &indir_index);
1441
1442 index2D.i[0] += indir_index.i[0];
1443 index2D.i[1] += indir_index.i[1];
1444 index2D.i[2] += indir_index.i[2];
1445 index2D.i[3] += indir_index.i[3];
1446
1447 /* for disabled execution channels, zero-out the index to
1448 * avoid using a potential garbage value.
1449 */
1450 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1451 if ((execmask & (1 << i)) == 0) {
1452 index2D.i[i] = 0;
1453 }
1454 }
1455 }
1456
1457 /* If by any chance there was a need for a 3D array of register
1458 * files, we would have to check whether Dimension is followed
1459 * by a dimension register and continue the saga.
1460 */
1461 } else {
1462 index2D.i[0] =
1463 index2D.i[1] =
1464 index2D.i[2] =
1465 index2D.i[3] = 0;
1466 }
1467
1468 switch (reg->Register.File) {
1469 case TGSI_FILE_NULL:
1470 dst = &null;
1471 break;
1472
1473 case TGSI_FILE_OUTPUT:
1474 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1475 + reg->Register.Index;
1476 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1477 #if 0
1478 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1479 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1480 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1481 if (execmask & (1 << i))
1482 fprintf(stderr, "%f, ", chan->f[i]);
1483 fprintf(stderr, ")\n");
1484 }
1485 #endif
1486 break;
1487
1488 case TGSI_FILE_TEMPORARY:
1489 index = reg->Register.Index;
1490 assert( index < TGSI_EXEC_NUM_TEMPS );
1491 dst = &mach->Temps[offset + index].xyzw[chan_index];
1492 break;
1493
1494 case TGSI_FILE_TEMPORARY_ARRAY:
1495 index = reg->Register.Index;
1496 assert( index < TGSI_EXEC_NUM_TEMPS );
1497 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1498 /* XXX we use index2D.i[0] here but somehow we might
1499 * end up with someone trying to store indirectly in
1500 * different buffers */
1501 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1502 break;
1503
1504 case TGSI_FILE_ADDRESS:
1505 index = reg->Register.Index;
1506 dst = &mach->Addrs[index].xyzw[chan_index];
1507 break;
1508
1509 case TGSI_FILE_PREDICATE:
1510 index = reg->Register.Index;
1511 assert(index < TGSI_EXEC_NUM_PREDS);
1512 dst = &mach->Predicates[index].xyzw[chan_index];
1513 break;
1514
1515 default:
1516 assert( 0 );
1517 return;
1518 }
1519
1520 if (inst->Instruction.Predicate) {
1521 uint swizzle;
1522 union tgsi_exec_channel *pred;
1523
1524 switch (chan_index) {
1525 case TGSI_CHAN_X:
1526 swizzle = inst->Predicate.SwizzleX;
1527 break;
1528 case TGSI_CHAN_Y:
1529 swizzle = inst->Predicate.SwizzleY;
1530 break;
1531 case TGSI_CHAN_Z:
1532 swizzle = inst->Predicate.SwizzleZ;
1533 break;
1534 case TGSI_CHAN_W:
1535 swizzle = inst->Predicate.SwizzleW;
1536 break;
1537 default:
1538 assert(0);
1539 return;
1540 }
1541
1542 assert(inst->Predicate.Index == 0);
1543
1544 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1545
1546 if (inst->Predicate.Negate) {
1547 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1548 if (pred->u[i]) {
1549 execmask &= ~(1 << i);
1550 }
1551 }
1552 } else {
1553 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1554 if (!pred->u[i]) {
1555 execmask &= ~(1 << i);
1556 }
1557 }
1558 }
1559 }
1560
1561 switch (inst->Instruction.Saturate) {
1562 case TGSI_SAT_NONE:
1563 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1564 if (execmask & (1 << i))
1565 dst->i[i] = chan->i[i];
1566 break;
1567
1568 case TGSI_SAT_ZERO_ONE:
1569 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1570 if (execmask & (1 << i)) {
1571 if (chan->f[i] < 0.0f)
1572 dst->f[i] = 0.0f;
1573 else if (chan->f[i] > 1.0f)
1574 dst->f[i] = 1.0f;
1575 else
1576 dst->i[i] = chan->i[i];
1577 }
1578 break;
1579
1580 case TGSI_SAT_MINUS_PLUS_ONE:
1581 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1582 if (execmask & (1 << i)) {
1583 if (chan->f[i] < -1.0f)
1584 dst->f[i] = -1.0f;
1585 else if (chan->f[i] > 1.0f)
1586 dst->f[i] = 1.0f;
1587 else
1588 dst->i[i] = chan->i[i];
1589 }
1590 break;
1591
1592 default:
1593 assert( 0 );
1594 }
1595 }
1596
1597 #define FETCH(VAL,INDEX,CHAN)\
1598 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1599
1600 #define IFETCH(VAL,INDEX,CHAN)\
1601 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1602
1603
1604 /**
1605 * Execute ARB-style KIL which is predicated by a src register.
1606 * Kill fragment if any of the four values is less than zero.
1607 */
1608 static void
1609 exec_kil(struct tgsi_exec_machine *mach,
1610 const struct tgsi_full_instruction *inst)
1611 {
1612 uint uniquemask;
1613 uint chan_index;
1614 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1615 union tgsi_exec_channel r[1];
1616
1617 /* This mask stores component bits that were already tested. */
1618 uniquemask = 0;
1619
1620 for (chan_index = 0; chan_index < 4; chan_index++)
1621 {
1622 uint swizzle;
1623 uint i;
1624
1625 /* unswizzle channel */
1626 swizzle = tgsi_util_get_full_src_register_swizzle (
1627 &inst->Src[0],
1628 chan_index);
1629
1630 /* check if the component has not been already tested */
1631 if (uniquemask & (1 << swizzle))
1632 continue;
1633 uniquemask |= 1 << swizzle;
1634
1635 FETCH(&r[0], 0, chan_index);
1636 for (i = 0; i < 4; i++)
1637 if (r[0].f[i] < 0.0f)
1638 kilmask |= 1 << i;
1639 }
1640
1641 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1642 }
1643
1644 /**
1645 * Execute NVIDIA-style KIL which is predicated by a condition code.
1646 * Kill fragment if the condition code is TRUE.
1647 */
1648 static void
1649 exec_kilp(struct tgsi_exec_machine *mach,
1650 const struct tgsi_full_instruction *inst)
1651 {
1652 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1653
1654 /* "unconditional" kil */
1655 kilmask = mach->ExecMask;
1656 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1657 }
1658
1659 static void
1660 emit_vertex(struct tgsi_exec_machine *mach)
1661 {
1662 /* FIXME: check for exec mask correctly
1663 unsigned i;
1664 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1665 if ((mach->ExecMask & (1 << i)))
1666 */
1667 if (mach->ExecMask) {
1668 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1669 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1670 }
1671 }
1672
1673 static void
1674 emit_primitive(struct tgsi_exec_machine *mach)
1675 {
1676 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1677 /* FIXME: check for exec mask correctly
1678 unsigned i;
1679 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1680 if ((mach->ExecMask & (1 << i)))
1681 */
1682 if (mach->ExecMask) {
1683 ++(*prim_count);
1684 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1685 mach->Primitives[*prim_count] = 0;
1686 }
1687 }
1688
1689 static void
1690 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1691 {
1692 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1693 int emitted_verts =
1694 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1695 if (emitted_verts) {
1696 emit_primitive(mach);
1697 }
1698 }
1699 }
1700
1701
1702 /*
1703 * Fetch four texture samples using STR texture coordinates.
1704 */
1705 static void
1706 fetch_texel( struct tgsi_sampler *sampler,
1707 const union tgsi_exec_channel *s,
1708 const union tgsi_exec_channel *t,
1709 const union tgsi_exec_channel *p,
1710 const union tgsi_exec_channel *c0,
1711 const union tgsi_exec_channel *c1,
1712 enum tgsi_sampler_control control,
1713 union tgsi_exec_channel *r,
1714 union tgsi_exec_channel *g,
1715 union tgsi_exec_channel *b,
1716 union tgsi_exec_channel *a )
1717 {
1718 uint j;
1719 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1720
1721 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, c1->f, control, rgba);
1722
1723 for (j = 0; j < 4; j++) {
1724 r->f[j] = rgba[0][j];
1725 g->f[j] = rgba[1][j];
1726 b->f[j] = rgba[2][j];
1727 a->f[j] = rgba[3][j];
1728 }
1729 }
1730
1731
1732 #define TEX_MODIFIER_NONE 0
1733 #define TEX_MODIFIER_PROJECTED 1
1734 #define TEX_MODIFIER_LOD_BIAS 2
1735 #define TEX_MODIFIER_EXPLICIT_LOD 3
1736
1737 /*
1738 * execute a texture instruction.
1739 *
1740 * modifier is used to control the channel routing for the\
1741 * instruction variants like proj, lod, and texture with lod bias.
1742 * sampler indicates which src register the sampler is contained in.
1743 */
1744 static void
1745 exec_tex(struct tgsi_exec_machine *mach,
1746 const struct tgsi_full_instruction *inst,
1747 uint modifier, uint sampler)
1748 {
1749 const uint unit = inst->Src[sampler].Register.Index;
1750 union tgsi_exec_channel r[4], cubearraycomp, cubelod;
1751 const union tgsi_exec_channel *lod = &ZeroVec;
1752 enum tgsi_sampler_control control;
1753 uint chan;
1754
1755 if (modifier != TEX_MODIFIER_NONE && (sampler == 1)) {
1756 FETCH(&r[3], 0, TGSI_CHAN_W);
1757 if (modifier != TEX_MODIFIER_PROJECTED) {
1758 lod = &r[3];
1759 }
1760 }
1761
1762 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1763 control = tgsi_sampler_lod_explicit;
1764 } else {
1765 control = tgsi_sampler_lod_bias;
1766 }
1767
1768 switch (inst->Texture.Texture) {
1769 case TGSI_TEXTURE_1D:
1770 FETCH(&r[0], 0, TGSI_CHAN_X);
1771
1772 if (modifier == TEX_MODIFIER_PROJECTED) {
1773 micro_div(&r[0], &r[0], &r[3]);
1774 }
1775
1776 fetch_texel(mach->Samplers[unit],
1777 &r[0], &ZeroVec, &ZeroVec, lod, &ZeroVec, /* S, T, P, LOD */
1778 control,
1779 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1780 break;
1781 case TGSI_TEXTURE_SHADOW1D:
1782 FETCH(&r[0], 0, TGSI_CHAN_X);
1783 FETCH(&r[2], 0, TGSI_CHAN_Z);
1784
1785 if (modifier == TEX_MODIFIER_PROJECTED) {
1786 micro_div(&r[0], &r[0], &r[3]);
1787 }
1788
1789 fetch_texel(mach->Samplers[unit],
1790 &r[0], &ZeroVec, &r[2], lod, &ZeroVec, /* S, T, P, LOD */
1791 control,
1792 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1793 break;
1794
1795 case TGSI_TEXTURE_2D:
1796 case TGSI_TEXTURE_RECT:
1797 case TGSI_TEXTURE_SHADOW2D:
1798 case TGSI_TEXTURE_SHADOWRECT:
1799 FETCH(&r[0], 0, TGSI_CHAN_X);
1800 FETCH(&r[1], 0, TGSI_CHAN_Y);
1801 FETCH(&r[2], 0, TGSI_CHAN_Z);
1802
1803 if (modifier == TEX_MODIFIER_PROJECTED) {
1804 micro_div(&r[0], &r[0], &r[3]);
1805 micro_div(&r[1], &r[1], &r[3]);
1806 micro_div(&r[2], &r[2], &r[3]);
1807 }
1808
1809 fetch_texel(mach->Samplers[unit],
1810 &r[0], &r[1], &r[2], lod, &ZeroVec, /* S, T, P, LOD */
1811 control,
1812 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1813 break;
1814
1815 case TGSI_TEXTURE_1D_ARRAY:
1816 FETCH(&r[0], 0, TGSI_CHAN_X);
1817 FETCH(&r[1], 0, TGSI_CHAN_Y);
1818
1819 if (modifier == TEX_MODIFIER_PROJECTED) {
1820 micro_div(&r[0], &r[0], &r[3]);
1821 }
1822
1823 fetch_texel(mach->Samplers[unit],
1824 &r[0], &r[1], &ZeroVec, lod, &ZeroVec, /* S, T, P, LOD */
1825 control,
1826 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1827 break;
1828 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1829 FETCH(&r[0], 0, TGSI_CHAN_X);
1830 FETCH(&r[1], 0, TGSI_CHAN_Y);
1831 FETCH(&r[2], 0, TGSI_CHAN_Z);
1832
1833 if (modifier == TEX_MODIFIER_PROJECTED) {
1834 micro_div(&r[0], &r[0], &r[3]);
1835 }
1836
1837 fetch_texel(mach->Samplers[unit],
1838 &r[0], &r[1], &r[2], lod, &ZeroVec, /* S, T, P, LOD */
1839 control,
1840 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1841 break;
1842
1843 case TGSI_TEXTURE_2D_ARRAY:
1844 FETCH(&r[0], 0, TGSI_CHAN_X);
1845 FETCH(&r[1], 0, TGSI_CHAN_Y);
1846 FETCH(&r[2], 0, TGSI_CHAN_Z);
1847
1848 if (modifier == TEX_MODIFIER_PROJECTED) {
1849 micro_div(&r[0], &r[0], &r[3]);
1850 micro_div(&r[1], &r[1], &r[3]);
1851 }
1852
1853 fetch_texel(mach->Samplers[unit],
1854 &r[0], &r[1], &r[2], lod, &ZeroVec, /* S, T, P, LOD */
1855 control,
1856 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1857 break;
1858 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1859 case TGSI_TEXTURE_SHADOWCUBE:
1860 FETCH(&r[0], 0, TGSI_CHAN_X);
1861 FETCH(&r[1], 0, TGSI_CHAN_Y);
1862 FETCH(&r[2], 0, TGSI_CHAN_Z);
1863 FETCH(&r[3], 0, TGSI_CHAN_W);
1864
1865 fetch_texel(mach->Samplers[unit],
1866 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* S, T, P, LOD */
1867 control,
1868 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1869 break;
1870 case TGSI_TEXTURE_CUBE_ARRAY:
1871 FETCH(&r[0], 0, TGSI_CHAN_X);
1872 FETCH(&r[1], 0, TGSI_CHAN_Y);
1873 FETCH(&r[2], 0, TGSI_CHAN_Z);
1874 FETCH(&r[3], 0, TGSI_CHAN_W);
1875
1876 if (modifier == TEX_MODIFIER_EXPLICIT_LOD ||
1877 modifier == TEX_MODIFIER_LOD_BIAS)
1878 FETCH(&cubelod, 1, TGSI_CHAN_X);
1879 else
1880 cubelod = ZeroVec;
1881
1882 fetch_texel(mach->Samplers[unit],
1883 &r[0], &r[1], &r[2], &r[3], &cubelod, /* S, T, P, LOD */
1884 control,
1885 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1886 break;
1887 case TGSI_TEXTURE_3D:
1888 case TGSI_TEXTURE_CUBE:
1889 FETCH(&r[0], 0, TGSI_CHAN_X);
1890 FETCH(&r[1], 0, TGSI_CHAN_Y);
1891 FETCH(&r[2], 0, TGSI_CHAN_Z);
1892
1893 if (modifier == TEX_MODIFIER_PROJECTED) {
1894 micro_div(&r[0], &r[0], &r[3]);
1895 micro_div(&r[1], &r[1], &r[3]);
1896 micro_div(&r[2], &r[2], &r[3]);
1897 }
1898
1899 fetch_texel(mach->Samplers[unit],
1900 &r[0], &r[1], &r[2], lod, &ZeroVec,
1901 control,
1902 &r[0], &r[1], &r[2], &r[3]);
1903 break;
1904
1905 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1906 FETCH(&r[0], 0, TGSI_CHAN_X);
1907 FETCH(&r[1], 0, TGSI_CHAN_Y);
1908 FETCH(&r[2], 0, TGSI_CHAN_Z);
1909 FETCH(&r[3], 0, TGSI_CHAN_W);
1910
1911 FETCH(&cubearraycomp, 1, TGSI_CHAN_X);
1912
1913 fetch_texel(mach->Samplers[unit],
1914 &r[0], &r[1], &r[2], &r[3], &cubearraycomp, /* S, T, P, LOD */
1915 control,
1916 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1917 break;
1918 default:
1919 assert(0);
1920 }
1921
1922 #if 0
1923 debug_printf("fetch r: %g %g %g %g\n",
1924 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1925 debug_printf("fetch g: %g %g %g %g\n",
1926 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1927 debug_printf("fetch b: %g %g %g %g\n",
1928 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1929 debug_printf("fetch a: %g %g %g %g\n",
1930 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1931 #endif
1932
1933 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1934 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1935 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1936 }
1937 }
1938 }
1939
1940 static void
1941 exec_txd(struct tgsi_exec_machine *mach,
1942 const struct tgsi_full_instruction *inst)
1943 {
1944 const uint unit = inst->Src[3].Register.Index;
1945 union tgsi_exec_channel r[4];
1946 uint chan;
1947
1948 /*
1949 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1950 */
1951
1952 switch (inst->Texture.Texture) {
1953 case TGSI_TEXTURE_1D:
1954 case TGSI_TEXTURE_SHADOW1D:
1955
1956 FETCH(&r[0], 0, TGSI_CHAN_X);
1957
1958 fetch_texel(mach->Samplers[unit],
1959 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1960 tgsi_sampler_lod_bias,
1961 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1962 break;
1963
1964 case TGSI_TEXTURE_1D_ARRAY:
1965 case TGSI_TEXTURE_2D:
1966 case TGSI_TEXTURE_RECT:
1967 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1968 case TGSI_TEXTURE_SHADOW2D:
1969 case TGSI_TEXTURE_SHADOWRECT:
1970
1971 FETCH(&r[0], 0, TGSI_CHAN_X);
1972 FETCH(&r[1], 0, TGSI_CHAN_Y);
1973 FETCH(&r[2], 0, TGSI_CHAN_Z);
1974
1975 fetch_texel(mach->Samplers[unit],
1976 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
1977 tgsi_sampler_lod_bias,
1978 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1979 break;
1980
1981 case TGSI_TEXTURE_2D_ARRAY:
1982 case TGSI_TEXTURE_3D:
1983 case TGSI_TEXTURE_CUBE:
1984 case TGSI_TEXTURE_CUBE_ARRAY:
1985 FETCH(&r[0], 0, TGSI_CHAN_X);
1986 FETCH(&r[1], 0, TGSI_CHAN_Y);
1987 FETCH(&r[2], 0, TGSI_CHAN_Z);
1988
1989 fetch_texel(mach->Samplers[unit],
1990 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec,
1991 tgsi_sampler_lod_bias,
1992 &r[0], &r[1], &r[2], &r[3]);
1993 break;
1994
1995 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1996
1997 FETCH(&r[0], 0, TGSI_CHAN_X);
1998 FETCH(&r[1], 0, TGSI_CHAN_Y);
1999 FETCH(&r[2], 0, TGSI_CHAN_Z);
2000 FETCH(&r[3], 0, TGSI_CHAN_W);
2001
2002 fetch_texel(mach->Samplers[unit],
2003 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2004 tgsi_sampler_lod_bias,
2005 &r[0], &r[1], &r[2], &r[3]);
2006 break;
2007
2008 default:
2009 assert(0);
2010 }
2011
2012 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2013 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2014 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2015 }
2016 }
2017 }
2018
2019
2020 static void
2021 exec_txf(struct tgsi_exec_machine *mach,
2022 const struct tgsi_full_instruction *inst)
2023 {
2024 struct tgsi_sampler *sampler;
2025 const uint unit = inst->Src[2].Register.Index;
2026 union tgsi_exec_channel r[4];
2027 union tgsi_exec_channel offset[3];
2028 uint chan;
2029 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2030 int j;
2031 int8_t offsets[3];
2032
2033 if (inst->Texture.NumOffsets == 1) {
2034 union tgsi_exec_channel index;
2035 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
2036 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2037 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
2038 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2039 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
2040 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2041 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
2042 offsets[0] = offset[0].i[0];
2043 offsets[1] = offset[1].i[0];
2044 offsets[2] = offset[2].i[0];
2045 } else
2046 offsets[0] = offsets[1] = offsets[2] = 0;
2047
2048 IFETCH(&r[3], 0, TGSI_CHAN_W);
2049
2050 switch(inst->Texture.Texture) {
2051 case TGSI_TEXTURE_3D:
2052 case TGSI_TEXTURE_2D_ARRAY:
2053 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2054 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2055 /* fallthrough */
2056 case TGSI_TEXTURE_2D:
2057 case TGSI_TEXTURE_RECT:
2058 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2059 case TGSI_TEXTURE_SHADOW2D:
2060 case TGSI_TEXTURE_SHADOWRECT:
2061 case TGSI_TEXTURE_1D_ARRAY:
2062 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2063 /* fallthrough */
2064 case TGSI_TEXTURE_BUFFER:
2065 case TGSI_TEXTURE_1D:
2066 case TGSI_TEXTURE_SHADOW1D:
2067 IFETCH(&r[0], 0, TGSI_CHAN_X);
2068 break;
2069 default:
2070 assert(0);
2071 break;
2072 }
2073
2074 sampler = mach->Samplers[unit];
2075 sampler->get_texel(sampler, r[0].i, r[1].i, r[2].i, r[3].i,
2076 offsets, rgba);
2077
2078 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2079 r[0].f[j] = rgba[0][j];
2080 r[1].f[j] = rgba[1][j];
2081 r[2].f[j] = rgba[2][j];
2082 r[3].f[j] = rgba[3][j];
2083 }
2084
2085 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2086 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2087 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2088 }
2089 }
2090 }
2091
2092 static void
2093 exec_txq(struct tgsi_exec_machine *mach,
2094 const struct tgsi_full_instruction *inst)
2095 {
2096 struct tgsi_sampler *sampler;
2097 const uint unit = inst->Src[1].Register.Index;
2098 int result[4];
2099 union tgsi_exec_channel r[4], src;
2100 uint chan;
2101 int i,j;
2102
2103 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2104 sampler = mach->Samplers[unit];
2105
2106 sampler->get_dims(sampler, src.i[0], result);
2107
2108 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2109 for (j = 0; j < 4; j++) {
2110 r[j].i[i] = result[j];
2111 }
2112 }
2113
2114 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2115 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2116 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2117 TGSI_EXEC_DATA_INT);
2118 }
2119 }
2120 }
2121
2122 static void
2123 exec_sample(struct tgsi_exec_machine *mach,
2124 const struct tgsi_full_instruction *inst,
2125 uint modifier)
2126 {
2127 const uint resource_unit = inst->Src[1].Register.Index;
2128 const uint sampler_unit = inst->Src[2].Register.Index;
2129 union tgsi_exec_channel r[4];
2130 const union tgsi_exec_channel *lod = &ZeroVec;
2131 enum tgsi_sampler_control control;
2132 uint chan;
2133
2134 if (modifier != TEX_MODIFIER_NONE) {
2135 if (modifier == TEX_MODIFIER_LOD_BIAS)
2136 FETCH(&r[3], 3, TGSI_CHAN_X);
2137 else /*TEX_MODIFIER_LOD*/
2138 FETCH(&r[3], 0, TGSI_CHAN_W);
2139
2140 if (modifier != TEX_MODIFIER_PROJECTED) {
2141 lod = &r[3];
2142 }
2143 }
2144
2145 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2146 control = tgsi_sampler_lod_explicit;
2147 } else {
2148 control = tgsi_sampler_lod_bias;
2149 }
2150
2151 switch (mach->SamplerViews[resource_unit].Resource) {
2152 case TGSI_TEXTURE_1D:
2153 case TGSI_TEXTURE_SHADOW1D:
2154 FETCH(&r[0], 0, TGSI_CHAN_X);
2155
2156 if (modifier == TEX_MODIFIER_PROJECTED) {
2157 micro_div(&r[0], &r[0], &r[3]);
2158 }
2159
2160 fetch_texel(mach->Samplers[sampler_unit],
2161 &r[0], &ZeroVec, &ZeroVec, lod, &ZeroVec, /* S, T, P, LOD */
2162 control,
2163 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2164 break;
2165
2166 case TGSI_TEXTURE_1D_ARRAY:
2167 case TGSI_TEXTURE_2D:
2168 case TGSI_TEXTURE_RECT:
2169 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2170 case TGSI_TEXTURE_SHADOW2D:
2171 case TGSI_TEXTURE_SHADOWRECT:
2172 FETCH(&r[0], 0, TGSI_CHAN_X);
2173 FETCH(&r[1], 0, TGSI_CHAN_Y);
2174 FETCH(&r[2], 0, TGSI_CHAN_Z);
2175
2176 if (modifier == TEX_MODIFIER_PROJECTED) {
2177 micro_div(&r[0], &r[0], &r[3]);
2178 micro_div(&r[1], &r[1], &r[3]);
2179 micro_div(&r[2], &r[2], &r[3]);
2180 }
2181
2182 fetch_texel(mach->Samplers[sampler_unit],
2183 &r[0], &r[1], &r[2], lod, &ZeroVec, /* S, T, P, LOD */
2184 control,
2185 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2186 break;
2187
2188 case TGSI_TEXTURE_2D_ARRAY:
2189 case TGSI_TEXTURE_3D:
2190 case TGSI_TEXTURE_CUBE:
2191 case TGSI_TEXTURE_CUBE_ARRAY:
2192 FETCH(&r[0], 0, TGSI_CHAN_X);
2193 FETCH(&r[1], 0, TGSI_CHAN_Y);
2194 FETCH(&r[2], 0, TGSI_CHAN_Z);
2195
2196 if (modifier == TEX_MODIFIER_PROJECTED) {
2197 micro_div(&r[0], &r[0], &r[3]);
2198 micro_div(&r[1], &r[1], &r[3]);
2199 micro_div(&r[2], &r[2], &r[3]);
2200 }
2201
2202 fetch_texel(mach->Samplers[sampler_unit],
2203 &r[0], &r[1], &r[2], lod, &ZeroVec,
2204 control,
2205 &r[0], &r[1], &r[2], &r[3]);
2206 break;
2207
2208 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2209 case TGSI_TEXTURE_SHADOWCUBE:
2210 FETCH(&r[0], 0, TGSI_CHAN_X);
2211 FETCH(&r[1], 0, TGSI_CHAN_Y);
2212 FETCH(&r[2], 0, TGSI_CHAN_Z);
2213 FETCH(&r[3], 0, TGSI_CHAN_W);
2214
2215 assert(modifier != TEX_MODIFIER_PROJECTED);
2216
2217 fetch_texel(mach->Samplers[sampler_unit],
2218 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2219 control,
2220 &r[0], &r[1], &r[2], &r[3]);
2221 break;
2222
2223 default:
2224 assert(0);
2225 }
2226
2227 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2228 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2229 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2230 }
2231 }
2232 }
2233
2234 static void
2235 exec_sample_d(struct tgsi_exec_machine *mach,
2236 const struct tgsi_full_instruction *inst)
2237 {
2238 const uint resource_unit = inst->Src[1].Register.Index;
2239 const uint sampler_unit = inst->Src[2].Register.Index;
2240 union tgsi_exec_channel r[4];
2241 uint chan;
2242 /*
2243 * XXX: This is fake SAMPLE_D -- the derivatives are not taken into account, yet.
2244 */
2245
2246 switch (mach->SamplerViews[resource_unit].Resource) {
2247 case TGSI_TEXTURE_1D:
2248 case TGSI_TEXTURE_SHADOW1D:
2249
2250 FETCH(&r[0], 0, TGSI_CHAN_X);
2251
2252 fetch_texel(mach->Samplers[sampler_unit],
2253 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
2254 tgsi_sampler_lod_bias,
2255 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2256 break;
2257
2258 case TGSI_TEXTURE_2D:
2259 case TGSI_TEXTURE_RECT:
2260 case TGSI_TEXTURE_SHADOW2D:
2261 case TGSI_TEXTURE_SHADOWRECT:
2262
2263 FETCH(&r[0], 0, TGSI_CHAN_X);
2264 FETCH(&r[1], 0, TGSI_CHAN_Y);
2265 FETCH(&r[2], 0, TGSI_CHAN_Z);
2266
2267 fetch_texel(mach->Samplers[sampler_unit],
2268 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2269 tgsi_sampler_lod_bias,
2270 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2271 break;
2272
2273 case TGSI_TEXTURE_3D:
2274 case TGSI_TEXTURE_CUBE:
2275 case TGSI_TEXTURE_CUBE_ARRAY:
2276
2277 FETCH(&r[0], 0, TGSI_CHAN_X);
2278 FETCH(&r[1], 0, TGSI_CHAN_Y);
2279 FETCH(&r[2], 0, TGSI_CHAN_Z);
2280
2281 fetch_texel(mach->Samplers[sampler_unit],
2282 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec,
2283 tgsi_sampler_lod_bias,
2284 &r[0], &r[1], &r[2], &r[3]);
2285 break;
2286
2287 default:
2288 assert(0);
2289 }
2290
2291 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2292 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2293 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2294 }
2295 }
2296 }
2297
2298
2299 /**
2300 * Evaluate a constant-valued coefficient at the position of the
2301 * current quad.
2302 */
2303 static void
2304 eval_constant_coef(
2305 struct tgsi_exec_machine *mach,
2306 unsigned attrib,
2307 unsigned chan )
2308 {
2309 unsigned i;
2310
2311 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2312 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2313 }
2314 }
2315
2316 /**
2317 * Evaluate a linear-valued coefficient at the position of the
2318 * current quad.
2319 */
2320 static void
2321 eval_linear_coef(
2322 struct tgsi_exec_machine *mach,
2323 unsigned attrib,
2324 unsigned chan )
2325 {
2326 const float x = mach->QuadPos.xyzw[0].f[0];
2327 const float y = mach->QuadPos.xyzw[1].f[0];
2328 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2329 const float dady = mach->InterpCoefs[attrib].dady[chan];
2330 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2331 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2332 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2333 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2334 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2335 }
2336
2337 /**
2338 * Evaluate a perspective-valued coefficient at the position of the
2339 * current quad.
2340 */
2341 static void
2342 eval_perspective_coef(
2343 struct tgsi_exec_machine *mach,
2344 unsigned attrib,
2345 unsigned chan )
2346 {
2347 const float x = mach->QuadPos.xyzw[0].f[0];
2348 const float y = mach->QuadPos.xyzw[1].f[0];
2349 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2350 const float dady = mach->InterpCoefs[attrib].dady[chan];
2351 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2352 const float *w = mach->QuadPos.xyzw[3].f;
2353 /* divide by W here */
2354 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2355 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2356 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2357 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2358 }
2359
2360
2361 typedef void (* eval_coef_func)(
2362 struct tgsi_exec_machine *mach,
2363 unsigned attrib,
2364 unsigned chan );
2365
2366 static void
2367 exec_declaration(struct tgsi_exec_machine *mach,
2368 const struct tgsi_full_declaration *decl)
2369 {
2370 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2371 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2372 return;
2373 }
2374
2375 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2376 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2377 uint first, last, mask;
2378
2379 first = decl->Range.First;
2380 last = decl->Range.Last;
2381 mask = decl->Declaration.UsageMask;
2382
2383 /* XXX we could remove this special-case code since
2384 * mach->InterpCoefs[first].a0 should already have the
2385 * front/back-face value. But we should first update the
2386 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2387 * Then, we could remove the tgsi_exec_machine::Face field.
2388 */
2389 /* XXX make FACE a system value */
2390 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2391 uint i;
2392
2393 assert(decl->Semantic.Index == 0);
2394 assert(first == last);
2395
2396 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2397 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2398 }
2399 } else {
2400 eval_coef_func eval;
2401 uint i, j;
2402
2403 switch (decl->Interp.Interpolate) {
2404 case TGSI_INTERPOLATE_CONSTANT:
2405 eval = eval_constant_coef;
2406 break;
2407
2408 case TGSI_INTERPOLATE_LINEAR:
2409 eval = eval_linear_coef;
2410 break;
2411
2412 case TGSI_INTERPOLATE_PERSPECTIVE:
2413 eval = eval_perspective_coef;
2414 break;
2415
2416 case TGSI_INTERPOLATE_COLOR:
2417 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2418 break;
2419
2420 default:
2421 assert(0);
2422 return;
2423 }
2424
2425 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2426 if (mask & (1 << j)) {
2427 for (i = first; i <= last; i++) {
2428 eval(mach, i, j);
2429 }
2430 }
2431 }
2432 }
2433 }
2434 }
2435
2436 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2437 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2438 }
2439 }
2440
2441
2442 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2443
2444 static void
2445 exec_vector(struct tgsi_exec_machine *mach,
2446 const struct tgsi_full_instruction *inst,
2447 micro_op op,
2448 enum tgsi_exec_datatype dst_datatype)
2449 {
2450 unsigned int chan;
2451
2452 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2453 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2454 union tgsi_exec_channel dst;
2455
2456 op(&dst);
2457 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2458 }
2459 }
2460 }
2461
2462 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2463 const union tgsi_exec_channel *src);
2464
2465 static void
2466 exec_scalar_unary(struct tgsi_exec_machine *mach,
2467 const struct tgsi_full_instruction *inst,
2468 micro_unary_op op,
2469 enum tgsi_exec_datatype dst_datatype,
2470 enum tgsi_exec_datatype src_datatype)
2471 {
2472 unsigned int chan;
2473 union tgsi_exec_channel src;
2474 union tgsi_exec_channel dst;
2475
2476 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2477 op(&dst, &src);
2478 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2479 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2480 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2481 }
2482 }
2483 }
2484
2485 static void
2486 exec_vector_unary(struct tgsi_exec_machine *mach,
2487 const struct tgsi_full_instruction *inst,
2488 micro_unary_op op,
2489 enum tgsi_exec_datatype dst_datatype,
2490 enum tgsi_exec_datatype src_datatype)
2491 {
2492 unsigned int chan;
2493 struct tgsi_exec_vector dst;
2494
2495 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2496 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2497 union tgsi_exec_channel src;
2498
2499 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2500 op(&dst.xyzw[chan], &src);
2501 }
2502 }
2503 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2504 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2505 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2506 }
2507 }
2508 }
2509
2510 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2511 const union tgsi_exec_channel *src0,
2512 const union tgsi_exec_channel *src1);
2513
2514 static void
2515 exec_scalar_binary(struct tgsi_exec_machine *mach,
2516 const struct tgsi_full_instruction *inst,
2517 micro_binary_op op,
2518 enum tgsi_exec_datatype dst_datatype,
2519 enum tgsi_exec_datatype src_datatype)
2520 {
2521 unsigned int chan;
2522 union tgsi_exec_channel src[2];
2523 union tgsi_exec_channel dst;
2524
2525 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2526 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_Y, src_datatype);
2527 op(&dst, &src[0], &src[1]);
2528 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2529 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2530 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2531 }
2532 }
2533 }
2534
2535 static void
2536 exec_vector_binary(struct tgsi_exec_machine *mach,
2537 const struct tgsi_full_instruction *inst,
2538 micro_binary_op op,
2539 enum tgsi_exec_datatype dst_datatype,
2540 enum tgsi_exec_datatype src_datatype)
2541 {
2542 unsigned int chan;
2543 struct tgsi_exec_vector dst;
2544
2545 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2546 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2547 union tgsi_exec_channel src[2];
2548
2549 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2550 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2551 op(&dst.xyzw[chan], &src[0], &src[1]);
2552 }
2553 }
2554 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2555 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2556 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2557 }
2558 }
2559 }
2560
2561 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2562 const union tgsi_exec_channel *src0,
2563 const union tgsi_exec_channel *src1,
2564 const union tgsi_exec_channel *src2);
2565
2566 static void
2567 exec_vector_trinary(struct tgsi_exec_machine *mach,
2568 const struct tgsi_full_instruction *inst,
2569 micro_trinary_op op,
2570 enum tgsi_exec_datatype dst_datatype,
2571 enum tgsi_exec_datatype src_datatype)
2572 {
2573 unsigned int chan;
2574 struct tgsi_exec_vector dst;
2575
2576 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2577 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2578 union tgsi_exec_channel src[3];
2579
2580 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2581 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2582 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2583 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2584 }
2585 }
2586 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2587 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2588 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2589 }
2590 }
2591 }
2592
2593 static void
2594 exec_dp3(struct tgsi_exec_machine *mach,
2595 const struct tgsi_full_instruction *inst)
2596 {
2597 unsigned int chan;
2598 union tgsi_exec_channel arg[3];
2599
2600 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2601 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2602 micro_mul(&arg[2], &arg[0], &arg[1]);
2603
2604 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2605 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2606 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2607 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2608 }
2609
2610 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2611 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2612 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2613 }
2614 }
2615 }
2616
2617 static void
2618 exec_dp4(struct tgsi_exec_machine *mach,
2619 const struct tgsi_full_instruction *inst)
2620 {
2621 unsigned int chan;
2622 union tgsi_exec_channel arg[3];
2623
2624 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2625 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2626 micro_mul(&arg[2], &arg[0], &arg[1]);
2627
2628 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2629 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2630 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2631 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2632 }
2633
2634 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2635 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2636 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2637 }
2638 }
2639 }
2640
2641 static void
2642 exec_dp2a(struct tgsi_exec_machine *mach,
2643 const struct tgsi_full_instruction *inst)
2644 {
2645 unsigned int chan;
2646 union tgsi_exec_channel arg[3];
2647
2648 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2649 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2650 micro_mul(&arg[2], &arg[0], &arg[1]);
2651
2652 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2653 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2654 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2655
2656 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2657 micro_add(&arg[0], &arg[0], &arg[1]);
2658
2659 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2660 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2661 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2662 }
2663 }
2664 }
2665
2666 static void
2667 exec_dph(struct tgsi_exec_machine *mach,
2668 const struct tgsi_full_instruction *inst)
2669 {
2670 unsigned int chan;
2671 union tgsi_exec_channel arg[3];
2672
2673 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2674 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2675 micro_mul(&arg[2], &arg[0], &arg[1]);
2676
2677 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2678 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2679 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2680
2681 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2682 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2683 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2684
2685 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2686 micro_add(&arg[0], &arg[0], &arg[1]);
2687
2688 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2689 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2690 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2691 }
2692 }
2693 }
2694
2695 static void
2696 exec_dp2(struct tgsi_exec_machine *mach,
2697 const struct tgsi_full_instruction *inst)
2698 {
2699 unsigned int chan;
2700 union tgsi_exec_channel arg[3];
2701
2702 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2703 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2704 micro_mul(&arg[2], &arg[0], &arg[1]);
2705
2706 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2707 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2708 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2709
2710 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2711 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2712 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2713 }
2714 }
2715 }
2716
2717 static void
2718 exec_nrm4(struct tgsi_exec_machine *mach,
2719 const struct tgsi_full_instruction *inst)
2720 {
2721 unsigned int chan;
2722 union tgsi_exec_channel arg[4];
2723 union tgsi_exec_channel scale;
2724
2725 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2726 micro_mul(&scale, &arg[0], &arg[0]);
2727
2728 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2729 union tgsi_exec_channel product;
2730
2731 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2732 micro_mul(&product, &arg[chan], &arg[chan]);
2733 micro_add(&scale, &scale, &product);
2734 }
2735
2736 micro_rsq(&scale, &scale);
2737
2738 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2739 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2740 micro_mul(&arg[chan], &arg[chan], &scale);
2741 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2742 }
2743 }
2744 }
2745
2746 static void
2747 exec_nrm3(struct tgsi_exec_machine *mach,
2748 const struct tgsi_full_instruction *inst)
2749 {
2750 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2751 unsigned int chan;
2752 union tgsi_exec_channel arg[3];
2753 union tgsi_exec_channel scale;
2754
2755 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2756 micro_mul(&scale, &arg[0], &arg[0]);
2757
2758 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2759 union tgsi_exec_channel product;
2760
2761 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2762 micro_mul(&product, &arg[chan], &arg[chan]);
2763 micro_add(&scale, &scale, &product);
2764 }
2765
2766 micro_rsq(&scale, &scale);
2767
2768 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2769 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2770 micro_mul(&arg[chan], &arg[chan], &scale);
2771 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2772 }
2773 }
2774 }
2775
2776 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2777 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2778 }
2779 }
2780
2781 static void
2782 exec_scs(struct tgsi_exec_machine *mach,
2783 const struct tgsi_full_instruction *inst)
2784 {
2785 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2786 union tgsi_exec_channel arg;
2787 union tgsi_exec_channel result;
2788
2789 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2790
2791 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2792 micro_cos(&result, &arg);
2793 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2794 }
2795 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2796 micro_sin(&result, &arg);
2797 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2798 }
2799 }
2800 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2801 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2802 }
2803 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2804 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2805 }
2806 }
2807
2808 static void
2809 exec_x2d(struct tgsi_exec_machine *mach,
2810 const struct tgsi_full_instruction *inst)
2811 {
2812 union tgsi_exec_channel r[4];
2813 union tgsi_exec_channel d[2];
2814
2815 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2816 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2817 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2818 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2819 micro_mul(&r[2], &r[2], &r[0]);
2820 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2821 micro_mul(&r[3], &r[3], &r[1]);
2822 micro_add(&r[2], &r[2], &r[3]);
2823 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2824 micro_add(&d[0], &r[2], &r[3]);
2825 }
2826 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2827 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2828 micro_mul(&r[2], &r[2], &r[0]);
2829 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2830 micro_mul(&r[3], &r[3], &r[1]);
2831 micro_add(&r[2], &r[2], &r[3]);
2832 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2833 micro_add(&d[1], &r[2], &r[3]);
2834 }
2835 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2836 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2837 }
2838 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2839 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2840 }
2841 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2842 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2843 }
2844 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2845 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2846 }
2847 }
2848
2849 static void
2850 exec_rfl(struct tgsi_exec_machine *mach,
2851 const struct tgsi_full_instruction *inst)
2852 {
2853 union tgsi_exec_channel r[9];
2854
2855 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2856 /* r0 = dp3(src0, src0) */
2857 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2858 micro_mul(&r[0], &r[2], &r[2]);
2859 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2860 micro_mul(&r[8], &r[4], &r[4]);
2861 micro_add(&r[0], &r[0], &r[8]);
2862 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2863 micro_mul(&r[8], &r[6], &r[6]);
2864 micro_add(&r[0], &r[0], &r[8]);
2865
2866 /* r1 = dp3(src0, src1) */
2867 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2868 micro_mul(&r[1], &r[2], &r[3]);
2869 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2870 micro_mul(&r[8], &r[4], &r[5]);
2871 micro_add(&r[1], &r[1], &r[8]);
2872 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2873 micro_mul(&r[8], &r[6], &r[7]);
2874 micro_add(&r[1], &r[1], &r[8]);
2875
2876 /* r1 = 2 * r1 / r0 */
2877 micro_add(&r[1], &r[1], &r[1]);
2878 micro_div(&r[1], &r[1], &r[0]);
2879
2880 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2881 micro_mul(&r[2], &r[2], &r[1]);
2882 micro_sub(&r[2], &r[2], &r[3]);
2883 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2884 }
2885 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2886 micro_mul(&r[4], &r[4], &r[1]);
2887 micro_sub(&r[4], &r[4], &r[5]);
2888 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2889 }
2890 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2891 micro_mul(&r[6], &r[6], &r[1]);
2892 micro_sub(&r[6], &r[6], &r[7]);
2893 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2894 }
2895 }
2896 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2897 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2898 }
2899 }
2900
2901 static void
2902 exec_xpd(struct tgsi_exec_machine *mach,
2903 const struct tgsi_full_instruction *inst)
2904 {
2905 union tgsi_exec_channel r[6];
2906 union tgsi_exec_channel d[3];
2907
2908 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2909 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2910
2911 micro_mul(&r[2], &r[0], &r[1]);
2912
2913 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2914 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2915
2916 micro_mul(&r[5], &r[3], &r[4] );
2917 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2918
2919 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2920
2921 micro_mul(&r[3], &r[3], &r[2]);
2922
2923 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2924
2925 micro_mul(&r[1], &r[1], &r[5]);
2926 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2927
2928 micro_mul(&r[5], &r[5], &r[4]);
2929 micro_mul(&r[0], &r[0], &r[2]);
2930 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2931
2932 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2933 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2934 }
2935 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2936 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2937 }
2938 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2939 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2940 }
2941 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2942 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2943 }
2944 }
2945
2946 static void
2947 exec_dst(struct tgsi_exec_machine *mach,
2948 const struct tgsi_full_instruction *inst)
2949 {
2950 union tgsi_exec_channel r[2];
2951 union tgsi_exec_channel d[4];
2952
2953 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2954 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2955 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2956 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2957 }
2958 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2959 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2960 }
2961 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2962 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2963 }
2964
2965 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2966 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2967 }
2968 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2969 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2970 }
2971 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2972 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2973 }
2974 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2975 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2976 }
2977 }
2978
2979 static void
2980 exec_log(struct tgsi_exec_machine *mach,
2981 const struct tgsi_full_instruction *inst)
2982 {
2983 union tgsi_exec_channel r[3];
2984
2985 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2986 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2987 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2988 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2989 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2990 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2991 }
2992 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2993 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2994 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2995 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2996 }
2997 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2998 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2999 }
3000 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3001 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3002 }
3003 }
3004
3005 static void
3006 exec_exp(struct tgsi_exec_machine *mach,
3007 const struct tgsi_full_instruction *inst)
3008 {
3009 union tgsi_exec_channel r[3];
3010
3011 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3012 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3013 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3014 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3015 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3016 }
3017 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3018 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3019 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3020 }
3021 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3022 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3023 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3024 }
3025 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3026 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3027 }
3028 }
3029
3030 static void
3031 exec_lit(struct tgsi_exec_machine *mach,
3032 const struct tgsi_full_instruction *inst)
3033 {
3034 union tgsi_exec_channel r[3];
3035 union tgsi_exec_channel d[3];
3036
3037 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3038 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3039 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3040 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3041 micro_max(&r[1], &r[1], &ZeroVec);
3042
3043 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3044 micro_min(&r[2], &r[2], &P128Vec);
3045 micro_max(&r[2], &r[2], &M128Vec);
3046 micro_pow(&r[1], &r[1], &r[2]);
3047 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3048 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3049 }
3050 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3051 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3052 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3053 }
3054 }
3055 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3056 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3057 }
3058
3059 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3060 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3061 }
3062 }
3063
3064 static void
3065 exec_break(struct tgsi_exec_machine *mach)
3066 {
3067 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3068 /* turn off loop channels for each enabled exec channel */
3069 mach->LoopMask &= ~mach->ExecMask;
3070 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3071 UPDATE_EXEC_MASK(mach);
3072 } else {
3073 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3074
3075 mach->Switch.mask = 0x0;
3076
3077 UPDATE_EXEC_MASK(mach);
3078 }
3079 }
3080
3081 static void
3082 exec_switch(struct tgsi_exec_machine *mach,
3083 const struct tgsi_full_instruction *inst)
3084 {
3085 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3086 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3087
3088 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3089 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3090 mach->Switch.mask = 0x0;
3091 mach->Switch.defaultMask = 0x0;
3092
3093 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3094 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3095
3096 UPDATE_EXEC_MASK(mach);
3097 }
3098
3099 static void
3100 exec_case(struct tgsi_exec_machine *mach,
3101 const struct tgsi_full_instruction *inst)
3102 {
3103 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3104 union tgsi_exec_channel src;
3105 uint mask = 0;
3106
3107 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3108
3109 if (mach->Switch.selector.u[0] == src.u[0]) {
3110 mask |= 0x1;
3111 }
3112 if (mach->Switch.selector.u[1] == src.u[1]) {
3113 mask |= 0x2;
3114 }
3115 if (mach->Switch.selector.u[2] == src.u[2]) {
3116 mask |= 0x4;
3117 }
3118 if (mach->Switch.selector.u[3] == src.u[3]) {
3119 mask |= 0x8;
3120 }
3121
3122 mach->Switch.defaultMask |= mask;
3123
3124 mach->Switch.mask |= mask & prevMask;
3125
3126 UPDATE_EXEC_MASK(mach);
3127 }
3128
3129 static void
3130 exec_default(struct tgsi_exec_machine *mach)
3131 {
3132 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3133
3134 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3135
3136 UPDATE_EXEC_MASK(mach);
3137 }
3138
3139 static void
3140 exec_endswitch(struct tgsi_exec_machine *mach)
3141 {
3142 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3143 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3144
3145 UPDATE_EXEC_MASK(mach);
3146 }
3147
3148 static void
3149 micro_i2f(union tgsi_exec_channel *dst,
3150 const union tgsi_exec_channel *src)
3151 {
3152 dst->f[0] = (float)src->i[0];
3153 dst->f[1] = (float)src->i[1];
3154 dst->f[2] = (float)src->i[2];
3155 dst->f[3] = (float)src->i[3];
3156 }
3157
3158 static void
3159 micro_not(union tgsi_exec_channel *dst,
3160 const union tgsi_exec_channel *src)
3161 {
3162 dst->u[0] = ~src->u[0];
3163 dst->u[1] = ~src->u[1];
3164 dst->u[2] = ~src->u[2];
3165 dst->u[3] = ~src->u[3];
3166 }
3167
3168 static void
3169 micro_shl(union tgsi_exec_channel *dst,
3170 const union tgsi_exec_channel *src0,
3171 const union tgsi_exec_channel *src1)
3172 {
3173 dst->u[0] = src0->u[0] << src1->u[0];
3174 dst->u[1] = src0->u[1] << src1->u[1];
3175 dst->u[2] = src0->u[2] << src1->u[2];
3176 dst->u[3] = src0->u[3] << src1->u[3];
3177 }
3178
3179 static void
3180 micro_and(union tgsi_exec_channel *dst,
3181 const union tgsi_exec_channel *src0,
3182 const union tgsi_exec_channel *src1)
3183 {
3184 dst->u[0] = src0->u[0] & src1->u[0];
3185 dst->u[1] = src0->u[1] & src1->u[1];
3186 dst->u[2] = src0->u[2] & src1->u[2];
3187 dst->u[3] = src0->u[3] & src1->u[3];
3188 }
3189
3190 static void
3191 micro_or(union tgsi_exec_channel *dst,
3192 const union tgsi_exec_channel *src0,
3193 const union tgsi_exec_channel *src1)
3194 {
3195 dst->u[0] = src0->u[0] | src1->u[0];
3196 dst->u[1] = src0->u[1] | src1->u[1];
3197 dst->u[2] = src0->u[2] | src1->u[2];
3198 dst->u[3] = src0->u[3] | src1->u[3];
3199 }
3200
3201 static void
3202 micro_xor(union tgsi_exec_channel *dst,
3203 const union tgsi_exec_channel *src0,
3204 const union tgsi_exec_channel *src1)
3205 {
3206 dst->u[0] = src0->u[0] ^ src1->u[0];
3207 dst->u[1] = src0->u[1] ^ src1->u[1];
3208 dst->u[2] = src0->u[2] ^ src1->u[2];
3209 dst->u[3] = src0->u[3] ^ src1->u[3];
3210 }
3211
3212 static void
3213 micro_mod(union tgsi_exec_channel *dst,
3214 const union tgsi_exec_channel *src0,
3215 const union tgsi_exec_channel *src1)
3216 {
3217 dst->i[0] = src0->i[0] % src1->i[0];
3218 dst->i[1] = src0->i[1] % src1->i[1];
3219 dst->i[2] = src0->i[2] % src1->i[2];
3220 dst->i[3] = src0->i[3] % src1->i[3];
3221 }
3222
3223 static void
3224 micro_f2i(union tgsi_exec_channel *dst,
3225 const union tgsi_exec_channel *src)
3226 {
3227 dst->i[0] = (int)src->f[0];
3228 dst->i[1] = (int)src->f[1];
3229 dst->i[2] = (int)src->f[2];
3230 dst->i[3] = (int)src->f[3];
3231 }
3232
3233 static void
3234 micro_idiv(union tgsi_exec_channel *dst,
3235 const union tgsi_exec_channel *src0,
3236 const union tgsi_exec_channel *src1)
3237 {
3238 dst->i[0] = src0->i[0] / src1->i[0];
3239 dst->i[1] = src0->i[1] / src1->i[1];
3240 dst->i[2] = src0->i[2] / src1->i[2];
3241 dst->i[3] = src0->i[3] / src1->i[3];
3242 }
3243
3244 static void
3245 micro_imax(union tgsi_exec_channel *dst,
3246 const union tgsi_exec_channel *src0,
3247 const union tgsi_exec_channel *src1)
3248 {
3249 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3250 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3251 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3252 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3253 }
3254
3255 static void
3256 micro_imin(union tgsi_exec_channel *dst,
3257 const union tgsi_exec_channel *src0,
3258 const union tgsi_exec_channel *src1)
3259 {
3260 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3261 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3262 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3263 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3264 }
3265
3266 static void
3267 micro_isge(union tgsi_exec_channel *dst,
3268 const union tgsi_exec_channel *src0,
3269 const union tgsi_exec_channel *src1)
3270 {
3271 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3272 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3273 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3274 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3275 }
3276
3277 static void
3278 micro_ishr(union tgsi_exec_channel *dst,
3279 const union tgsi_exec_channel *src0,
3280 const union tgsi_exec_channel *src1)
3281 {
3282 dst->i[0] = src0->i[0] >> src1->i[0];
3283 dst->i[1] = src0->i[1] >> src1->i[1];
3284 dst->i[2] = src0->i[2] >> src1->i[2];
3285 dst->i[3] = src0->i[3] >> src1->i[3];
3286 }
3287
3288 static void
3289 micro_islt(union tgsi_exec_channel *dst,
3290 const union tgsi_exec_channel *src0,
3291 const union tgsi_exec_channel *src1)
3292 {
3293 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3294 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3295 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3296 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3297 }
3298
3299 static void
3300 micro_f2u(union tgsi_exec_channel *dst,
3301 const union tgsi_exec_channel *src)
3302 {
3303 dst->u[0] = (uint)src->f[0];
3304 dst->u[1] = (uint)src->f[1];
3305 dst->u[2] = (uint)src->f[2];
3306 dst->u[3] = (uint)src->f[3];
3307 }
3308
3309 static void
3310 micro_u2f(union tgsi_exec_channel *dst,
3311 const union tgsi_exec_channel *src)
3312 {
3313 dst->f[0] = (float)src->u[0];
3314 dst->f[1] = (float)src->u[1];
3315 dst->f[2] = (float)src->u[2];
3316 dst->f[3] = (float)src->u[3];
3317 }
3318
3319 static void
3320 micro_uadd(union tgsi_exec_channel *dst,
3321 const union tgsi_exec_channel *src0,
3322 const union tgsi_exec_channel *src1)
3323 {
3324 dst->u[0] = src0->u[0] + src1->u[0];
3325 dst->u[1] = src0->u[1] + src1->u[1];
3326 dst->u[2] = src0->u[2] + src1->u[2];
3327 dst->u[3] = src0->u[3] + src1->u[3];
3328 }
3329
3330 static void
3331 micro_udiv(union tgsi_exec_channel *dst,
3332 const union tgsi_exec_channel *src0,
3333 const union tgsi_exec_channel *src1)
3334 {
3335 dst->u[0] = src0->u[0] / src1->u[0];
3336 dst->u[1] = src0->u[1] / src1->u[1];
3337 dst->u[2] = src0->u[2] / src1->u[2];
3338 dst->u[3] = src0->u[3] / src1->u[3];
3339 }
3340
3341 static void
3342 micro_umad(union tgsi_exec_channel *dst,
3343 const union tgsi_exec_channel *src0,
3344 const union tgsi_exec_channel *src1,
3345 const union tgsi_exec_channel *src2)
3346 {
3347 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3348 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3349 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3350 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3351 }
3352
3353 static void
3354 micro_umax(union tgsi_exec_channel *dst,
3355 const union tgsi_exec_channel *src0,
3356 const union tgsi_exec_channel *src1)
3357 {
3358 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3359 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3360 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3361 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3362 }
3363
3364 static void
3365 micro_umin(union tgsi_exec_channel *dst,
3366 const union tgsi_exec_channel *src0,
3367 const union tgsi_exec_channel *src1)
3368 {
3369 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3370 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3371 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3372 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3373 }
3374
3375 static void
3376 micro_umod(union tgsi_exec_channel *dst,
3377 const union tgsi_exec_channel *src0,
3378 const union tgsi_exec_channel *src1)
3379 {
3380 dst->u[0] = src0->u[0] % src1->u[0];
3381 dst->u[1] = src0->u[1] % src1->u[1];
3382 dst->u[2] = src0->u[2] % src1->u[2];
3383 dst->u[3] = src0->u[3] % src1->u[3];
3384 }
3385
3386 static void
3387 micro_umul(union tgsi_exec_channel *dst,
3388 const union tgsi_exec_channel *src0,
3389 const union tgsi_exec_channel *src1)
3390 {
3391 dst->u[0] = src0->u[0] * src1->u[0];
3392 dst->u[1] = src0->u[1] * src1->u[1];
3393 dst->u[2] = src0->u[2] * src1->u[2];
3394 dst->u[3] = src0->u[3] * src1->u[3];
3395 }
3396
3397 static void
3398 micro_useq(union tgsi_exec_channel *dst,
3399 const union tgsi_exec_channel *src0,
3400 const union tgsi_exec_channel *src1)
3401 {
3402 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3403 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3404 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3405 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3406 }
3407
3408 static void
3409 micro_usge(union tgsi_exec_channel *dst,
3410 const union tgsi_exec_channel *src0,
3411 const union tgsi_exec_channel *src1)
3412 {
3413 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3414 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3415 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3416 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3417 }
3418
3419 static void
3420 micro_ushr(union tgsi_exec_channel *dst,
3421 const union tgsi_exec_channel *src0,
3422 const union tgsi_exec_channel *src1)
3423 {
3424 dst->u[0] = src0->u[0] >> src1->u[0];
3425 dst->u[1] = src0->u[1] >> src1->u[1];
3426 dst->u[2] = src0->u[2] >> src1->u[2];
3427 dst->u[3] = src0->u[3] >> src1->u[3];
3428 }
3429
3430 static void
3431 micro_uslt(union tgsi_exec_channel *dst,
3432 const union tgsi_exec_channel *src0,
3433 const union tgsi_exec_channel *src1)
3434 {
3435 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3436 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3437 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3438 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3439 }
3440
3441 static void
3442 micro_usne(union tgsi_exec_channel *dst,
3443 const union tgsi_exec_channel *src0,
3444 const union tgsi_exec_channel *src1)
3445 {
3446 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3447 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3448 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3449 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3450 }
3451
3452 static void
3453 micro_uarl(union tgsi_exec_channel *dst,
3454 const union tgsi_exec_channel *src)
3455 {
3456 dst->i[0] = src->u[0];
3457 dst->i[1] = src->u[1];
3458 dst->i[2] = src->u[2];
3459 dst->i[3] = src->u[3];
3460 }
3461
3462 static void
3463 micro_ucmp(union tgsi_exec_channel *dst,
3464 const union tgsi_exec_channel *src0,
3465 const union tgsi_exec_channel *src1,
3466 const union tgsi_exec_channel *src2)
3467 {
3468 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3469 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3470 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3471 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3472 }
3473
3474 static void
3475 exec_instruction(
3476 struct tgsi_exec_machine *mach,
3477 const struct tgsi_full_instruction *inst,
3478 int *pc )
3479 {
3480 union tgsi_exec_channel r[10];
3481
3482 (*pc)++;
3483
3484 switch (inst->Instruction.Opcode) {
3485 case TGSI_OPCODE_ARL:
3486 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3487 break;
3488
3489 case TGSI_OPCODE_MOV:
3490 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3491 break;
3492
3493 case TGSI_OPCODE_LIT:
3494 exec_lit(mach, inst);
3495 break;
3496
3497 case TGSI_OPCODE_RCP:
3498 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3499 break;
3500
3501 case TGSI_OPCODE_RSQ:
3502 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3503 break;
3504
3505 case TGSI_OPCODE_EXP:
3506 exec_exp(mach, inst);
3507 break;
3508
3509 case TGSI_OPCODE_LOG:
3510 exec_log(mach, inst);
3511 break;
3512
3513 case TGSI_OPCODE_MUL:
3514 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3515 break;
3516
3517 case TGSI_OPCODE_ADD:
3518 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3519 break;
3520
3521 case TGSI_OPCODE_DP3:
3522 exec_dp3(mach, inst);
3523 break;
3524
3525 case TGSI_OPCODE_DP4:
3526 exec_dp4(mach, inst);
3527 break;
3528
3529 case TGSI_OPCODE_DST:
3530 exec_dst(mach, inst);
3531 break;
3532
3533 case TGSI_OPCODE_MIN:
3534 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3535 break;
3536
3537 case TGSI_OPCODE_MAX:
3538 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3539 break;
3540
3541 case TGSI_OPCODE_SLT:
3542 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3543 break;
3544
3545 case TGSI_OPCODE_SGE:
3546 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3547 break;
3548
3549 case TGSI_OPCODE_MAD:
3550 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3551 break;
3552
3553 case TGSI_OPCODE_SUB:
3554 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3555 break;
3556
3557 case TGSI_OPCODE_LRP:
3558 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3559 break;
3560
3561 case TGSI_OPCODE_CND:
3562 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3563 break;
3564
3565 case TGSI_OPCODE_DP2A:
3566 exec_dp2a(mach, inst);
3567 break;
3568
3569 case TGSI_OPCODE_FRC:
3570 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3571 break;
3572
3573 case TGSI_OPCODE_CLAMP:
3574 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3575 break;
3576
3577 case TGSI_OPCODE_FLR:
3578 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3579 break;
3580
3581 case TGSI_OPCODE_ROUND:
3582 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3583 break;
3584
3585 case TGSI_OPCODE_EX2:
3586 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3587 break;
3588
3589 case TGSI_OPCODE_LG2:
3590 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3591 break;
3592
3593 case TGSI_OPCODE_POW:
3594 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3595 break;
3596
3597 case TGSI_OPCODE_XPD:
3598 exec_xpd(mach, inst);
3599 break;
3600
3601 case TGSI_OPCODE_ABS:
3602 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3603 break;
3604
3605 case TGSI_OPCODE_RCC:
3606 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3607 break;
3608
3609 case TGSI_OPCODE_DPH:
3610 exec_dph(mach, inst);
3611 break;
3612
3613 case TGSI_OPCODE_COS:
3614 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3615 break;
3616
3617 case TGSI_OPCODE_DDX:
3618 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3619 break;
3620
3621 case TGSI_OPCODE_DDY:
3622 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3623 break;
3624
3625 case TGSI_OPCODE_KILP:
3626 exec_kilp (mach, inst);
3627 break;
3628
3629 case TGSI_OPCODE_KIL:
3630 exec_kil (mach, inst);
3631 break;
3632
3633 case TGSI_OPCODE_PK2H:
3634 assert (0);
3635 break;
3636
3637 case TGSI_OPCODE_PK2US:
3638 assert (0);
3639 break;
3640
3641 case TGSI_OPCODE_PK4B:
3642 assert (0);
3643 break;
3644
3645 case TGSI_OPCODE_PK4UB:
3646 assert (0);
3647 break;
3648
3649 case TGSI_OPCODE_RFL:
3650 exec_rfl(mach, inst);
3651 break;
3652
3653 case TGSI_OPCODE_SEQ:
3654 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3655 break;
3656
3657 case TGSI_OPCODE_SFL:
3658 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3659 break;
3660
3661 case TGSI_OPCODE_SGT:
3662 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3663 break;
3664
3665 case TGSI_OPCODE_SIN:
3666 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3667 break;
3668
3669 case TGSI_OPCODE_SLE:
3670 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3671 break;
3672
3673 case TGSI_OPCODE_SNE:
3674 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3675 break;
3676
3677 case TGSI_OPCODE_STR:
3678 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3679 break;
3680
3681 case TGSI_OPCODE_TEX:
3682 /* simple texture lookup */
3683 /* src[0] = texcoord */
3684 /* src[1] = sampler unit */
3685 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3686 break;
3687
3688 case TGSI_OPCODE_TXB:
3689 /* Texture lookup with lod bias */
3690 /* src[0] = texcoord (src[0].w = LOD bias) */
3691 /* src[1] = sampler unit */
3692 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3693 break;
3694
3695 case TGSI_OPCODE_TXD:
3696 /* Texture lookup with explict partial derivatives */
3697 /* src[0] = texcoord */
3698 /* src[1] = d[strq]/dx */
3699 /* src[2] = d[strq]/dy */
3700 /* src[3] = sampler unit */
3701 exec_txd(mach, inst);
3702 break;
3703
3704 case TGSI_OPCODE_TXL:
3705 /* Texture lookup with explit LOD */
3706 /* src[0] = texcoord (src[0].w = LOD) */
3707 /* src[1] = sampler unit */
3708 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3709 break;
3710
3711 case TGSI_OPCODE_TXP:
3712 /* Texture lookup with projection */
3713 /* src[0] = texcoord (src[0].w = projection) */
3714 /* src[1] = sampler unit */
3715 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3716 break;
3717
3718 case TGSI_OPCODE_UP2H:
3719 assert (0);
3720 break;
3721
3722 case TGSI_OPCODE_UP2US:
3723 assert (0);
3724 break;
3725
3726 case TGSI_OPCODE_UP4B:
3727 assert (0);
3728 break;
3729
3730 case TGSI_OPCODE_UP4UB:
3731 assert (0);
3732 break;
3733
3734 case TGSI_OPCODE_X2D:
3735 exec_x2d(mach, inst);
3736 break;
3737
3738 case TGSI_OPCODE_ARA:
3739 assert (0);
3740 break;
3741
3742 case TGSI_OPCODE_ARR:
3743 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3744 break;
3745
3746 case TGSI_OPCODE_BRA:
3747 assert (0);
3748 break;
3749
3750 case TGSI_OPCODE_CAL:
3751 /* skip the call if no execution channels are enabled */
3752 if (mach->ExecMask) {
3753 /* do the call */
3754
3755 /* First, record the depths of the execution stacks.
3756 * This is important for deeply nested/looped return statements.
3757 * We have to unwind the stacks by the correct amount. For a
3758 * real code generator, we could determine the number of entries
3759 * to pop off each stack with simple static analysis and avoid
3760 * implementing this data structure at run time.
3761 */
3762 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3763 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3764 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3765 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3766 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3767 /* note that PC was already incremented above */
3768 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3769
3770 mach->CallStackTop++;
3771
3772 /* Second, push the Cond, Loop, Cont, Func stacks */
3773 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3774 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3775 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3776 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3777 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3778 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3779
3780 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3781 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3782 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3783 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3784 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3785 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3786
3787 /* Finally, jump to the subroutine */
3788 *pc = inst->Label.Label;
3789 }
3790 break;
3791
3792 case TGSI_OPCODE_RET:
3793 mach->FuncMask &= ~mach->ExecMask;
3794 UPDATE_EXEC_MASK(mach);
3795
3796 if (mach->FuncMask == 0x0) {
3797 /* really return now (otherwise, keep executing */
3798
3799 if (mach->CallStackTop == 0) {
3800 /* returning from main() */
3801 mach->CondStackTop = 0;
3802 mach->LoopStackTop = 0;
3803 *pc = -1;
3804 return;
3805 }
3806
3807 assert(mach->CallStackTop > 0);
3808 mach->CallStackTop--;
3809
3810 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3811 mach->CondMask = mach->CondStack[mach->CondStackTop];
3812
3813 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3814 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3815
3816 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3817 mach->ContMask = mach->ContStack[mach->ContStackTop];
3818
3819 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3820 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3821
3822 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3823 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3824
3825 assert(mach->FuncStackTop > 0);
3826 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3827
3828 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3829
3830 UPDATE_EXEC_MASK(mach);
3831 }
3832 break;
3833
3834 case TGSI_OPCODE_SSG:
3835 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3836 break;
3837
3838 case TGSI_OPCODE_CMP:
3839 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3840 break;
3841
3842 case TGSI_OPCODE_SCS:
3843 exec_scs(mach, inst);
3844 break;
3845
3846 case TGSI_OPCODE_NRM:
3847 exec_nrm3(mach, inst);
3848 break;
3849
3850 case TGSI_OPCODE_NRM4:
3851 exec_nrm4(mach, inst);
3852 break;
3853
3854 case TGSI_OPCODE_DIV:
3855 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3856 break;
3857
3858 case TGSI_OPCODE_DP2:
3859 exec_dp2(mach, inst);
3860 break;
3861
3862 case TGSI_OPCODE_IF:
3863 /* push CondMask */
3864 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3865 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3866 FETCH( &r[0], 0, TGSI_CHAN_X );
3867 /* update CondMask */
3868 if( ! r[0].u[0] ) {
3869 mach->CondMask &= ~0x1;
3870 }
3871 if( ! r[0].u[1] ) {
3872 mach->CondMask &= ~0x2;
3873 }
3874 if( ! r[0].u[2] ) {
3875 mach->CondMask &= ~0x4;
3876 }
3877 if( ! r[0].u[3] ) {
3878 mach->CondMask &= ~0x8;
3879 }
3880 UPDATE_EXEC_MASK(mach);
3881 /* Todo: If CondMask==0, jump to ELSE */
3882 break;
3883
3884 case TGSI_OPCODE_ELSE:
3885 /* invert CondMask wrt previous mask */
3886 {
3887 uint prevMask;
3888 assert(mach->CondStackTop > 0);
3889 prevMask = mach->CondStack[mach->CondStackTop - 1];
3890 mach->CondMask = ~mach->CondMask & prevMask;
3891 UPDATE_EXEC_MASK(mach);
3892 /* Todo: If CondMask==0, jump to ENDIF */
3893 }
3894 break;
3895
3896 case TGSI_OPCODE_ENDIF:
3897 /* pop CondMask */
3898 assert(mach->CondStackTop > 0);
3899 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3900 UPDATE_EXEC_MASK(mach);
3901 break;
3902
3903 case TGSI_OPCODE_END:
3904 /* make sure we end primitives which haven't
3905 * been explicitly emitted */
3906 conditional_emit_primitive(mach);
3907 /* halt execution */
3908 *pc = -1;
3909 break;
3910
3911 case TGSI_OPCODE_PUSHA:
3912 assert (0);
3913 break;
3914
3915 case TGSI_OPCODE_POPA:
3916 assert (0);
3917 break;
3918
3919 case TGSI_OPCODE_CEIL:
3920 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3921 break;
3922
3923 case TGSI_OPCODE_I2F:
3924 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3925 break;
3926
3927 case TGSI_OPCODE_NOT:
3928 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3929 break;
3930
3931 case TGSI_OPCODE_TRUNC:
3932 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3933 break;
3934
3935 case TGSI_OPCODE_SHL:
3936 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3937 break;
3938
3939 case TGSI_OPCODE_AND:
3940 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3941 break;
3942
3943 case TGSI_OPCODE_OR:
3944 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3945 break;
3946
3947 case TGSI_OPCODE_MOD:
3948 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3949 break;
3950
3951 case TGSI_OPCODE_XOR:
3952 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3953 break;
3954
3955 case TGSI_OPCODE_SAD:
3956 assert (0);
3957 break;
3958
3959 case TGSI_OPCODE_TXF:
3960 exec_txf(mach, inst);
3961 break;
3962
3963 case TGSI_OPCODE_TXQ:
3964 exec_txq(mach, inst);
3965 break;
3966
3967 case TGSI_OPCODE_EMIT:
3968 emit_vertex(mach);
3969 break;
3970
3971 case TGSI_OPCODE_ENDPRIM:
3972 emit_primitive(mach);
3973 break;
3974
3975 case TGSI_OPCODE_BGNLOOP:
3976 /* push LoopMask and ContMasks */
3977 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3978 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3979 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3980 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3981
3982 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3983 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3984 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3985 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3986 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3987 break;
3988
3989 case TGSI_OPCODE_ENDLOOP:
3990 /* Restore ContMask, but don't pop */
3991 assert(mach->ContStackTop > 0);
3992 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3993 UPDATE_EXEC_MASK(mach);
3994 if (mach->ExecMask) {
3995 /* repeat loop: jump to instruction just past BGNLOOP */
3996 assert(mach->LoopLabelStackTop > 0);
3997 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3998 }
3999 else {
4000 /* exit loop: pop LoopMask */
4001 assert(mach->LoopStackTop > 0);
4002 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4003 /* pop ContMask */
4004 assert(mach->ContStackTop > 0);
4005 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4006 assert(mach->LoopLabelStackTop > 0);
4007 --mach->LoopLabelStackTop;
4008
4009 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4010 }
4011 UPDATE_EXEC_MASK(mach);
4012 break;
4013
4014 case TGSI_OPCODE_BRK:
4015 exec_break(mach);
4016 break;
4017
4018 case TGSI_OPCODE_CONT:
4019 /* turn off cont channels for each enabled exec channel */
4020 mach->ContMask &= ~mach->ExecMask;
4021 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4022 UPDATE_EXEC_MASK(mach);
4023 break;
4024
4025 case TGSI_OPCODE_BGNSUB:
4026 /* no-op */
4027 break;
4028
4029 case TGSI_OPCODE_ENDSUB:
4030 /*
4031 * XXX: This really should be a no-op. We should never reach this opcode.
4032 */
4033
4034 assert(mach->CallStackTop > 0);
4035 mach->CallStackTop--;
4036
4037 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4038 mach->CondMask = mach->CondStack[mach->CondStackTop];
4039
4040 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4041 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4042
4043 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4044 mach->ContMask = mach->ContStack[mach->ContStackTop];
4045
4046 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4047 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4048
4049 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4050 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4051
4052 assert(mach->FuncStackTop > 0);
4053 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4054
4055 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4056
4057 UPDATE_EXEC_MASK(mach);
4058 break;
4059
4060 case TGSI_OPCODE_NOP:
4061 break;
4062
4063 case TGSI_OPCODE_BREAKC:
4064 FETCH(&r[0], 0, TGSI_CHAN_X);
4065 /* update CondMask */
4066 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4067 mach->LoopMask &= ~0x1;
4068 }
4069 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4070 mach->LoopMask &= ~0x2;
4071 }
4072 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4073 mach->LoopMask &= ~0x4;
4074 }
4075 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4076 mach->LoopMask &= ~0x8;
4077 }
4078 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4079 UPDATE_EXEC_MASK(mach);
4080 break;
4081
4082 case TGSI_OPCODE_F2I:
4083 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4084 break;
4085
4086 case TGSI_OPCODE_IDIV:
4087 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4088 break;
4089
4090 case TGSI_OPCODE_IMAX:
4091 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4092 break;
4093
4094 case TGSI_OPCODE_IMIN:
4095 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4096 break;
4097
4098 case TGSI_OPCODE_INEG:
4099 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4100 break;
4101
4102 case TGSI_OPCODE_ISGE:
4103 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4104 break;
4105
4106 case TGSI_OPCODE_ISHR:
4107 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4108 break;
4109
4110 case TGSI_OPCODE_ISLT:
4111 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4112 break;
4113
4114 case TGSI_OPCODE_F2U:
4115 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4116 break;
4117
4118 case TGSI_OPCODE_U2F:
4119 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4120 break;
4121
4122 case TGSI_OPCODE_UADD:
4123 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4124 break;
4125
4126 case TGSI_OPCODE_UDIV:
4127 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4128 break;
4129
4130 case TGSI_OPCODE_UMAD:
4131 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4132 break;
4133
4134 case TGSI_OPCODE_UMAX:
4135 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4136 break;
4137
4138 case TGSI_OPCODE_UMIN:
4139 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4140 break;
4141
4142 case TGSI_OPCODE_UMOD:
4143 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4144 break;
4145
4146 case TGSI_OPCODE_UMUL:
4147 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4148 break;
4149
4150 case TGSI_OPCODE_USEQ:
4151 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4152 break;
4153
4154 case TGSI_OPCODE_USGE:
4155 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4156 break;
4157
4158 case TGSI_OPCODE_USHR:
4159 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4160 break;
4161
4162 case TGSI_OPCODE_USLT:
4163 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4164 break;
4165
4166 case TGSI_OPCODE_USNE:
4167 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4168 break;
4169
4170 case TGSI_OPCODE_SWITCH:
4171 exec_switch(mach, inst);
4172 break;
4173
4174 case TGSI_OPCODE_CASE:
4175 exec_case(mach, inst);
4176 break;
4177
4178 case TGSI_OPCODE_DEFAULT:
4179 exec_default(mach);
4180 break;
4181
4182 case TGSI_OPCODE_ENDSWITCH:
4183 exec_endswitch(mach);
4184 break;
4185
4186 case TGSI_OPCODE_SAMPLE_I:
4187 assert(0);
4188 break;
4189
4190 case TGSI_OPCODE_SAMPLE_I_MS:
4191 assert(0);
4192 break;
4193
4194 case TGSI_OPCODE_SAMPLE:
4195 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4196 break;
4197
4198 case TGSI_OPCODE_SAMPLE_B:
4199 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4200 break;
4201
4202 case TGSI_OPCODE_SAMPLE_C:
4203 exec_sample(mach, inst, TEX_MODIFIER_NONE);
4204 break;
4205
4206 case TGSI_OPCODE_SAMPLE_C_LZ:
4207 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
4208 break;
4209
4210 case TGSI_OPCODE_SAMPLE_D:
4211 exec_sample_d(mach, inst);
4212 break;
4213
4214 case TGSI_OPCODE_SAMPLE_L:
4215 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
4216 break;
4217
4218 case TGSI_OPCODE_GATHER4:
4219 assert(0);
4220 break;
4221
4222 case TGSI_OPCODE_SVIEWINFO:
4223 assert(0);
4224 break;
4225
4226 case TGSI_OPCODE_SAMPLE_POS:
4227 assert(0);
4228 break;
4229
4230 case TGSI_OPCODE_SAMPLE_INFO:
4231 assert(0);
4232 break;
4233
4234 case TGSI_OPCODE_UARL:
4235 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4236 break;
4237
4238 case TGSI_OPCODE_UCMP:
4239 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4240 break;
4241
4242 case TGSI_OPCODE_IABS:
4243 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4244 break;
4245
4246 case TGSI_OPCODE_ISSG:
4247 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4248 break;
4249
4250 case TGSI_OPCODE_TEX2:
4251 /* simple texture lookup */
4252 /* src[0] = texcoord */
4253 /* src[1] = compare */
4254 /* src[2] = sampler unit */
4255 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4256 break;
4257 case TGSI_OPCODE_TXB2:
4258 /* simple texture lookup */
4259 /* src[0] = texcoord */
4260 /* src[1] = bias */
4261 /* src[2] = sampler unit */
4262 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4263 break;
4264 case TGSI_OPCODE_TXL2:
4265 /* simple texture lookup */
4266 /* src[0] = texcoord */
4267 /* src[1] = lod */
4268 /* src[2] = sampler unit */
4269 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4270 break;
4271 default:
4272 assert( 0 );
4273 }
4274 }
4275
4276
4277 #define DEBUG_EXECUTION 0
4278
4279
4280 /**
4281 * Run TGSI interpreter.
4282 * \return bitmask of "alive" quad components
4283 */
4284 uint
4285 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4286 {
4287 uint i;
4288 int pc = 0;
4289
4290 mach->CondMask = 0xf;
4291 mach->LoopMask = 0xf;
4292 mach->ContMask = 0xf;
4293 mach->FuncMask = 0xf;
4294 mach->ExecMask = 0xf;
4295
4296 mach->Switch.mask = 0xf;
4297
4298 assert(mach->CondStackTop == 0);
4299 assert(mach->LoopStackTop == 0);
4300 assert(mach->ContStackTop == 0);
4301 assert(mach->SwitchStackTop == 0);
4302 assert(mach->BreakStackTop == 0);
4303 assert(mach->CallStackTop == 0);
4304
4305 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4306 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4307
4308 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4309 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4310 mach->Primitives[0] = 0;
4311 }
4312
4313 /* execute declarations (interpolants) */
4314 for (i = 0; i < mach->NumDeclarations; i++) {
4315 exec_declaration( mach, mach->Declarations+i );
4316 }
4317
4318 {
4319 #if DEBUG_EXECUTION
4320 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4321 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4322 uint inst = 1;
4323
4324 memcpy(temps, mach->Temps, sizeof(temps));
4325 memcpy(outputs, mach->Outputs, sizeof(outputs));
4326 #endif
4327
4328 /* execute instructions, until pc is set to -1 */
4329 while (pc != -1) {
4330
4331 #if DEBUG_EXECUTION
4332 uint i;
4333
4334 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4335 #endif
4336
4337 assert(pc < (int) mach->NumInstructions);
4338 exec_instruction(mach, mach->Instructions + pc, &pc);
4339
4340 #if DEBUG_EXECUTION
4341 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4342 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4343 uint j;
4344
4345 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4346 debug_printf("TEMP[%2u] = ", i);
4347 for (j = 0; j < 4; j++) {
4348 if (j > 0) {
4349 debug_printf(" ");
4350 }
4351 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4352 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4353 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4354 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4355 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4356 }
4357 }
4358 }
4359 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4360 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4361 uint j;
4362
4363 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4364 debug_printf("OUT[%2u] = ", i);
4365 for (j = 0; j < 4; j++) {
4366 if (j > 0) {
4367 debug_printf(" ");
4368 }
4369 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4370 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4371 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4372 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4373 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4374 }
4375 }
4376 }
4377 #endif
4378 }
4379 }
4380
4381 #if 0
4382 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4383 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4384 /*
4385 * Scale back depth component.
4386 */
4387 for (i = 0; i < 4; i++)
4388 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4389 }
4390 #endif
4391
4392 /* Strictly speaking, these assertions aren't really needed but they
4393 * can potentially catch some bugs in the control flow code.
4394 */
4395 assert(mach->CondStackTop == 0);
4396 assert(mach->LoopStackTop == 0);
4397 assert(mach->ContStackTop == 0);
4398 assert(mach->SwitchStackTop == 0);
4399 assert(mach->BreakStackTop == 0);
4400 assert(mach->CallStackTop == 0);
4401
4402 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4403 }