1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
66 #define DEBUG_EXECUTION 0
71 #define TILE_TOP_LEFT 0
72 #define TILE_TOP_RIGHT 1
73 #define TILE_BOTTOM_LEFT 2
74 #define TILE_BOTTOM_RIGHT 3
76 union tgsi_double_channel
{
77 double d
[TGSI_QUAD_SIZE
];
78 unsigned u
[TGSI_QUAD_SIZE
][2];
81 struct tgsi_double_vector
{
82 union tgsi_double_channel xy
;
83 union tgsi_double_channel zw
;
87 micro_abs(union tgsi_exec_channel
*dst
,
88 const union tgsi_exec_channel
*src
)
90 dst
->f
[0] = fabsf(src
->f
[0]);
91 dst
->f
[1] = fabsf(src
->f
[1]);
92 dst
->f
[2] = fabsf(src
->f
[2]);
93 dst
->f
[3] = fabsf(src
->f
[3]);
97 micro_arl(union tgsi_exec_channel
*dst
,
98 const union tgsi_exec_channel
*src
)
100 dst
->i
[0] = (int)floorf(src
->f
[0]);
101 dst
->i
[1] = (int)floorf(src
->f
[1]);
102 dst
->i
[2] = (int)floorf(src
->f
[2]);
103 dst
->i
[3] = (int)floorf(src
->f
[3]);
107 micro_arr(union tgsi_exec_channel
*dst
,
108 const union tgsi_exec_channel
*src
)
110 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
111 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
112 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
113 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
117 micro_ceil(union tgsi_exec_channel
*dst
,
118 const union tgsi_exec_channel
*src
)
120 dst
->f
[0] = ceilf(src
->f
[0]);
121 dst
->f
[1] = ceilf(src
->f
[1]);
122 dst
->f
[2] = ceilf(src
->f
[2]);
123 dst
->f
[3] = ceilf(src
->f
[3]);
127 micro_clamp(union tgsi_exec_channel
*dst
,
128 const union tgsi_exec_channel
*src0
,
129 const union tgsi_exec_channel
*src1
,
130 const union tgsi_exec_channel
*src2
)
132 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
133 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
134 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
135 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
139 micro_cmp(union tgsi_exec_channel
*dst
,
140 const union tgsi_exec_channel
*src0
,
141 const union tgsi_exec_channel
*src1
,
142 const union tgsi_exec_channel
*src2
)
144 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
145 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
146 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
147 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
151 micro_cos(union tgsi_exec_channel
*dst
,
152 const union tgsi_exec_channel
*src
)
154 dst
->f
[0] = cosf(src
->f
[0]);
155 dst
->f
[1] = cosf(src
->f
[1]);
156 dst
->f
[2] = cosf(src
->f
[2]);
157 dst
->f
[3] = cosf(src
->f
[3]);
161 micro_d2f(union tgsi_exec_channel
*dst
,
162 const union tgsi_double_channel
*src
)
164 dst
->f
[0] = (float)src
->d
[0];
165 dst
->f
[1] = (float)src
->d
[1];
166 dst
->f
[2] = (float)src
->d
[2];
167 dst
->f
[3] = (float)src
->d
[3];
171 micro_d2i(union tgsi_exec_channel
*dst
,
172 const union tgsi_double_channel
*src
)
174 dst
->i
[0] = (int)src
->d
[0];
175 dst
->i
[1] = (int)src
->d
[1];
176 dst
->i
[2] = (int)src
->d
[2];
177 dst
->i
[3] = (int)src
->d
[3];
181 micro_d2u(union tgsi_exec_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->u
[0] = (unsigned)src
->d
[0];
185 dst
->u
[1] = (unsigned)src
->d
[1];
186 dst
->u
[2] = (unsigned)src
->d
[2];
187 dst
->u
[3] = (unsigned)src
->d
[3];
190 micro_dabs(union tgsi_double_channel
*dst
,
191 const union tgsi_double_channel
*src
)
193 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
194 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
195 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
196 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
200 micro_dadd(union tgsi_double_channel
*dst
,
201 const union tgsi_double_channel
*src
)
203 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
204 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
205 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
206 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
210 micro_ddx(union tgsi_exec_channel
*dst
,
211 const union tgsi_exec_channel
*src
)
216 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
220 micro_ddy(union tgsi_exec_channel
*dst
,
221 const union tgsi_exec_channel
*src
)
226 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
230 micro_dmul(union tgsi_double_channel
*dst
,
231 const union tgsi_double_channel
*src
)
233 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
234 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
235 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
236 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
240 micro_dmax(union tgsi_double_channel
*dst
,
241 const union tgsi_double_channel
*src
)
243 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
244 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
245 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
246 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
250 micro_dmin(union tgsi_double_channel
*dst
,
251 const union tgsi_double_channel
*src
)
253 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
254 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
255 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
256 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
260 micro_dneg(union tgsi_double_channel
*dst
,
261 const union tgsi_double_channel
*src
)
263 dst
->d
[0] = -src
->d
[0];
264 dst
->d
[1] = -src
->d
[1];
265 dst
->d
[2] = -src
->d
[2];
266 dst
->d
[3] = -src
->d
[3];
270 micro_dslt(union tgsi_double_channel
*dst
,
271 const union tgsi_double_channel
*src
)
273 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
274 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
275 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
276 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
280 micro_dsne(union tgsi_double_channel
*dst
,
281 const union tgsi_double_channel
*src
)
283 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
284 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
285 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
286 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
290 micro_dsge(union tgsi_double_channel
*dst
,
291 const union tgsi_double_channel
*src
)
293 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
294 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
295 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
296 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
300 micro_dseq(union tgsi_double_channel
*dst
,
301 const union tgsi_double_channel
*src
)
303 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
304 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
305 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
306 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
310 micro_drcp(union tgsi_double_channel
*dst
,
311 const union tgsi_double_channel
*src
)
313 dst
->d
[0] = 1.0 / src
->d
[0];
314 dst
->d
[1] = 1.0 / src
->d
[1];
315 dst
->d
[2] = 1.0 / src
->d
[2];
316 dst
->d
[3] = 1.0 / src
->d
[3];
320 micro_dsqrt(union tgsi_double_channel
*dst
,
321 const union tgsi_double_channel
*src
)
323 dst
->d
[0] = sqrt(src
->d
[0]);
324 dst
->d
[1] = sqrt(src
->d
[1]);
325 dst
->d
[2] = sqrt(src
->d
[2]);
326 dst
->d
[3] = sqrt(src
->d
[3]);
330 micro_drsq(union tgsi_double_channel
*dst
,
331 const union tgsi_double_channel
*src
)
333 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
334 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
335 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
336 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
340 micro_dmad(union tgsi_double_channel
*dst
,
341 const union tgsi_double_channel
*src
)
343 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
344 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
345 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
346 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
350 micro_dfrac(union tgsi_double_channel
*dst
,
351 const union tgsi_double_channel
*src
)
353 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
354 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
355 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
356 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
360 micro_dldexp(union tgsi_double_channel
*dst
,
361 const union tgsi_double_channel
*src0
,
362 union tgsi_exec_channel
*src1
)
364 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
365 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
366 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
367 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
371 micro_dfracexp(union tgsi_double_channel
*dst
,
372 union tgsi_exec_channel
*dst_exp
,
373 const union tgsi_double_channel
*src
)
375 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
376 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
377 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
378 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
382 micro_exp2(union tgsi_exec_channel
*dst
,
383 const union tgsi_exec_channel
*src
)
386 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
387 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
388 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
389 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
392 /* Inf is okay for this instruction, so clamp it to silence assertions. */
394 union tgsi_exec_channel clamped
;
396 for (i
= 0; i
< 4; i
++) {
397 if (src
->f
[i
] > 127.99999f
) {
398 clamped
.f
[i
] = 127.99999f
;
399 } else if (src
->f
[i
] < -126.99999f
) {
400 clamped
.f
[i
] = -126.99999f
;
402 clamped
.f
[i
] = src
->f
[i
];
408 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
409 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
410 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
411 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
412 #endif /* FAST_MATH */
416 micro_f2d(union tgsi_double_channel
*dst
,
417 const union tgsi_exec_channel
*src
)
419 dst
->d
[0] = (double)src
->f
[0];
420 dst
->d
[1] = (double)src
->f
[1];
421 dst
->d
[2] = (double)src
->f
[2];
422 dst
->d
[3] = (double)src
->f
[3];
426 micro_flr(union tgsi_exec_channel
*dst
,
427 const union tgsi_exec_channel
*src
)
429 dst
->f
[0] = floorf(src
->f
[0]);
430 dst
->f
[1] = floorf(src
->f
[1]);
431 dst
->f
[2] = floorf(src
->f
[2]);
432 dst
->f
[3] = floorf(src
->f
[3]);
436 micro_frc(union tgsi_exec_channel
*dst
,
437 const union tgsi_exec_channel
*src
)
439 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
440 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
441 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
442 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
446 micro_i2d(union tgsi_double_channel
*dst
,
447 const union tgsi_exec_channel
*src
)
449 dst
->d
[0] = (double)src
->i
[0];
450 dst
->d
[1] = (double)src
->i
[1];
451 dst
->d
[2] = (double)src
->i
[2];
452 dst
->d
[3] = (double)src
->i
[3];
456 micro_iabs(union tgsi_exec_channel
*dst
,
457 const union tgsi_exec_channel
*src
)
459 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
460 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
461 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
462 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
466 micro_ineg(union tgsi_exec_channel
*dst
,
467 const union tgsi_exec_channel
*src
)
469 dst
->i
[0] = -src
->i
[0];
470 dst
->i
[1] = -src
->i
[1];
471 dst
->i
[2] = -src
->i
[2];
472 dst
->i
[3] = -src
->i
[3];
476 micro_lg2(union tgsi_exec_channel
*dst
,
477 const union tgsi_exec_channel
*src
)
480 dst
->f
[0] = util_fast_log2(src
->f
[0]);
481 dst
->f
[1] = util_fast_log2(src
->f
[1]);
482 dst
->f
[2] = util_fast_log2(src
->f
[2]);
483 dst
->f
[3] = util_fast_log2(src
->f
[3]);
485 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
486 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
487 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
488 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
493 micro_lrp(union tgsi_exec_channel
*dst
,
494 const union tgsi_exec_channel
*src0
,
495 const union tgsi_exec_channel
*src1
,
496 const union tgsi_exec_channel
*src2
)
498 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
499 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
500 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
501 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
505 micro_mad(union tgsi_exec_channel
*dst
,
506 const union tgsi_exec_channel
*src0
,
507 const union tgsi_exec_channel
*src1
,
508 const union tgsi_exec_channel
*src2
)
510 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
511 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
512 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
513 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
517 micro_mov(union tgsi_exec_channel
*dst
,
518 const union tgsi_exec_channel
*src
)
520 dst
->u
[0] = src
->u
[0];
521 dst
->u
[1] = src
->u
[1];
522 dst
->u
[2] = src
->u
[2];
523 dst
->u
[3] = src
->u
[3];
527 micro_rcp(union tgsi_exec_channel
*dst
,
528 const union tgsi_exec_channel
*src
)
530 #if 0 /* for debugging */
531 assert(src
->f
[0] != 0.0f
);
532 assert(src
->f
[1] != 0.0f
);
533 assert(src
->f
[2] != 0.0f
);
534 assert(src
->f
[3] != 0.0f
);
536 dst
->f
[0] = 1.0f
/ src
->f
[0];
537 dst
->f
[1] = 1.0f
/ src
->f
[1];
538 dst
->f
[2] = 1.0f
/ src
->f
[2];
539 dst
->f
[3] = 1.0f
/ src
->f
[3];
543 micro_rnd(union tgsi_exec_channel
*dst
,
544 const union tgsi_exec_channel
*src
)
546 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
547 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
548 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
549 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
553 micro_rsq(union tgsi_exec_channel
*dst
,
554 const union tgsi_exec_channel
*src
)
556 #if 0 /* for debugging */
557 assert(src
->f
[0] != 0.0f
);
558 assert(src
->f
[1] != 0.0f
);
559 assert(src
->f
[2] != 0.0f
);
560 assert(src
->f
[3] != 0.0f
);
562 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
563 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
564 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
565 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
569 micro_sqrt(union tgsi_exec_channel
*dst
,
570 const union tgsi_exec_channel
*src
)
572 dst
->f
[0] = sqrtf(src
->f
[0]);
573 dst
->f
[1] = sqrtf(src
->f
[1]);
574 dst
->f
[2] = sqrtf(src
->f
[2]);
575 dst
->f
[3] = sqrtf(src
->f
[3]);
579 micro_seq(union tgsi_exec_channel
*dst
,
580 const union tgsi_exec_channel
*src0
,
581 const union tgsi_exec_channel
*src1
)
583 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
584 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
585 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
586 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
590 micro_sge(union tgsi_exec_channel
*dst
,
591 const union tgsi_exec_channel
*src0
,
592 const union tgsi_exec_channel
*src1
)
594 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
595 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
596 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
597 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
601 micro_sgn(union tgsi_exec_channel
*dst
,
602 const union tgsi_exec_channel
*src
)
604 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
605 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
611 micro_isgn(union tgsi_exec_channel
*dst
,
612 const union tgsi_exec_channel
*src
)
614 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
615 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
616 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
617 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
621 micro_sgt(union tgsi_exec_channel
*dst
,
622 const union tgsi_exec_channel
*src0
,
623 const union tgsi_exec_channel
*src1
)
625 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
626 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
627 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
628 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
632 micro_sin(union tgsi_exec_channel
*dst
,
633 const union tgsi_exec_channel
*src
)
635 dst
->f
[0] = sinf(src
->f
[0]);
636 dst
->f
[1] = sinf(src
->f
[1]);
637 dst
->f
[2] = sinf(src
->f
[2]);
638 dst
->f
[3] = sinf(src
->f
[3]);
642 micro_sle(union tgsi_exec_channel
*dst
,
643 const union tgsi_exec_channel
*src0
,
644 const union tgsi_exec_channel
*src1
)
646 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
647 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
648 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
649 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
653 micro_slt(union tgsi_exec_channel
*dst
,
654 const union tgsi_exec_channel
*src0
,
655 const union tgsi_exec_channel
*src1
)
657 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
658 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
659 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
660 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
664 micro_sne(union tgsi_exec_channel
*dst
,
665 const union tgsi_exec_channel
*src0
,
666 const union tgsi_exec_channel
*src1
)
668 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
669 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
670 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
671 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
675 micro_trunc(union tgsi_exec_channel
*dst
,
676 const union tgsi_exec_channel
*src
)
678 dst
->f
[0] = (float)(int)src
->f
[0];
679 dst
->f
[1] = (float)(int)src
->f
[1];
680 dst
->f
[2] = (float)(int)src
->f
[2];
681 dst
->f
[3] = (float)(int)src
->f
[3];
685 micro_u2d(union tgsi_double_channel
*dst
,
686 const union tgsi_exec_channel
*src
)
688 dst
->d
[0] = (double)src
->u
[0];
689 dst
->d
[1] = (double)src
->u
[1];
690 dst
->d
[2] = (double)src
->u
[2];
691 dst
->d
[3] = (double)src
->u
[3];
694 enum tgsi_exec_datatype
{
695 TGSI_EXEC_DATA_FLOAT
,
698 TGSI_EXEC_DATA_DOUBLE
702 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
704 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
705 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
706 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
707 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
708 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
709 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
712 /** The execution mask depends on the conditional mask and the loop mask */
713 #define UPDATE_EXEC_MASK(MACH) \
714 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
717 static const union tgsi_exec_channel ZeroVec
=
718 { { 0.0, 0.0, 0.0, 0.0 } };
720 static const union tgsi_exec_channel OneVec
= {
721 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
724 static const union tgsi_exec_channel P128Vec
= {
725 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
728 static const union tgsi_exec_channel M128Vec
= {
729 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
734 * Assert that none of the float values in 'chan' are infinite or NaN.
735 * NaN and Inf may occur normally during program execution and should
736 * not lead to crashes, etc. But when debugging, it's helpful to catch
740 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
742 assert(!util_is_inf_or_nan((chan
)->f
[0]));
743 assert(!util_is_inf_or_nan((chan
)->f
[1]));
744 assert(!util_is_inf_or_nan((chan
)->f
[2]));
745 assert(!util_is_inf_or_nan((chan
)->f
[3]));
751 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
753 debug_printf("%s = {%f, %f, %f, %f}\n",
754 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
761 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
763 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
765 debug_printf("Temp[%u] =\n", index
);
766 for (i
= 0; i
< 4; i
++) {
767 debug_printf(" %c: { %f, %f, %f, %f }\n",
779 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
782 const unsigned *buf_sizes
)
786 for (i
= 0; i
< num_bufs
; i
++) {
787 mach
->Consts
[i
] = bufs
[i
];
788 mach
->ConstsSize
[i
] = buf_sizes
[i
];
794 * Check if there's a potential src/dst register data dependency when
795 * using SOA execution.
798 * This would expand into:
803 * The second instruction will have the wrong value for t0 if executed as-is.
806 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
810 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
811 if (writemask
== TGSI_WRITEMASK_X
||
812 writemask
== TGSI_WRITEMASK_Y
||
813 writemask
== TGSI_WRITEMASK_Z
||
814 writemask
== TGSI_WRITEMASK_W
||
815 writemask
== TGSI_WRITEMASK_NONE
) {
816 /* no chance of data dependency */
820 /* loop over src regs */
821 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
822 if ((inst
->Src
[i
].Register
.File
==
823 inst
->Dst
[0].Register
.File
) &&
824 ((inst
->Src
[i
].Register
.Index
==
825 inst
->Dst
[0].Register
.Index
) ||
826 inst
->Src
[i
].Register
.Indirect
||
827 inst
->Dst
[0].Register
.Indirect
)) {
828 /* loop over dest channels */
829 uint channelsWritten
= 0x0;
830 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
831 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
832 /* check if we're reading a channel that's been written */
833 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
834 if (channelsWritten
& (1 << swizzle
)) {
838 channelsWritten
|= (1 << chan
);
848 * Initialize machine state by expanding tokens to full instructions,
849 * allocating temporary storage, setting up constants, etc.
850 * After this, we can call tgsi_exec_machine_run() many times.
853 tgsi_exec_machine_bind_shader(
854 struct tgsi_exec_machine
*mach
,
855 const struct tgsi_token
*tokens
,
856 struct tgsi_sampler
*sampler
,
857 struct tgsi_image
*image
,
858 struct tgsi_buffer
*buffer
)
861 struct tgsi_parse_context parse
;
862 struct tgsi_full_instruction
*instructions
;
863 struct tgsi_full_declaration
*declarations
;
864 uint maxInstructions
= 10, numInstructions
= 0;
865 uint maxDeclarations
= 10, numDeclarations
= 0;
868 tgsi_dump(tokens
, 0);
874 mach
->Tokens
= tokens
;
875 mach
->Sampler
= sampler
;
877 mach
->Buffer
= buffer
;
880 /* unbind and free all */
881 FREE(mach
->Declarations
);
882 mach
->Declarations
= NULL
;
883 mach
->NumDeclarations
= 0;
885 FREE(mach
->Instructions
);
886 mach
->Instructions
= NULL
;
887 mach
->NumInstructions
= 0;
892 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
893 if (k
!= TGSI_PARSE_OK
) {
894 debug_printf( "Problem parsing!\n" );
898 mach
->Processor
= parse
.FullHeader
.Processor
.Processor
;
900 mach
->NumOutputs
= 0;
902 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
&&
903 !mach
->UsedGeometryShader
) {
904 struct tgsi_exec_vector
*inputs
;
905 struct tgsi_exec_vector
*outputs
;
907 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
908 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
914 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
915 TGSI_MAX_TOTAL_VERTICES
, 16);
922 align_free(mach
->Inputs
);
923 align_free(mach
->Outputs
);
925 mach
->Inputs
= inputs
;
926 mach
->Outputs
= outputs
;
927 mach
->UsedGeometryShader
= TRUE
;
930 declarations
= (struct tgsi_full_declaration
*)
931 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
937 instructions
= (struct tgsi_full_instruction
*)
938 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
941 FREE( declarations
);
945 while( !tgsi_parse_end_of_tokens( &parse
) ) {
948 tgsi_parse_token( &parse
);
949 switch( parse
.FullToken
.Token
.Type
) {
950 case TGSI_TOKEN_TYPE_DECLARATION
:
951 /* save expanded declaration */
952 if (numDeclarations
== maxDeclarations
) {
953 declarations
= REALLOC(declarations
,
955 * sizeof(struct tgsi_full_declaration
),
956 (maxDeclarations
+ 10)
957 * sizeof(struct tgsi_full_declaration
));
958 maxDeclarations
+= 10;
960 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
962 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
963 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
968 memcpy(declarations
+ numDeclarations
,
969 &parse
.FullToken
.FullDeclaration
,
970 sizeof(declarations
[0]));
974 case TGSI_TOKEN_TYPE_IMMEDIATE
:
976 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
978 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
980 for( i
= 0; i
< size
; i
++ ) {
981 mach
->Imms
[mach
->ImmLimit
][i
] =
982 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
988 case TGSI_TOKEN_TYPE_INSTRUCTION
:
990 /* save expanded instruction */
991 if (numInstructions
== maxInstructions
) {
992 instructions
= REALLOC(instructions
,
994 * sizeof(struct tgsi_full_instruction
),
995 (maxInstructions
+ 10)
996 * sizeof(struct tgsi_full_instruction
));
997 maxInstructions
+= 10;
1000 memcpy(instructions
+ numInstructions
,
1001 &parse
.FullToken
.FullInstruction
,
1002 sizeof(instructions
[0]));
1007 case TGSI_TOKEN_TYPE_PROPERTY
:
1008 if (mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
1009 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1010 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1019 tgsi_parse_free (&parse
);
1021 FREE(mach
->Declarations
);
1022 mach
->Declarations
= declarations
;
1023 mach
->NumDeclarations
= numDeclarations
;
1025 FREE(mach
->Instructions
);
1026 mach
->Instructions
= instructions
;
1027 mach
->NumInstructions
= numInstructions
;
1031 struct tgsi_exec_machine
*
1032 tgsi_exec_machine_create( void )
1034 struct tgsi_exec_machine
*mach
;
1037 mach
= align_malloc( sizeof *mach
, 16 );
1041 memset(mach
, 0, sizeof(*mach
));
1043 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1044 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1045 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
1047 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1048 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1049 if (!mach
->Inputs
|| !mach
->Outputs
)
1052 /* Setup constants needed by the SSE2 executor. */
1053 for( i
= 0; i
< 4; i
++ ) {
1054 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1055 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1056 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1057 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1058 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1059 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1060 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1061 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1062 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1063 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1067 /* silence warnings */
1076 align_free(mach
->Inputs
);
1077 align_free(mach
->Outputs
);
1085 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1088 FREE(mach
->Instructions
);
1089 FREE(mach
->Declarations
);
1091 align_free(mach
->Inputs
);
1092 align_free(mach
->Outputs
);
1099 micro_add(union tgsi_exec_channel
*dst
,
1100 const union tgsi_exec_channel
*src0
,
1101 const union tgsi_exec_channel
*src1
)
1103 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1104 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1105 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1106 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1111 union tgsi_exec_channel
*dst
,
1112 const union tgsi_exec_channel
*src0
,
1113 const union tgsi_exec_channel
*src1
)
1115 if (src1
->f
[0] != 0) {
1116 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1118 if (src1
->f
[1] != 0) {
1119 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1121 if (src1
->f
[2] != 0) {
1122 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1124 if (src1
->f
[3] != 0) {
1125 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1131 union tgsi_exec_channel
*dst
,
1132 const union tgsi_exec_channel
*src0
,
1133 const union tgsi_exec_channel
*src1
,
1134 const union tgsi_exec_channel
*src2
,
1135 const union tgsi_exec_channel
*src3
)
1137 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1138 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1139 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1140 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1144 micro_max(union tgsi_exec_channel
*dst
,
1145 const union tgsi_exec_channel
*src0
,
1146 const union tgsi_exec_channel
*src1
)
1148 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1149 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1150 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1151 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1155 micro_min(union tgsi_exec_channel
*dst
,
1156 const union tgsi_exec_channel
*src0
,
1157 const union tgsi_exec_channel
*src1
)
1159 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1160 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1161 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1162 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1166 micro_mul(union tgsi_exec_channel
*dst
,
1167 const union tgsi_exec_channel
*src0
,
1168 const union tgsi_exec_channel
*src1
)
1170 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1171 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1172 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1173 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1178 union tgsi_exec_channel
*dst
,
1179 const union tgsi_exec_channel
*src
)
1181 dst
->f
[0] = -src
->f
[0];
1182 dst
->f
[1] = -src
->f
[1];
1183 dst
->f
[2] = -src
->f
[2];
1184 dst
->f
[3] = -src
->f
[3];
1189 union tgsi_exec_channel
*dst
,
1190 const union tgsi_exec_channel
*src0
,
1191 const union tgsi_exec_channel
*src1
)
1194 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1195 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1196 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1197 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1199 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1200 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1201 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1202 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1207 micro_sub(union tgsi_exec_channel
*dst
,
1208 const union tgsi_exec_channel
*src0
,
1209 const union tgsi_exec_channel
*src1
)
1211 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1212 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1213 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1214 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1218 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1219 const uint chan_index
,
1222 const union tgsi_exec_channel
*index
,
1223 const union tgsi_exec_channel
*index2D
,
1224 union tgsi_exec_channel
*chan
)
1228 assert(swizzle
< 4);
1231 case TGSI_FILE_CONSTANT
:
1232 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1233 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1234 assert(mach
->Consts
[index2D
->i
[i
]]);
1236 if (index
->i
[i
] < 0) {
1239 /* NOTE: copying the const value as a uint instead of float */
1240 const uint constbuf
= index2D
->i
[i
];
1241 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1242 const int pos
= index
->i
[i
] * 4 + swizzle
;
1243 /* const buffer bounds check */
1244 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1246 /* Debug: print warning */
1247 static int count
= 0;
1249 debug_printf("TGSI Exec: const buffer index %d"
1250 " out of bounds\n", pos
);
1255 chan
->u
[i
] = buf
[pos
];
1260 case TGSI_FILE_INPUT
:
1261 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1263 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1264 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1265 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1266 index2D->i[i], index->i[i]);
1268 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1270 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1271 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1275 case TGSI_FILE_SYSTEM_VALUE
:
1276 /* XXX no swizzling at this point. Will be needed if we put
1277 * gl_FragCoord, for example, in a sys value register.
1279 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1280 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].u
[i
];
1284 case TGSI_FILE_TEMPORARY
:
1285 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1286 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1287 assert(index2D
->i
[i
] == 0);
1289 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1293 case TGSI_FILE_IMMEDIATE
:
1294 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1295 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1296 assert(index2D
->i
[i
] == 0);
1298 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1302 case TGSI_FILE_ADDRESS
:
1303 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1304 assert(index
->i
[i
] >= 0);
1305 assert(index2D
->i
[i
] == 0);
1307 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1311 case TGSI_FILE_PREDICATE
:
1312 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1313 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1314 assert(index2D
->i
[i
] == 0);
1316 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1320 case TGSI_FILE_OUTPUT
:
1321 /* vertex/fragment output vars can be read too */
1322 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1323 assert(index
->i
[i
] >= 0);
1324 assert(index2D
->i
[i
] == 0);
1326 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1332 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1339 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1340 union tgsi_exec_channel
*chan
,
1341 const struct tgsi_full_src_register
*reg
,
1342 const uint chan_index
,
1343 enum tgsi_exec_datatype src_datatype
)
1345 union tgsi_exec_channel index
;
1346 union tgsi_exec_channel index2D
;
1349 /* We start with a direct index into a register file.
1353 * file = Register.File
1354 * [1] = Register.Index
1359 index
.i
[3] = reg
->Register
.Index
;
1361 /* There is an extra source register that indirectly subscripts
1362 * a register file. The direct index now becomes an offset
1363 * that is being added to the indirect register.
1367 * ind = Indirect.File
1368 * [2] = Indirect.Index
1369 * .x = Indirect.SwizzleX
1371 if (reg
->Register
.Indirect
) {
1372 union tgsi_exec_channel index2
;
1373 union tgsi_exec_channel indir_index
;
1374 const uint execmask
= mach
->ExecMask
;
1377 /* which address register (always zero now) */
1381 index2
.i
[3] = reg
->Indirect
.Index
;
1382 /* get current value of address register[swizzle] */
1383 swizzle
= reg
->Indirect
.Swizzle
;
1384 fetch_src_file_channel(mach
,
1392 /* add value of address register to the offset */
1393 index
.i
[0] += indir_index
.i
[0];
1394 index
.i
[1] += indir_index
.i
[1];
1395 index
.i
[2] += indir_index
.i
[2];
1396 index
.i
[3] += indir_index
.i
[3];
1398 /* for disabled execution channels, zero-out the index to
1399 * avoid using a potential garbage value.
1401 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1402 if ((execmask
& (1 << i
)) == 0)
1407 /* There is an extra source register that is a second
1408 * subscript to a register file. Effectively it means that
1409 * the register file is actually a 2D array of registers.
1413 * [3] = Dimension.Index
1415 if (reg
->Register
.Dimension
) {
1419 index2D
.i
[3] = reg
->Dimension
.Index
;
1421 /* Again, the second subscript index can be addressed indirectly
1422 * identically to the first one.
1423 * Nothing stops us from indirectly addressing the indirect register,
1424 * but there is no need for that, so we won't exercise it.
1426 * file[ind[4].y+3][1],
1428 * ind = DimIndirect.File
1429 * [4] = DimIndirect.Index
1430 * .y = DimIndirect.SwizzleX
1432 if (reg
->Dimension
.Indirect
) {
1433 union tgsi_exec_channel index2
;
1434 union tgsi_exec_channel indir_index
;
1435 const uint execmask
= mach
->ExecMask
;
1441 index2
.i
[3] = reg
->DimIndirect
.Index
;
1443 swizzle
= reg
->DimIndirect
.Swizzle
;
1444 fetch_src_file_channel(mach
,
1446 reg
->DimIndirect
.File
,
1452 index2D
.i
[0] += indir_index
.i
[0];
1453 index2D
.i
[1] += indir_index
.i
[1];
1454 index2D
.i
[2] += indir_index
.i
[2];
1455 index2D
.i
[3] += indir_index
.i
[3];
1457 /* for disabled execution channels, zero-out the index to
1458 * avoid using a potential garbage value.
1460 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1461 if ((execmask
& (1 << i
)) == 0) {
1467 /* If by any chance there was a need for a 3D array of register
1468 * files, we would have to check whether Dimension is followed
1469 * by a dimension register and continue the saga.
1478 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1479 fetch_src_file_channel(mach
,
1489 fetch_source(const struct tgsi_exec_machine
*mach
,
1490 union tgsi_exec_channel
*chan
,
1491 const struct tgsi_full_src_register
*reg
,
1492 const uint chan_index
,
1493 enum tgsi_exec_datatype src_datatype
)
1495 fetch_source_d(mach
, chan
, reg
, chan_index
, src_datatype
);
1497 if (reg
->Register
.Absolute
) {
1498 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1499 micro_abs(chan
, chan
);
1501 micro_iabs(chan
, chan
);
1505 if (reg
->Register
.Negate
) {
1506 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1507 micro_neg(chan
, chan
);
1509 micro_ineg(chan
, chan
);
1514 static union tgsi_exec_channel
*
1515 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1516 const union tgsi_exec_channel
*chan
,
1517 const struct tgsi_full_dst_register
*reg
,
1518 const struct tgsi_full_instruction
*inst
,
1520 enum tgsi_exec_datatype dst_datatype
)
1523 static union tgsi_exec_channel null
;
1524 union tgsi_exec_channel
*dst
;
1525 union tgsi_exec_channel index2D
;
1526 uint execmask
= mach
->ExecMask
;
1527 int offset
= 0; /* indirection offset */
1531 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1532 check_inf_or_nan(chan
);
1535 /* There is an extra source register that indirectly subscripts
1536 * a register file. The direct index now becomes an offset
1537 * that is being added to the indirect register.
1541 * ind = Indirect.File
1542 * [2] = Indirect.Index
1543 * .x = Indirect.SwizzleX
1545 if (reg
->Register
.Indirect
) {
1546 union tgsi_exec_channel index
;
1547 union tgsi_exec_channel indir_index
;
1550 /* which address register (always zero for now) */
1554 index
.i
[3] = reg
->Indirect
.Index
;
1556 /* get current value of address register[swizzle] */
1557 swizzle
= reg
->Indirect
.Swizzle
;
1559 /* fetch values from the address/indirection register */
1560 fetch_src_file_channel(mach
,
1568 /* save indirection offset */
1569 offset
= indir_index
.i
[0];
1572 /* There is an extra source register that is a second
1573 * subscript to a register file. Effectively it means that
1574 * the register file is actually a 2D array of registers.
1578 * [3] = Dimension.Index
1580 if (reg
->Register
.Dimension
) {
1584 index2D
.i
[3] = reg
->Dimension
.Index
;
1586 /* Again, the second subscript index can be addressed indirectly
1587 * identically to the first one.
1588 * Nothing stops us from indirectly addressing the indirect register,
1589 * but there is no need for that, so we won't exercise it.
1591 * file[ind[4].y+3][1],
1593 * ind = DimIndirect.File
1594 * [4] = DimIndirect.Index
1595 * .y = DimIndirect.SwizzleX
1597 if (reg
->Dimension
.Indirect
) {
1598 union tgsi_exec_channel index2
;
1599 union tgsi_exec_channel indir_index
;
1600 const uint execmask
= mach
->ExecMask
;
1607 index2
.i
[3] = reg
->DimIndirect
.Index
;
1609 swizzle
= reg
->DimIndirect
.Swizzle
;
1610 fetch_src_file_channel(mach
,
1612 reg
->DimIndirect
.File
,
1618 index2D
.i
[0] += indir_index
.i
[0];
1619 index2D
.i
[1] += indir_index
.i
[1];
1620 index2D
.i
[2] += indir_index
.i
[2];
1621 index2D
.i
[3] += indir_index
.i
[3];
1623 /* for disabled execution channels, zero-out the index to
1624 * avoid using a potential garbage value.
1626 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1627 if ((execmask
& (1 << i
)) == 0) {
1633 /* If by any chance there was a need for a 3D array of register
1634 * files, we would have to check whether Dimension is followed
1635 * by a dimension register and continue the saga.
1644 switch (reg
->Register
.File
) {
1645 case TGSI_FILE_NULL
:
1649 case TGSI_FILE_OUTPUT
:
1650 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1651 + reg
->Register
.Index
;
1652 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1654 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1655 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1656 reg
->Register
.Index
);
1657 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1658 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1659 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1660 if (execmask
& (1 << i
))
1661 debug_printf("%f, ", chan
->f
[i
]);
1662 debug_printf(")\n");
1667 case TGSI_FILE_TEMPORARY
:
1668 index
= reg
->Register
.Index
;
1669 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1670 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1673 case TGSI_FILE_ADDRESS
:
1674 index
= reg
->Register
.Index
;
1675 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1678 case TGSI_FILE_PREDICATE
:
1679 index
= reg
->Register
.Index
;
1680 assert(index
< TGSI_EXEC_NUM_PREDS
);
1681 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1689 if (inst
->Instruction
.Predicate
) {
1691 union tgsi_exec_channel
*pred
;
1693 switch (chan_index
) {
1695 swizzle
= inst
->Predicate
.SwizzleX
;
1698 swizzle
= inst
->Predicate
.SwizzleY
;
1701 swizzle
= inst
->Predicate
.SwizzleZ
;
1704 swizzle
= inst
->Predicate
.SwizzleW
;
1711 assert(inst
->Predicate
.Index
== 0);
1713 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1715 if (inst
->Predicate
.Negate
) {
1716 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1718 execmask
&= ~(1 << i
);
1722 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1724 execmask
&= ~(1 << i
);
1734 store_dest_double(struct tgsi_exec_machine
*mach
,
1735 const union tgsi_exec_channel
*chan
,
1736 const struct tgsi_full_dst_register
*reg
,
1737 const struct tgsi_full_instruction
*inst
,
1739 enum tgsi_exec_datatype dst_datatype
)
1741 union tgsi_exec_channel
*dst
;
1742 const uint execmask
= mach
->ExecMask
;
1745 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1751 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1752 if (execmask
& (1 << i
))
1753 dst
->i
[i
] = chan
->i
[i
];
1757 store_dest(struct tgsi_exec_machine
*mach
,
1758 const union tgsi_exec_channel
*chan
,
1759 const struct tgsi_full_dst_register
*reg
,
1760 const struct tgsi_full_instruction
*inst
,
1762 enum tgsi_exec_datatype dst_datatype
)
1764 union tgsi_exec_channel
*dst
;
1765 const uint execmask
= mach
->ExecMask
;
1768 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1773 if (!inst
->Instruction
.Saturate
) {
1774 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1775 if (execmask
& (1 << i
))
1776 dst
->i
[i
] = chan
->i
[i
];
1779 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1780 if (execmask
& (1 << i
)) {
1781 if (chan
->f
[i
] < 0.0f
)
1783 else if (chan
->f
[i
] > 1.0f
)
1786 dst
->i
[i
] = chan
->i
[i
];
1791 #define FETCH(VAL,INDEX,CHAN)\
1792 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1794 #define IFETCH(VAL,INDEX,CHAN)\
1795 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1799 * Execute ARB-style KIL which is predicated by a src register.
1800 * Kill fragment if any of the four values is less than zero.
1803 exec_kill_if(struct tgsi_exec_machine
*mach
,
1804 const struct tgsi_full_instruction
*inst
)
1808 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1809 union tgsi_exec_channel r
[1];
1811 /* This mask stores component bits that were already tested. */
1814 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1819 /* unswizzle channel */
1820 swizzle
= tgsi_util_get_full_src_register_swizzle (
1824 /* check if the component has not been already tested */
1825 if (uniquemask
& (1 << swizzle
))
1827 uniquemask
|= 1 << swizzle
;
1829 FETCH(&r
[0], 0, chan_index
);
1830 for (i
= 0; i
< 4; i
++)
1831 if (r
[0].f
[i
] < 0.0f
)
1835 /* restrict to fragments currently executing */
1836 kilmask
&= mach
->ExecMask
;
1838 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1842 * Unconditional fragment kill/discard.
1845 exec_kill(struct tgsi_exec_machine
*mach
,
1846 const struct tgsi_full_instruction
*inst
)
1848 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1850 /* kill fragment for all fragments currently executing */
1851 kilmask
= mach
->ExecMask
;
1852 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1856 emit_vertex(struct tgsi_exec_machine
*mach
)
1858 /* FIXME: check for exec mask correctly
1860 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1861 if ((mach->ExecMask & (1 << i)))
1863 if (mach
->ExecMask
) {
1864 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
1867 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1868 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1873 emit_primitive(struct tgsi_exec_machine
*mach
)
1875 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1876 /* FIXME: check for exec mask correctly
1878 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1879 if ((mach->ExecMask & (1 << i)))
1881 if (mach
->ExecMask
) {
1883 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1884 mach
->Primitives
[*prim_count
] = 0;
1889 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1891 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1893 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1894 if (emitted_verts
) {
1895 emit_primitive(mach
);
1902 * Fetch four texture samples using STR texture coordinates.
1905 fetch_texel( struct tgsi_sampler
*sampler
,
1906 const unsigned sview_idx
,
1907 const unsigned sampler_idx
,
1908 const union tgsi_exec_channel
*s
,
1909 const union tgsi_exec_channel
*t
,
1910 const union tgsi_exec_channel
*p
,
1911 const union tgsi_exec_channel
*c0
,
1912 const union tgsi_exec_channel
*c1
,
1913 float derivs
[3][2][TGSI_QUAD_SIZE
],
1914 const int8_t offset
[3],
1915 enum tgsi_sampler_control control
,
1916 union tgsi_exec_channel
*r
,
1917 union tgsi_exec_channel
*g
,
1918 union tgsi_exec_channel
*b
,
1919 union tgsi_exec_channel
*a
)
1922 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1924 /* FIXME: handle explicit derivs, offsets */
1925 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
1926 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
1928 for (j
= 0; j
< 4; j
++) {
1929 r
->f
[j
] = rgba
[0][j
];
1930 g
->f
[j
] = rgba
[1][j
];
1931 b
->f
[j
] = rgba
[2][j
];
1932 a
->f
[j
] = rgba
[3][j
];
1937 #define TEX_MODIFIER_NONE 0
1938 #define TEX_MODIFIER_PROJECTED 1
1939 #define TEX_MODIFIER_LOD_BIAS 2
1940 #define TEX_MODIFIER_EXPLICIT_LOD 3
1941 #define TEX_MODIFIER_LEVEL_ZERO 4
1942 #define TEX_MODIFIER_GATHER 5
1945 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1948 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
1949 const struct tgsi_full_instruction
*inst
,
1952 if (inst
->Texture
.NumOffsets
== 1) {
1953 union tgsi_exec_channel index
;
1954 union tgsi_exec_channel offset
[3];
1955 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
1956 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1957 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
1958 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1959 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
1960 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1961 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
1962 offsets
[0] = offset
[0].i
[0];
1963 offsets
[1] = offset
[1].i
[0];
1964 offsets
[2] = offset
[2].i
[0];
1966 assert(inst
->Texture
.NumOffsets
== 0);
1967 offsets
[0] = offsets
[1] = offsets
[2] = 0;
1973 * Fetch dx and dy values for one channel (s, t or r).
1974 * Put dx values into one float array, dy values into another.
1977 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
1978 const struct tgsi_full_instruction
*inst
,
1981 float derivs
[2][TGSI_QUAD_SIZE
])
1983 union tgsi_exec_channel d
;
1984 FETCH(&d
, regdsrcx
, chan
);
1985 derivs
[0][0] = d
.f
[0];
1986 derivs
[0][1] = d
.f
[1];
1987 derivs
[0][2] = d
.f
[2];
1988 derivs
[0][3] = d
.f
[3];
1989 FETCH(&d
, regdsrcx
+ 1, chan
);
1990 derivs
[1][0] = d
.f
[0];
1991 derivs
[1][1] = d
.f
[1];
1992 derivs
[1][2] = d
.f
[2];
1993 derivs
[1][3] = d
.f
[3];
1997 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
1998 const struct tgsi_full_instruction
*inst
,
2003 if (inst
->Src
[sampler
].Register
.Indirect
) {
2004 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2005 union tgsi_exec_channel indir_index
, index2
;
2006 const uint execmask
= mach
->ExecMask
;
2010 index2
.i
[3] = reg
->Indirect
.Index
;
2012 fetch_src_file_channel(mach
,
2015 reg
->Indirect
.Swizzle
,
2019 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2020 if (execmask
& (1 << i
)) {
2021 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2027 unit
= inst
->Src
[sampler
].Register
.Index
;
2033 * execute a texture instruction.
2035 * modifier is used to control the channel routing for the
2036 * instruction variants like proj, lod, and texture with lod bias.
2037 * sampler indicates which src register the sampler is contained in.
2040 exec_tex(struct tgsi_exec_machine
*mach
,
2041 const struct tgsi_full_instruction
*inst
,
2042 uint modifier
, uint sampler
)
2044 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2045 union tgsi_exec_channel r
[5];
2046 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2050 int dim
, shadow_ref
, i
;
2052 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2053 /* always fetch all 3 offsets, overkill but keeps code simple */
2054 fetch_texel_offsets(mach
, inst
, offsets
);
2056 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2057 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2059 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2060 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2063 if (shadow_ref
>= 0)
2064 assert(shadow_ref
>= dim
&& shadow_ref
< Elements(args
));
2066 /* fetch modifier to the last argument */
2067 if (modifier
!= TEX_MODIFIER_NONE
) {
2068 const int last
= Elements(args
) - 1;
2070 /* fetch modifier from src0.w or src1.x */
2072 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2073 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2076 assert(shadow_ref
!= 4);
2077 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2080 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2081 args
[last
] = &r
[last
];
2085 args
[last
] = &ZeroVec
;
2088 /* point unused arguments to zero vector */
2089 for (i
= dim
; i
< last
; i
++)
2092 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2093 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2094 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2095 control
= TGSI_SAMPLER_LOD_BIAS
;
2096 else if (modifier
== TEX_MODIFIER_GATHER
)
2097 control
= TGSI_SAMPLER_GATHER
;
2100 for (i
= dim
; i
< Elements(args
); i
++)
2104 /* fetch coordinates */
2105 for (i
= 0; i
< dim
; i
++) {
2106 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2109 micro_div(&r
[i
], &r
[i
], proj
);
2114 /* fetch reference value */
2115 if (shadow_ref
>= 0) {
2116 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2119 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2121 args
[shadow_ref
] = &r
[shadow_ref
];
2124 fetch_texel(mach
->Sampler
, unit
, unit
,
2125 args
[0], args
[1], args
[2], args
[3], args
[4],
2126 NULL
, offsets
, control
,
2127 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2130 debug_printf("fetch r: %g %g %g %g\n",
2131 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2132 debug_printf("fetch g: %g %g %g %g\n",
2133 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2134 debug_printf("fetch b: %g %g %g %g\n",
2135 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2136 debug_printf("fetch a: %g %g %g %g\n",
2137 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2140 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2141 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2142 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2148 exec_lodq(struct tgsi_exec_machine
*mach
,
2149 const struct tgsi_full_instruction
*inst
)
2154 union tgsi_exec_channel coords
[4];
2155 const union tgsi_exec_channel
*args
[Elements(coords
)];
2156 union tgsi_exec_channel r
[2];
2158 unit
= fetch_sampler_unit(mach
, inst
, 1);
2159 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2160 assert(dim
<= Elements(coords
));
2161 /* fetch coordinates */
2162 for (i
= 0; i
< dim
; i
++) {
2163 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2164 args
[i
] = &coords
[i
];
2166 for (i
= dim
; i
< Elements(coords
); i
++) {
2169 mach
->Sampler
->query_lod(mach
->Sampler
, unit
, unit
,
2174 TGSI_SAMPLER_LOD_NONE
,
2178 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2179 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2180 TGSI_EXEC_DATA_FLOAT
);
2182 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2183 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2184 TGSI_EXEC_DATA_FLOAT
);
2189 exec_txd(struct tgsi_exec_machine
*mach
,
2190 const struct tgsi_full_instruction
*inst
)
2192 union tgsi_exec_channel r
[4];
2193 float derivs
[3][2][TGSI_QUAD_SIZE
];
2198 unit
= fetch_sampler_unit(mach
, inst
, 3);
2199 /* always fetch all 3 offsets, overkill but keeps code simple */
2200 fetch_texel_offsets(mach
, inst
, offsets
);
2202 switch (inst
->Texture
.Texture
) {
2203 case TGSI_TEXTURE_1D
:
2204 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2206 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2208 fetch_texel(mach
->Sampler
, unit
, unit
,
2209 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2210 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2211 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2214 case TGSI_TEXTURE_SHADOW1D
:
2215 case TGSI_TEXTURE_1D_ARRAY
:
2216 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2217 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2218 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2219 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2220 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2222 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2224 fetch_texel(mach
->Sampler
, unit
, unit
,
2225 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2226 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2227 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2230 case TGSI_TEXTURE_2D
:
2231 case TGSI_TEXTURE_RECT
:
2232 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2233 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2235 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2236 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2238 fetch_texel(mach
->Sampler
, unit
, unit
,
2239 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2240 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2241 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2245 case TGSI_TEXTURE_SHADOW2D
:
2246 case TGSI_TEXTURE_SHADOWRECT
:
2247 case TGSI_TEXTURE_2D_ARRAY
:
2248 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2249 /* only SHADOW2D_ARRAY actually needs W */
2250 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2251 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2252 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2253 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2255 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2256 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2258 fetch_texel(mach
->Sampler
, unit
, unit
,
2259 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2260 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2261 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2264 case TGSI_TEXTURE_3D
:
2265 case TGSI_TEXTURE_CUBE
:
2266 case TGSI_TEXTURE_CUBE_ARRAY
:
2267 case TGSI_TEXTURE_SHADOWCUBE
:
2268 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2269 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2270 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2271 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2272 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2274 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2275 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2276 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2278 fetch_texel(mach
->Sampler
, unit
, unit
,
2279 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2280 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2281 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2288 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2289 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2290 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2297 exec_txf(struct tgsi_exec_machine
*mach
,
2298 const struct tgsi_full_instruction
*inst
)
2300 union tgsi_exec_channel r
[4];
2303 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2308 unit
= fetch_sampler_unit(mach
, inst
, 1);
2309 /* always fetch all 3 offsets, overkill but keeps code simple */
2310 fetch_texel_offsets(mach
, inst
, offsets
);
2312 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2314 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2315 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2316 target
= mach
->SamplerViews
[unit
].Resource
;
2319 target
= inst
->Texture
.Texture
;
2322 case TGSI_TEXTURE_3D
:
2323 case TGSI_TEXTURE_2D_ARRAY
:
2324 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2325 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2326 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2328 case TGSI_TEXTURE_2D
:
2329 case TGSI_TEXTURE_RECT
:
2330 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2331 case TGSI_TEXTURE_SHADOW2D
:
2332 case TGSI_TEXTURE_SHADOWRECT
:
2333 case TGSI_TEXTURE_1D_ARRAY
:
2334 case TGSI_TEXTURE_2D_MSAA
:
2335 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2337 case TGSI_TEXTURE_BUFFER
:
2338 case TGSI_TEXTURE_1D
:
2339 case TGSI_TEXTURE_SHADOW1D
:
2340 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2347 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2350 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2351 r
[0].f
[j
] = rgba
[0][j
];
2352 r
[1].f
[j
] = rgba
[1][j
];
2353 r
[2].f
[j
] = rgba
[2][j
];
2354 r
[3].f
[j
] = rgba
[3][j
];
2357 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2358 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2359 unsigned char swizzles
[4];
2360 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2361 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2362 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2363 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2365 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2366 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2367 store_dest(mach
, &r
[swizzles
[chan
]],
2368 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2373 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2374 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2375 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2382 exec_txq(struct tgsi_exec_machine
*mach
,
2383 const struct tgsi_full_instruction
*inst
)
2386 union tgsi_exec_channel r
[4], src
;
2391 unit
= fetch_sampler_unit(mach
, inst
, 1);
2393 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2395 /* XXX: This interface can't return per-pixel values */
2396 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2398 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2399 for (j
= 0; j
< 4; j
++) {
2400 r
[j
].i
[i
] = result
[j
];
2404 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2405 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2406 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2407 TGSI_EXEC_DATA_INT
);
2413 exec_sample(struct tgsi_exec_machine
*mach
,
2414 const struct tgsi_full_instruction
*inst
,
2415 uint modifier
, boolean compare
)
2417 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2418 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2419 union tgsi_exec_channel r
[5], c1
;
2420 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2421 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2423 unsigned char swizzles
[4];
2426 /* always fetch all 3 offsets, overkill but keeps code simple */
2427 fetch_texel_offsets(mach
, inst
, offsets
);
2429 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2431 if (modifier
!= TEX_MODIFIER_NONE
) {
2432 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2433 FETCH(&c1
, 3, TGSI_CHAN_X
);
2435 control
= TGSI_SAMPLER_LOD_BIAS
;
2437 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2438 FETCH(&c1
, 3, TGSI_CHAN_X
);
2440 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2443 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2444 control
= TGSI_SAMPLER_LOD_ZERO
;
2448 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2450 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2451 case TGSI_TEXTURE_1D
:
2453 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2454 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2455 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2456 NULL
, offsets
, control
,
2457 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2460 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2461 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2462 NULL
, offsets
, control
,
2463 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2467 case TGSI_TEXTURE_1D_ARRAY
:
2468 case TGSI_TEXTURE_2D
:
2469 case TGSI_TEXTURE_RECT
:
2470 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2472 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2473 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2474 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2475 NULL
, offsets
, control
,
2476 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2479 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2480 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2481 NULL
, offsets
, control
,
2482 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2486 case TGSI_TEXTURE_2D_ARRAY
:
2487 case TGSI_TEXTURE_3D
:
2488 case TGSI_TEXTURE_CUBE
:
2489 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2490 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2492 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2493 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2494 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2495 NULL
, offsets
, control
,
2496 &r
[0], &r
[1], &r
[2], &r
[3]);
2499 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2500 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2501 NULL
, offsets
, control
,
2502 &r
[0], &r
[1], &r
[2], &r
[3]);
2506 case TGSI_TEXTURE_CUBE_ARRAY
:
2507 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2508 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2509 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2511 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2512 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2513 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2514 NULL
, offsets
, control
,
2515 &r
[0], &r
[1], &r
[2], &r
[3]);
2518 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2519 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2520 NULL
, offsets
, control
,
2521 &r
[0], &r
[1], &r
[2], &r
[3]);
2530 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2531 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2532 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2533 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2535 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2536 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2537 store_dest(mach
, &r
[swizzles
[chan
]],
2538 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2544 exec_sample_d(struct tgsi_exec_machine
*mach
,
2545 const struct tgsi_full_instruction
*inst
)
2547 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2548 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2549 union tgsi_exec_channel r
[4];
2550 float derivs
[3][2][TGSI_QUAD_SIZE
];
2552 unsigned char swizzles
[4];
2555 /* always fetch all 3 offsets, overkill but keeps code simple */
2556 fetch_texel_offsets(mach
, inst
, offsets
);
2558 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2560 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2561 case TGSI_TEXTURE_1D
:
2562 case TGSI_TEXTURE_1D_ARRAY
:
2563 /* only 1D array actually needs Y */
2564 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2566 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2568 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2569 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2570 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2571 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2574 case TGSI_TEXTURE_2D
:
2575 case TGSI_TEXTURE_RECT
:
2576 case TGSI_TEXTURE_2D_ARRAY
:
2577 /* only 2D array actually needs Z */
2578 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2579 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2581 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2582 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2584 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2585 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2586 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2587 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2590 case TGSI_TEXTURE_3D
:
2591 case TGSI_TEXTURE_CUBE
:
2592 case TGSI_TEXTURE_CUBE_ARRAY
:
2593 /* only cube array actually needs W */
2594 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2595 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2596 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2598 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2599 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2600 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2602 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2603 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2604 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2605 &r
[0], &r
[1], &r
[2], &r
[3]);
2612 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2613 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2614 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2615 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2617 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2618 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2619 store_dest(mach
, &r
[swizzles
[chan
]],
2620 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2627 * Evaluate a constant-valued coefficient at the position of the
2632 struct tgsi_exec_machine
*mach
,
2638 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2639 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2644 * Evaluate a linear-valued coefficient at the position of the
2649 struct tgsi_exec_machine
*mach
,
2653 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2654 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2655 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2656 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2657 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2658 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2659 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2660 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2661 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2665 * Evaluate a perspective-valued coefficient at the position of the
2669 eval_perspective_coef(
2670 struct tgsi_exec_machine
*mach
,
2674 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2675 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2676 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2677 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2678 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2679 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2680 /* divide by W here */
2681 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2682 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2683 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2684 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2688 typedef void (* eval_coef_func
)(
2689 struct tgsi_exec_machine
*mach
,
2694 exec_declaration(struct tgsi_exec_machine
*mach
,
2695 const struct tgsi_full_declaration
*decl
)
2697 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2698 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2702 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
2703 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2704 uint first
, last
, mask
;
2706 first
= decl
->Range
.First
;
2707 last
= decl
->Range
.Last
;
2708 mask
= decl
->Declaration
.UsageMask
;
2710 /* XXX we could remove this special-case code since
2711 * mach->InterpCoefs[first].a0 should already have the
2712 * front/back-face value. But we should first update the
2713 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2714 * Then, we could remove the tgsi_exec_machine::Face field.
2716 /* XXX make FACE a system value */
2717 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2720 assert(decl
->Semantic
.Index
== 0);
2721 assert(first
== last
);
2723 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2724 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2727 eval_coef_func eval
;
2730 switch (decl
->Interp
.Interpolate
) {
2731 case TGSI_INTERPOLATE_CONSTANT
:
2732 eval
= eval_constant_coef
;
2735 case TGSI_INTERPOLATE_LINEAR
:
2736 eval
= eval_linear_coef
;
2739 case TGSI_INTERPOLATE_PERSPECTIVE
:
2740 eval
= eval_perspective_coef
;
2743 case TGSI_INTERPOLATE_COLOR
:
2744 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2752 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2753 if (mask
& (1 << j
)) {
2754 for (i
= first
; i
<= last
; i
++) {
2761 if (DEBUG_EXECUTION
) {
2763 for (i
= first
; i
<= last
; ++i
) {
2764 debug_printf("IN[%2u] = ", i
);
2765 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2769 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2770 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2771 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2772 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2773 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2780 if (decl
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
2781 mach
->SysSemanticToIndex
[decl
->Declaration
.Semantic
] = decl
->Range
.First
;
2785 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2786 const union tgsi_exec_channel
*src
);
2789 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2790 const struct tgsi_full_instruction
*inst
,
2792 enum tgsi_exec_datatype dst_datatype
,
2793 enum tgsi_exec_datatype src_datatype
)
2796 union tgsi_exec_channel src
;
2797 union tgsi_exec_channel dst
;
2799 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2801 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2802 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2803 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2809 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2810 const struct tgsi_full_instruction
*inst
,
2812 enum tgsi_exec_datatype dst_datatype
,
2813 enum tgsi_exec_datatype src_datatype
)
2816 struct tgsi_exec_vector dst
;
2818 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2819 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2820 union tgsi_exec_channel src
;
2822 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2823 op(&dst
.xyzw
[chan
], &src
);
2826 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2827 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2828 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2833 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2834 const union tgsi_exec_channel
*src0
,
2835 const union tgsi_exec_channel
*src1
);
2838 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2839 const struct tgsi_full_instruction
*inst
,
2841 enum tgsi_exec_datatype dst_datatype
,
2842 enum tgsi_exec_datatype src_datatype
)
2845 union tgsi_exec_channel src
[2];
2846 union tgsi_exec_channel dst
;
2848 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2849 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
2850 op(&dst
, &src
[0], &src
[1]);
2851 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2852 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2853 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2859 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2860 const struct tgsi_full_instruction
*inst
,
2862 enum tgsi_exec_datatype dst_datatype
,
2863 enum tgsi_exec_datatype src_datatype
)
2866 struct tgsi_exec_vector dst
;
2868 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2869 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2870 union tgsi_exec_channel src
[2];
2872 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2873 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2874 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2877 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2878 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2879 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2884 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2885 const union tgsi_exec_channel
*src0
,
2886 const union tgsi_exec_channel
*src1
,
2887 const union tgsi_exec_channel
*src2
);
2890 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2891 const struct tgsi_full_instruction
*inst
,
2892 micro_trinary_op op
,
2893 enum tgsi_exec_datatype dst_datatype
,
2894 enum tgsi_exec_datatype src_datatype
)
2897 struct tgsi_exec_vector dst
;
2899 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2900 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2901 union tgsi_exec_channel src
[3];
2903 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2904 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2905 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2906 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2909 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2910 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2911 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2916 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
2917 const union tgsi_exec_channel
*src0
,
2918 const union tgsi_exec_channel
*src1
,
2919 const union tgsi_exec_channel
*src2
,
2920 const union tgsi_exec_channel
*src3
);
2923 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
2924 const struct tgsi_full_instruction
*inst
,
2925 micro_quaternary_op op
,
2926 enum tgsi_exec_datatype dst_datatype
,
2927 enum tgsi_exec_datatype src_datatype
)
2930 struct tgsi_exec_vector dst
;
2932 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2933 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2934 union tgsi_exec_channel src
[4];
2936 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2937 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2938 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2939 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
2940 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
2943 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2944 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2945 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2951 exec_dp3(struct tgsi_exec_machine
*mach
,
2952 const struct tgsi_full_instruction
*inst
)
2955 union tgsi_exec_channel arg
[3];
2957 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2958 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2959 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2961 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2962 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2963 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2964 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2967 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2968 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2969 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2975 exec_dp4(struct tgsi_exec_machine
*mach
,
2976 const struct tgsi_full_instruction
*inst
)
2979 union tgsi_exec_channel arg
[3];
2981 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2982 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2983 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2985 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2986 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2987 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2988 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2991 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2992 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2993 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2999 exec_dp2a(struct tgsi_exec_machine
*mach
,
3000 const struct tgsi_full_instruction
*inst
)
3003 union tgsi_exec_channel arg
[3];
3005 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3006 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3007 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3009 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3010 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3011 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3013 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3014 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3016 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3017 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3018 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3024 exec_dph(struct tgsi_exec_machine
*mach
,
3025 const struct tgsi_full_instruction
*inst
)
3028 union tgsi_exec_channel arg
[3];
3030 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3031 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3032 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3034 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3035 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3036 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3038 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3039 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3040 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3042 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3043 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3045 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3046 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3047 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3053 exec_dp2(struct tgsi_exec_machine
*mach
,
3054 const struct tgsi_full_instruction
*inst
)
3057 union tgsi_exec_channel arg
[3];
3059 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3060 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3061 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3063 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3064 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3065 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3067 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3068 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3069 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3075 exec_pk2h(struct tgsi_exec_machine
*mach
,
3076 const struct tgsi_full_instruction
*inst
)
3079 union tgsi_exec_channel arg
[2], dst
;
3081 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3082 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3083 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3084 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3085 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3087 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3088 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3089 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3095 exec_up2h(struct tgsi_exec_machine
*mach
,
3096 const struct tgsi_full_instruction
*inst
)
3099 union tgsi_exec_channel arg
, dst
[2];
3101 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3102 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3103 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3104 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3106 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3107 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3108 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3114 exec_scs(struct tgsi_exec_machine
*mach
,
3115 const struct tgsi_full_instruction
*inst
)
3117 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
3118 union tgsi_exec_channel arg
;
3119 union tgsi_exec_channel result
;
3121 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3123 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3124 micro_cos(&result
, &arg
);
3125 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3127 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3128 micro_sin(&result
, &arg
);
3129 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3132 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3133 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3135 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3136 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3141 exec_xpd(struct tgsi_exec_machine
*mach
,
3142 const struct tgsi_full_instruction
*inst
)
3144 union tgsi_exec_channel r
[6];
3145 union tgsi_exec_channel d
[3];
3147 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3148 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3150 micro_mul(&r
[2], &r
[0], &r
[1]);
3152 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3153 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3155 micro_mul(&r
[5], &r
[3], &r
[4] );
3156 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
3158 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3160 micro_mul(&r
[3], &r
[3], &r
[2]);
3162 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3164 micro_mul(&r
[1], &r
[1], &r
[5]);
3165 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
3167 micro_mul(&r
[5], &r
[5], &r
[4]);
3168 micro_mul(&r
[0], &r
[0], &r
[2]);
3169 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
3171 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3172 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3174 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3175 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3177 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3178 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3180 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3181 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3186 exec_dst(struct tgsi_exec_machine
*mach
,
3187 const struct tgsi_full_instruction
*inst
)
3189 union tgsi_exec_channel r
[2];
3190 union tgsi_exec_channel d
[4];
3192 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3193 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3194 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3195 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3197 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3198 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3200 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3201 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3204 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3205 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3207 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3208 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3210 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3211 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3213 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3214 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3219 exec_log(struct tgsi_exec_machine
*mach
,
3220 const struct tgsi_full_instruction
*inst
)
3222 union tgsi_exec_channel r
[3];
3224 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3225 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3226 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3227 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3228 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3229 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3231 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3232 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3233 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3234 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3236 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3237 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3239 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3240 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3245 exec_exp(struct tgsi_exec_machine
*mach
,
3246 const struct tgsi_full_instruction
*inst
)
3248 union tgsi_exec_channel r
[3];
3250 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3251 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3252 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3253 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3254 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3256 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3257 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3258 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3260 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3261 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3262 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3264 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3265 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3270 exec_lit(struct tgsi_exec_machine
*mach
,
3271 const struct tgsi_full_instruction
*inst
)
3273 union tgsi_exec_channel r
[3];
3274 union tgsi_exec_channel d
[3];
3276 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3277 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3278 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3279 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3280 micro_max(&r
[1], &r
[1], &ZeroVec
);
3282 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3283 micro_min(&r
[2], &r
[2], &P128Vec
);
3284 micro_max(&r
[2], &r
[2], &M128Vec
);
3285 micro_pow(&r
[1], &r
[1], &r
[2]);
3286 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3287 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3289 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3290 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3291 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3294 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3295 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3298 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3299 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3304 exec_break(struct tgsi_exec_machine
*mach
)
3306 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3307 /* turn off loop channels for each enabled exec channel */
3308 mach
->LoopMask
&= ~mach
->ExecMask
;
3309 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3310 UPDATE_EXEC_MASK(mach
);
3312 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3314 mach
->Switch
.mask
= 0x0;
3316 UPDATE_EXEC_MASK(mach
);
3321 exec_switch(struct tgsi_exec_machine
*mach
,
3322 const struct tgsi_full_instruction
*inst
)
3324 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3325 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3327 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3328 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3329 mach
->Switch
.mask
= 0x0;
3330 mach
->Switch
.defaultMask
= 0x0;
3332 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3333 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3335 UPDATE_EXEC_MASK(mach
);
3339 exec_case(struct tgsi_exec_machine
*mach
,
3340 const struct tgsi_full_instruction
*inst
)
3342 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3343 union tgsi_exec_channel src
;
3346 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3348 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3351 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3354 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3357 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3361 mach
->Switch
.defaultMask
|= mask
;
3363 mach
->Switch
.mask
|= mask
& prevMask
;
3365 UPDATE_EXEC_MASK(mach
);
3368 /* FIXME: this will only work if default is last */
3370 exec_default(struct tgsi_exec_machine
*mach
)
3372 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3374 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3376 UPDATE_EXEC_MASK(mach
);
3380 exec_endswitch(struct tgsi_exec_machine
*mach
)
3382 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3383 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3385 UPDATE_EXEC_MASK(mach
);
3388 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3389 const union tgsi_double_channel
*src
);
3392 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3393 union tgsi_double_channel
*chan
,
3394 const struct tgsi_full_src_register
*reg
,
3398 union tgsi_exec_channel src
[2];
3401 fetch_source_d(mach
, &src
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3402 fetch_source_d(mach
, &src
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3404 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3405 chan
->u
[i
][0] = src
[0].u
[i
];
3406 chan
->u
[i
][1] = src
[1].u
[i
];
3408 if (reg
->Register
.Absolute
) {
3409 micro_dabs(chan
, chan
);
3411 if (reg
->Register
.Negate
) {
3412 micro_dneg(chan
, chan
);
3417 store_double_channel(struct tgsi_exec_machine
*mach
,
3418 const union tgsi_double_channel
*chan
,
3419 const struct tgsi_full_dst_register
*reg
,
3420 const struct tgsi_full_instruction
*inst
,
3424 union tgsi_exec_channel dst
[2];
3426 union tgsi_double_channel temp
;
3427 const uint execmask
= mach
->ExecMask
;
3429 if (!inst
->Instruction
.Saturate
) {
3430 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3431 if (execmask
& (1 << i
)) {
3432 dst
[0].u
[i
] = chan
->u
[i
][0];
3433 dst
[1].u
[i
] = chan
->u
[i
][1];
3437 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3438 if (execmask
& (1 << i
)) {
3439 if (chan
->d
[i
] < 0.0)
3441 else if (chan
->d
[i
] > 1.0)
3444 temp
.d
[i
] = chan
->d
[i
];
3446 dst
[0].u
[i
] = temp
.u
[i
][0];
3447 dst
[1].u
[i
] = temp
.u
[i
][1];
3451 store_dest_double(mach
, &dst
[0], reg
, inst
, chan_0
, TGSI_EXEC_DATA_UINT
);
3453 store_dest_double(mach
, &dst
[1], reg
, inst
, chan_1
, TGSI_EXEC_DATA_UINT
);
3457 exec_double_unary(struct tgsi_exec_machine
*mach
,
3458 const struct tgsi_full_instruction
*inst
,
3461 union tgsi_double_channel src
;
3462 union tgsi_double_channel dst
;
3464 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3465 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3467 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3469 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3470 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3472 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3477 exec_double_binary(struct tgsi_exec_machine
*mach
,
3478 const struct tgsi_full_instruction
*inst
,
3480 enum tgsi_exec_datatype dst_datatype
)
3482 union tgsi_double_channel src
[2];
3483 union tgsi_double_channel dst
;
3484 int first_dest_chan
, second_dest_chan
;
3487 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3488 /* these are & because of the way DSLT etc store their destinations */
3489 if (wmask
& TGSI_WRITEMASK_XY
) {
3490 first_dest_chan
= TGSI_CHAN_X
;
3491 second_dest_chan
= TGSI_CHAN_Y
;
3492 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3493 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3494 second_dest_chan
= -1;
3497 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3498 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3500 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3503 if (wmask
& TGSI_WRITEMASK_ZW
) {
3504 first_dest_chan
= TGSI_CHAN_Z
;
3505 second_dest_chan
= TGSI_CHAN_W
;
3506 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3507 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3508 second_dest_chan
= -1;
3511 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3512 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3514 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3519 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3520 const struct tgsi_full_instruction
*inst
,
3523 union tgsi_double_channel src
[3];
3524 union tgsi_double_channel dst
;
3526 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3527 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3528 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3529 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3531 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3533 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3534 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3535 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3536 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3538 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3543 exec_f2d(struct tgsi_exec_machine
*mach
,
3544 const struct tgsi_full_instruction
*inst
)
3546 union tgsi_exec_channel src
;
3547 union tgsi_double_channel dst
;
3549 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3550 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3551 micro_f2d(&dst
, &src
);
3552 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3554 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3555 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3556 micro_f2d(&dst
, &src
);
3557 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3562 exec_d2f(struct tgsi_exec_machine
*mach
,
3563 const struct tgsi_full_instruction
*inst
)
3565 union tgsi_double_channel src
;
3566 union tgsi_exec_channel dst
;
3567 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3570 for (i
= 0; i
< 2; i
++) {
3573 wm
&= ~(1 << (bit
- 1));
3575 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3577 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3578 micro_d2f(&dst
, &src
);
3579 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_FLOAT
);
3585 exec_i2d(struct tgsi_exec_machine
*mach
,
3586 const struct tgsi_full_instruction
*inst
)
3588 union tgsi_exec_channel src
;
3589 union tgsi_double_channel dst
;
3591 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3592 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3593 micro_i2d(&dst
, &src
);
3594 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3596 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3597 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_INT
);
3598 micro_i2d(&dst
, &src
);
3599 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3604 exec_d2i(struct tgsi_exec_machine
*mach
,
3605 const struct tgsi_full_instruction
*inst
)
3607 union tgsi_double_channel src
;
3608 union tgsi_exec_channel dst
;
3609 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3612 for (i
= 0; i
< 2; i
++) {
3615 wm
&= ~(1 << (bit
- 1));
3617 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3619 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3620 micro_d2i(&dst
, &src
);
3621 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_INT
);
3626 exec_u2d(struct tgsi_exec_machine
*mach
,
3627 const struct tgsi_full_instruction
*inst
)
3629 union tgsi_exec_channel src
;
3630 union tgsi_double_channel dst
;
3632 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3633 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3634 micro_u2d(&dst
, &src
);
3635 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3637 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3638 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_UINT
);
3639 micro_u2d(&dst
, &src
);
3640 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3645 exec_d2u(struct tgsi_exec_machine
*mach
,
3646 const struct tgsi_full_instruction
*inst
)
3648 union tgsi_double_channel src
;
3649 union tgsi_exec_channel dst
;
3650 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3653 for (i
= 0; i
< 2; i
++) {
3656 wm
&= ~(1 << (bit
- 1));
3658 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3660 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3661 micro_d2u(&dst
, &src
);
3662 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_UINT
);
3668 exec_dldexp(struct tgsi_exec_machine
*mach
,
3669 const struct tgsi_full_instruction
*inst
)
3671 union tgsi_double_channel src0
;
3672 union tgsi_exec_channel src1
;
3673 union tgsi_double_channel dst
;
3676 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3677 if (wmask
& TGSI_WRITEMASK_XY
) {
3678 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3679 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3680 micro_dldexp(&dst
, &src0
, &src1
);
3681 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3684 if (wmask
& TGSI_WRITEMASK_ZW
) {
3685 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3686 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3687 micro_dldexp(&dst
, &src0
, &src1
);
3688 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3693 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3694 const struct tgsi_full_instruction
*inst
)
3696 union tgsi_double_channel src
;
3697 union tgsi_double_channel dst
;
3698 union tgsi_exec_channel dst_exp
;
3700 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)) {
3701 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3702 micro_dfracexp(&dst
, &dst_exp
, &src
);
3703 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3704 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3706 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)) {
3707 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3708 micro_dfracexp(&dst
, &dst_exp
, &src
);
3709 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3710 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3715 get_image_coord_dim(unsigned tgsi_tex
)
3719 case TGSI_TEXTURE_BUFFER
:
3720 case TGSI_TEXTURE_1D
:
3723 case TGSI_TEXTURE_2D
:
3724 case TGSI_TEXTURE_RECT
:
3725 case TGSI_TEXTURE_1D_ARRAY
:
3726 case TGSI_TEXTURE_2D_MSAA
:
3729 case TGSI_TEXTURE_3D
:
3730 case TGSI_TEXTURE_CUBE
:
3731 case TGSI_TEXTURE_2D_ARRAY
:
3732 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3733 case TGSI_TEXTURE_CUBE_ARRAY
:
3737 assert(!"unknown texture target");
3746 get_image_coord_sample(unsigned tgsi_tex
)
3750 case TGSI_TEXTURE_2D_MSAA
:
3753 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3763 exec_load_img(struct tgsi_exec_machine
*mach
,
3764 const struct tgsi_full_instruction
*inst
)
3766 union tgsi_exec_channel r
[4], sample_r
;
3772 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3773 struct tgsi_image_params params
;
3774 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3776 unit
= fetch_sampler_unit(mach
, inst
, 0);
3777 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3778 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3781 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3783 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3784 params
.format
= inst
->Memory
.Format
;
3786 for (i
= 0; i
< dim
; i
++) {
3787 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3791 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3793 mach
->Image
->load(mach
->Image
, ¶ms
,
3794 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3796 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3797 r
[0].f
[j
] = rgba
[0][j
];
3798 r
[1].f
[j
] = rgba
[1][j
];
3799 r
[2].f
[j
] = rgba
[2][j
];
3800 r
[3].f
[j
] = rgba
[3][j
];
3802 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3803 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3804 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3810 exec_load_buf(struct tgsi_exec_machine
*mach
,
3811 const struct tgsi_full_instruction
*inst
)
3813 union tgsi_exec_channel r
[4];
3817 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3818 struct tgsi_buffer_params params
;
3819 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3821 unit
= fetch_sampler_unit(mach
, inst
, 0);
3823 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3825 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3827 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3829 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3830 r
[0].f
[j
] = rgba
[0][j
];
3831 r
[1].f
[j
] = rgba
[1][j
];
3832 r
[2].f
[j
] = rgba
[2][j
];
3833 r
[3].f
[j
] = rgba
[3][j
];
3835 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3836 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3837 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3843 exec_load(struct tgsi_exec_machine
*mach
,
3844 const struct tgsi_full_instruction
*inst
)
3846 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
3847 exec_load_img(mach
, inst
);
3849 exec_load_buf(mach
, inst
);
3853 exec_store_img(struct tgsi_exec_machine
*mach
,
3854 const struct tgsi_full_instruction
*inst
)
3856 union tgsi_exec_channel r
[3], sample_r
;
3857 union tgsi_exec_channel value
[4];
3858 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3859 struct tgsi_image_params params
;
3864 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3865 unit
= inst
->Dst
[0].Register
.Index
;
3866 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3867 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3870 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3872 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3873 params
.format
= inst
->Memory
.Format
;
3875 for (i
= 0; i
< dim
; i
++) {
3876 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
3879 for (i
= 0; i
< 4; i
++) {
3880 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3883 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
3885 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3886 rgba
[0][j
] = value
[0].f
[j
];
3887 rgba
[1][j
] = value
[1].f
[j
];
3888 rgba
[2][j
] = value
[2].f
[j
];
3889 rgba
[3][j
] = value
[3].f
[j
];
3892 mach
->Image
->store(mach
->Image
, ¶ms
,
3893 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3898 exec_store_buf(struct tgsi_exec_machine
*mach
,
3899 const struct tgsi_full_instruction
*inst
)
3901 union tgsi_exec_channel r
[3];
3902 union tgsi_exec_channel value
[4];
3903 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3904 struct tgsi_buffer_params params
;
3907 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3909 unit
= inst
->Dst
[0].Register
.Index
;
3911 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3913 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
3915 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
3916 for (i
= 0; i
< 4; i
++) {
3917 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3920 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3921 rgba
[0][j
] = value
[0].f
[j
];
3922 rgba
[1][j
] = value
[1].f
[j
];
3923 rgba
[2][j
] = value
[2].f
[j
];
3924 rgba
[3][j
] = value
[3].f
[j
];
3927 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
3933 exec_store(struct tgsi_exec_machine
*mach
,
3934 const struct tgsi_full_instruction
*inst
)
3936 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
3937 exec_store_img(mach
, inst
);
3939 exec_store_buf(mach
, inst
);
3943 exec_atomop_img(struct tgsi_exec_machine
*mach
,
3944 const struct tgsi_full_instruction
*inst
)
3946 union tgsi_exec_channel r
[4], sample_r
;
3947 union tgsi_exec_channel value
[4], value2
[4];
3948 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3949 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3950 struct tgsi_image_params params
;
3955 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3956 unit
= fetch_sampler_unit(mach
, inst
, 0);
3957 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3958 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3961 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3963 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3964 params
.format
= inst
->Memory
.Format
;
3966 for (i
= 0; i
< dim
; i
++) {
3967 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3970 for (i
= 0; i
< 4; i
++) {
3971 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
3972 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
3973 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
3976 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3978 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3979 rgba
[0][j
] = value
[0].f
[j
];
3980 rgba
[1][j
] = value
[1].f
[j
];
3981 rgba
[2][j
] = value
[2].f
[j
];
3982 rgba
[3][j
] = value
[3].f
[j
];
3984 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
3985 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3986 rgba2
[0][j
] = value2
[0].f
[j
];
3987 rgba2
[1][j
] = value2
[1].f
[j
];
3988 rgba2
[2][j
] = value2
[2].f
[j
];
3989 rgba2
[3][j
] = value2
[3].f
[j
];
3993 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
3994 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3997 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3998 r
[0].f
[j
] = rgba
[0][j
];
3999 r
[1].f
[j
] = rgba
[1][j
];
4000 r
[2].f
[j
] = rgba
[2][j
];
4001 r
[3].f
[j
] = rgba
[3][j
];
4003 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4004 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4005 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4011 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4012 const struct tgsi_full_instruction
*inst
)
4014 union tgsi_exec_channel r
[4];
4015 union tgsi_exec_channel value
[4], value2
[4];
4016 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4017 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4018 struct tgsi_buffer_params params
;
4021 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4023 unit
= fetch_sampler_unit(mach
, inst
, 0);
4025 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4027 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4029 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4031 for (i
= 0; i
< 4; i
++) {
4032 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4033 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4034 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4037 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4038 rgba
[0][j
] = value
[0].f
[j
];
4039 rgba
[1][j
] = value
[1].f
[j
];
4040 rgba
[2][j
] = value
[2].f
[j
];
4041 rgba
[3][j
] = value
[3].f
[j
];
4043 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4044 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4045 rgba2
[0][j
] = value2
[0].f
[j
];
4046 rgba2
[1][j
] = value2
[1].f
[j
];
4047 rgba2
[2][j
] = value2
[2].f
[j
];
4048 rgba2
[3][j
] = value2
[3].f
[j
];
4052 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4056 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4057 r
[0].f
[j
] = rgba
[0][j
];
4058 r
[1].f
[j
] = rgba
[1][j
];
4059 r
[2].f
[j
] = rgba
[2][j
];
4060 r
[3].f
[j
] = rgba
[3][j
];
4062 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4063 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4064 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4070 exec_atomop(struct tgsi_exec_machine
*mach
,
4071 const struct tgsi_full_instruction
*inst
)
4073 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4074 exec_atomop_img(mach
, inst
);
4076 exec_atomop_buf(mach
, inst
);
4080 exec_resq_img(struct tgsi_exec_machine
*mach
,
4081 const struct tgsi_full_instruction
*inst
)
4084 union tgsi_exec_channel r
[4];
4087 struct tgsi_image_params params
;
4088 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4090 unit
= fetch_sampler_unit(mach
, inst
, 0);
4092 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4094 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4095 params
.format
= inst
->Memory
.Format
;
4097 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4099 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4100 for (j
= 0; j
< 4; j
++) {
4101 r
[j
].i
[i
] = result
[j
];
4105 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4106 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4107 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4108 TGSI_EXEC_DATA_INT
);
4114 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4115 const struct tgsi_full_instruction
*inst
)
4118 union tgsi_exec_channel r
[4];
4121 struct tgsi_buffer_params params
;
4122 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4124 unit
= fetch_sampler_unit(mach
, inst
, 0);
4126 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4129 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4131 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4135 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4136 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4137 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4138 TGSI_EXEC_DATA_INT
);
4144 exec_resq(struct tgsi_exec_machine
*mach
,
4145 const struct tgsi_full_instruction
*inst
)
4147 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4148 exec_resq_img(mach
, inst
);
4150 exec_resq_buf(mach
, inst
);
4154 micro_i2f(union tgsi_exec_channel
*dst
,
4155 const union tgsi_exec_channel
*src
)
4157 dst
->f
[0] = (float)src
->i
[0];
4158 dst
->f
[1] = (float)src
->i
[1];
4159 dst
->f
[2] = (float)src
->i
[2];
4160 dst
->f
[3] = (float)src
->i
[3];
4164 micro_not(union tgsi_exec_channel
*dst
,
4165 const union tgsi_exec_channel
*src
)
4167 dst
->u
[0] = ~src
->u
[0];
4168 dst
->u
[1] = ~src
->u
[1];
4169 dst
->u
[2] = ~src
->u
[2];
4170 dst
->u
[3] = ~src
->u
[3];
4174 micro_shl(union tgsi_exec_channel
*dst
,
4175 const union tgsi_exec_channel
*src0
,
4176 const union tgsi_exec_channel
*src1
)
4178 unsigned masked_count
;
4179 masked_count
= src1
->u
[0] & 0x1f;
4180 dst
->u
[0] = src0
->u
[0] << masked_count
;
4181 masked_count
= src1
->u
[1] & 0x1f;
4182 dst
->u
[1] = src0
->u
[1] << masked_count
;
4183 masked_count
= src1
->u
[2] & 0x1f;
4184 dst
->u
[2] = src0
->u
[2] << masked_count
;
4185 masked_count
= src1
->u
[3] & 0x1f;
4186 dst
->u
[3] = src0
->u
[3] << masked_count
;
4190 micro_and(union tgsi_exec_channel
*dst
,
4191 const union tgsi_exec_channel
*src0
,
4192 const union tgsi_exec_channel
*src1
)
4194 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4195 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4196 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4197 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4201 micro_or(union tgsi_exec_channel
*dst
,
4202 const union tgsi_exec_channel
*src0
,
4203 const union tgsi_exec_channel
*src1
)
4205 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4206 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4207 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4208 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4212 micro_xor(union tgsi_exec_channel
*dst
,
4213 const union tgsi_exec_channel
*src0
,
4214 const union tgsi_exec_channel
*src1
)
4216 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4217 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4218 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4219 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4223 micro_mod(union tgsi_exec_channel
*dst
,
4224 const union tgsi_exec_channel
*src0
,
4225 const union tgsi_exec_channel
*src1
)
4227 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
4228 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
4229 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
4230 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
4234 micro_f2i(union tgsi_exec_channel
*dst
,
4235 const union tgsi_exec_channel
*src
)
4237 dst
->i
[0] = (int)src
->f
[0];
4238 dst
->i
[1] = (int)src
->f
[1];
4239 dst
->i
[2] = (int)src
->f
[2];
4240 dst
->i
[3] = (int)src
->f
[3];
4244 micro_fseq(union tgsi_exec_channel
*dst
,
4245 const union tgsi_exec_channel
*src0
,
4246 const union tgsi_exec_channel
*src1
)
4248 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4249 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4250 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4251 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4255 micro_fsge(union tgsi_exec_channel
*dst
,
4256 const union tgsi_exec_channel
*src0
,
4257 const union tgsi_exec_channel
*src1
)
4259 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4260 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4261 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4262 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4266 micro_fslt(union tgsi_exec_channel
*dst
,
4267 const union tgsi_exec_channel
*src0
,
4268 const union tgsi_exec_channel
*src1
)
4270 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4271 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4272 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4273 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4277 micro_fsne(union tgsi_exec_channel
*dst
,
4278 const union tgsi_exec_channel
*src0
,
4279 const union tgsi_exec_channel
*src1
)
4281 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4282 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4283 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4284 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4288 micro_idiv(union tgsi_exec_channel
*dst
,
4289 const union tgsi_exec_channel
*src0
,
4290 const union tgsi_exec_channel
*src1
)
4292 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4293 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4294 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4295 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4299 micro_imax(union tgsi_exec_channel
*dst
,
4300 const union tgsi_exec_channel
*src0
,
4301 const union tgsi_exec_channel
*src1
)
4303 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4304 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4305 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4306 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4310 micro_imin(union tgsi_exec_channel
*dst
,
4311 const union tgsi_exec_channel
*src0
,
4312 const union tgsi_exec_channel
*src1
)
4314 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4315 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4316 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4317 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4321 micro_isge(union tgsi_exec_channel
*dst
,
4322 const union tgsi_exec_channel
*src0
,
4323 const union tgsi_exec_channel
*src1
)
4325 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4326 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4327 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4328 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4332 micro_ishr(union tgsi_exec_channel
*dst
,
4333 const union tgsi_exec_channel
*src0
,
4334 const union tgsi_exec_channel
*src1
)
4336 unsigned masked_count
;
4337 masked_count
= src1
->i
[0] & 0x1f;
4338 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4339 masked_count
= src1
->i
[1] & 0x1f;
4340 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4341 masked_count
= src1
->i
[2] & 0x1f;
4342 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4343 masked_count
= src1
->i
[3] & 0x1f;
4344 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4348 micro_islt(union tgsi_exec_channel
*dst
,
4349 const union tgsi_exec_channel
*src0
,
4350 const union tgsi_exec_channel
*src1
)
4352 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4353 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4354 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4355 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4359 micro_f2u(union tgsi_exec_channel
*dst
,
4360 const union tgsi_exec_channel
*src
)
4362 dst
->u
[0] = (uint
)src
->f
[0];
4363 dst
->u
[1] = (uint
)src
->f
[1];
4364 dst
->u
[2] = (uint
)src
->f
[2];
4365 dst
->u
[3] = (uint
)src
->f
[3];
4369 micro_u2f(union tgsi_exec_channel
*dst
,
4370 const union tgsi_exec_channel
*src
)
4372 dst
->f
[0] = (float)src
->u
[0];
4373 dst
->f
[1] = (float)src
->u
[1];
4374 dst
->f
[2] = (float)src
->u
[2];
4375 dst
->f
[3] = (float)src
->u
[3];
4379 micro_uadd(union tgsi_exec_channel
*dst
,
4380 const union tgsi_exec_channel
*src0
,
4381 const union tgsi_exec_channel
*src1
)
4383 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4384 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4385 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4386 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4390 micro_udiv(union tgsi_exec_channel
*dst
,
4391 const union tgsi_exec_channel
*src0
,
4392 const union tgsi_exec_channel
*src1
)
4394 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4395 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4396 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4397 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4401 micro_umad(union tgsi_exec_channel
*dst
,
4402 const union tgsi_exec_channel
*src0
,
4403 const union tgsi_exec_channel
*src1
,
4404 const union tgsi_exec_channel
*src2
)
4406 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4407 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4408 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4409 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4413 micro_umax(union tgsi_exec_channel
*dst
,
4414 const union tgsi_exec_channel
*src0
,
4415 const union tgsi_exec_channel
*src1
)
4417 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4418 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4419 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4420 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4424 micro_umin(union tgsi_exec_channel
*dst
,
4425 const union tgsi_exec_channel
*src0
,
4426 const union tgsi_exec_channel
*src1
)
4428 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4429 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4430 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4431 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4435 micro_umod(union tgsi_exec_channel
*dst
,
4436 const union tgsi_exec_channel
*src0
,
4437 const union tgsi_exec_channel
*src1
)
4439 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4440 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4441 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4442 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4446 micro_umul(union tgsi_exec_channel
*dst
,
4447 const union tgsi_exec_channel
*src0
,
4448 const union tgsi_exec_channel
*src1
)
4450 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4451 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4452 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4453 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4457 micro_imul_hi(union tgsi_exec_channel
*dst
,
4458 const union tgsi_exec_channel
*src0
,
4459 const union tgsi_exec_channel
*src1
)
4461 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4462 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4463 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4464 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4465 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4470 micro_umul_hi(union tgsi_exec_channel
*dst
,
4471 const union tgsi_exec_channel
*src0
,
4472 const union tgsi_exec_channel
*src1
)
4474 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4475 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4476 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4477 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4478 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4483 micro_useq(union tgsi_exec_channel
*dst
,
4484 const union tgsi_exec_channel
*src0
,
4485 const union tgsi_exec_channel
*src1
)
4487 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4488 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4489 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4490 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4494 micro_usge(union tgsi_exec_channel
*dst
,
4495 const union tgsi_exec_channel
*src0
,
4496 const union tgsi_exec_channel
*src1
)
4498 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4499 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4500 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4501 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4505 micro_ushr(union tgsi_exec_channel
*dst
,
4506 const union tgsi_exec_channel
*src0
,
4507 const union tgsi_exec_channel
*src1
)
4509 unsigned masked_count
;
4510 masked_count
= src1
->u
[0] & 0x1f;
4511 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4512 masked_count
= src1
->u
[1] & 0x1f;
4513 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4514 masked_count
= src1
->u
[2] & 0x1f;
4515 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4516 masked_count
= src1
->u
[3] & 0x1f;
4517 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4521 micro_uslt(union tgsi_exec_channel
*dst
,
4522 const union tgsi_exec_channel
*src0
,
4523 const union tgsi_exec_channel
*src1
)
4525 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4526 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4527 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4528 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4532 micro_usne(union tgsi_exec_channel
*dst
,
4533 const union tgsi_exec_channel
*src0
,
4534 const union tgsi_exec_channel
*src1
)
4536 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4537 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4538 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4539 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4543 micro_uarl(union tgsi_exec_channel
*dst
,
4544 const union tgsi_exec_channel
*src
)
4546 dst
->i
[0] = src
->u
[0];
4547 dst
->i
[1] = src
->u
[1];
4548 dst
->i
[2] = src
->u
[2];
4549 dst
->i
[3] = src
->u
[3];
4553 micro_ucmp(union tgsi_exec_channel
*dst
,
4554 const union tgsi_exec_channel
*src0
,
4555 const union tgsi_exec_channel
*src1
,
4556 const union tgsi_exec_channel
*src2
)
4558 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
4559 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
4560 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
4561 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
4565 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4568 micro_ibfe(union tgsi_exec_channel
*dst
,
4569 const union tgsi_exec_channel
*src0
,
4570 const union tgsi_exec_channel
*src1
,
4571 const union tgsi_exec_channel
*src2
)
4574 for (i
= 0; i
< 4; i
++) {
4575 int width
= src2
->i
[i
] & 0x1f;
4576 int offset
= src1
->i
[i
] & 0x1f;
4579 else if (width
+ offset
< 32)
4580 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
4582 dst
->i
[i
] = src0
->i
[i
] >> offset
;
4587 * Unsigned bitfield extract
4590 micro_ubfe(union tgsi_exec_channel
*dst
,
4591 const union tgsi_exec_channel
*src0
,
4592 const union tgsi_exec_channel
*src1
,
4593 const union tgsi_exec_channel
*src2
)
4596 for (i
= 0; i
< 4; i
++) {
4597 int width
= src2
->u
[i
] & 0x1f;
4598 int offset
= src1
->u
[i
] & 0x1f;
4601 else if (width
+ offset
< 32)
4602 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
4604 dst
->u
[i
] = src0
->u
[i
] >> offset
;
4609 * Bitfield insert: copy low bits from src1 into a region of src0.
4612 micro_bfi(union tgsi_exec_channel
*dst
,
4613 const union tgsi_exec_channel
*src0
,
4614 const union tgsi_exec_channel
*src1
,
4615 const union tgsi_exec_channel
*src2
,
4616 const union tgsi_exec_channel
*src3
)
4619 for (i
= 0; i
< 4; i
++) {
4620 int width
= src3
->u
[i
] & 0x1f;
4621 int offset
= src2
->u
[i
] & 0x1f;
4622 int bitmask
= ((1 << width
) - 1) << offset
;
4623 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
4628 micro_brev(union tgsi_exec_channel
*dst
,
4629 const union tgsi_exec_channel
*src
)
4631 dst
->u
[0] = util_bitreverse(src
->u
[0]);
4632 dst
->u
[1] = util_bitreverse(src
->u
[1]);
4633 dst
->u
[2] = util_bitreverse(src
->u
[2]);
4634 dst
->u
[3] = util_bitreverse(src
->u
[3]);
4638 micro_popc(union tgsi_exec_channel
*dst
,
4639 const union tgsi_exec_channel
*src
)
4641 dst
->u
[0] = util_bitcount(src
->u
[0]);
4642 dst
->u
[1] = util_bitcount(src
->u
[1]);
4643 dst
->u
[2] = util_bitcount(src
->u
[2]);
4644 dst
->u
[3] = util_bitcount(src
->u
[3]);
4648 micro_lsb(union tgsi_exec_channel
*dst
,
4649 const union tgsi_exec_channel
*src
)
4651 dst
->i
[0] = ffs(src
->u
[0]) - 1;
4652 dst
->i
[1] = ffs(src
->u
[1]) - 1;
4653 dst
->i
[2] = ffs(src
->u
[2]) - 1;
4654 dst
->i
[3] = ffs(src
->u
[3]) - 1;
4658 micro_imsb(union tgsi_exec_channel
*dst
,
4659 const union tgsi_exec_channel
*src
)
4661 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
4662 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
4663 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
4664 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
4668 micro_umsb(union tgsi_exec_channel
*dst
,
4669 const union tgsi_exec_channel
*src
)
4671 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
4672 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
4673 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
4674 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
4679 struct tgsi_exec_machine
*mach
,
4680 const struct tgsi_full_instruction
*inst
,
4683 union tgsi_exec_channel r
[10];
4687 switch (inst
->Instruction
.Opcode
) {
4688 case TGSI_OPCODE_ARL
:
4689 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4692 case TGSI_OPCODE_MOV
:
4693 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4696 case TGSI_OPCODE_LIT
:
4697 exec_lit(mach
, inst
);
4700 case TGSI_OPCODE_RCP
:
4701 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4704 case TGSI_OPCODE_RSQ
:
4705 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4708 case TGSI_OPCODE_EXP
:
4709 exec_exp(mach
, inst
);
4712 case TGSI_OPCODE_LOG
:
4713 exec_log(mach
, inst
);
4716 case TGSI_OPCODE_MUL
:
4717 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4720 case TGSI_OPCODE_ADD
:
4721 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4724 case TGSI_OPCODE_DP3
:
4725 exec_dp3(mach
, inst
);
4728 case TGSI_OPCODE_DP4
:
4729 exec_dp4(mach
, inst
);
4732 case TGSI_OPCODE_DST
:
4733 exec_dst(mach
, inst
);
4736 case TGSI_OPCODE_MIN
:
4737 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4740 case TGSI_OPCODE_MAX
:
4741 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4744 case TGSI_OPCODE_SLT
:
4745 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4748 case TGSI_OPCODE_SGE
:
4749 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4752 case TGSI_OPCODE_MAD
:
4753 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4756 case TGSI_OPCODE_SUB
:
4757 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4760 case TGSI_OPCODE_LRP
:
4761 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4764 case TGSI_OPCODE_SQRT
:
4765 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4768 case TGSI_OPCODE_DP2A
:
4769 exec_dp2a(mach
, inst
);
4772 case TGSI_OPCODE_FRC
:
4773 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4776 case TGSI_OPCODE_CLAMP
:
4777 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4780 case TGSI_OPCODE_FLR
:
4781 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4784 case TGSI_OPCODE_ROUND
:
4785 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4788 case TGSI_OPCODE_EX2
:
4789 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4792 case TGSI_OPCODE_LG2
:
4793 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4796 case TGSI_OPCODE_POW
:
4797 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4800 case TGSI_OPCODE_XPD
:
4801 exec_xpd(mach
, inst
);
4804 case TGSI_OPCODE_ABS
:
4805 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4808 case TGSI_OPCODE_DPH
:
4809 exec_dph(mach
, inst
);
4812 case TGSI_OPCODE_COS
:
4813 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4816 case TGSI_OPCODE_DDX
:
4817 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4820 case TGSI_OPCODE_DDY
:
4821 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4824 case TGSI_OPCODE_KILL
:
4825 exec_kill (mach
, inst
);
4828 case TGSI_OPCODE_KILL_IF
:
4829 exec_kill_if (mach
, inst
);
4832 case TGSI_OPCODE_PK2H
:
4833 exec_pk2h(mach
, inst
);
4836 case TGSI_OPCODE_PK2US
:
4840 case TGSI_OPCODE_PK4B
:
4844 case TGSI_OPCODE_PK4UB
:
4848 case TGSI_OPCODE_SEQ
:
4849 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4852 case TGSI_OPCODE_SGT
:
4853 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4856 case TGSI_OPCODE_SIN
:
4857 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4860 case TGSI_OPCODE_SLE
:
4861 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4864 case TGSI_OPCODE_SNE
:
4865 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4868 case TGSI_OPCODE_TEX
:
4869 /* simple texture lookup */
4870 /* src[0] = texcoord */
4871 /* src[1] = sampler unit */
4872 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
4875 case TGSI_OPCODE_TXB
:
4876 /* Texture lookup with lod bias */
4877 /* src[0] = texcoord (src[0].w = LOD bias) */
4878 /* src[1] = sampler unit */
4879 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
4882 case TGSI_OPCODE_TXD
:
4883 /* Texture lookup with explict partial derivatives */
4884 /* src[0] = texcoord */
4885 /* src[1] = d[strq]/dx */
4886 /* src[2] = d[strq]/dy */
4887 /* src[3] = sampler unit */
4888 exec_txd(mach
, inst
);
4891 case TGSI_OPCODE_TXL
:
4892 /* Texture lookup with explit LOD */
4893 /* src[0] = texcoord (src[0].w = LOD) */
4894 /* src[1] = sampler unit */
4895 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
4898 case TGSI_OPCODE_TXP
:
4899 /* Texture lookup with projection */
4900 /* src[0] = texcoord (src[0].w = projection) */
4901 /* src[1] = sampler unit */
4902 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
4905 case TGSI_OPCODE_TG4
:
4906 /* src[0] = texcoord */
4907 /* src[1] = component */
4908 /* src[2] = sampler unit */
4909 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
4912 case TGSI_OPCODE_LODQ
:
4913 /* src[0] = texcoord */
4914 /* src[1] = sampler unit */
4915 exec_lodq(mach
, inst
);
4918 case TGSI_OPCODE_UP2H
:
4919 exec_up2h(mach
, inst
);
4922 case TGSI_OPCODE_UP2US
:
4926 case TGSI_OPCODE_UP4B
:
4930 case TGSI_OPCODE_UP4UB
:
4934 case TGSI_OPCODE_ARR
:
4935 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4938 case TGSI_OPCODE_CAL
:
4939 /* skip the call if no execution channels are enabled */
4940 if (mach
->ExecMask
) {
4943 /* First, record the depths of the execution stacks.
4944 * This is important for deeply nested/looped return statements.
4945 * We have to unwind the stacks by the correct amount. For a
4946 * real code generator, we could determine the number of entries
4947 * to pop off each stack with simple static analysis and avoid
4948 * implementing this data structure at run time.
4950 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
4951 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
4952 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
4953 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
4954 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
4955 /* note that PC was already incremented above */
4956 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
4958 mach
->CallStackTop
++;
4960 /* Second, push the Cond, Loop, Cont, Func stacks */
4961 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
4962 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4963 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
4964 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
4965 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
4966 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
4968 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
4969 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
4970 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
4971 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
4972 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
4973 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
4975 /* Finally, jump to the subroutine. The label is a pointer
4976 * (an instruction number) to the BGNSUB instruction.
4978 *pc
= inst
->Label
.Label
;
4979 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
4980 == TGSI_OPCODE_BGNSUB
);
4984 case TGSI_OPCODE_RET
:
4985 mach
->FuncMask
&= ~mach
->ExecMask
;
4986 UPDATE_EXEC_MASK(mach
);
4988 if (mach
->FuncMask
== 0x0) {
4989 /* really return now (otherwise, keep executing */
4991 if (mach
->CallStackTop
== 0) {
4992 /* returning from main() */
4993 mach
->CondStackTop
= 0;
4994 mach
->LoopStackTop
= 0;
4999 assert(mach
->CallStackTop
> 0);
5000 mach
->CallStackTop
--;
5002 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5003 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5005 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5006 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5008 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5009 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5011 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5012 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5014 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5015 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5017 assert(mach
->FuncStackTop
> 0);
5018 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5020 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5022 UPDATE_EXEC_MASK(mach
);
5026 case TGSI_OPCODE_SSG
:
5027 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5030 case TGSI_OPCODE_CMP
:
5031 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5034 case TGSI_OPCODE_SCS
:
5035 exec_scs(mach
, inst
);
5038 case TGSI_OPCODE_DIV
:
5039 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5042 case TGSI_OPCODE_DP2
:
5043 exec_dp2(mach
, inst
);
5046 case TGSI_OPCODE_IF
:
5048 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5049 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5050 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5051 /* update CondMask */
5053 mach
->CondMask
&= ~0x1;
5056 mach
->CondMask
&= ~0x2;
5059 mach
->CondMask
&= ~0x4;
5062 mach
->CondMask
&= ~0x8;
5064 UPDATE_EXEC_MASK(mach
);
5065 /* Todo: If CondMask==0, jump to ELSE */
5068 case TGSI_OPCODE_UIF
:
5070 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5071 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5072 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5073 /* update CondMask */
5075 mach
->CondMask
&= ~0x1;
5078 mach
->CondMask
&= ~0x2;
5081 mach
->CondMask
&= ~0x4;
5084 mach
->CondMask
&= ~0x8;
5086 UPDATE_EXEC_MASK(mach
);
5087 /* Todo: If CondMask==0, jump to ELSE */
5090 case TGSI_OPCODE_ELSE
:
5091 /* invert CondMask wrt previous mask */
5094 assert(mach
->CondStackTop
> 0);
5095 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5096 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5097 UPDATE_EXEC_MASK(mach
);
5098 /* Todo: If CondMask==0, jump to ENDIF */
5102 case TGSI_OPCODE_ENDIF
:
5104 assert(mach
->CondStackTop
> 0);
5105 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5106 UPDATE_EXEC_MASK(mach
);
5109 case TGSI_OPCODE_END
:
5110 /* make sure we end primitives which haven't
5111 * been explicitly emitted */
5112 conditional_emit_primitive(mach
);
5113 /* halt execution */
5117 case TGSI_OPCODE_PUSHA
:
5121 case TGSI_OPCODE_POPA
:
5125 case TGSI_OPCODE_CEIL
:
5126 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5129 case TGSI_OPCODE_I2F
:
5130 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5133 case TGSI_OPCODE_NOT
:
5134 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5137 case TGSI_OPCODE_TRUNC
:
5138 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5141 case TGSI_OPCODE_SHL
:
5142 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5145 case TGSI_OPCODE_AND
:
5146 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5149 case TGSI_OPCODE_OR
:
5150 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5153 case TGSI_OPCODE_MOD
:
5154 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5157 case TGSI_OPCODE_XOR
:
5158 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5161 case TGSI_OPCODE_SAD
:
5165 case TGSI_OPCODE_TXF
:
5166 exec_txf(mach
, inst
);
5169 case TGSI_OPCODE_TXQ
:
5170 exec_txq(mach
, inst
);
5173 case TGSI_OPCODE_EMIT
:
5177 case TGSI_OPCODE_ENDPRIM
:
5178 emit_primitive(mach
);
5181 case TGSI_OPCODE_BGNLOOP
:
5182 /* push LoopMask and ContMasks */
5183 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5184 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5185 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5186 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5188 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5189 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5190 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5191 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5192 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5195 case TGSI_OPCODE_ENDLOOP
:
5196 /* Restore ContMask, but don't pop */
5197 assert(mach
->ContStackTop
> 0);
5198 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5199 UPDATE_EXEC_MASK(mach
);
5200 if (mach
->ExecMask
) {
5201 /* repeat loop: jump to instruction just past BGNLOOP */
5202 assert(mach
->LoopLabelStackTop
> 0);
5203 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5206 /* exit loop: pop LoopMask */
5207 assert(mach
->LoopStackTop
> 0);
5208 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5210 assert(mach
->ContStackTop
> 0);
5211 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5212 assert(mach
->LoopLabelStackTop
> 0);
5213 --mach
->LoopLabelStackTop
;
5215 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5217 UPDATE_EXEC_MASK(mach
);
5220 case TGSI_OPCODE_BRK
:
5224 case TGSI_OPCODE_CONT
:
5225 /* turn off cont channels for each enabled exec channel */
5226 mach
->ContMask
&= ~mach
->ExecMask
;
5227 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5228 UPDATE_EXEC_MASK(mach
);
5231 case TGSI_OPCODE_BGNSUB
:
5235 case TGSI_OPCODE_ENDSUB
:
5237 * XXX: This really should be a no-op. We should never reach this opcode.
5240 assert(mach
->CallStackTop
> 0);
5241 mach
->CallStackTop
--;
5243 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5244 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5246 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5247 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5249 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5250 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5252 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5253 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5255 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5256 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5258 assert(mach
->FuncStackTop
> 0);
5259 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5261 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5263 UPDATE_EXEC_MASK(mach
);
5266 case TGSI_OPCODE_NOP
:
5269 case TGSI_OPCODE_BREAKC
:
5270 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
5271 /* update CondMask */
5272 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
5273 mach
->LoopMask
&= ~0x1;
5275 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
5276 mach
->LoopMask
&= ~0x2;
5278 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
5279 mach
->LoopMask
&= ~0x4;
5281 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
5282 mach
->LoopMask
&= ~0x8;
5284 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5285 UPDATE_EXEC_MASK(mach
);
5288 case TGSI_OPCODE_F2I
:
5289 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5292 case TGSI_OPCODE_FSEQ
:
5293 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5296 case TGSI_OPCODE_FSGE
:
5297 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5300 case TGSI_OPCODE_FSLT
:
5301 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5304 case TGSI_OPCODE_FSNE
:
5305 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5308 case TGSI_OPCODE_IDIV
:
5309 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5312 case TGSI_OPCODE_IMAX
:
5313 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5316 case TGSI_OPCODE_IMIN
:
5317 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5320 case TGSI_OPCODE_INEG
:
5321 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5324 case TGSI_OPCODE_ISGE
:
5325 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5328 case TGSI_OPCODE_ISHR
:
5329 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5332 case TGSI_OPCODE_ISLT
:
5333 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5336 case TGSI_OPCODE_F2U
:
5337 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5340 case TGSI_OPCODE_U2F
:
5341 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5344 case TGSI_OPCODE_UADD
:
5345 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5348 case TGSI_OPCODE_UDIV
:
5349 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5352 case TGSI_OPCODE_UMAD
:
5353 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5356 case TGSI_OPCODE_UMAX
:
5357 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5360 case TGSI_OPCODE_UMIN
:
5361 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5364 case TGSI_OPCODE_UMOD
:
5365 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5368 case TGSI_OPCODE_UMUL
:
5369 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5372 case TGSI_OPCODE_IMUL_HI
:
5373 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5376 case TGSI_OPCODE_UMUL_HI
:
5377 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5380 case TGSI_OPCODE_USEQ
:
5381 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5384 case TGSI_OPCODE_USGE
:
5385 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5388 case TGSI_OPCODE_USHR
:
5389 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5392 case TGSI_OPCODE_USLT
:
5393 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5396 case TGSI_OPCODE_USNE
:
5397 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5400 case TGSI_OPCODE_SWITCH
:
5401 exec_switch(mach
, inst
);
5404 case TGSI_OPCODE_CASE
:
5405 exec_case(mach
, inst
);
5408 case TGSI_OPCODE_DEFAULT
:
5412 case TGSI_OPCODE_ENDSWITCH
:
5413 exec_endswitch(mach
);
5416 case TGSI_OPCODE_SAMPLE_I
:
5417 exec_txf(mach
, inst
);
5420 case TGSI_OPCODE_SAMPLE_I_MS
:
5421 exec_txf(mach
, inst
);
5424 case TGSI_OPCODE_SAMPLE
:
5425 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5428 case TGSI_OPCODE_SAMPLE_B
:
5429 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5432 case TGSI_OPCODE_SAMPLE_C
:
5433 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5436 case TGSI_OPCODE_SAMPLE_C_LZ
:
5437 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5440 case TGSI_OPCODE_SAMPLE_D
:
5441 exec_sample_d(mach
, inst
);
5444 case TGSI_OPCODE_SAMPLE_L
:
5445 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5448 case TGSI_OPCODE_GATHER4
:
5452 case TGSI_OPCODE_SVIEWINFO
:
5453 exec_txq(mach
, inst
);
5456 case TGSI_OPCODE_SAMPLE_POS
:
5460 case TGSI_OPCODE_SAMPLE_INFO
:
5464 case TGSI_OPCODE_UARL
:
5465 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5468 case TGSI_OPCODE_UCMP
:
5469 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5472 case TGSI_OPCODE_IABS
:
5473 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5476 case TGSI_OPCODE_ISSG
:
5477 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5480 case TGSI_OPCODE_TEX2
:
5481 /* simple texture lookup */
5482 /* src[0] = texcoord */
5483 /* src[1] = compare */
5484 /* src[2] = sampler unit */
5485 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5487 case TGSI_OPCODE_TXB2
:
5488 /* simple texture lookup */
5489 /* src[0] = texcoord */
5491 /* src[2] = sampler unit */
5492 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5494 case TGSI_OPCODE_TXL2
:
5495 /* simple texture lookup */
5496 /* src[0] = texcoord */
5498 /* src[2] = sampler unit */
5499 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5502 case TGSI_OPCODE_IBFE
:
5503 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5505 case TGSI_OPCODE_UBFE
:
5506 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5508 case TGSI_OPCODE_BFI
:
5509 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5511 case TGSI_OPCODE_BREV
:
5512 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5514 case TGSI_OPCODE_POPC
:
5515 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5517 case TGSI_OPCODE_LSB
:
5518 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5520 case TGSI_OPCODE_IMSB
:
5521 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5523 case TGSI_OPCODE_UMSB
:
5524 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5527 case TGSI_OPCODE_F2D
:
5528 exec_f2d(mach
, inst
);
5531 case TGSI_OPCODE_D2F
:
5532 exec_d2f(mach
, inst
);
5535 case TGSI_OPCODE_DABS
:
5536 exec_double_unary(mach
, inst
, micro_dabs
);
5539 case TGSI_OPCODE_DNEG
:
5540 exec_double_unary(mach
, inst
, micro_dneg
);
5543 case TGSI_OPCODE_DADD
:
5544 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5547 case TGSI_OPCODE_DMUL
:
5548 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
5551 case TGSI_OPCODE_DMAX
:
5552 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
5555 case TGSI_OPCODE_DMIN
:
5556 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
5559 case TGSI_OPCODE_DSLT
:
5560 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
5563 case TGSI_OPCODE_DSGE
:
5564 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
5567 case TGSI_OPCODE_DSEQ
:
5568 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
5571 case TGSI_OPCODE_DSNE
:
5572 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
5575 case TGSI_OPCODE_DRCP
:
5576 exec_double_unary(mach
, inst
, micro_drcp
);
5579 case TGSI_OPCODE_DSQRT
:
5580 exec_double_unary(mach
, inst
, micro_dsqrt
);
5583 case TGSI_OPCODE_DRSQ
:
5584 exec_double_unary(mach
, inst
, micro_drsq
);
5587 case TGSI_OPCODE_DMAD
:
5588 exec_double_trinary(mach
, inst
, micro_dmad
);
5591 case TGSI_OPCODE_DFRAC
:
5592 exec_double_unary(mach
, inst
, micro_dfrac
);
5595 case TGSI_OPCODE_DLDEXP
:
5596 exec_dldexp(mach
, inst
);
5599 case TGSI_OPCODE_DFRACEXP
:
5600 exec_dfracexp(mach
, inst
);
5603 case TGSI_OPCODE_I2D
:
5604 exec_i2d(mach
, inst
);
5607 case TGSI_OPCODE_D2I
:
5608 exec_d2i(mach
, inst
);
5611 case TGSI_OPCODE_U2D
:
5612 exec_u2d(mach
, inst
);
5615 case TGSI_OPCODE_D2U
:
5616 exec_d2u(mach
, inst
);
5619 case TGSI_OPCODE_LOAD
:
5620 exec_load(mach
, inst
);
5623 case TGSI_OPCODE_STORE
:
5624 exec_store(mach
, inst
);
5627 case TGSI_OPCODE_ATOMUADD
:
5628 case TGSI_OPCODE_ATOMXCHG
:
5629 case TGSI_OPCODE_ATOMCAS
:
5630 case TGSI_OPCODE_ATOMAND
:
5631 case TGSI_OPCODE_ATOMOR
:
5632 case TGSI_OPCODE_ATOMXOR
:
5633 case TGSI_OPCODE_ATOMUMIN
:
5634 case TGSI_OPCODE_ATOMUMAX
:
5635 case TGSI_OPCODE_ATOMIMIN
:
5636 case TGSI_OPCODE_ATOMIMAX
:
5637 exec_atomop(mach
, inst
);
5640 case TGSI_OPCODE_RESQ
:
5641 exec_resq(mach
, inst
);
5643 case TGSI_OPCODE_BARRIER
:
5644 case TGSI_OPCODE_MEMBAR
:
5653 * Run TGSI interpreter.
5654 * \return bitmask of "alive" quad components
5657 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
)
5661 uint default_mask
= 0xf;
5663 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
5664 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
5666 if( mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
5667 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
5668 mach
->Primitives
[0] = 0;
5669 /* GS runs on a single primitive for now */
5673 if (mach
->NonHelperMask
== 0)
5674 mach
->NonHelperMask
= default_mask
;
5675 mach
->CondMask
= default_mask
;
5676 mach
->LoopMask
= default_mask
;
5677 mach
->ContMask
= default_mask
;
5678 mach
->FuncMask
= default_mask
;
5679 mach
->ExecMask
= default_mask
;
5681 mach
->Switch
.mask
= default_mask
;
5683 assert(mach
->CondStackTop
== 0);
5684 assert(mach
->LoopStackTop
== 0);
5685 assert(mach
->ContStackTop
== 0);
5686 assert(mach
->SwitchStackTop
== 0);
5687 assert(mach
->BreakStackTop
== 0);
5688 assert(mach
->CallStackTop
== 0);
5691 /* execute declarations (interpolants) */
5692 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
5693 exec_declaration( mach
, mach
->Declarations
+i
);
5698 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
5699 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
5702 memset(mach
->Temps
, 0, sizeof(temps
));
5703 memset(mach
->Outputs
, 0, sizeof(outputs
));
5704 memset(temps
, 0, sizeof(temps
));
5705 memset(outputs
, 0, sizeof(outputs
));
5708 /* execute instructions, until pc is set to -1 */
5714 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
5717 assert(pc
< (int) mach
->NumInstructions
);
5718 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
5721 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
5722 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
5725 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
5726 debug_printf("TEMP[%2u] = ", i
);
5727 for (j
= 0; j
< 4; j
++) {
5731 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5732 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
5733 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
5734 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
5735 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
5739 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
5740 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
5743 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
5744 debug_printf("OUT[%2u] = ", i
);
5745 for (j
= 0; j
< 4; j
++) {
5749 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5750 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
5751 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
5752 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
5753 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
5762 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5763 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
5765 * Scale back depth component.
5767 for (i
= 0; i
< 4; i
++)
5768 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
5772 /* Strictly speaking, these assertions aren't really needed but they
5773 * can potentially catch some bugs in the control flow code.
5775 assert(mach
->CondStackTop
== 0);
5776 assert(mach
->LoopStackTop
== 0);
5777 assert(mach
->ContStackTop
== 0);
5778 assert(mach
->SwitchStackTop
== 0);
5779 assert(mach
->BreakStackTop
== 0);
5780 assert(mach
->CallStackTop
== 0);
5782 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];