1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
82 struct tgsi_double_vector
{
83 union tgsi_double_channel xy
;
84 union tgsi_double_channel zw
;
88 micro_abs(union tgsi_exec_channel
*dst
,
89 const union tgsi_exec_channel
*src
)
91 dst
->f
[0] = fabsf(src
->f
[0]);
92 dst
->f
[1] = fabsf(src
->f
[1]);
93 dst
->f
[2] = fabsf(src
->f
[2]);
94 dst
->f
[3] = fabsf(src
->f
[3]);
98 micro_arl(union tgsi_exec_channel
*dst
,
99 const union tgsi_exec_channel
*src
)
101 dst
->i
[0] = (int)floorf(src
->f
[0]);
102 dst
->i
[1] = (int)floorf(src
->f
[1]);
103 dst
->i
[2] = (int)floorf(src
->f
[2]);
104 dst
->i
[3] = (int)floorf(src
->f
[3]);
108 micro_arr(union tgsi_exec_channel
*dst
,
109 const union tgsi_exec_channel
*src
)
111 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
112 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
113 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
114 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
118 micro_ceil(union tgsi_exec_channel
*dst
,
119 const union tgsi_exec_channel
*src
)
121 dst
->f
[0] = ceilf(src
->f
[0]);
122 dst
->f
[1] = ceilf(src
->f
[1]);
123 dst
->f
[2] = ceilf(src
->f
[2]);
124 dst
->f
[3] = ceilf(src
->f
[3]);
128 micro_clamp(union tgsi_exec_channel
*dst
,
129 const union tgsi_exec_channel
*src0
,
130 const union tgsi_exec_channel
*src1
,
131 const union tgsi_exec_channel
*src2
)
133 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
134 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
135 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
136 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
140 micro_cmp(union tgsi_exec_channel
*dst
,
141 const union tgsi_exec_channel
*src0
,
142 const union tgsi_exec_channel
*src1
,
143 const union tgsi_exec_channel
*src2
)
145 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
146 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
147 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
148 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
152 micro_cos(union tgsi_exec_channel
*dst
,
153 const union tgsi_exec_channel
*src
)
155 dst
->f
[0] = cosf(src
->f
[0]);
156 dst
->f
[1] = cosf(src
->f
[1]);
157 dst
->f
[2] = cosf(src
->f
[2]);
158 dst
->f
[3] = cosf(src
->f
[3]);
162 micro_d2f(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->f
[0] = (float)src
->d
[0];
166 dst
->f
[1] = (float)src
->d
[1];
167 dst
->f
[2] = (float)src
->d
[2];
168 dst
->f
[3] = (float)src
->d
[3];
172 micro_d2i(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->i
[0] = (int)src
->d
[0];
176 dst
->i
[1] = (int)src
->d
[1];
177 dst
->i
[2] = (int)src
->d
[2];
178 dst
->i
[3] = (int)src
->d
[3];
182 micro_d2u(union tgsi_exec_channel
*dst
,
183 const union tgsi_double_channel
*src
)
185 dst
->u
[0] = (unsigned)src
->d
[0];
186 dst
->u
[1] = (unsigned)src
->d
[1];
187 dst
->u
[2] = (unsigned)src
->d
[2];
188 dst
->u
[3] = (unsigned)src
->d
[3];
191 micro_dabs(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
195 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
196 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
197 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
201 micro_dadd(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddy(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
231 micro_dmul(union tgsi_double_channel
*dst
,
232 const union tgsi_double_channel
*src
)
234 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
235 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
236 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
237 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
241 micro_dmax(union tgsi_double_channel
*dst
,
242 const union tgsi_double_channel
*src
)
244 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
245 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
246 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
247 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
251 micro_dmin(union tgsi_double_channel
*dst
,
252 const union tgsi_double_channel
*src
)
254 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
255 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
256 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
257 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
261 micro_dneg(union tgsi_double_channel
*dst
,
262 const union tgsi_double_channel
*src
)
264 dst
->d
[0] = -src
->d
[0];
265 dst
->d
[1] = -src
->d
[1];
266 dst
->d
[2] = -src
->d
[2];
267 dst
->d
[3] = -src
->d
[3];
271 micro_dslt(union tgsi_double_channel
*dst
,
272 const union tgsi_double_channel
*src
)
274 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
275 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
276 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
277 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
281 micro_dsne(union tgsi_double_channel
*dst
,
282 const union tgsi_double_channel
*src
)
284 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
285 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
286 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
287 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
291 micro_dsge(union tgsi_double_channel
*dst
,
292 const union tgsi_double_channel
*src
)
294 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
295 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
296 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
297 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
301 micro_dseq(union tgsi_double_channel
*dst
,
302 const union tgsi_double_channel
*src
)
304 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
305 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
306 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
307 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
311 micro_drcp(union tgsi_double_channel
*dst
,
312 const union tgsi_double_channel
*src
)
314 dst
->d
[0] = 1.0 / src
->d
[0];
315 dst
->d
[1] = 1.0 / src
->d
[1];
316 dst
->d
[2] = 1.0 / src
->d
[2];
317 dst
->d
[3] = 1.0 / src
->d
[3];
321 micro_dsqrt(union tgsi_double_channel
*dst
,
322 const union tgsi_double_channel
*src
)
324 dst
->d
[0] = sqrt(src
->d
[0]);
325 dst
->d
[1] = sqrt(src
->d
[1]);
326 dst
->d
[2] = sqrt(src
->d
[2]);
327 dst
->d
[3] = sqrt(src
->d
[3]);
331 micro_drsq(union tgsi_double_channel
*dst
,
332 const union tgsi_double_channel
*src
)
334 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
335 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
336 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
337 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
341 micro_dmad(union tgsi_double_channel
*dst
,
342 const union tgsi_double_channel
*src
)
344 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
345 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
346 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
347 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
351 micro_dfrac(union tgsi_double_channel
*dst
,
352 const union tgsi_double_channel
*src
)
354 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
355 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
356 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
357 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
361 micro_dldexp(union tgsi_double_channel
*dst
,
362 const union tgsi_double_channel
*src0
,
363 union tgsi_exec_channel
*src1
)
365 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
366 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
367 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
368 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
372 micro_dfracexp(union tgsi_double_channel
*dst
,
373 union tgsi_exec_channel
*dst_exp
,
374 const union tgsi_double_channel
*src
)
376 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
377 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
378 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
379 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
383 micro_exp2(union tgsi_exec_channel
*dst
,
384 const union tgsi_exec_channel
*src
)
387 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
388 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
389 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
390 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
395 union tgsi_exec_channel clamped
;
397 for (i
= 0; i
< 4; i
++) {
398 if (src
->f
[i
] > 127.99999f
) {
399 clamped
.f
[i
] = 127.99999f
;
400 } else if (src
->f
[i
] < -126.99999f
) {
401 clamped
.f
[i
] = -126.99999f
;
403 clamped
.f
[i
] = src
->f
[i
];
409 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
410 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
411 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
412 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
413 #endif /* FAST_MATH */
417 micro_f2d(union tgsi_double_channel
*dst
,
418 const union tgsi_exec_channel
*src
)
420 dst
->d
[0] = (double)src
->f
[0];
421 dst
->d
[1] = (double)src
->f
[1];
422 dst
->d
[2] = (double)src
->f
[2];
423 dst
->d
[3] = (double)src
->f
[3];
427 micro_flr(union tgsi_exec_channel
*dst
,
428 const union tgsi_exec_channel
*src
)
430 dst
->f
[0] = floorf(src
->f
[0]);
431 dst
->f
[1] = floorf(src
->f
[1]);
432 dst
->f
[2] = floorf(src
->f
[2]);
433 dst
->f
[3] = floorf(src
->f
[3]);
437 micro_frc(union tgsi_exec_channel
*dst
,
438 const union tgsi_exec_channel
*src
)
440 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
441 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
442 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
443 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
447 micro_i2d(union tgsi_double_channel
*dst
,
448 const union tgsi_exec_channel
*src
)
450 dst
->d
[0] = (double)src
->i
[0];
451 dst
->d
[1] = (double)src
->i
[1];
452 dst
->d
[2] = (double)src
->i
[2];
453 dst
->d
[3] = (double)src
->i
[3];
457 micro_iabs(union tgsi_exec_channel
*dst
,
458 const union tgsi_exec_channel
*src
)
460 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
461 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
462 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
463 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
467 micro_ineg(union tgsi_exec_channel
*dst
,
468 const union tgsi_exec_channel
*src
)
470 dst
->i
[0] = -src
->i
[0];
471 dst
->i
[1] = -src
->i
[1];
472 dst
->i
[2] = -src
->i
[2];
473 dst
->i
[3] = -src
->i
[3];
477 micro_lg2(union tgsi_exec_channel
*dst
,
478 const union tgsi_exec_channel
*src
)
481 dst
->f
[0] = util_fast_log2(src
->f
[0]);
482 dst
->f
[1] = util_fast_log2(src
->f
[1]);
483 dst
->f
[2] = util_fast_log2(src
->f
[2]);
484 dst
->f
[3] = util_fast_log2(src
->f
[3]);
486 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
487 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
488 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
489 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
494 micro_lrp(union tgsi_exec_channel
*dst
,
495 const union tgsi_exec_channel
*src0
,
496 const union tgsi_exec_channel
*src1
,
497 const union tgsi_exec_channel
*src2
)
499 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
500 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
501 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
502 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
506 micro_mad(union tgsi_exec_channel
*dst
,
507 const union tgsi_exec_channel
*src0
,
508 const union tgsi_exec_channel
*src1
,
509 const union tgsi_exec_channel
*src2
)
511 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
512 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
513 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
514 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
518 micro_mov(union tgsi_exec_channel
*dst
,
519 const union tgsi_exec_channel
*src
)
521 dst
->u
[0] = src
->u
[0];
522 dst
->u
[1] = src
->u
[1];
523 dst
->u
[2] = src
->u
[2];
524 dst
->u
[3] = src
->u
[3];
528 micro_rcp(union tgsi_exec_channel
*dst
,
529 const union tgsi_exec_channel
*src
)
531 #if 0 /* for debugging */
532 assert(src
->f
[0] != 0.0f
);
533 assert(src
->f
[1] != 0.0f
);
534 assert(src
->f
[2] != 0.0f
);
535 assert(src
->f
[3] != 0.0f
);
537 dst
->f
[0] = 1.0f
/ src
->f
[0];
538 dst
->f
[1] = 1.0f
/ src
->f
[1];
539 dst
->f
[2] = 1.0f
/ src
->f
[2];
540 dst
->f
[3] = 1.0f
/ src
->f
[3];
544 micro_rnd(union tgsi_exec_channel
*dst
,
545 const union tgsi_exec_channel
*src
)
547 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
548 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
549 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
550 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
554 micro_rsq(union tgsi_exec_channel
*dst
,
555 const union tgsi_exec_channel
*src
)
557 #if 0 /* for debugging */
558 assert(src
->f
[0] != 0.0f
);
559 assert(src
->f
[1] != 0.0f
);
560 assert(src
->f
[2] != 0.0f
);
561 assert(src
->f
[3] != 0.0f
);
563 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
564 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
565 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
566 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
570 micro_sqrt(union tgsi_exec_channel
*dst
,
571 const union tgsi_exec_channel
*src
)
573 dst
->f
[0] = sqrtf(src
->f
[0]);
574 dst
->f
[1] = sqrtf(src
->f
[1]);
575 dst
->f
[2] = sqrtf(src
->f
[2]);
576 dst
->f
[3] = sqrtf(src
->f
[3]);
580 micro_seq(union tgsi_exec_channel
*dst
,
581 const union tgsi_exec_channel
*src0
,
582 const union tgsi_exec_channel
*src1
)
584 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
585 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
586 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
587 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
591 micro_sge(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src0
,
593 const union tgsi_exec_channel
*src1
)
595 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
596 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
597 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
598 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
602 micro_sgn(union tgsi_exec_channel
*dst
,
603 const union tgsi_exec_channel
*src
)
605 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
608 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
612 micro_isgn(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src
)
615 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
616 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
617 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
618 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
622 micro_sgt(union tgsi_exec_channel
*dst
,
623 const union tgsi_exec_channel
*src0
,
624 const union tgsi_exec_channel
*src1
)
626 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
627 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
628 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
629 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
633 micro_sin(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->f
[0] = sinf(src
->f
[0]);
637 dst
->f
[1] = sinf(src
->f
[1]);
638 dst
->f
[2] = sinf(src
->f
[2]);
639 dst
->f
[3] = sinf(src
->f
[3]);
643 micro_sle(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_slt(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src0
,
656 const union tgsi_exec_channel
*src1
)
658 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
659 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
660 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
661 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
665 micro_sne(union tgsi_exec_channel
*dst
,
666 const union tgsi_exec_channel
*src0
,
667 const union tgsi_exec_channel
*src1
)
669 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
670 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
671 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
672 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
676 micro_trunc(union tgsi_exec_channel
*dst
,
677 const union tgsi_exec_channel
*src
)
679 dst
->f
[0] = truncf(src
->f
[0]);
680 dst
->f
[1] = truncf(src
->f
[1]);
681 dst
->f
[2] = truncf(src
->f
[2]);
682 dst
->f
[3] = truncf(src
->f
[3]);
686 micro_u2d(union tgsi_double_channel
*dst
,
687 const union tgsi_exec_channel
*src
)
689 dst
->d
[0] = (double)src
->u
[0];
690 dst
->d
[1] = (double)src
->u
[1];
691 dst
->d
[2] = (double)src
->u
[2];
692 dst
->d
[3] = (double)src
->u
[3];
695 enum tgsi_exec_datatype
{
696 TGSI_EXEC_DATA_FLOAT
,
699 TGSI_EXEC_DATA_DOUBLE
703 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
705 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
706 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
707 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
708 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
709 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
710 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
713 /** The execution mask depends on the conditional mask and the loop mask */
714 #define UPDATE_EXEC_MASK(MACH) \
715 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
718 static const union tgsi_exec_channel ZeroVec
=
719 { { 0.0, 0.0, 0.0, 0.0 } };
721 static const union tgsi_exec_channel OneVec
= {
722 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
725 static const union tgsi_exec_channel P128Vec
= {
726 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
729 static const union tgsi_exec_channel M128Vec
= {
730 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
735 * Assert that none of the float values in 'chan' are infinite or NaN.
736 * NaN and Inf may occur normally during program execution and should
737 * not lead to crashes, etc. But when debugging, it's helpful to catch
741 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
743 assert(!util_is_inf_or_nan((chan
)->f
[0]));
744 assert(!util_is_inf_or_nan((chan
)->f
[1]));
745 assert(!util_is_inf_or_nan((chan
)->f
[2]));
746 assert(!util_is_inf_or_nan((chan
)->f
[3]));
752 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
754 debug_printf("%s = {%f, %f, %f, %f}\n",
755 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
762 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
764 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
766 debug_printf("Temp[%u] =\n", index
);
767 for (i
= 0; i
< 4; i
++) {
768 debug_printf(" %c: { %f, %f, %f, %f }\n",
780 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
783 const unsigned *buf_sizes
)
787 for (i
= 0; i
< num_bufs
; i
++) {
788 mach
->Consts
[i
] = bufs
[i
];
789 mach
->ConstsSize
[i
] = buf_sizes
[i
];
795 * Check if there's a potential src/dst register data dependency when
796 * using SOA execution.
799 * This would expand into:
804 * The second instruction will have the wrong value for t0 if executed as-is.
807 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
811 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
812 if (writemask
== TGSI_WRITEMASK_X
||
813 writemask
== TGSI_WRITEMASK_Y
||
814 writemask
== TGSI_WRITEMASK_Z
||
815 writemask
== TGSI_WRITEMASK_W
||
816 writemask
== TGSI_WRITEMASK_NONE
) {
817 /* no chance of data dependency */
821 /* loop over src regs */
822 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
823 if ((inst
->Src
[i
].Register
.File
==
824 inst
->Dst
[0].Register
.File
) &&
825 ((inst
->Src
[i
].Register
.Index
==
826 inst
->Dst
[0].Register
.Index
) ||
827 inst
->Src
[i
].Register
.Indirect
||
828 inst
->Dst
[0].Register
.Indirect
)) {
829 /* loop over dest channels */
830 uint channelsWritten
= 0x0;
831 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
832 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
833 /* check if we're reading a channel that's been written */
834 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
835 if (channelsWritten
& (1 << swizzle
)) {
839 channelsWritten
|= (1 << chan
);
849 * Initialize machine state by expanding tokens to full instructions,
850 * allocating temporary storage, setting up constants, etc.
851 * After this, we can call tgsi_exec_machine_run() many times.
854 tgsi_exec_machine_bind_shader(
855 struct tgsi_exec_machine
*mach
,
856 const struct tgsi_token
*tokens
,
857 struct tgsi_sampler
*sampler
,
858 struct tgsi_image
*image
,
859 struct tgsi_buffer
*buffer
)
862 struct tgsi_parse_context parse
;
863 struct tgsi_full_instruction
*instructions
;
864 struct tgsi_full_declaration
*declarations
;
865 uint maxInstructions
= 10, numInstructions
= 0;
866 uint maxDeclarations
= 10, numDeclarations
= 0;
869 tgsi_dump(tokens
, 0);
875 mach
->Tokens
= tokens
;
876 mach
->Sampler
= sampler
;
878 mach
->Buffer
= buffer
;
881 /* unbind and free all */
882 FREE(mach
->Declarations
);
883 mach
->Declarations
= NULL
;
884 mach
->NumDeclarations
= 0;
886 FREE(mach
->Instructions
);
887 mach
->Instructions
= NULL
;
888 mach
->NumInstructions
= 0;
893 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
894 if (k
!= TGSI_PARSE_OK
) {
895 debug_printf( "Problem parsing!\n" );
900 mach
->NumOutputs
= 0;
902 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
903 mach
->SysSemanticToIndex
[k
] = -1;
905 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
906 !mach
->UsedGeometryShader
) {
907 struct tgsi_exec_vector
*inputs
;
908 struct tgsi_exec_vector
*outputs
;
910 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
911 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
917 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
918 TGSI_MAX_TOTAL_VERTICES
, 16);
925 align_free(mach
->Inputs
);
926 align_free(mach
->Outputs
);
928 mach
->Inputs
= inputs
;
929 mach
->Outputs
= outputs
;
930 mach
->UsedGeometryShader
= TRUE
;
933 declarations
= (struct tgsi_full_declaration
*)
934 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
940 instructions
= (struct tgsi_full_instruction
*)
941 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
944 FREE( declarations
);
948 while( !tgsi_parse_end_of_tokens( &parse
) ) {
951 tgsi_parse_token( &parse
);
952 switch( parse
.FullToken
.Token
.Type
) {
953 case TGSI_TOKEN_TYPE_DECLARATION
:
954 /* save expanded declaration */
955 if (numDeclarations
== maxDeclarations
) {
956 declarations
= REALLOC(declarations
,
958 * sizeof(struct tgsi_full_declaration
),
959 (maxDeclarations
+ 10)
960 * sizeof(struct tgsi_full_declaration
));
961 maxDeclarations
+= 10;
963 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
965 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
966 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
971 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
972 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
973 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
976 memcpy(declarations
+ numDeclarations
,
977 &parse
.FullToken
.FullDeclaration
,
978 sizeof(declarations
[0]));
982 case TGSI_TOKEN_TYPE_IMMEDIATE
:
984 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
986 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
988 for( i
= 0; i
< size
; i
++ ) {
989 mach
->Imms
[mach
->ImmLimit
][i
] =
990 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
996 case TGSI_TOKEN_TYPE_INSTRUCTION
:
998 /* save expanded instruction */
999 if (numInstructions
== maxInstructions
) {
1000 instructions
= REALLOC(instructions
,
1002 * sizeof(struct tgsi_full_instruction
),
1003 (maxInstructions
+ 10)
1004 * sizeof(struct tgsi_full_instruction
));
1005 maxInstructions
+= 10;
1008 memcpy(instructions
+ numInstructions
,
1009 &parse
.FullToken
.FullInstruction
,
1010 sizeof(instructions
[0]));
1015 case TGSI_TOKEN_TYPE_PROPERTY
:
1016 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1017 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1018 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1027 tgsi_parse_free (&parse
);
1029 FREE(mach
->Declarations
);
1030 mach
->Declarations
= declarations
;
1031 mach
->NumDeclarations
= numDeclarations
;
1033 FREE(mach
->Instructions
);
1034 mach
->Instructions
= instructions
;
1035 mach
->NumInstructions
= numInstructions
;
1039 struct tgsi_exec_machine
*
1040 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1042 struct tgsi_exec_machine
*mach
;
1045 mach
= align_malloc( sizeof *mach
, 16 );
1049 memset(mach
, 0, sizeof(*mach
));
1051 mach
->ShaderType
= shader_type
;
1052 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1053 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1054 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
1056 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1057 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1058 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1059 if (!mach
->Inputs
|| !mach
->Outputs
)
1063 /* Setup constants needed by the SSE2 executor. */
1064 for( i
= 0; i
< 4; i
++ ) {
1065 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1066 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1067 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1068 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1069 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1070 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1071 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1072 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1073 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1074 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1078 /* silence warnings */
1087 align_free(mach
->Inputs
);
1088 align_free(mach
->Outputs
);
1096 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1099 FREE(mach
->Instructions
);
1100 FREE(mach
->Declarations
);
1102 align_free(mach
->Inputs
);
1103 align_free(mach
->Outputs
);
1110 micro_add(union tgsi_exec_channel
*dst
,
1111 const union tgsi_exec_channel
*src0
,
1112 const union tgsi_exec_channel
*src1
)
1114 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1115 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1116 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1117 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1122 union tgsi_exec_channel
*dst
,
1123 const union tgsi_exec_channel
*src0
,
1124 const union tgsi_exec_channel
*src1
)
1126 if (src1
->f
[0] != 0) {
1127 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1129 if (src1
->f
[1] != 0) {
1130 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1132 if (src1
->f
[2] != 0) {
1133 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1135 if (src1
->f
[3] != 0) {
1136 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1142 union tgsi_exec_channel
*dst
,
1143 const union tgsi_exec_channel
*src0
,
1144 const union tgsi_exec_channel
*src1
,
1145 const union tgsi_exec_channel
*src2
,
1146 const union tgsi_exec_channel
*src3
)
1148 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1149 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1150 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1151 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1155 micro_max(union tgsi_exec_channel
*dst
,
1156 const union tgsi_exec_channel
*src0
,
1157 const union tgsi_exec_channel
*src1
)
1159 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1160 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1161 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1162 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1166 micro_min(union tgsi_exec_channel
*dst
,
1167 const union tgsi_exec_channel
*src0
,
1168 const union tgsi_exec_channel
*src1
)
1170 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1171 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1172 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1173 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1177 micro_mul(union tgsi_exec_channel
*dst
,
1178 const union tgsi_exec_channel
*src0
,
1179 const union tgsi_exec_channel
*src1
)
1181 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1182 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1183 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1184 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1189 union tgsi_exec_channel
*dst
,
1190 const union tgsi_exec_channel
*src
)
1192 dst
->f
[0] = -src
->f
[0];
1193 dst
->f
[1] = -src
->f
[1];
1194 dst
->f
[2] = -src
->f
[2];
1195 dst
->f
[3] = -src
->f
[3];
1200 union tgsi_exec_channel
*dst
,
1201 const union tgsi_exec_channel
*src0
,
1202 const union tgsi_exec_channel
*src1
)
1205 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1206 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1207 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1208 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1210 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1211 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1212 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1213 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1218 micro_sub(union tgsi_exec_channel
*dst
,
1219 const union tgsi_exec_channel
*src0
,
1220 const union tgsi_exec_channel
*src1
)
1222 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1223 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1224 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1225 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1229 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1230 const uint chan_index
,
1233 const union tgsi_exec_channel
*index
,
1234 const union tgsi_exec_channel
*index2D
,
1235 union tgsi_exec_channel
*chan
)
1239 assert(swizzle
< 4);
1242 case TGSI_FILE_CONSTANT
:
1243 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1244 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1245 assert(mach
->Consts
[index2D
->i
[i
]]);
1247 if (index
->i
[i
] < 0) {
1250 /* NOTE: copying the const value as a uint instead of float */
1251 const uint constbuf
= index2D
->i
[i
];
1252 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1253 const int pos
= index
->i
[i
] * 4 + swizzle
;
1254 /* const buffer bounds check */
1255 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1257 /* Debug: print warning */
1258 static int count
= 0;
1260 debug_printf("TGSI Exec: const buffer index %d"
1261 " out of bounds\n", pos
);
1266 chan
->u
[i
] = buf
[pos
];
1271 case TGSI_FILE_INPUT
:
1272 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1274 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1275 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1276 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1277 index2D->i[i], index->i[i]);
1279 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1281 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1282 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1286 case TGSI_FILE_SYSTEM_VALUE
:
1287 /* XXX no swizzling at this point. Will be needed if we put
1288 * gl_FragCoord, for example, in a sys value register.
1290 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1291 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1295 case TGSI_FILE_TEMPORARY
:
1296 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1297 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1298 assert(index2D
->i
[i
] == 0);
1300 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1304 case TGSI_FILE_IMMEDIATE
:
1305 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1306 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1307 assert(index2D
->i
[i
] == 0);
1309 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1313 case TGSI_FILE_ADDRESS
:
1314 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1315 assert(index
->i
[i
] >= 0);
1316 assert(index2D
->i
[i
] == 0);
1318 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1322 case TGSI_FILE_PREDICATE
:
1323 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1324 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1325 assert(index2D
->i
[i
] == 0);
1327 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1331 case TGSI_FILE_OUTPUT
:
1332 /* vertex/fragment output vars can be read too */
1333 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1334 assert(index
->i
[i
] >= 0);
1335 assert(index2D
->i
[i
] == 0);
1337 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1343 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1350 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1351 union tgsi_exec_channel
*chan
,
1352 const struct tgsi_full_src_register
*reg
,
1353 const uint chan_index
,
1354 enum tgsi_exec_datatype src_datatype
)
1356 union tgsi_exec_channel index
;
1357 union tgsi_exec_channel index2D
;
1360 /* We start with a direct index into a register file.
1364 * file = Register.File
1365 * [1] = Register.Index
1370 index
.i
[3] = reg
->Register
.Index
;
1372 /* There is an extra source register that indirectly subscripts
1373 * a register file. The direct index now becomes an offset
1374 * that is being added to the indirect register.
1378 * ind = Indirect.File
1379 * [2] = Indirect.Index
1380 * .x = Indirect.SwizzleX
1382 if (reg
->Register
.Indirect
) {
1383 union tgsi_exec_channel index2
;
1384 union tgsi_exec_channel indir_index
;
1385 const uint execmask
= mach
->ExecMask
;
1388 /* which address register (always zero now) */
1392 index2
.i
[3] = reg
->Indirect
.Index
;
1393 /* get current value of address register[swizzle] */
1394 swizzle
= reg
->Indirect
.Swizzle
;
1395 fetch_src_file_channel(mach
,
1403 /* add value of address register to the offset */
1404 index
.i
[0] += indir_index
.i
[0];
1405 index
.i
[1] += indir_index
.i
[1];
1406 index
.i
[2] += indir_index
.i
[2];
1407 index
.i
[3] += indir_index
.i
[3];
1409 /* for disabled execution channels, zero-out the index to
1410 * avoid using a potential garbage value.
1412 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1413 if ((execmask
& (1 << i
)) == 0)
1418 /* There is an extra source register that is a second
1419 * subscript to a register file. Effectively it means that
1420 * the register file is actually a 2D array of registers.
1424 * [3] = Dimension.Index
1426 if (reg
->Register
.Dimension
) {
1430 index2D
.i
[3] = reg
->Dimension
.Index
;
1432 /* Again, the second subscript index can be addressed indirectly
1433 * identically to the first one.
1434 * Nothing stops us from indirectly addressing the indirect register,
1435 * but there is no need for that, so we won't exercise it.
1437 * file[ind[4].y+3][1],
1439 * ind = DimIndirect.File
1440 * [4] = DimIndirect.Index
1441 * .y = DimIndirect.SwizzleX
1443 if (reg
->Dimension
.Indirect
) {
1444 union tgsi_exec_channel index2
;
1445 union tgsi_exec_channel indir_index
;
1446 const uint execmask
= mach
->ExecMask
;
1452 index2
.i
[3] = reg
->DimIndirect
.Index
;
1454 swizzle
= reg
->DimIndirect
.Swizzle
;
1455 fetch_src_file_channel(mach
,
1457 reg
->DimIndirect
.File
,
1463 index2D
.i
[0] += indir_index
.i
[0];
1464 index2D
.i
[1] += indir_index
.i
[1];
1465 index2D
.i
[2] += indir_index
.i
[2];
1466 index2D
.i
[3] += indir_index
.i
[3];
1468 /* for disabled execution channels, zero-out the index to
1469 * avoid using a potential garbage value.
1471 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1472 if ((execmask
& (1 << i
)) == 0) {
1478 /* If by any chance there was a need for a 3D array of register
1479 * files, we would have to check whether Dimension is followed
1480 * by a dimension register and continue the saga.
1489 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1490 fetch_src_file_channel(mach
,
1500 fetch_source(const struct tgsi_exec_machine
*mach
,
1501 union tgsi_exec_channel
*chan
,
1502 const struct tgsi_full_src_register
*reg
,
1503 const uint chan_index
,
1504 enum tgsi_exec_datatype src_datatype
)
1506 fetch_source_d(mach
, chan
, reg
, chan_index
, src_datatype
);
1508 if (reg
->Register
.Absolute
) {
1509 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1510 micro_abs(chan
, chan
);
1512 micro_iabs(chan
, chan
);
1516 if (reg
->Register
.Negate
) {
1517 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1518 micro_neg(chan
, chan
);
1520 micro_ineg(chan
, chan
);
1525 static union tgsi_exec_channel
*
1526 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1527 const union tgsi_exec_channel
*chan
,
1528 const struct tgsi_full_dst_register
*reg
,
1529 const struct tgsi_full_instruction
*inst
,
1531 enum tgsi_exec_datatype dst_datatype
)
1534 static union tgsi_exec_channel null
;
1535 union tgsi_exec_channel
*dst
;
1536 union tgsi_exec_channel index2D
;
1537 uint execmask
= mach
->ExecMask
;
1538 int offset
= 0; /* indirection offset */
1542 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1543 check_inf_or_nan(chan
);
1546 /* There is an extra source register that indirectly subscripts
1547 * a register file. The direct index now becomes an offset
1548 * that is being added to the indirect register.
1552 * ind = Indirect.File
1553 * [2] = Indirect.Index
1554 * .x = Indirect.SwizzleX
1556 if (reg
->Register
.Indirect
) {
1557 union tgsi_exec_channel index
;
1558 union tgsi_exec_channel indir_index
;
1561 /* which address register (always zero for now) */
1565 index
.i
[3] = reg
->Indirect
.Index
;
1567 /* get current value of address register[swizzle] */
1568 swizzle
= reg
->Indirect
.Swizzle
;
1570 /* fetch values from the address/indirection register */
1571 fetch_src_file_channel(mach
,
1579 /* save indirection offset */
1580 offset
= indir_index
.i
[0];
1583 /* There is an extra source register that is a second
1584 * subscript to a register file. Effectively it means that
1585 * the register file is actually a 2D array of registers.
1589 * [3] = Dimension.Index
1591 if (reg
->Register
.Dimension
) {
1595 index2D
.i
[3] = reg
->Dimension
.Index
;
1597 /* Again, the second subscript index can be addressed indirectly
1598 * identically to the first one.
1599 * Nothing stops us from indirectly addressing the indirect register,
1600 * but there is no need for that, so we won't exercise it.
1602 * file[ind[4].y+3][1],
1604 * ind = DimIndirect.File
1605 * [4] = DimIndirect.Index
1606 * .y = DimIndirect.SwizzleX
1608 if (reg
->Dimension
.Indirect
) {
1609 union tgsi_exec_channel index2
;
1610 union tgsi_exec_channel indir_index
;
1611 const uint execmask
= mach
->ExecMask
;
1618 index2
.i
[3] = reg
->DimIndirect
.Index
;
1620 swizzle
= reg
->DimIndirect
.Swizzle
;
1621 fetch_src_file_channel(mach
,
1623 reg
->DimIndirect
.File
,
1629 index2D
.i
[0] += indir_index
.i
[0];
1630 index2D
.i
[1] += indir_index
.i
[1];
1631 index2D
.i
[2] += indir_index
.i
[2];
1632 index2D
.i
[3] += indir_index
.i
[3];
1634 /* for disabled execution channels, zero-out the index to
1635 * avoid using a potential garbage value.
1637 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1638 if ((execmask
& (1 << i
)) == 0) {
1644 /* If by any chance there was a need for a 3D array of register
1645 * files, we would have to check whether Dimension is followed
1646 * by a dimension register and continue the saga.
1655 switch (reg
->Register
.File
) {
1656 case TGSI_FILE_NULL
:
1660 case TGSI_FILE_OUTPUT
:
1661 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1662 + reg
->Register
.Index
;
1663 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1665 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1666 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1667 reg
->Register
.Index
);
1668 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1669 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1670 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1671 if (execmask
& (1 << i
))
1672 debug_printf("%f, ", chan
->f
[i
]);
1673 debug_printf(")\n");
1678 case TGSI_FILE_TEMPORARY
:
1679 index
= reg
->Register
.Index
;
1680 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1681 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1684 case TGSI_FILE_ADDRESS
:
1685 index
= reg
->Register
.Index
;
1686 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1689 case TGSI_FILE_PREDICATE
:
1690 index
= reg
->Register
.Index
;
1691 assert(index
< TGSI_EXEC_NUM_PREDS
);
1692 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1700 if (inst
->Instruction
.Predicate
) {
1702 union tgsi_exec_channel
*pred
;
1704 switch (chan_index
) {
1706 swizzle
= inst
->Predicate
.SwizzleX
;
1709 swizzle
= inst
->Predicate
.SwizzleY
;
1712 swizzle
= inst
->Predicate
.SwizzleZ
;
1715 swizzle
= inst
->Predicate
.SwizzleW
;
1722 assert(inst
->Predicate
.Index
== 0);
1724 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1726 if (inst
->Predicate
.Negate
) {
1727 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1729 execmask
&= ~(1 << i
);
1733 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1735 execmask
&= ~(1 << i
);
1745 store_dest_double(struct tgsi_exec_machine
*mach
,
1746 const union tgsi_exec_channel
*chan
,
1747 const struct tgsi_full_dst_register
*reg
,
1748 const struct tgsi_full_instruction
*inst
,
1750 enum tgsi_exec_datatype dst_datatype
)
1752 union tgsi_exec_channel
*dst
;
1753 const uint execmask
= mach
->ExecMask
;
1756 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1762 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1763 if (execmask
& (1 << i
))
1764 dst
->i
[i
] = chan
->i
[i
];
1768 store_dest(struct tgsi_exec_machine
*mach
,
1769 const union tgsi_exec_channel
*chan
,
1770 const struct tgsi_full_dst_register
*reg
,
1771 const struct tgsi_full_instruction
*inst
,
1773 enum tgsi_exec_datatype dst_datatype
)
1775 union tgsi_exec_channel
*dst
;
1776 const uint execmask
= mach
->ExecMask
;
1779 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
1784 if (!inst
->Instruction
.Saturate
) {
1785 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1786 if (execmask
& (1 << i
))
1787 dst
->i
[i
] = chan
->i
[i
];
1790 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1791 if (execmask
& (1 << i
)) {
1792 if (chan
->f
[i
] < 0.0f
)
1794 else if (chan
->f
[i
] > 1.0f
)
1797 dst
->i
[i
] = chan
->i
[i
];
1802 #define FETCH(VAL,INDEX,CHAN)\
1803 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1805 #define IFETCH(VAL,INDEX,CHAN)\
1806 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1810 * Execute ARB-style KIL which is predicated by a src register.
1811 * Kill fragment if any of the four values is less than zero.
1814 exec_kill_if(struct tgsi_exec_machine
*mach
,
1815 const struct tgsi_full_instruction
*inst
)
1819 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1820 union tgsi_exec_channel r
[1];
1822 /* This mask stores component bits that were already tested. */
1825 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1830 /* unswizzle channel */
1831 swizzle
= tgsi_util_get_full_src_register_swizzle (
1835 /* check if the component has not been already tested */
1836 if (uniquemask
& (1 << swizzle
))
1838 uniquemask
|= 1 << swizzle
;
1840 FETCH(&r
[0], 0, chan_index
);
1841 for (i
= 0; i
< 4; i
++)
1842 if (r
[0].f
[i
] < 0.0f
)
1846 /* restrict to fragments currently executing */
1847 kilmask
&= mach
->ExecMask
;
1849 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1853 * Unconditional fragment kill/discard.
1856 exec_kill(struct tgsi_exec_machine
*mach
,
1857 const struct tgsi_full_instruction
*inst
)
1859 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1861 /* kill fragment for all fragments currently executing */
1862 kilmask
= mach
->ExecMask
;
1863 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1867 emit_vertex(struct tgsi_exec_machine
*mach
)
1869 /* FIXME: check for exec mask correctly
1871 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1872 if ((mach->ExecMask & (1 << i)))
1874 if (mach
->ExecMask
) {
1875 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
1878 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1879 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1884 emit_primitive(struct tgsi_exec_machine
*mach
)
1886 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1887 /* FIXME: check for exec mask correctly
1889 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1890 if ((mach->ExecMask & (1 << i)))
1892 if (mach
->ExecMask
) {
1894 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1895 mach
->Primitives
[*prim_count
] = 0;
1900 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1902 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1904 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1905 if (emitted_verts
) {
1906 emit_primitive(mach
);
1913 * Fetch four texture samples using STR texture coordinates.
1916 fetch_texel( struct tgsi_sampler
*sampler
,
1917 const unsigned sview_idx
,
1918 const unsigned sampler_idx
,
1919 const union tgsi_exec_channel
*s
,
1920 const union tgsi_exec_channel
*t
,
1921 const union tgsi_exec_channel
*p
,
1922 const union tgsi_exec_channel
*c0
,
1923 const union tgsi_exec_channel
*c1
,
1924 float derivs
[3][2][TGSI_QUAD_SIZE
],
1925 const int8_t offset
[3],
1926 enum tgsi_sampler_control control
,
1927 union tgsi_exec_channel
*r
,
1928 union tgsi_exec_channel
*g
,
1929 union tgsi_exec_channel
*b
,
1930 union tgsi_exec_channel
*a
)
1933 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
1935 /* FIXME: handle explicit derivs, offsets */
1936 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
1937 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
1939 for (j
= 0; j
< 4; j
++) {
1940 r
->f
[j
] = rgba
[0][j
];
1941 g
->f
[j
] = rgba
[1][j
];
1942 b
->f
[j
] = rgba
[2][j
];
1943 a
->f
[j
] = rgba
[3][j
];
1948 #define TEX_MODIFIER_NONE 0
1949 #define TEX_MODIFIER_PROJECTED 1
1950 #define TEX_MODIFIER_LOD_BIAS 2
1951 #define TEX_MODIFIER_EXPLICIT_LOD 3
1952 #define TEX_MODIFIER_LEVEL_ZERO 4
1953 #define TEX_MODIFIER_GATHER 5
1956 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1959 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
1960 const struct tgsi_full_instruction
*inst
,
1963 if (inst
->Texture
.NumOffsets
== 1) {
1964 union tgsi_exec_channel index
;
1965 union tgsi_exec_channel offset
[3];
1966 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
1967 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1968 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
1969 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1970 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
1971 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
1972 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
1973 offsets
[0] = offset
[0].i
[0];
1974 offsets
[1] = offset
[1].i
[0];
1975 offsets
[2] = offset
[2].i
[0];
1977 assert(inst
->Texture
.NumOffsets
== 0);
1978 offsets
[0] = offsets
[1] = offsets
[2] = 0;
1984 * Fetch dx and dy values for one channel (s, t or r).
1985 * Put dx values into one float array, dy values into another.
1988 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
1989 const struct tgsi_full_instruction
*inst
,
1992 float derivs
[2][TGSI_QUAD_SIZE
])
1994 union tgsi_exec_channel d
;
1995 FETCH(&d
, regdsrcx
, chan
);
1996 derivs
[0][0] = d
.f
[0];
1997 derivs
[0][1] = d
.f
[1];
1998 derivs
[0][2] = d
.f
[2];
1999 derivs
[0][3] = d
.f
[3];
2000 FETCH(&d
, regdsrcx
+ 1, chan
);
2001 derivs
[1][0] = d
.f
[0];
2002 derivs
[1][1] = d
.f
[1];
2003 derivs
[1][2] = d
.f
[2];
2004 derivs
[1][3] = d
.f
[3];
2008 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2009 const struct tgsi_full_instruction
*inst
,
2014 if (inst
->Src
[sampler
].Register
.Indirect
) {
2015 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2016 union tgsi_exec_channel indir_index
, index2
;
2017 const uint execmask
= mach
->ExecMask
;
2021 index2
.i
[3] = reg
->Indirect
.Index
;
2023 fetch_src_file_channel(mach
,
2026 reg
->Indirect
.Swizzle
,
2030 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2031 if (execmask
& (1 << i
)) {
2032 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2038 unit
= inst
->Src
[sampler
].Register
.Index
;
2044 * execute a texture instruction.
2046 * modifier is used to control the channel routing for the
2047 * instruction variants like proj, lod, and texture with lod bias.
2048 * sampler indicates which src register the sampler is contained in.
2051 exec_tex(struct tgsi_exec_machine
*mach
,
2052 const struct tgsi_full_instruction
*inst
,
2053 uint modifier
, uint sampler
)
2055 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2056 union tgsi_exec_channel r
[5];
2057 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2061 int dim
, shadow_ref
, i
;
2063 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2064 /* always fetch all 3 offsets, overkill but keeps code simple */
2065 fetch_texel_offsets(mach
, inst
, offsets
);
2067 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2068 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2070 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2071 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2074 if (shadow_ref
>= 0)
2075 assert(shadow_ref
>= dim
&& shadow_ref
< ARRAY_SIZE(args
));
2077 /* fetch modifier to the last argument */
2078 if (modifier
!= TEX_MODIFIER_NONE
) {
2079 const int last
= ARRAY_SIZE(args
) - 1;
2081 /* fetch modifier from src0.w or src1.x */
2083 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2084 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2087 assert(shadow_ref
!= 4);
2088 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2091 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2092 args
[last
] = &r
[last
];
2096 args
[last
] = &ZeroVec
;
2099 /* point unused arguments to zero vector */
2100 for (i
= dim
; i
< last
; i
++)
2103 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2104 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2105 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2106 control
= TGSI_SAMPLER_LOD_BIAS
;
2107 else if (modifier
== TEX_MODIFIER_GATHER
)
2108 control
= TGSI_SAMPLER_GATHER
;
2111 for (i
= dim
; i
< ARRAY_SIZE(args
); i
++)
2115 /* fetch coordinates */
2116 for (i
= 0; i
< dim
; i
++) {
2117 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2120 micro_div(&r
[i
], &r
[i
], proj
);
2125 /* fetch reference value */
2126 if (shadow_ref
>= 0) {
2127 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2130 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2132 args
[shadow_ref
] = &r
[shadow_ref
];
2135 fetch_texel(mach
->Sampler
, unit
, unit
,
2136 args
[0], args
[1], args
[2], args
[3], args
[4],
2137 NULL
, offsets
, control
,
2138 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2141 debug_printf("fetch r: %g %g %g %g\n",
2142 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2143 debug_printf("fetch g: %g %g %g %g\n",
2144 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2145 debug_printf("fetch b: %g %g %g %g\n",
2146 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2147 debug_printf("fetch a: %g %g %g %g\n",
2148 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2151 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2152 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2153 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2159 exec_lodq(struct tgsi_exec_machine
*mach
,
2160 const struct tgsi_full_instruction
*inst
)
2165 union tgsi_exec_channel coords
[4];
2166 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2167 union tgsi_exec_channel r
[2];
2169 unit
= fetch_sampler_unit(mach
, inst
, 1);
2170 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2171 assert(dim
<= ARRAY_SIZE(coords
));
2172 /* fetch coordinates */
2173 for (i
= 0; i
< dim
; i
++) {
2174 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2175 args
[i
] = &coords
[i
];
2177 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2180 mach
->Sampler
->query_lod(mach
->Sampler
, unit
, unit
,
2185 TGSI_SAMPLER_LOD_NONE
,
2189 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2190 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2191 TGSI_EXEC_DATA_FLOAT
);
2193 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2194 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2195 TGSI_EXEC_DATA_FLOAT
);
2200 exec_txd(struct tgsi_exec_machine
*mach
,
2201 const struct tgsi_full_instruction
*inst
)
2203 union tgsi_exec_channel r
[4];
2204 float derivs
[3][2][TGSI_QUAD_SIZE
];
2209 unit
= fetch_sampler_unit(mach
, inst
, 3);
2210 /* always fetch all 3 offsets, overkill but keeps code simple */
2211 fetch_texel_offsets(mach
, inst
, offsets
);
2213 switch (inst
->Texture
.Texture
) {
2214 case TGSI_TEXTURE_1D
:
2215 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2217 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2219 fetch_texel(mach
->Sampler
, unit
, unit
,
2220 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2221 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2222 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2225 case TGSI_TEXTURE_SHADOW1D
:
2226 case TGSI_TEXTURE_1D_ARRAY
:
2227 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2228 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2229 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2230 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2231 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2233 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2235 fetch_texel(mach
->Sampler
, unit
, unit
,
2236 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2237 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2238 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2241 case TGSI_TEXTURE_2D
:
2242 case TGSI_TEXTURE_RECT
:
2243 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2244 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2246 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2247 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2249 fetch_texel(mach
->Sampler
, unit
, unit
,
2250 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2251 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2252 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2256 case TGSI_TEXTURE_SHADOW2D
:
2257 case TGSI_TEXTURE_SHADOWRECT
:
2258 case TGSI_TEXTURE_2D_ARRAY
:
2259 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2260 /* only SHADOW2D_ARRAY actually needs W */
2261 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2262 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2263 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2264 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2266 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2267 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2269 fetch_texel(mach
->Sampler
, unit
, unit
,
2270 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2271 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2272 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2275 case TGSI_TEXTURE_3D
:
2276 case TGSI_TEXTURE_CUBE
:
2277 case TGSI_TEXTURE_CUBE_ARRAY
:
2278 case TGSI_TEXTURE_SHADOWCUBE
:
2279 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2280 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2281 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2282 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2283 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2285 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2286 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2287 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2289 fetch_texel(mach
->Sampler
, unit
, unit
,
2290 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2291 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2292 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2299 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2300 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2301 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2308 exec_txf(struct tgsi_exec_machine
*mach
,
2309 const struct tgsi_full_instruction
*inst
)
2311 union tgsi_exec_channel r
[4];
2314 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2319 unit
= fetch_sampler_unit(mach
, inst
, 1);
2320 /* always fetch all 3 offsets, overkill but keeps code simple */
2321 fetch_texel_offsets(mach
, inst
, offsets
);
2323 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2325 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2326 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2327 target
= mach
->SamplerViews
[unit
].Resource
;
2330 target
= inst
->Texture
.Texture
;
2333 case TGSI_TEXTURE_3D
:
2334 case TGSI_TEXTURE_2D_ARRAY
:
2335 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2336 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2337 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2339 case TGSI_TEXTURE_2D
:
2340 case TGSI_TEXTURE_RECT
:
2341 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2342 case TGSI_TEXTURE_SHADOW2D
:
2343 case TGSI_TEXTURE_SHADOWRECT
:
2344 case TGSI_TEXTURE_1D_ARRAY
:
2345 case TGSI_TEXTURE_2D_MSAA
:
2346 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2348 case TGSI_TEXTURE_BUFFER
:
2349 case TGSI_TEXTURE_1D
:
2350 case TGSI_TEXTURE_SHADOW1D
:
2351 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2358 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2361 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2362 r
[0].f
[j
] = rgba
[0][j
];
2363 r
[1].f
[j
] = rgba
[1][j
];
2364 r
[2].f
[j
] = rgba
[2][j
];
2365 r
[3].f
[j
] = rgba
[3][j
];
2368 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2369 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2370 unsigned char swizzles
[4];
2371 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2372 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2373 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2374 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2376 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2377 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2378 store_dest(mach
, &r
[swizzles
[chan
]],
2379 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2384 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2385 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2386 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2393 exec_txq(struct tgsi_exec_machine
*mach
,
2394 const struct tgsi_full_instruction
*inst
)
2397 union tgsi_exec_channel r
[4], src
;
2402 unit
= fetch_sampler_unit(mach
, inst
, 1);
2404 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2406 /* XXX: This interface can't return per-pixel values */
2407 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2409 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2410 for (j
= 0; j
< 4; j
++) {
2411 r
[j
].i
[i
] = result
[j
];
2415 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2416 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2417 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2418 TGSI_EXEC_DATA_INT
);
2424 exec_sample(struct tgsi_exec_machine
*mach
,
2425 const struct tgsi_full_instruction
*inst
,
2426 uint modifier
, boolean compare
)
2428 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2429 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2430 union tgsi_exec_channel r
[5], c1
;
2431 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2432 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2434 unsigned char swizzles
[4];
2437 /* always fetch all 3 offsets, overkill but keeps code simple */
2438 fetch_texel_offsets(mach
, inst
, offsets
);
2440 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2442 if (modifier
!= TEX_MODIFIER_NONE
) {
2443 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2444 FETCH(&c1
, 3, TGSI_CHAN_X
);
2446 control
= TGSI_SAMPLER_LOD_BIAS
;
2448 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2449 FETCH(&c1
, 3, TGSI_CHAN_X
);
2451 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2454 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2455 control
= TGSI_SAMPLER_LOD_ZERO
;
2459 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2461 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2462 case TGSI_TEXTURE_1D
:
2464 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2465 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2466 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2467 NULL
, offsets
, control
,
2468 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2471 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2472 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2473 NULL
, offsets
, control
,
2474 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2478 case TGSI_TEXTURE_1D_ARRAY
:
2479 case TGSI_TEXTURE_2D
:
2480 case TGSI_TEXTURE_RECT
:
2481 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2483 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2484 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2485 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2486 NULL
, offsets
, control
,
2487 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2490 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2491 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2492 NULL
, offsets
, control
,
2493 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2497 case TGSI_TEXTURE_2D_ARRAY
:
2498 case TGSI_TEXTURE_3D
:
2499 case TGSI_TEXTURE_CUBE
:
2500 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2501 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2503 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2504 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2505 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2506 NULL
, offsets
, control
,
2507 &r
[0], &r
[1], &r
[2], &r
[3]);
2510 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2511 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2512 NULL
, offsets
, control
,
2513 &r
[0], &r
[1], &r
[2], &r
[3]);
2517 case TGSI_TEXTURE_CUBE_ARRAY
:
2518 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2519 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2520 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2522 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2523 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2524 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2525 NULL
, offsets
, control
,
2526 &r
[0], &r
[1], &r
[2], &r
[3]);
2529 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2530 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2531 NULL
, offsets
, control
,
2532 &r
[0], &r
[1], &r
[2], &r
[3]);
2541 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2542 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2543 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2544 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2546 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2547 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2548 store_dest(mach
, &r
[swizzles
[chan
]],
2549 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2555 exec_sample_d(struct tgsi_exec_machine
*mach
,
2556 const struct tgsi_full_instruction
*inst
)
2558 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2559 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2560 union tgsi_exec_channel r
[4];
2561 float derivs
[3][2][TGSI_QUAD_SIZE
];
2563 unsigned char swizzles
[4];
2566 /* always fetch all 3 offsets, overkill but keeps code simple */
2567 fetch_texel_offsets(mach
, inst
, offsets
);
2569 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2571 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2572 case TGSI_TEXTURE_1D
:
2573 case TGSI_TEXTURE_1D_ARRAY
:
2574 /* only 1D array actually needs Y */
2575 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2577 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2579 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2580 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2581 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2582 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2585 case TGSI_TEXTURE_2D
:
2586 case TGSI_TEXTURE_RECT
:
2587 case TGSI_TEXTURE_2D_ARRAY
:
2588 /* only 2D array actually needs Z */
2589 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2590 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2592 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2593 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2595 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2596 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2597 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2598 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2601 case TGSI_TEXTURE_3D
:
2602 case TGSI_TEXTURE_CUBE
:
2603 case TGSI_TEXTURE_CUBE_ARRAY
:
2604 /* only cube array actually needs W */
2605 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2606 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2607 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2609 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2610 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2611 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2613 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2614 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2615 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2616 &r
[0], &r
[1], &r
[2], &r
[3]);
2623 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2624 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2625 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2626 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2628 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2629 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2630 store_dest(mach
, &r
[swizzles
[chan
]],
2631 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2638 * Evaluate a constant-valued coefficient at the position of the
2643 struct tgsi_exec_machine
*mach
,
2649 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2650 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2655 * Evaluate a linear-valued coefficient at the position of the
2660 struct tgsi_exec_machine
*mach
,
2664 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2665 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2666 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2667 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2668 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2669 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2670 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2671 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2672 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2676 * Evaluate a perspective-valued coefficient at the position of the
2680 eval_perspective_coef(
2681 struct tgsi_exec_machine
*mach
,
2685 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2686 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2687 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2688 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2689 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2690 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2691 /* divide by W here */
2692 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2693 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2694 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2695 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2699 typedef void (* eval_coef_func
)(
2700 struct tgsi_exec_machine
*mach
,
2705 exec_declaration(struct tgsi_exec_machine
*mach
,
2706 const struct tgsi_full_declaration
*decl
)
2708 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2709 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2713 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2714 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2715 uint first
, last
, mask
;
2717 first
= decl
->Range
.First
;
2718 last
= decl
->Range
.Last
;
2719 mask
= decl
->Declaration
.UsageMask
;
2721 /* XXX we could remove this special-case code since
2722 * mach->InterpCoefs[first].a0 should already have the
2723 * front/back-face value. But we should first update the
2724 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2725 * Then, we could remove the tgsi_exec_machine::Face field.
2727 /* XXX make FACE a system value */
2728 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2731 assert(decl
->Semantic
.Index
== 0);
2732 assert(first
== last
);
2734 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2735 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2738 eval_coef_func eval
;
2741 switch (decl
->Interp
.Interpolate
) {
2742 case TGSI_INTERPOLATE_CONSTANT
:
2743 eval
= eval_constant_coef
;
2746 case TGSI_INTERPOLATE_LINEAR
:
2747 eval
= eval_linear_coef
;
2750 case TGSI_INTERPOLATE_PERSPECTIVE
:
2751 eval
= eval_perspective_coef
;
2754 case TGSI_INTERPOLATE_COLOR
:
2755 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2763 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2764 if (mask
& (1 << j
)) {
2765 for (i
= first
; i
<= last
; i
++) {
2772 if (DEBUG_EXECUTION
) {
2774 for (i
= first
; i
<= last
; ++i
) {
2775 debug_printf("IN[%2u] = ", i
);
2776 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2780 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2781 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
2782 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
2783 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
2784 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
2793 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
2794 const union tgsi_exec_channel
*src
);
2797 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
2798 const struct tgsi_full_instruction
*inst
,
2800 enum tgsi_exec_datatype dst_datatype
,
2801 enum tgsi_exec_datatype src_datatype
)
2804 union tgsi_exec_channel src
;
2805 union tgsi_exec_channel dst
;
2807 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2809 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2810 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2811 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2817 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2818 const struct tgsi_full_instruction
*inst
,
2820 enum tgsi_exec_datatype dst_datatype
,
2821 enum tgsi_exec_datatype src_datatype
)
2824 struct tgsi_exec_vector dst
;
2826 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2827 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2828 union tgsi_exec_channel src
;
2830 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2831 op(&dst
.xyzw
[chan
], &src
);
2834 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2835 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2836 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2841 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2842 const union tgsi_exec_channel
*src0
,
2843 const union tgsi_exec_channel
*src1
);
2846 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2847 const struct tgsi_full_instruction
*inst
,
2849 enum tgsi_exec_datatype dst_datatype
,
2850 enum tgsi_exec_datatype src_datatype
)
2853 union tgsi_exec_channel src
[2];
2854 union tgsi_exec_channel dst
;
2856 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
2857 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
2858 op(&dst
, &src
[0], &src
[1]);
2859 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2860 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2861 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2867 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2868 const struct tgsi_full_instruction
*inst
,
2870 enum tgsi_exec_datatype dst_datatype
,
2871 enum tgsi_exec_datatype src_datatype
)
2874 struct tgsi_exec_vector dst
;
2876 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2877 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2878 union tgsi_exec_channel src
[2];
2880 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2881 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2882 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2885 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2886 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2887 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2892 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2893 const union tgsi_exec_channel
*src0
,
2894 const union tgsi_exec_channel
*src1
,
2895 const union tgsi_exec_channel
*src2
);
2898 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2899 const struct tgsi_full_instruction
*inst
,
2900 micro_trinary_op op
,
2901 enum tgsi_exec_datatype dst_datatype
,
2902 enum tgsi_exec_datatype src_datatype
)
2905 struct tgsi_exec_vector dst
;
2907 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2908 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2909 union tgsi_exec_channel src
[3];
2911 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2912 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2913 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2914 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2917 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2918 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2919 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2924 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
2925 const union tgsi_exec_channel
*src0
,
2926 const union tgsi_exec_channel
*src1
,
2927 const union tgsi_exec_channel
*src2
,
2928 const union tgsi_exec_channel
*src3
);
2931 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
2932 const struct tgsi_full_instruction
*inst
,
2933 micro_quaternary_op op
,
2934 enum tgsi_exec_datatype dst_datatype
,
2935 enum tgsi_exec_datatype src_datatype
)
2938 struct tgsi_exec_vector dst
;
2940 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2941 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2942 union tgsi_exec_channel src
[4];
2944 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2945 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2946 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2947 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
2948 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
2951 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2952 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2953 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2959 exec_dp3(struct tgsi_exec_machine
*mach
,
2960 const struct tgsi_full_instruction
*inst
)
2963 union tgsi_exec_channel arg
[3];
2965 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2966 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2967 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2969 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
2970 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2971 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2972 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2975 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2976 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2977 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2983 exec_dp4(struct tgsi_exec_machine
*mach
,
2984 const struct tgsi_full_instruction
*inst
)
2987 union tgsi_exec_channel arg
[3];
2989 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2990 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2991 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2993 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
2994 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2995 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2996 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2999 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3000 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3001 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3007 exec_dp2a(struct tgsi_exec_machine
*mach
,
3008 const struct tgsi_full_instruction
*inst
)
3011 union tgsi_exec_channel arg
[3];
3013 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3014 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3015 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3017 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3018 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3019 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3021 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3022 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3024 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3025 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3026 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3032 exec_dph(struct tgsi_exec_machine
*mach
,
3033 const struct tgsi_full_instruction
*inst
)
3036 union tgsi_exec_channel arg
[3];
3038 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3039 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3040 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3042 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3043 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3044 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3046 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3047 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3048 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3050 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3051 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3053 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3054 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3055 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3061 exec_dp2(struct tgsi_exec_machine
*mach
,
3062 const struct tgsi_full_instruction
*inst
)
3065 union tgsi_exec_channel arg
[3];
3067 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3068 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3069 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3071 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3072 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3073 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3075 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3076 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3077 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3083 exec_pk2h(struct tgsi_exec_machine
*mach
,
3084 const struct tgsi_full_instruction
*inst
)
3087 union tgsi_exec_channel arg
[2], dst
;
3089 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3090 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3091 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3092 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3093 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3095 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3096 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3097 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3103 exec_up2h(struct tgsi_exec_machine
*mach
,
3104 const struct tgsi_full_instruction
*inst
)
3107 union tgsi_exec_channel arg
, dst
[2];
3109 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3110 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3111 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3112 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3114 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3115 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3116 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3122 exec_scs(struct tgsi_exec_machine
*mach
,
3123 const struct tgsi_full_instruction
*inst
)
3125 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
3126 union tgsi_exec_channel arg
;
3127 union tgsi_exec_channel result
;
3129 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3131 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3132 micro_cos(&result
, &arg
);
3133 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3135 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3136 micro_sin(&result
, &arg
);
3137 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3140 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3141 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3143 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3144 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3149 exec_xpd(struct tgsi_exec_machine
*mach
,
3150 const struct tgsi_full_instruction
*inst
)
3152 union tgsi_exec_channel r
[6];
3153 union tgsi_exec_channel d
[3];
3155 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3156 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3158 micro_mul(&r
[2], &r
[0], &r
[1]);
3160 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3161 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3163 micro_mul(&r
[5], &r
[3], &r
[4] );
3164 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
3166 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3168 micro_mul(&r
[3], &r
[3], &r
[2]);
3170 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3172 micro_mul(&r
[1], &r
[1], &r
[5]);
3173 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
3175 micro_mul(&r
[5], &r
[5], &r
[4]);
3176 micro_mul(&r
[0], &r
[0], &r
[2]);
3177 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
3179 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3180 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3182 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3183 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3185 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3186 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3188 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3189 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3194 exec_dst(struct tgsi_exec_machine
*mach
,
3195 const struct tgsi_full_instruction
*inst
)
3197 union tgsi_exec_channel r
[2];
3198 union tgsi_exec_channel d
[4];
3200 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3201 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3202 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3203 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3205 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3206 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3208 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3209 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3212 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3213 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3215 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3216 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3218 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3219 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3221 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3222 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3227 exec_log(struct tgsi_exec_machine
*mach
,
3228 const struct tgsi_full_instruction
*inst
)
3230 union tgsi_exec_channel r
[3];
3232 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3233 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3234 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3235 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3236 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3237 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3239 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3240 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3241 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3242 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3244 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3245 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3247 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3248 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3253 exec_exp(struct tgsi_exec_machine
*mach
,
3254 const struct tgsi_full_instruction
*inst
)
3256 union tgsi_exec_channel r
[3];
3258 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3259 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3260 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3261 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3262 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3264 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3265 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3266 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3268 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3269 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3270 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3272 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3273 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3278 exec_lit(struct tgsi_exec_machine
*mach
,
3279 const struct tgsi_full_instruction
*inst
)
3281 union tgsi_exec_channel r
[3];
3282 union tgsi_exec_channel d
[3];
3284 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3285 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3286 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3287 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3288 micro_max(&r
[1], &r
[1], &ZeroVec
);
3290 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3291 micro_min(&r
[2], &r
[2], &P128Vec
);
3292 micro_max(&r
[2], &r
[2], &M128Vec
);
3293 micro_pow(&r
[1], &r
[1], &r
[2]);
3294 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3295 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3297 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3298 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3299 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3302 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3303 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3306 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3307 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3312 exec_break(struct tgsi_exec_machine
*mach
)
3314 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3315 /* turn off loop channels for each enabled exec channel */
3316 mach
->LoopMask
&= ~mach
->ExecMask
;
3317 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3318 UPDATE_EXEC_MASK(mach
);
3320 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3322 mach
->Switch
.mask
= 0x0;
3324 UPDATE_EXEC_MASK(mach
);
3329 exec_switch(struct tgsi_exec_machine
*mach
,
3330 const struct tgsi_full_instruction
*inst
)
3332 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3333 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3335 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3336 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3337 mach
->Switch
.mask
= 0x0;
3338 mach
->Switch
.defaultMask
= 0x0;
3340 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3341 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3343 UPDATE_EXEC_MASK(mach
);
3347 exec_case(struct tgsi_exec_machine
*mach
,
3348 const struct tgsi_full_instruction
*inst
)
3350 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3351 union tgsi_exec_channel src
;
3354 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3356 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3359 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3362 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3365 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3369 mach
->Switch
.defaultMask
|= mask
;
3371 mach
->Switch
.mask
|= mask
& prevMask
;
3373 UPDATE_EXEC_MASK(mach
);
3376 /* FIXME: this will only work if default is last */
3378 exec_default(struct tgsi_exec_machine
*mach
)
3380 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3382 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3384 UPDATE_EXEC_MASK(mach
);
3388 exec_endswitch(struct tgsi_exec_machine
*mach
)
3390 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3391 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3393 UPDATE_EXEC_MASK(mach
);
3396 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3397 const union tgsi_double_channel
*src
);
3400 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3401 union tgsi_double_channel
*chan
,
3402 const struct tgsi_full_src_register
*reg
,
3406 union tgsi_exec_channel src
[2];
3409 fetch_source_d(mach
, &src
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3410 fetch_source_d(mach
, &src
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3412 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3413 chan
->u
[i
][0] = src
[0].u
[i
];
3414 chan
->u
[i
][1] = src
[1].u
[i
];
3416 if (reg
->Register
.Absolute
) {
3417 micro_dabs(chan
, chan
);
3419 if (reg
->Register
.Negate
) {
3420 micro_dneg(chan
, chan
);
3425 store_double_channel(struct tgsi_exec_machine
*mach
,
3426 const union tgsi_double_channel
*chan
,
3427 const struct tgsi_full_dst_register
*reg
,
3428 const struct tgsi_full_instruction
*inst
,
3432 union tgsi_exec_channel dst
[2];
3434 union tgsi_double_channel temp
;
3435 const uint execmask
= mach
->ExecMask
;
3437 if (!inst
->Instruction
.Saturate
) {
3438 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3439 if (execmask
& (1 << i
)) {
3440 dst
[0].u
[i
] = chan
->u
[i
][0];
3441 dst
[1].u
[i
] = chan
->u
[i
][1];
3445 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3446 if (execmask
& (1 << i
)) {
3447 if (chan
->d
[i
] < 0.0)
3449 else if (chan
->d
[i
] > 1.0)
3452 temp
.d
[i
] = chan
->d
[i
];
3454 dst
[0].u
[i
] = temp
.u
[i
][0];
3455 dst
[1].u
[i
] = temp
.u
[i
][1];
3459 store_dest_double(mach
, &dst
[0], reg
, inst
, chan_0
, TGSI_EXEC_DATA_UINT
);
3461 store_dest_double(mach
, &dst
[1], reg
, inst
, chan_1
, TGSI_EXEC_DATA_UINT
);
3465 exec_double_unary(struct tgsi_exec_machine
*mach
,
3466 const struct tgsi_full_instruction
*inst
,
3469 union tgsi_double_channel src
;
3470 union tgsi_double_channel dst
;
3472 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3473 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3475 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3477 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3478 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3480 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3485 exec_double_binary(struct tgsi_exec_machine
*mach
,
3486 const struct tgsi_full_instruction
*inst
,
3488 enum tgsi_exec_datatype dst_datatype
)
3490 union tgsi_double_channel src
[2];
3491 union tgsi_double_channel dst
;
3492 int first_dest_chan
, second_dest_chan
;
3495 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3496 /* these are & because of the way DSLT etc store their destinations */
3497 if (wmask
& TGSI_WRITEMASK_XY
) {
3498 first_dest_chan
= TGSI_CHAN_X
;
3499 second_dest_chan
= TGSI_CHAN_Y
;
3500 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3501 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3502 second_dest_chan
= -1;
3505 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3506 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3508 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3511 if (wmask
& TGSI_WRITEMASK_ZW
) {
3512 first_dest_chan
= TGSI_CHAN_Z
;
3513 second_dest_chan
= TGSI_CHAN_W
;
3514 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3515 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3516 second_dest_chan
= -1;
3519 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3520 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3522 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3527 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3528 const struct tgsi_full_instruction
*inst
,
3531 union tgsi_double_channel src
[3];
3532 union tgsi_double_channel dst
;
3534 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3535 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3536 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3537 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3539 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3541 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3542 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3543 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3544 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3546 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3551 exec_f2d(struct tgsi_exec_machine
*mach
,
3552 const struct tgsi_full_instruction
*inst
)
3554 union tgsi_exec_channel src
;
3555 union tgsi_double_channel dst
;
3557 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3558 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3559 micro_f2d(&dst
, &src
);
3560 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3562 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3563 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3564 micro_f2d(&dst
, &src
);
3565 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3570 exec_d2f(struct tgsi_exec_machine
*mach
,
3571 const struct tgsi_full_instruction
*inst
)
3573 union tgsi_double_channel src
;
3574 union tgsi_exec_channel dst
;
3575 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3578 for (i
= 0; i
< 2; i
++) {
3581 wm
&= ~(1 << (bit
- 1));
3583 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3585 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3586 micro_d2f(&dst
, &src
);
3587 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_FLOAT
);
3593 exec_i2d(struct tgsi_exec_machine
*mach
,
3594 const struct tgsi_full_instruction
*inst
)
3596 union tgsi_exec_channel src
;
3597 union tgsi_double_channel dst
;
3599 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3600 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3601 micro_i2d(&dst
, &src
);
3602 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3604 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3605 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_INT
);
3606 micro_i2d(&dst
, &src
);
3607 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3612 exec_d2i(struct tgsi_exec_machine
*mach
,
3613 const struct tgsi_full_instruction
*inst
)
3615 union tgsi_double_channel src
;
3616 union tgsi_exec_channel dst
;
3617 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3620 for (i
= 0; i
< 2; i
++) {
3623 wm
&= ~(1 << (bit
- 1));
3625 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3627 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3628 micro_d2i(&dst
, &src
);
3629 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_INT
);
3634 exec_u2d(struct tgsi_exec_machine
*mach
,
3635 const struct tgsi_full_instruction
*inst
)
3637 union tgsi_exec_channel src
;
3638 union tgsi_double_channel dst
;
3640 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3641 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3642 micro_u2d(&dst
, &src
);
3643 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3645 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3646 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_UINT
);
3647 micro_u2d(&dst
, &src
);
3648 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3653 exec_d2u(struct tgsi_exec_machine
*mach
,
3654 const struct tgsi_full_instruction
*inst
)
3656 union tgsi_double_channel src
;
3657 union tgsi_exec_channel dst
;
3658 int wm
= inst
->Dst
[0].Register
.WriteMask
;
3661 for (i
= 0; i
< 2; i
++) {
3664 wm
&= ~(1 << (bit
- 1));
3666 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3668 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3669 micro_d2u(&dst
, &src
);
3670 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, TGSI_EXEC_DATA_UINT
);
3676 exec_dldexp(struct tgsi_exec_machine
*mach
,
3677 const struct tgsi_full_instruction
*inst
)
3679 union tgsi_double_channel src0
;
3680 union tgsi_exec_channel src1
;
3681 union tgsi_double_channel dst
;
3684 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3685 if (wmask
& TGSI_WRITEMASK_XY
) {
3686 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3687 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3688 micro_dldexp(&dst
, &src0
, &src1
);
3689 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3692 if (wmask
& TGSI_WRITEMASK_ZW
) {
3693 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3694 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3695 micro_dldexp(&dst
, &src0
, &src1
);
3696 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3701 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3702 const struct tgsi_full_instruction
*inst
)
3704 union tgsi_double_channel src
;
3705 union tgsi_double_channel dst
;
3706 union tgsi_exec_channel dst_exp
;
3708 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)) {
3709 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3710 micro_dfracexp(&dst
, &dst_exp
, &src
);
3711 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3712 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3714 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)) {
3715 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3716 micro_dfracexp(&dst
, &dst_exp
, &src
);
3717 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3718 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3723 get_image_coord_dim(unsigned tgsi_tex
)
3727 case TGSI_TEXTURE_BUFFER
:
3728 case TGSI_TEXTURE_1D
:
3731 case TGSI_TEXTURE_2D
:
3732 case TGSI_TEXTURE_RECT
:
3733 case TGSI_TEXTURE_1D_ARRAY
:
3734 case TGSI_TEXTURE_2D_MSAA
:
3737 case TGSI_TEXTURE_3D
:
3738 case TGSI_TEXTURE_CUBE
:
3739 case TGSI_TEXTURE_2D_ARRAY
:
3740 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3741 case TGSI_TEXTURE_CUBE_ARRAY
:
3745 assert(!"unknown texture target");
3754 get_image_coord_sample(unsigned tgsi_tex
)
3758 case TGSI_TEXTURE_2D_MSAA
:
3761 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3771 exec_load_img(struct tgsi_exec_machine
*mach
,
3772 const struct tgsi_full_instruction
*inst
)
3774 union tgsi_exec_channel r
[4], sample_r
;
3780 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3781 struct tgsi_image_params params
;
3782 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3784 unit
= fetch_sampler_unit(mach
, inst
, 0);
3785 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3786 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3789 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3791 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3792 params
.format
= inst
->Memory
.Format
;
3794 for (i
= 0; i
< dim
; i
++) {
3795 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3799 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3801 mach
->Image
->load(mach
->Image
, ¶ms
,
3802 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3804 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3805 r
[0].f
[j
] = rgba
[0][j
];
3806 r
[1].f
[j
] = rgba
[1][j
];
3807 r
[2].f
[j
] = rgba
[2][j
];
3808 r
[3].f
[j
] = rgba
[3][j
];
3810 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3811 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3812 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3818 exec_load_buf(struct tgsi_exec_machine
*mach
,
3819 const struct tgsi_full_instruction
*inst
)
3821 union tgsi_exec_channel r
[4];
3825 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3826 struct tgsi_buffer_params params
;
3827 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3829 unit
= fetch_sampler_unit(mach
, inst
, 0);
3831 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3833 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3835 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3837 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3838 r
[0].f
[j
] = rgba
[0][j
];
3839 r
[1].f
[j
] = rgba
[1][j
];
3840 r
[2].f
[j
] = rgba
[2][j
];
3841 r
[3].f
[j
] = rgba
[3][j
];
3843 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3844 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3845 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3851 exec_load_mem(struct tgsi_exec_machine
*mach
,
3852 const struct tgsi_full_instruction
*inst
)
3854 union tgsi_exec_channel r
[4];
3856 char *ptr
= mach
->LocalMem
;
3860 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3861 if (r
[0].u
[0] >= mach
->LocalMemSize
)
3867 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3868 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3869 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3870 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
3875 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3876 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3877 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3883 exec_load(struct tgsi_exec_machine
*mach
,
3884 const struct tgsi_full_instruction
*inst
)
3886 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
3887 exec_load_img(mach
, inst
);
3888 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
3889 exec_load_buf(mach
, inst
);
3890 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
3891 exec_load_mem(mach
, inst
);
3895 exec_store_img(struct tgsi_exec_machine
*mach
,
3896 const struct tgsi_full_instruction
*inst
)
3898 union tgsi_exec_channel r
[3], sample_r
;
3899 union tgsi_exec_channel value
[4];
3900 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3901 struct tgsi_image_params params
;
3906 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3907 unit
= inst
->Dst
[0].Register
.Index
;
3908 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3909 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3912 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3914 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3915 params
.format
= inst
->Memory
.Format
;
3917 for (i
= 0; i
< dim
; i
++) {
3918 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
3921 for (i
= 0; i
< 4; i
++) {
3922 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3925 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
3927 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3928 rgba
[0][j
] = value
[0].f
[j
];
3929 rgba
[1][j
] = value
[1].f
[j
];
3930 rgba
[2][j
] = value
[2].f
[j
];
3931 rgba
[3][j
] = value
[3].f
[j
];
3934 mach
->Image
->store(mach
->Image
, ¶ms
,
3935 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3940 exec_store_buf(struct tgsi_exec_machine
*mach
,
3941 const struct tgsi_full_instruction
*inst
)
3943 union tgsi_exec_channel r
[3];
3944 union tgsi_exec_channel value
[4];
3945 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3946 struct tgsi_buffer_params params
;
3949 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3951 unit
= inst
->Dst
[0].Register
.Index
;
3953 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3955 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
3957 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
3958 for (i
= 0; i
< 4; i
++) {
3959 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3962 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3963 rgba
[0][j
] = value
[0].f
[j
];
3964 rgba
[1][j
] = value
[1].f
[j
];
3965 rgba
[2][j
] = value
[2].f
[j
];
3966 rgba
[3][j
] = value
[3].f
[j
];
3969 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
3975 exec_store_mem(struct tgsi_exec_machine
*mach
,
3976 const struct tgsi_full_instruction
*inst
)
3978 union tgsi_exec_channel r
[3];
3979 union tgsi_exec_channel value
[4];
3981 char *ptr
= mach
->LocalMem
;
3982 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3983 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3985 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
3987 for (i
= 0; i
< 4; i
++) {
3988 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3991 if (r
[0].u
[0] >= mach
->LocalMemSize
)
3995 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3996 if (execmask
& (1 << i
)) {
3997 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3998 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3999 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4007 exec_store(struct tgsi_exec_machine
*mach
,
4008 const struct tgsi_full_instruction
*inst
)
4010 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4011 exec_store_img(mach
, inst
);
4012 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4013 exec_store_buf(mach
, inst
);
4014 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4015 exec_store_mem(mach
, inst
);
4019 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4020 const struct tgsi_full_instruction
*inst
)
4022 union tgsi_exec_channel r
[4], sample_r
;
4023 union tgsi_exec_channel value
[4], value2
[4];
4024 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4025 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4026 struct tgsi_image_params params
;
4031 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4032 unit
= fetch_sampler_unit(mach
, inst
, 0);
4033 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4034 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4037 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4039 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4040 params
.format
= inst
->Memory
.Format
;
4042 for (i
= 0; i
< dim
; i
++) {
4043 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4046 for (i
= 0; i
< 4; i
++) {
4047 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4048 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4049 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4052 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4054 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4055 rgba
[0][j
] = value
[0].f
[j
];
4056 rgba
[1][j
] = value
[1].f
[j
];
4057 rgba
[2][j
] = value
[2].f
[j
];
4058 rgba
[3][j
] = value
[3].f
[j
];
4060 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4061 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4062 rgba2
[0][j
] = value2
[0].f
[j
];
4063 rgba2
[1][j
] = value2
[1].f
[j
];
4064 rgba2
[2][j
] = value2
[2].f
[j
];
4065 rgba2
[3][j
] = value2
[3].f
[j
];
4069 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4070 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4073 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4074 r
[0].f
[j
] = rgba
[0][j
];
4075 r
[1].f
[j
] = rgba
[1][j
];
4076 r
[2].f
[j
] = rgba
[2][j
];
4077 r
[3].f
[j
] = rgba
[3][j
];
4079 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4080 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4081 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4087 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4088 const struct tgsi_full_instruction
*inst
)
4090 union tgsi_exec_channel r
[4];
4091 union tgsi_exec_channel value
[4], value2
[4];
4092 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4093 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4094 struct tgsi_buffer_params params
;
4097 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4099 unit
= fetch_sampler_unit(mach
, inst
, 0);
4101 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4103 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4105 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4107 for (i
= 0; i
< 4; i
++) {
4108 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4109 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4110 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4113 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4114 rgba
[0][j
] = value
[0].f
[j
];
4115 rgba
[1][j
] = value
[1].f
[j
];
4116 rgba
[2][j
] = value
[2].f
[j
];
4117 rgba
[3][j
] = value
[3].f
[j
];
4119 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4120 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4121 rgba2
[0][j
] = value2
[0].f
[j
];
4122 rgba2
[1][j
] = value2
[1].f
[j
];
4123 rgba2
[2][j
] = value2
[2].f
[j
];
4124 rgba2
[3][j
] = value2
[3].f
[j
];
4128 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4132 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4133 r
[0].f
[j
] = rgba
[0][j
];
4134 r
[1].f
[j
] = rgba
[1][j
];
4135 r
[2].f
[j
] = rgba
[2][j
];
4136 r
[3].f
[j
] = rgba
[3][j
];
4138 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4139 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4140 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4146 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4147 const struct tgsi_full_instruction
*inst
)
4149 union tgsi_exec_channel r
[4];
4150 union tgsi_exec_channel value
[4], value2
[4];
4151 char *ptr
= mach
->LocalMem
;
4155 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4156 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4157 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4159 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4164 for (i
= 0; i
< 4; i
++) {
4165 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4166 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4167 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4170 memcpy(&r
[0].u
[0], ptr
, 4);
4172 switch (inst
->Instruction
.Opcode
) {
4173 case TGSI_OPCODE_ATOMUADD
:
4174 val
+= value
[0].u
[0];
4176 case TGSI_OPCODE_ATOMXOR
:
4177 val
^= value
[0].u
[0];
4179 case TGSI_OPCODE_ATOMOR
:
4180 val
|= value
[0].u
[0];
4182 case TGSI_OPCODE_ATOMAND
:
4183 val
&= value
[0].u
[0];
4185 case TGSI_OPCODE_ATOMUMIN
:
4186 val
= MIN2(val
, value
[0].u
[0]);
4188 case TGSI_OPCODE_ATOMUMAX
:
4189 val
= MAX2(val
, value
[0].u
[0]);
4191 case TGSI_OPCODE_ATOMIMIN
:
4192 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4194 case TGSI_OPCODE_ATOMIMAX
:
4195 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4197 case TGSI_OPCODE_ATOMXCHG
:
4198 val
= value
[0].i
[0];
4200 case TGSI_OPCODE_ATOMCAS
:
4201 if (val
== value
[0].u
[0])
4202 val
= value2
[0].u
[0];
4207 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4208 if (execmask
& (1 << i
))
4209 memcpy(ptr
, &val
, 4);
4211 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4212 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4213 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4219 exec_atomop(struct tgsi_exec_machine
*mach
,
4220 const struct tgsi_full_instruction
*inst
)
4222 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4223 exec_atomop_img(mach
, inst
);
4224 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4225 exec_atomop_buf(mach
, inst
);
4226 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4227 exec_atomop_mem(mach
, inst
);
4231 exec_resq_img(struct tgsi_exec_machine
*mach
,
4232 const struct tgsi_full_instruction
*inst
)
4235 union tgsi_exec_channel r
[4];
4238 struct tgsi_image_params params
;
4239 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4241 unit
= fetch_sampler_unit(mach
, inst
, 0);
4243 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4245 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4246 params
.format
= inst
->Memory
.Format
;
4248 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4250 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4251 for (j
= 0; j
< 4; j
++) {
4252 r
[j
].i
[i
] = result
[j
];
4256 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4257 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4258 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4259 TGSI_EXEC_DATA_INT
);
4265 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4266 const struct tgsi_full_instruction
*inst
)
4269 union tgsi_exec_channel r
[4];
4272 struct tgsi_buffer_params params
;
4273 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4275 unit
= fetch_sampler_unit(mach
, inst
, 0);
4277 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4280 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4282 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4286 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4287 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4288 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4289 TGSI_EXEC_DATA_INT
);
4295 exec_resq(struct tgsi_exec_machine
*mach
,
4296 const struct tgsi_full_instruction
*inst
)
4298 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4299 exec_resq_img(mach
, inst
);
4301 exec_resq_buf(mach
, inst
);
4305 micro_i2f(union tgsi_exec_channel
*dst
,
4306 const union tgsi_exec_channel
*src
)
4308 dst
->f
[0] = (float)src
->i
[0];
4309 dst
->f
[1] = (float)src
->i
[1];
4310 dst
->f
[2] = (float)src
->i
[2];
4311 dst
->f
[3] = (float)src
->i
[3];
4315 micro_not(union tgsi_exec_channel
*dst
,
4316 const union tgsi_exec_channel
*src
)
4318 dst
->u
[0] = ~src
->u
[0];
4319 dst
->u
[1] = ~src
->u
[1];
4320 dst
->u
[2] = ~src
->u
[2];
4321 dst
->u
[3] = ~src
->u
[3];
4325 micro_shl(union tgsi_exec_channel
*dst
,
4326 const union tgsi_exec_channel
*src0
,
4327 const union tgsi_exec_channel
*src1
)
4329 unsigned masked_count
;
4330 masked_count
= src1
->u
[0] & 0x1f;
4331 dst
->u
[0] = src0
->u
[0] << masked_count
;
4332 masked_count
= src1
->u
[1] & 0x1f;
4333 dst
->u
[1] = src0
->u
[1] << masked_count
;
4334 masked_count
= src1
->u
[2] & 0x1f;
4335 dst
->u
[2] = src0
->u
[2] << masked_count
;
4336 masked_count
= src1
->u
[3] & 0x1f;
4337 dst
->u
[3] = src0
->u
[3] << masked_count
;
4341 micro_and(union tgsi_exec_channel
*dst
,
4342 const union tgsi_exec_channel
*src0
,
4343 const union tgsi_exec_channel
*src1
)
4345 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4346 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4347 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4348 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4352 micro_or(union tgsi_exec_channel
*dst
,
4353 const union tgsi_exec_channel
*src0
,
4354 const union tgsi_exec_channel
*src1
)
4356 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4357 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4358 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4359 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4363 micro_xor(union tgsi_exec_channel
*dst
,
4364 const union tgsi_exec_channel
*src0
,
4365 const union tgsi_exec_channel
*src1
)
4367 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4368 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4369 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4370 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4374 micro_mod(union tgsi_exec_channel
*dst
,
4375 const union tgsi_exec_channel
*src0
,
4376 const union tgsi_exec_channel
*src1
)
4378 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
4379 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
4380 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
4381 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
4385 micro_f2i(union tgsi_exec_channel
*dst
,
4386 const union tgsi_exec_channel
*src
)
4388 dst
->i
[0] = (int)src
->f
[0];
4389 dst
->i
[1] = (int)src
->f
[1];
4390 dst
->i
[2] = (int)src
->f
[2];
4391 dst
->i
[3] = (int)src
->f
[3];
4395 micro_fseq(union tgsi_exec_channel
*dst
,
4396 const union tgsi_exec_channel
*src0
,
4397 const union tgsi_exec_channel
*src1
)
4399 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4400 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4401 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4402 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4406 micro_fsge(union tgsi_exec_channel
*dst
,
4407 const union tgsi_exec_channel
*src0
,
4408 const union tgsi_exec_channel
*src1
)
4410 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4411 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4412 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4413 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4417 micro_fslt(union tgsi_exec_channel
*dst
,
4418 const union tgsi_exec_channel
*src0
,
4419 const union tgsi_exec_channel
*src1
)
4421 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4422 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4423 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4424 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4428 micro_fsne(union tgsi_exec_channel
*dst
,
4429 const union tgsi_exec_channel
*src0
,
4430 const union tgsi_exec_channel
*src1
)
4432 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4433 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4434 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4435 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4439 micro_idiv(union tgsi_exec_channel
*dst
,
4440 const union tgsi_exec_channel
*src0
,
4441 const union tgsi_exec_channel
*src1
)
4443 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4444 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4445 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4446 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4450 micro_imax(union tgsi_exec_channel
*dst
,
4451 const union tgsi_exec_channel
*src0
,
4452 const union tgsi_exec_channel
*src1
)
4454 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4455 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4456 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4457 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4461 micro_imin(union tgsi_exec_channel
*dst
,
4462 const union tgsi_exec_channel
*src0
,
4463 const union tgsi_exec_channel
*src1
)
4465 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4466 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4467 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4468 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4472 micro_isge(union tgsi_exec_channel
*dst
,
4473 const union tgsi_exec_channel
*src0
,
4474 const union tgsi_exec_channel
*src1
)
4476 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4477 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4478 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4479 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4483 micro_ishr(union tgsi_exec_channel
*dst
,
4484 const union tgsi_exec_channel
*src0
,
4485 const union tgsi_exec_channel
*src1
)
4487 unsigned masked_count
;
4488 masked_count
= src1
->i
[0] & 0x1f;
4489 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4490 masked_count
= src1
->i
[1] & 0x1f;
4491 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4492 masked_count
= src1
->i
[2] & 0x1f;
4493 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4494 masked_count
= src1
->i
[3] & 0x1f;
4495 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4499 micro_islt(union tgsi_exec_channel
*dst
,
4500 const union tgsi_exec_channel
*src0
,
4501 const union tgsi_exec_channel
*src1
)
4503 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4504 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4505 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4506 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4510 micro_f2u(union tgsi_exec_channel
*dst
,
4511 const union tgsi_exec_channel
*src
)
4513 dst
->u
[0] = (uint
)src
->f
[0];
4514 dst
->u
[1] = (uint
)src
->f
[1];
4515 dst
->u
[2] = (uint
)src
->f
[2];
4516 dst
->u
[3] = (uint
)src
->f
[3];
4520 micro_u2f(union tgsi_exec_channel
*dst
,
4521 const union tgsi_exec_channel
*src
)
4523 dst
->f
[0] = (float)src
->u
[0];
4524 dst
->f
[1] = (float)src
->u
[1];
4525 dst
->f
[2] = (float)src
->u
[2];
4526 dst
->f
[3] = (float)src
->u
[3];
4530 micro_uadd(union tgsi_exec_channel
*dst
,
4531 const union tgsi_exec_channel
*src0
,
4532 const union tgsi_exec_channel
*src1
)
4534 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4535 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4536 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4537 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4541 micro_udiv(union tgsi_exec_channel
*dst
,
4542 const union tgsi_exec_channel
*src0
,
4543 const union tgsi_exec_channel
*src1
)
4545 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4546 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4547 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4548 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4552 micro_umad(union tgsi_exec_channel
*dst
,
4553 const union tgsi_exec_channel
*src0
,
4554 const union tgsi_exec_channel
*src1
,
4555 const union tgsi_exec_channel
*src2
)
4557 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4558 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4559 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4560 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4564 micro_umax(union tgsi_exec_channel
*dst
,
4565 const union tgsi_exec_channel
*src0
,
4566 const union tgsi_exec_channel
*src1
)
4568 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4569 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4570 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4571 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4575 micro_umin(union tgsi_exec_channel
*dst
,
4576 const union tgsi_exec_channel
*src0
,
4577 const union tgsi_exec_channel
*src1
)
4579 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4580 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4581 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4582 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4586 micro_umod(union tgsi_exec_channel
*dst
,
4587 const union tgsi_exec_channel
*src0
,
4588 const union tgsi_exec_channel
*src1
)
4590 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4591 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4592 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4593 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4597 micro_umul(union tgsi_exec_channel
*dst
,
4598 const union tgsi_exec_channel
*src0
,
4599 const union tgsi_exec_channel
*src1
)
4601 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4602 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4603 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4604 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4608 micro_imul_hi(union tgsi_exec_channel
*dst
,
4609 const union tgsi_exec_channel
*src0
,
4610 const union tgsi_exec_channel
*src1
)
4612 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4613 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4614 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4615 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4616 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4621 micro_umul_hi(union tgsi_exec_channel
*dst
,
4622 const union tgsi_exec_channel
*src0
,
4623 const union tgsi_exec_channel
*src1
)
4625 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4626 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4627 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4628 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4629 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4634 micro_useq(union tgsi_exec_channel
*dst
,
4635 const union tgsi_exec_channel
*src0
,
4636 const union tgsi_exec_channel
*src1
)
4638 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4639 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4640 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4641 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4645 micro_usge(union tgsi_exec_channel
*dst
,
4646 const union tgsi_exec_channel
*src0
,
4647 const union tgsi_exec_channel
*src1
)
4649 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4650 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4651 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4652 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4656 micro_ushr(union tgsi_exec_channel
*dst
,
4657 const union tgsi_exec_channel
*src0
,
4658 const union tgsi_exec_channel
*src1
)
4660 unsigned masked_count
;
4661 masked_count
= src1
->u
[0] & 0x1f;
4662 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4663 masked_count
= src1
->u
[1] & 0x1f;
4664 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4665 masked_count
= src1
->u
[2] & 0x1f;
4666 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4667 masked_count
= src1
->u
[3] & 0x1f;
4668 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4672 micro_uslt(union tgsi_exec_channel
*dst
,
4673 const union tgsi_exec_channel
*src0
,
4674 const union tgsi_exec_channel
*src1
)
4676 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4677 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4678 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4679 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4683 micro_usne(union tgsi_exec_channel
*dst
,
4684 const union tgsi_exec_channel
*src0
,
4685 const union tgsi_exec_channel
*src1
)
4687 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4688 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4689 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4690 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4694 micro_uarl(union tgsi_exec_channel
*dst
,
4695 const union tgsi_exec_channel
*src
)
4697 dst
->i
[0] = src
->u
[0];
4698 dst
->i
[1] = src
->u
[1];
4699 dst
->i
[2] = src
->u
[2];
4700 dst
->i
[3] = src
->u
[3];
4704 micro_ucmp(union tgsi_exec_channel
*dst
,
4705 const union tgsi_exec_channel
*src0
,
4706 const union tgsi_exec_channel
*src1
,
4707 const union tgsi_exec_channel
*src2
)
4709 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
4710 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
4711 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
4712 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
4716 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4719 micro_ibfe(union tgsi_exec_channel
*dst
,
4720 const union tgsi_exec_channel
*src0
,
4721 const union tgsi_exec_channel
*src1
,
4722 const union tgsi_exec_channel
*src2
)
4725 for (i
= 0; i
< 4; i
++) {
4726 int width
= src2
->i
[i
] & 0x1f;
4727 int offset
= src1
->i
[i
] & 0x1f;
4730 else if (width
+ offset
< 32)
4731 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
4733 dst
->i
[i
] = src0
->i
[i
] >> offset
;
4738 * Unsigned bitfield extract
4741 micro_ubfe(union tgsi_exec_channel
*dst
,
4742 const union tgsi_exec_channel
*src0
,
4743 const union tgsi_exec_channel
*src1
,
4744 const union tgsi_exec_channel
*src2
)
4747 for (i
= 0; i
< 4; i
++) {
4748 int width
= src2
->u
[i
] & 0x1f;
4749 int offset
= src1
->u
[i
] & 0x1f;
4752 else if (width
+ offset
< 32)
4753 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
4755 dst
->u
[i
] = src0
->u
[i
] >> offset
;
4760 * Bitfield insert: copy low bits from src1 into a region of src0.
4763 micro_bfi(union tgsi_exec_channel
*dst
,
4764 const union tgsi_exec_channel
*src0
,
4765 const union tgsi_exec_channel
*src1
,
4766 const union tgsi_exec_channel
*src2
,
4767 const union tgsi_exec_channel
*src3
)
4770 for (i
= 0; i
< 4; i
++) {
4771 int width
= src3
->u
[i
] & 0x1f;
4772 int offset
= src2
->u
[i
] & 0x1f;
4773 int bitmask
= ((1 << width
) - 1) << offset
;
4774 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
4779 micro_brev(union tgsi_exec_channel
*dst
,
4780 const union tgsi_exec_channel
*src
)
4782 dst
->u
[0] = util_bitreverse(src
->u
[0]);
4783 dst
->u
[1] = util_bitreverse(src
->u
[1]);
4784 dst
->u
[2] = util_bitreverse(src
->u
[2]);
4785 dst
->u
[3] = util_bitreverse(src
->u
[3]);
4789 micro_popc(union tgsi_exec_channel
*dst
,
4790 const union tgsi_exec_channel
*src
)
4792 dst
->u
[0] = util_bitcount(src
->u
[0]);
4793 dst
->u
[1] = util_bitcount(src
->u
[1]);
4794 dst
->u
[2] = util_bitcount(src
->u
[2]);
4795 dst
->u
[3] = util_bitcount(src
->u
[3]);
4799 micro_lsb(union tgsi_exec_channel
*dst
,
4800 const union tgsi_exec_channel
*src
)
4802 dst
->i
[0] = ffs(src
->u
[0]) - 1;
4803 dst
->i
[1] = ffs(src
->u
[1]) - 1;
4804 dst
->i
[2] = ffs(src
->u
[2]) - 1;
4805 dst
->i
[3] = ffs(src
->u
[3]) - 1;
4809 micro_imsb(union tgsi_exec_channel
*dst
,
4810 const union tgsi_exec_channel
*src
)
4812 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
4813 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
4814 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
4815 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
4819 micro_umsb(union tgsi_exec_channel
*dst
,
4820 const union tgsi_exec_channel
*src
)
4822 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
4823 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
4824 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
4825 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
4829 * Execute a TGSI instruction.
4830 * Returns TRUE if a barrier instruction is hit,
4835 struct tgsi_exec_machine
*mach
,
4836 const struct tgsi_full_instruction
*inst
,
4839 union tgsi_exec_channel r
[10];
4843 switch (inst
->Instruction
.Opcode
) {
4844 case TGSI_OPCODE_ARL
:
4845 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
4848 case TGSI_OPCODE_MOV
:
4849 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
4852 case TGSI_OPCODE_LIT
:
4853 exec_lit(mach
, inst
);
4856 case TGSI_OPCODE_RCP
:
4857 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4860 case TGSI_OPCODE_RSQ
:
4861 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4864 case TGSI_OPCODE_EXP
:
4865 exec_exp(mach
, inst
);
4868 case TGSI_OPCODE_LOG
:
4869 exec_log(mach
, inst
);
4872 case TGSI_OPCODE_MUL
:
4873 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4876 case TGSI_OPCODE_ADD
:
4877 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4880 case TGSI_OPCODE_DP3
:
4881 exec_dp3(mach
, inst
);
4884 case TGSI_OPCODE_DP4
:
4885 exec_dp4(mach
, inst
);
4888 case TGSI_OPCODE_DST
:
4889 exec_dst(mach
, inst
);
4892 case TGSI_OPCODE_MIN
:
4893 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4896 case TGSI_OPCODE_MAX
:
4897 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4900 case TGSI_OPCODE_SLT
:
4901 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4904 case TGSI_OPCODE_SGE
:
4905 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4908 case TGSI_OPCODE_MAD
:
4909 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4912 case TGSI_OPCODE_SUB
:
4913 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4916 case TGSI_OPCODE_LRP
:
4917 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4920 case TGSI_OPCODE_SQRT
:
4921 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4924 case TGSI_OPCODE_DP2A
:
4925 exec_dp2a(mach
, inst
);
4928 case TGSI_OPCODE_FRC
:
4929 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4932 case TGSI_OPCODE_CLAMP
:
4933 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4936 case TGSI_OPCODE_FLR
:
4937 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4940 case TGSI_OPCODE_ROUND
:
4941 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4944 case TGSI_OPCODE_EX2
:
4945 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4948 case TGSI_OPCODE_LG2
:
4949 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4952 case TGSI_OPCODE_POW
:
4953 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4956 case TGSI_OPCODE_XPD
:
4957 exec_xpd(mach
, inst
);
4960 case TGSI_OPCODE_ABS
:
4961 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4964 case TGSI_OPCODE_DPH
:
4965 exec_dph(mach
, inst
);
4968 case TGSI_OPCODE_COS
:
4969 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4972 case TGSI_OPCODE_DDX
:
4973 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4976 case TGSI_OPCODE_DDY
:
4977 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
4980 case TGSI_OPCODE_KILL
:
4981 exec_kill (mach
, inst
);
4984 case TGSI_OPCODE_KILL_IF
:
4985 exec_kill_if (mach
, inst
);
4988 case TGSI_OPCODE_PK2H
:
4989 exec_pk2h(mach
, inst
);
4992 case TGSI_OPCODE_PK2US
:
4996 case TGSI_OPCODE_PK4B
:
5000 case TGSI_OPCODE_PK4UB
:
5004 case TGSI_OPCODE_SEQ
:
5005 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5008 case TGSI_OPCODE_SGT
:
5009 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5012 case TGSI_OPCODE_SIN
:
5013 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5016 case TGSI_OPCODE_SLE
:
5017 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5020 case TGSI_OPCODE_SNE
:
5021 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5024 case TGSI_OPCODE_TEX
:
5025 /* simple texture lookup */
5026 /* src[0] = texcoord */
5027 /* src[1] = sampler unit */
5028 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5031 case TGSI_OPCODE_TXB
:
5032 /* Texture lookup with lod bias */
5033 /* src[0] = texcoord (src[0].w = LOD bias) */
5034 /* src[1] = sampler unit */
5035 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5038 case TGSI_OPCODE_TXD
:
5039 /* Texture lookup with explict partial derivatives */
5040 /* src[0] = texcoord */
5041 /* src[1] = d[strq]/dx */
5042 /* src[2] = d[strq]/dy */
5043 /* src[3] = sampler unit */
5044 exec_txd(mach
, inst
);
5047 case TGSI_OPCODE_TXL
:
5048 /* Texture lookup with explit LOD */
5049 /* src[0] = texcoord (src[0].w = LOD) */
5050 /* src[1] = sampler unit */
5051 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5054 case TGSI_OPCODE_TXP
:
5055 /* Texture lookup with projection */
5056 /* src[0] = texcoord (src[0].w = projection) */
5057 /* src[1] = sampler unit */
5058 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5061 case TGSI_OPCODE_TG4
:
5062 /* src[0] = texcoord */
5063 /* src[1] = component */
5064 /* src[2] = sampler unit */
5065 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5068 case TGSI_OPCODE_LODQ
:
5069 /* src[0] = texcoord */
5070 /* src[1] = sampler unit */
5071 exec_lodq(mach
, inst
);
5074 case TGSI_OPCODE_UP2H
:
5075 exec_up2h(mach
, inst
);
5078 case TGSI_OPCODE_UP2US
:
5082 case TGSI_OPCODE_UP4B
:
5086 case TGSI_OPCODE_UP4UB
:
5090 case TGSI_OPCODE_ARR
:
5091 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5094 case TGSI_OPCODE_CAL
:
5095 /* skip the call if no execution channels are enabled */
5096 if (mach
->ExecMask
) {
5099 /* First, record the depths of the execution stacks.
5100 * This is important for deeply nested/looped return statements.
5101 * We have to unwind the stacks by the correct amount. For a
5102 * real code generator, we could determine the number of entries
5103 * to pop off each stack with simple static analysis and avoid
5104 * implementing this data structure at run time.
5106 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5107 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5108 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5109 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5110 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5111 /* note that PC was already incremented above */
5112 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5114 mach
->CallStackTop
++;
5116 /* Second, push the Cond, Loop, Cont, Func stacks */
5117 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5118 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5119 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5120 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5121 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5122 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5124 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5125 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5126 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5127 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5128 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5129 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5131 /* Finally, jump to the subroutine. The label is a pointer
5132 * (an instruction number) to the BGNSUB instruction.
5134 *pc
= inst
->Label
.Label
;
5135 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5136 == TGSI_OPCODE_BGNSUB
);
5140 case TGSI_OPCODE_RET
:
5141 mach
->FuncMask
&= ~mach
->ExecMask
;
5142 UPDATE_EXEC_MASK(mach
);
5144 if (mach
->FuncMask
== 0x0) {
5145 /* really return now (otherwise, keep executing */
5147 if (mach
->CallStackTop
== 0) {
5148 /* returning from main() */
5149 mach
->CondStackTop
= 0;
5150 mach
->LoopStackTop
= 0;
5151 mach
->ContStackTop
= 0;
5152 mach
->LoopLabelStackTop
= 0;
5153 mach
->SwitchStackTop
= 0;
5154 mach
->BreakStackTop
= 0;
5159 assert(mach
->CallStackTop
> 0);
5160 mach
->CallStackTop
--;
5162 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5163 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5165 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5166 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5168 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5169 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5171 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5172 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5174 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5175 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5177 assert(mach
->FuncStackTop
> 0);
5178 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5180 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5182 UPDATE_EXEC_MASK(mach
);
5186 case TGSI_OPCODE_SSG
:
5187 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5190 case TGSI_OPCODE_CMP
:
5191 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5194 case TGSI_OPCODE_SCS
:
5195 exec_scs(mach
, inst
);
5198 case TGSI_OPCODE_DIV
:
5199 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5202 case TGSI_OPCODE_DP2
:
5203 exec_dp2(mach
, inst
);
5206 case TGSI_OPCODE_IF
:
5208 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5209 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5210 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5211 /* update CondMask */
5213 mach
->CondMask
&= ~0x1;
5216 mach
->CondMask
&= ~0x2;
5219 mach
->CondMask
&= ~0x4;
5222 mach
->CondMask
&= ~0x8;
5224 UPDATE_EXEC_MASK(mach
);
5225 /* Todo: If CondMask==0, jump to ELSE */
5228 case TGSI_OPCODE_UIF
:
5230 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5231 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5232 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5233 /* update CondMask */
5235 mach
->CondMask
&= ~0x1;
5238 mach
->CondMask
&= ~0x2;
5241 mach
->CondMask
&= ~0x4;
5244 mach
->CondMask
&= ~0x8;
5246 UPDATE_EXEC_MASK(mach
);
5247 /* Todo: If CondMask==0, jump to ELSE */
5250 case TGSI_OPCODE_ELSE
:
5251 /* invert CondMask wrt previous mask */
5254 assert(mach
->CondStackTop
> 0);
5255 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5256 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5257 UPDATE_EXEC_MASK(mach
);
5258 /* Todo: If CondMask==0, jump to ENDIF */
5262 case TGSI_OPCODE_ENDIF
:
5264 assert(mach
->CondStackTop
> 0);
5265 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5266 UPDATE_EXEC_MASK(mach
);
5269 case TGSI_OPCODE_END
:
5270 /* make sure we end primitives which haven't
5271 * been explicitly emitted */
5272 conditional_emit_primitive(mach
);
5273 /* halt execution */
5277 case TGSI_OPCODE_PUSHA
:
5281 case TGSI_OPCODE_POPA
:
5285 case TGSI_OPCODE_CEIL
:
5286 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5289 case TGSI_OPCODE_I2F
:
5290 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5293 case TGSI_OPCODE_NOT
:
5294 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5297 case TGSI_OPCODE_TRUNC
:
5298 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5301 case TGSI_OPCODE_SHL
:
5302 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5305 case TGSI_OPCODE_AND
:
5306 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5309 case TGSI_OPCODE_OR
:
5310 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5313 case TGSI_OPCODE_MOD
:
5314 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5317 case TGSI_OPCODE_XOR
:
5318 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5321 case TGSI_OPCODE_SAD
:
5325 case TGSI_OPCODE_TXF
:
5326 exec_txf(mach
, inst
);
5329 case TGSI_OPCODE_TXQ
:
5330 exec_txq(mach
, inst
);
5333 case TGSI_OPCODE_EMIT
:
5337 case TGSI_OPCODE_ENDPRIM
:
5338 emit_primitive(mach
);
5341 case TGSI_OPCODE_BGNLOOP
:
5342 /* push LoopMask and ContMasks */
5343 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5344 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5345 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5346 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5348 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5349 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5350 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5351 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5352 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5355 case TGSI_OPCODE_ENDLOOP
:
5356 /* Restore ContMask, but don't pop */
5357 assert(mach
->ContStackTop
> 0);
5358 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5359 UPDATE_EXEC_MASK(mach
);
5360 if (mach
->ExecMask
) {
5361 /* repeat loop: jump to instruction just past BGNLOOP */
5362 assert(mach
->LoopLabelStackTop
> 0);
5363 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5366 /* exit loop: pop LoopMask */
5367 assert(mach
->LoopStackTop
> 0);
5368 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5370 assert(mach
->ContStackTop
> 0);
5371 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5372 assert(mach
->LoopLabelStackTop
> 0);
5373 --mach
->LoopLabelStackTop
;
5375 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5377 UPDATE_EXEC_MASK(mach
);
5380 case TGSI_OPCODE_BRK
:
5384 case TGSI_OPCODE_CONT
:
5385 /* turn off cont channels for each enabled exec channel */
5386 mach
->ContMask
&= ~mach
->ExecMask
;
5387 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5388 UPDATE_EXEC_MASK(mach
);
5391 case TGSI_OPCODE_BGNSUB
:
5395 case TGSI_OPCODE_ENDSUB
:
5397 * XXX: This really should be a no-op. We should never reach this opcode.
5400 assert(mach
->CallStackTop
> 0);
5401 mach
->CallStackTop
--;
5403 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5404 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5406 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5407 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5409 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5410 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5412 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5413 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5415 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5416 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5418 assert(mach
->FuncStackTop
> 0);
5419 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5421 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5423 UPDATE_EXEC_MASK(mach
);
5426 case TGSI_OPCODE_NOP
:
5429 case TGSI_OPCODE_BREAKC
:
5430 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
5431 /* update CondMask */
5432 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
5433 mach
->LoopMask
&= ~0x1;
5435 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
5436 mach
->LoopMask
&= ~0x2;
5438 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
5439 mach
->LoopMask
&= ~0x4;
5441 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
5442 mach
->LoopMask
&= ~0x8;
5444 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5445 UPDATE_EXEC_MASK(mach
);
5448 case TGSI_OPCODE_F2I
:
5449 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5452 case TGSI_OPCODE_FSEQ
:
5453 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5456 case TGSI_OPCODE_FSGE
:
5457 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5460 case TGSI_OPCODE_FSLT
:
5461 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5464 case TGSI_OPCODE_FSNE
:
5465 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5468 case TGSI_OPCODE_IDIV
:
5469 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5472 case TGSI_OPCODE_IMAX
:
5473 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5476 case TGSI_OPCODE_IMIN
:
5477 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5480 case TGSI_OPCODE_INEG
:
5481 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5484 case TGSI_OPCODE_ISGE
:
5485 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5488 case TGSI_OPCODE_ISHR
:
5489 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5492 case TGSI_OPCODE_ISLT
:
5493 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5496 case TGSI_OPCODE_F2U
:
5497 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5500 case TGSI_OPCODE_U2F
:
5501 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5504 case TGSI_OPCODE_UADD
:
5505 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5508 case TGSI_OPCODE_UDIV
:
5509 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5512 case TGSI_OPCODE_UMAD
:
5513 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5516 case TGSI_OPCODE_UMAX
:
5517 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5520 case TGSI_OPCODE_UMIN
:
5521 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5524 case TGSI_OPCODE_UMOD
:
5525 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5528 case TGSI_OPCODE_UMUL
:
5529 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5532 case TGSI_OPCODE_IMUL_HI
:
5533 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5536 case TGSI_OPCODE_UMUL_HI
:
5537 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5540 case TGSI_OPCODE_USEQ
:
5541 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5544 case TGSI_OPCODE_USGE
:
5545 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5548 case TGSI_OPCODE_USHR
:
5549 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5552 case TGSI_OPCODE_USLT
:
5553 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5556 case TGSI_OPCODE_USNE
:
5557 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5560 case TGSI_OPCODE_SWITCH
:
5561 exec_switch(mach
, inst
);
5564 case TGSI_OPCODE_CASE
:
5565 exec_case(mach
, inst
);
5568 case TGSI_OPCODE_DEFAULT
:
5572 case TGSI_OPCODE_ENDSWITCH
:
5573 exec_endswitch(mach
);
5576 case TGSI_OPCODE_SAMPLE_I
:
5577 exec_txf(mach
, inst
);
5580 case TGSI_OPCODE_SAMPLE_I_MS
:
5581 exec_txf(mach
, inst
);
5584 case TGSI_OPCODE_SAMPLE
:
5585 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5588 case TGSI_OPCODE_SAMPLE_B
:
5589 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5592 case TGSI_OPCODE_SAMPLE_C
:
5593 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5596 case TGSI_OPCODE_SAMPLE_C_LZ
:
5597 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5600 case TGSI_OPCODE_SAMPLE_D
:
5601 exec_sample_d(mach
, inst
);
5604 case TGSI_OPCODE_SAMPLE_L
:
5605 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5608 case TGSI_OPCODE_GATHER4
:
5612 case TGSI_OPCODE_SVIEWINFO
:
5613 exec_txq(mach
, inst
);
5616 case TGSI_OPCODE_SAMPLE_POS
:
5620 case TGSI_OPCODE_SAMPLE_INFO
:
5624 case TGSI_OPCODE_UARL
:
5625 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5628 case TGSI_OPCODE_UCMP
:
5629 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5632 case TGSI_OPCODE_IABS
:
5633 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5636 case TGSI_OPCODE_ISSG
:
5637 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5640 case TGSI_OPCODE_TEX2
:
5641 /* simple texture lookup */
5642 /* src[0] = texcoord */
5643 /* src[1] = compare */
5644 /* src[2] = sampler unit */
5645 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5647 case TGSI_OPCODE_TXB2
:
5648 /* simple texture lookup */
5649 /* src[0] = texcoord */
5651 /* src[2] = sampler unit */
5652 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5654 case TGSI_OPCODE_TXL2
:
5655 /* simple texture lookup */
5656 /* src[0] = texcoord */
5658 /* src[2] = sampler unit */
5659 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5662 case TGSI_OPCODE_IBFE
:
5663 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5665 case TGSI_OPCODE_UBFE
:
5666 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5668 case TGSI_OPCODE_BFI
:
5669 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5671 case TGSI_OPCODE_BREV
:
5672 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5674 case TGSI_OPCODE_POPC
:
5675 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5677 case TGSI_OPCODE_LSB
:
5678 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5680 case TGSI_OPCODE_IMSB
:
5681 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5683 case TGSI_OPCODE_UMSB
:
5684 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5687 case TGSI_OPCODE_F2D
:
5688 exec_f2d(mach
, inst
);
5691 case TGSI_OPCODE_D2F
:
5692 exec_d2f(mach
, inst
);
5695 case TGSI_OPCODE_DABS
:
5696 exec_double_unary(mach
, inst
, micro_dabs
);
5699 case TGSI_OPCODE_DNEG
:
5700 exec_double_unary(mach
, inst
, micro_dneg
);
5703 case TGSI_OPCODE_DADD
:
5704 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5707 case TGSI_OPCODE_DMUL
:
5708 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
5711 case TGSI_OPCODE_DMAX
:
5712 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
5715 case TGSI_OPCODE_DMIN
:
5716 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
5719 case TGSI_OPCODE_DSLT
:
5720 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
5723 case TGSI_OPCODE_DSGE
:
5724 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
5727 case TGSI_OPCODE_DSEQ
:
5728 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
5731 case TGSI_OPCODE_DSNE
:
5732 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
5735 case TGSI_OPCODE_DRCP
:
5736 exec_double_unary(mach
, inst
, micro_drcp
);
5739 case TGSI_OPCODE_DSQRT
:
5740 exec_double_unary(mach
, inst
, micro_dsqrt
);
5743 case TGSI_OPCODE_DRSQ
:
5744 exec_double_unary(mach
, inst
, micro_drsq
);
5747 case TGSI_OPCODE_DMAD
:
5748 exec_double_trinary(mach
, inst
, micro_dmad
);
5751 case TGSI_OPCODE_DFRAC
:
5752 exec_double_unary(mach
, inst
, micro_dfrac
);
5755 case TGSI_OPCODE_DLDEXP
:
5756 exec_dldexp(mach
, inst
);
5759 case TGSI_OPCODE_DFRACEXP
:
5760 exec_dfracexp(mach
, inst
);
5763 case TGSI_OPCODE_I2D
:
5764 exec_i2d(mach
, inst
);
5767 case TGSI_OPCODE_D2I
:
5768 exec_d2i(mach
, inst
);
5771 case TGSI_OPCODE_U2D
:
5772 exec_u2d(mach
, inst
);
5775 case TGSI_OPCODE_D2U
:
5776 exec_d2u(mach
, inst
);
5779 case TGSI_OPCODE_LOAD
:
5780 exec_load(mach
, inst
);
5783 case TGSI_OPCODE_STORE
:
5784 exec_store(mach
, inst
);
5787 case TGSI_OPCODE_ATOMUADD
:
5788 case TGSI_OPCODE_ATOMXCHG
:
5789 case TGSI_OPCODE_ATOMCAS
:
5790 case TGSI_OPCODE_ATOMAND
:
5791 case TGSI_OPCODE_ATOMOR
:
5792 case TGSI_OPCODE_ATOMXOR
:
5793 case TGSI_OPCODE_ATOMUMIN
:
5794 case TGSI_OPCODE_ATOMUMAX
:
5795 case TGSI_OPCODE_ATOMIMIN
:
5796 case TGSI_OPCODE_ATOMIMAX
:
5797 exec_atomop(mach
, inst
);
5800 case TGSI_OPCODE_RESQ
:
5801 exec_resq(mach
, inst
);
5803 case TGSI_OPCODE_BARRIER
:
5804 case TGSI_OPCODE_MEMBAR
:
5814 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
5816 uint default_mask
= 0xf;
5818 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
5819 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
5821 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
5822 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
5823 mach
->Primitives
[0] = 0;
5824 /* GS runs on a single primitive for now */
5828 if (mach
->NonHelperMask
== 0)
5829 mach
->NonHelperMask
= default_mask
;
5830 mach
->CondMask
= default_mask
;
5831 mach
->LoopMask
= default_mask
;
5832 mach
->ContMask
= default_mask
;
5833 mach
->FuncMask
= default_mask
;
5834 mach
->ExecMask
= default_mask
;
5836 mach
->Switch
.mask
= default_mask
;
5838 assert(mach
->CondStackTop
== 0);
5839 assert(mach
->LoopStackTop
== 0);
5840 assert(mach
->ContStackTop
== 0);
5841 assert(mach
->SwitchStackTop
== 0);
5842 assert(mach
->BreakStackTop
== 0);
5843 assert(mach
->CallStackTop
== 0);
5847 * Run TGSI interpreter.
5848 * \return bitmask of "alive" quad components
5851 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
5855 mach
->pc
= start_pc
;
5858 tgsi_exec_machine_setup_masks(mach
);
5860 /* execute declarations (interpolants) */
5861 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
5862 exec_declaration( mach
, mach
->Declarations
+i
);
5868 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
5869 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
5873 memset(mach
->Temps
, 0, sizeof(temps
));
5875 memset(mach
->Outputs
, 0, sizeof(outputs
));
5876 memset(temps
, 0, sizeof(temps
));
5877 memset(outputs
, 0, sizeof(outputs
));
5881 /* execute instructions, until pc is set to -1 */
5882 while (mach
->pc
!= -1) {
5883 boolean barrier_hit
;
5887 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
5890 assert(mach
->pc
< (int) mach
->NumInstructions
);
5891 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
5893 /* for compute shaders if we hit a barrier return now for later rescheduling */
5894 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
5898 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
5899 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
5902 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
5903 debug_printf("TEMP[%2u] = ", i
);
5904 for (j
= 0; j
< 4; j
++) {
5908 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5909 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
5910 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
5911 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
5912 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
5916 if (mach
->Outputs
) {
5917 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
5918 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
5921 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
5922 debug_printf("OUT[%2u] = ", i
);
5923 for (j
= 0; j
< 4; j
++) {
5927 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5928 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
5929 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
5930 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
5931 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
5941 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5942 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
5944 * Scale back depth component.
5946 for (i
= 0; i
< 4; i
++)
5947 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
5951 /* Strictly speaking, these assertions aren't really needed but they
5952 * can potentially catch some bugs in the control flow code.
5954 assert(mach
->CondStackTop
== 0);
5955 assert(mach
->LoopStackTop
== 0);
5956 assert(mach
->ContStackTop
== 0);
5957 assert(mach
->SwitchStackTop
== 0);
5958 assert(mach
->BreakStackTop
== 0);
5959 assert(mach
->CallStackTop
== 0);
5961 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];