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tgsi: Implement new integer opcodes.
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /**
29 * TGSI interpreter/executor.
30 *
31 * Flow control information:
32 *
33 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
34 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
35 * care since a condition may be true for some quad components but false
36 * for other components.
37 *
38 * We basically execute all statements (even if they're in the part of
39 * an IF/ELSE clause that's "not taken") and use a special mask to
40 * control writing to destination registers. This is the ExecMask.
41 * See store_dest().
42 *
43 * The ExecMask is computed from three other masks (CondMask, LoopMask and
44 * ContMask) which are controlled by the flow control instructions (namely:
45 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
46 *
47 *
48 * Authors:
49 * Michal Krol
50 * Brian Paul
51 */
52
53 #include "pipe/p_compiler.h"
54 #include "pipe/p_state.h"
55 #include "pipe/p_shader_tokens.h"
56 #include "tgsi/tgsi_dump.h"
57 #include "tgsi/tgsi_parse.h"
58 #include "tgsi/tgsi_util.h"
59 #include "tgsi_exec.h"
60 #include "util/u_memory.h"
61 #include "util/u_math.h"
62
63 #define FAST_MATH 1
64
65 #define TILE_TOP_LEFT 0
66 #define TILE_TOP_RIGHT 1
67 #define TILE_BOTTOM_LEFT 2
68 #define TILE_BOTTOM_RIGHT 3
69
70 #define CHAN_X 0
71 #define CHAN_Y 1
72 #define CHAN_Z 2
73 #define CHAN_W 3
74
75 /*
76 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
77 */
78 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
79 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
80 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
81 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
82 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
83 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
84 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
85 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
86 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
87 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
88 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
89 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
90 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
91 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
92 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
93 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
94 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
95 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
96 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
97 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
98 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
99 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
100 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
101 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
102 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
103 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
104 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
105 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
106 #define TEMP_R0 TGSI_EXEC_TEMP_R0
107 #define TEMP_P0 TGSI_EXEC_TEMP_P0
108
109 #define IS_CHANNEL_ENABLED(INST, CHAN)\
110 ((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
111
112 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
113 ((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
114
115 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
116 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
117 if (IS_CHANNEL_ENABLED( INST, CHAN ))
118
119 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
120 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
121 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
122
123
124 /** The execution mask depends on the conditional mask and the loop mask */
125 #define UPDATE_EXEC_MASK(MACH) \
126 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->FuncMask
127
128
129 static const union tgsi_exec_channel ZeroVec =
130 { { 0.0, 0.0, 0.0, 0.0 } };
131
132
133 #ifdef DEBUG
134 static void
135 check_inf_or_nan(const union tgsi_exec_channel *chan)
136 {
137 assert(!util_is_inf_or_nan(chan->f[0]));
138 assert(!util_is_inf_or_nan(chan->f[1]));
139 assert(!util_is_inf_or_nan(chan->f[2]));
140 assert(!util_is_inf_or_nan(chan->f[3]));
141 }
142 #endif
143
144
145 #ifdef DEBUG
146 static void
147 print_chan(const char *msg, const union tgsi_exec_channel *chan)
148 {
149 debug_printf("%s = {%f, %f, %f, %f}\n",
150 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
151 }
152 #endif
153
154
155 #ifdef DEBUG
156 static void
157 print_temp(const struct tgsi_exec_machine *mach, uint index)
158 {
159 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
160 int i;
161 debug_printf("Temp[%u] =\n", index);
162 for (i = 0; i < 4; i++) {
163 debug_printf(" %c: { %f, %f, %f, %f }\n",
164 "XYZW"[i],
165 tmp->xyzw[i].f[0],
166 tmp->xyzw[i].f[1],
167 tmp->xyzw[i].f[2],
168 tmp->xyzw[i].f[3]);
169 }
170 }
171 #endif
172
173
174 /**
175 * Check if there's a potential src/dst register data dependency when
176 * using SOA execution.
177 * Example:
178 * MOV T, T.yxwz;
179 * This would expand into:
180 * MOV t0, t1;
181 * MOV t1, t0;
182 * MOV t2, t3;
183 * MOV t3, t2;
184 * The second instruction will have the wrong value for t0 if executed as-is.
185 */
186 boolean
187 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
188 {
189 uint i, chan;
190
191 uint writemask = inst->Dst[0].Register.WriteMask;
192 if (writemask == TGSI_WRITEMASK_X ||
193 writemask == TGSI_WRITEMASK_Y ||
194 writemask == TGSI_WRITEMASK_Z ||
195 writemask == TGSI_WRITEMASK_W ||
196 writemask == TGSI_WRITEMASK_NONE) {
197 /* no chance of data dependency */
198 return FALSE;
199 }
200
201 /* loop over src regs */
202 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
203 if ((inst->Src[i].Register.File ==
204 inst->Dst[0].Register.File) &&
205 (inst->Src[i].Register.Index ==
206 inst->Dst[0].Register.Index)) {
207 /* loop over dest channels */
208 uint channelsWritten = 0x0;
209 FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
210 /* check if we're reading a channel that's been written */
211 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
212 if (channelsWritten & (1 << swizzle)) {
213 return TRUE;
214 }
215
216 channelsWritten |= (1 << chan);
217 }
218 }
219 }
220 return FALSE;
221 }
222
223
224 /**
225 * Initialize machine state by expanding tokens to full instructions,
226 * allocating temporary storage, setting up constants, etc.
227 * After this, we can call tgsi_exec_machine_run() many times.
228 */
229 void
230 tgsi_exec_machine_bind_shader(
231 struct tgsi_exec_machine *mach,
232 const struct tgsi_token *tokens,
233 uint numSamplers,
234 struct tgsi_sampler **samplers)
235 {
236 uint k;
237 struct tgsi_parse_context parse;
238 struct tgsi_exec_labels *labels = &mach->Labels;
239 struct tgsi_full_instruction *instructions;
240 struct tgsi_full_declaration *declarations;
241 uint maxInstructions = 10, numInstructions = 0;
242 uint maxDeclarations = 10, numDeclarations = 0;
243 uint instno = 0;
244
245 #if 0
246 tgsi_dump(tokens, 0);
247 #endif
248
249 util_init_math();
250
251 mach->Tokens = tokens;
252 mach->Samplers = samplers;
253
254 k = tgsi_parse_init (&parse, mach->Tokens);
255 if (k != TGSI_PARSE_OK) {
256 debug_printf( "Problem parsing!\n" );
257 return;
258 }
259
260 mach->Processor = parse.FullHeader.Processor.Processor;
261 mach->ImmLimit = 0;
262 labels->count = 0;
263
264 declarations = (struct tgsi_full_declaration *)
265 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
266
267 if (!declarations) {
268 return;
269 }
270
271 instructions = (struct tgsi_full_instruction *)
272 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
273
274 if (!instructions) {
275 FREE( declarations );
276 return;
277 }
278
279 while( !tgsi_parse_end_of_tokens( &parse ) ) {
280 uint pointer = parse.Position;
281 uint i;
282
283 tgsi_parse_token( &parse );
284 switch( parse.FullToken.Token.Type ) {
285 case TGSI_TOKEN_TYPE_DECLARATION:
286 /* save expanded declaration */
287 if (numDeclarations == maxDeclarations) {
288 declarations = REALLOC(declarations,
289 maxDeclarations
290 * sizeof(struct tgsi_full_declaration),
291 (maxDeclarations + 10)
292 * sizeof(struct tgsi_full_declaration));
293 maxDeclarations += 10;
294 }
295 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
296 unsigned reg;
297 for (reg = parse.FullToken.FullDeclaration.Range.First;
298 reg <= parse.FullToken.FullDeclaration.Range.Last;
299 ++reg) {
300 ++mach->NumOutputs;
301 }
302 }
303 memcpy(declarations + numDeclarations,
304 &parse.FullToken.FullDeclaration,
305 sizeof(declarations[0]));
306 numDeclarations++;
307 break;
308
309 case TGSI_TOKEN_TYPE_IMMEDIATE:
310 {
311 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
312 assert( size <= 4 );
313 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
314
315 for( i = 0; i < size; i++ ) {
316 mach->Imms[mach->ImmLimit][i] =
317 parse.FullToken.FullImmediate.u[i].Float;
318 }
319 mach->ImmLimit += 1;
320 }
321 break;
322
323 case TGSI_TOKEN_TYPE_INSTRUCTION:
324 assert( labels->count < MAX_LABELS );
325
326 labels->labels[labels->count][0] = instno;
327 labels->labels[labels->count][1] = pointer;
328 labels->count++;
329
330 /* save expanded instruction */
331 if (numInstructions == maxInstructions) {
332 instructions = REALLOC(instructions,
333 maxInstructions
334 * sizeof(struct tgsi_full_instruction),
335 (maxInstructions + 10)
336 * sizeof(struct tgsi_full_instruction));
337 maxInstructions += 10;
338 }
339
340 memcpy(instructions + numInstructions,
341 &parse.FullToken.FullInstruction,
342 sizeof(instructions[0]));
343
344 numInstructions++;
345 break;
346
347 case TGSI_TOKEN_TYPE_PROPERTY:
348 break;
349
350 default:
351 assert( 0 );
352 }
353 }
354 tgsi_parse_free (&parse);
355
356 if (mach->Declarations) {
357 FREE( mach->Declarations );
358 }
359 mach->Declarations = declarations;
360 mach->NumDeclarations = numDeclarations;
361
362 if (mach->Instructions) {
363 FREE( mach->Instructions );
364 }
365 mach->Instructions = instructions;
366 mach->NumInstructions = numInstructions;
367 }
368
369
370 struct tgsi_exec_machine *
371 tgsi_exec_machine_create( void )
372 {
373 struct tgsi_exec_machine *mach;
374 uint i;
375
376 mach = align_malloc( sizeof *mach, 16 );
377 if (!mach)
378 goto fail;
379
380 memset(mach, 0, sizeof(*mach));
381
382 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
383 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
384 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
385
386 /* Setup constants. */
387 for( i = 0; i < 4; i++ ) {
388 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
389 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
390 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
391 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
392 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
393 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
394 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
395 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
396 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
397 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
398 }
399
400 #ifdef DEBUG
401 /* silence warnings */
402 (void) print_chan;
403 (void) print_temp;
404 #endif
405
406 return mach;
407
408 fail:
409 align_free(mach);
410 return NULL;
411 }
412
413
414 void
415 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
416 {
417 if (mach) {
418 FREE(mach->Instructions);
419 FREE(mach->Declarations);
420 }
421
422 align_free(mach);
423 }
424
425
426 static void
427 micro_abs(
428 union tgsi_exec_channel *dst,
429 const union tgsi_exec_channel *src )
430 {
431 dst->f[0] = fabsf( src->f[0] );
432 dst->f[1] = fabsf( src->f[1] );
433 dst->f[2] = fabsf( src->f[2] );
434 dst->f[3] = fabsf( src->f[3] );
435 }
436
437 static void
438 micro_add(
439 union tgsi_exec_channel *dst,
440 const union tgsi_exec_channel *src0,
441 const union tgsi_exec_channel *src1 )
442 {
443 dst->f[0] = src0->f[0] + src1->f[0];
444 dst->f[1] = src0->f[1] + src1->f[1];
445 dst->f[2] = src0->f[2] + src1->f[2];
446 dst->f[3] = src0->f[3] + src1->f[3];
447 }
448
449 static void
450 micro_and(
451 union tgsi_exec_channel *dst,
452 const union tgsi_exec_channel *src0,
453 const union tgsi_exec_channel *src1 )
454 {
455 dst->u[0] = src0->u[0] & src1->u[0];
456 dst->u[1] = src0->u[1] & src1->u[1];
457 dst->u[2] = src0->u[2] & src1->u[2];
458 dst->u[3] = src0->u[3] & src1->u[3];
459 }
460
461 static void
462 micro_ceil(
463 union tgsi_exec_channel *dst,
464 const union tgsi_exec_channel *src )
465 {
466 dst->f[0] = ceilf( src->f[0] );
467 dst->f[1] = ceilf( src->f[1] );
468 dst->f[2] = ceilf( src->f[2] );
469 dst->f[3] = ceilf( src->f[3] );
470 }
471
472 static void
473 micro_cos(
474 union tgsi_exec_channel *dst,
475 const union tgsi_exec_channel *src )
476 {
477 dst->f[0] = cosf( src->f[0] );
478 dst->f[1] = cosf( src->f[1] );
479 dst->f[2] = cosf( src->f[2] );
480 dst->f[3] = cosf( src->f[3] );
481 }
482
483 static void
484 micro_ddx(
485 union tgsi_exec_channel *dst,
486 const union tgsi_exec_channel *src )
487 {
488 dst->f[0] =
489 dst->f[1] =
490 dst->f[2] =
491 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
492 }
493
494 static void
495 micro_ddy(
496 union tgsi_exec_channel *dst,
497 const union tgsi_exec_channel *src )
498 {
499 dst->f[0] =
500 dst->f[1] =
501 dst->f[2] =
502 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
503 }
504
505 static void
506 micro_div(
507 union tgsi_exec_channel *dst,
508 const union tgsi_exec_channel *src0,
509 const union tgsi_exec_channel *src1 )
510 {
511 if (src1->f[0] != 0) {
512 dst->f[0] = src0->f[0] / src1->f[0];
513 }
514 if (src1->f[1] != 0) {
515 dst->f[1] = src0->f[1] / src1->f[1];
516 }
517 if (src1->f[2] != 0) {
518 dst->f[2] = src0->f[2] / src1->f[2];
519 }
520 if (src1->f[3] != 0) {
521 dst->f[3] = src0->f[3] / src1->f[3];
522 }
523 }
524
525 static void
526 micro_eq(
527 union tgsi_exec_channel *dst,
528 const union tgsi_exec_channel *src0,
529 const union tgsi_exec_channel *src1,
530 const union tgsi_exec_channel *src2,
531 const union tgsi_exec_channel *src3 )
532 {
533 dst->f[0] = src0->f[0] == src1->f[0] ? src2->f[0] : src3->f[0];
534 dst->f[1] = src0->f[1] == src1->f[1] ? src2->f[1] : src3->f[1];
535 dst->f[2] = src0->f[2] == src1->f[2] ? src2->f[2] : src3->f[2];
536 dst->f[3] = src0->f[3] == src1->f[3] ? src2->f[3] : src3->f[3];
537 }
538
539 static void
540 micro_exp2(
541 union tgsi_exec_channel *dst,
542 const union tgsi_exec_channel *src)
543 {
544 #if FAST_MATH
545 dst->f[0] = util_fast_exp2( src->f[0] );
546 dst->f[1] = util_fast_exp2( src->f[1] );
547 dst->f[2] = util_fast_exp2( src->f[2] );
548 dst->f[3] = util_fast_exp2( src->f[3] );
549 #else
550
551 #if DEBUG
552 /* Inf is okay for this instruction, so clamp it to silence assertions. */
553 uint i;
554 union tgsi_exec_channel clamped;
555
556 for (i = 0; i < 4; i++) {
557 if (src->f[i] > 127.99999f) {
558 clamped.f[i] = 127.99999f;
559 } else if (src->f[i] < -126.99999f) {
560 clamped.f[i] = -126.99999f;
561 } else {
562 clamped.f[i] = src->f[i];
563 }
564 }
565 src = &clamped;
566 #endif
567
568 dst->f[0] = powf( 2.0f, src->f[0] );
569 dst->f[1] = powf( 2.0f, src->f[1] );
570 dst->f[2] = powf( 2.0f, src->f[2] );
571 dst->f[3] = powf( 2.0f, src->f[3] );
572 #endif
573 }
574
575 static void
576 micro_float_clamp(union tgsi_exec_channel *dst,
577 const union tgsi_exec_channel *src)
578 {
579 uint i;
580
581 for (i = 0; i < 4; i++) {
582 if (src->f[i] > 0.0f) {
583 if (src->f[i] > 1.884467e+019f)
584 dst->f[i] = 1.884467e+019f;
585 else if (src->f[i] < 5.42101e-020f)
586 dst->f[i] = 5.42101e-020f;
587 else
588 dst->f[i] = src->f[i];
589 }
590 else {
591 if (src->f[i] < -1.884467e+019f)
592 dst->f[i] = -1.884467e+019f;
593 else if (src->f[i] > -5.42101e-020f)
594 dst->f[i] = -5.42101e-020f;
595 else
596 dst->f[i] = src->f[i];
597 }
598 }
599 }
600
601 static void
602 micro_flr(
603 union tgsi_exec_channel *dst,
604 const union tgsi_exec_channel *src )
605 {
606 dst->f[0] = floorf( src->f[0] );
607 dst->f[1] = floorf( src->f[1] );
608 dst->f[2] = floorf( src->f[2] );
609 dst->f[3] = floorf( src->f[3] );
610 }
611
612 static void
613 micro_frc(
614 union tgsi_exec_channel *dst,
615 const union tgsi_exec_channel *src )
616 {
617 dst->f[0] = src->f[0] - floorf( src->f[0] );
618 dst->f[1] = src->f[1] - floorf( src->f[1] );
619 dst->f[2] = src->f[2] - floorf( src->f[2] );
620 dst->f[3] = src->f[3] - floorf( src->f[3] );
621 }
622
623 static void
624 micro_i2f(
625 union tgsi_exec_channel *dst,
626 const union tgsi_exec_channel *src )
627 {
628 dst->f[0] = (float) src->i[0];
629 dst->f[1] = (float) src->i[1];
630 dst->f[2] = (float) src->i[2];
631 dst->f[3] = (float) src->i[3];
632 }
633
634 static void
635 micro_lg2(
636 union tgsi_exec_channel *dst,
637 const union tgsi_exec_channel *src )
638 {
639 #if FAST_MATH
640 dst->f[0] = util_fast_log2( src->f[0] );
641 dst->f[1] = util_fast_log2( src->f[1] );
642 dst->f[2] = util_fast_log2( src->f[2] );
643 dst->f[3] = util_fast_log2( src->f[3] );
644 #else
645 dst->f[0] = logf( src->f[0] ) * 1.442695f;
646 dst->f[1] = logf( src->f[1] ) * 1.442695f;
647 dst->f[2] = logf( src->f[2] ) * 1.442695f;
648 dst->f[3] = logf( src->f[3] ) * 1.442695f;
649 #endif
650 }
651
652 static void
653 micro_le(
654 union tgsi_exec_channel *dst,
655 const union tgsi_exec_channel *src0,
656 const union tgsi_exec_channel *src1,
657 const union tgsi_exec_channel *src2,
658 const union tgsi_exec_channel *src3 )
659 {
660 dst->f[0] = src0->f[0] <= src1->f[0] ? src2->f[0] : src3->f[0];
661 dst->f[1] = src0->f[1] <= src1->f[1] ? src2->f[1] : src3->f[1];
662 dst->f[2] = src0->f[2] <= src1->f[2] ? src2->f[2] : src3->f[2];
663 dst->f[3] = src0->f[3] <= src1->f[3] ? src2->f[3] : src3->f[3];
664 }
665
666 static void
667 micro_lt(
668 union tgsi_exec_channel *dst,
669 const union tgsi_exec_channel *src0,
670 const union tgsi_exec_channel *src1,
671 const union tgsi_exec_channel *src2,
672 const union tgsi_exec_channel *src3 )
673 {
674 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
675 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
676 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
677 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
678 }
679
680 static void
681 micro_max(
682 union tgsi_exec_channel *dst,
683 const union tgsi_exec_channel *src0,
684 const union tgsi_exec_channel *src1 )
685 {
686 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
687 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
688 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
689 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
690 }
691
692 static void
693 micro_min(
694 union tgsi_exec_channel *dst,
695 const union tgsi_exec_channel *src0,
696 const union tgsi_exec_channel *src1 )
697 {
698 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
699 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
700 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
701 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
702 }
703
704 #if 0
705 static void
706 micro_umod(
707 union tgsi_exec_channel *dst,
708 const union tgsi_exec_channel *src0,
709 const union tgsi_exec_channel *src1 )
710 {
711 dst->u[0] = src0->u[0] % src1->u[0];
712 dst->u[1] = src0->u[1] % src1->u[1];
713 dst->u[2] = src0->u[2] % src1->u[2];
714 dst->u[3] = src0->u[3] % src1->u[3];
715 }
716 #endif
717
718 static void
719 micro_mul(
720 union tgsi_exec_channel *dst,
721 const union tgsi_exec_channel *src0,
722 const union tgsi_exec_channel *src1 )
723 {
724 dst->f[0] = src0->f[0] * src1->f[0];
725 dst->f[1] = src0->f[1] * src1->f[1];
726 dst->f[2] = src0->f[2] * src1->f[2];
727 dst->f[3] = src0->f[3] * src1->f[3];
728 }
729
730 #if 0
731 static void
732 micro_imul64(
733 union tgsi_exec_channel *dst0,
734 union tgsi_exec_channel *dst1,
735 const union tgsi_exec_channel *src0,
736 const union tgsi_exec_channel *src1 )
737 {
738 dst1->i[0] = src0->i[0] * src1->i[0];
739 dst1->i[1] = src0->i[1] * src1->i[1];
740 dst1->i[2] = src0->i[2] * src1->i[2];
741 dst1->i[3] = src0->i[3] * src1->i[3];
742 dst0->i[0] = 0;
743 dst0->i[1] = 0;
744 dst0->i[2] = 0;
745 dst0->i[3] = 0;
746 }
747 #endif
748
749 #if 0
750 static void
751 micro_umul64(
752 union tgsi_exec_channel *dst0,
753 union tgsi_exec_channel *dst1,
754 const union tgsi_exec_channel *src0,
755 const union tgsi_exec_channel *src1 )
756 {
757 dst1->u[0] = src0->u[0] * src1->u[0];
758 dst1->u[1] = src0->u[1] * src1->u[1];
759 dst1->u[2] = src0->u[2] * src1->u[2];
760 dst1->u[3] = src0->u[3] * src1->u[3];
761 dst0->u[0] = 0;
762 dst0->u[1] = 0;
763 dst0->u[2] = 0;
764 dst0->u[3] = 0;
765 }
766 #endif
767
768
769 #if 0
770 static void
771 micro_movc(
772 union tgsi_exec_channel *dst,
773 const union tgsi_exec_channel *src0,
774 const union tgsi_exec_channel *src1,
775 const union tgsi_exec_channel *src2 )
776 {
777 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
778 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
779 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
780 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
781 }
782 #endif
783
784 static void
785 micro_neg(
786 union tgsi_exec_channel *dst,
787 const union tgsi_exec_channel *src )
788 {
789 dst->f[0] = -src->f[0];
790 dst->f[1] = -src->f[1];
791 dst->f[2] = -src->f[2];
792 dst->f[3] = -src->f[3];
793 }
794
795 static void
796 micro_not(
797 union tgsi_exec_channel *dst,
798 const union tgsi_exec_channel *src )
799 {
800 dst->u[0] = ~src->u[0];
801 dst->u[1] = ~src->u[1];
802 dst->u[2] = ~src->u[2];
803 dst->u[3] = ~src->u[3];
804 }
805
806 static void
807 micro_or(
808 union tgsi_exec_channel *dst,
809 const union tgsi_exec_channel *src0,
810 const union tgsi_exec_channel *src1 )
811 {
812 dst->u[0] = src0->u[0] | src1->u[0];
813 dst->u[1] = src0->u[1] | src1->u[1];
814 dst->u[2] = src0->u[2] | src1->u[2];
815 dst->u[3] = src0->u[3] | src1->u[3];
816 }
817
818 static void
819 micro_pow(
820 union tgsi_exec_channel *dst,
821 const union tgsi_exec_channel *src0,
822 const union tgsi_exec_channel *src1 )
823 {
824 #if FAST_MATH
825 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
826 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
827 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
828 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
829 #else
830 dst->f[0] = powf( src0->f[0], src1->f[0] );
831 dst->f[1] = powf( src0->f[1], src1->f[1] );
832 dst->f[2] = powf( src0->f[2], src1->f[2] );
833 dst->f[3] = powf( src0->f[3], src1->f[3] );
834 #endif
835 }
836
837 static void
838 micro_rnd(
839 union tgsi_exec_channel *dst,
840 const union tgsi_exec_channel *src )
841 {
842 dst->f[0] = floorf( src->f[0] + 0.5f );
843 dst->f[1] = floorf( src->f[1] + 0.5f );
844 dst->f[2] = floorf( src->f[2] + 0.5f );
845 dst->f[3] = floorf( src->f[3] + 0.5f );
846 }
847
848 static void
849 micro_sgn(
850 union tgsi_exec_channel *dst,
851 const union tgsi_exec_channel *src )
852 {
853 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
854 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
855 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
856 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
857 }
858
859 static void
860 micro_shl(
861 union tgsi_exec_channel *dst,
862 const union tgsi_exec_channel *src0,
863 const union tgsi_exec_channel *src1 )
864 {
865 dst->i[0] = src0->i[0] << src1->i[0];
866 dst->i[1] = src0->i[1] << src1->i[1];
867 dst->i[2] = src0->i[2] << src1->i[2];
868 dst->i[3] = src0->i[3] << src1->i[3];
869 }
870
871 static void
872 micro_trunc(
873 union tgsi_exec_channel *dst,
874 const union tgsi_exec_channel *src0 )
875 {
876 dst->f[0] = (float) (int) src0->f[0];
877 dst->f[1] = (float) (int) src0->f[1];
878 dst->f[2] = (float) (int) src0->f[2];
879 dst->f[3] = (float) (int) src0->f[3];
880 }
881
882 static void
883 micro_sin(
884 union tgsi_exec_channel *dst,
885 const union tgsi_exec_channel *src )
886 {
887 dst->f[0] = sinf( src->f[0] );
888 dst->f[1] = sinf( src->f[1] );
889 dst->f[2] = sinf( src->f[2] );
890 dst->f[3] = sinf( src->f[3] );
891 }
892
893 static void
894 micro_sqrt( union tgsi_exec_channel *dst,
895 const union tgsi_exec_channel *src )
896 {
897 dst->f[0] = sqrtf( src->f[0] );
898 dst->f[1] = sqrtf( src->f[1] );
899 dst->f[2] = sqrtf( src->f[2] );
900 dst->f[3] = sqrtf( src->f[3] );
901 }
902
903 static void
904 micro_sub(
905 union tgsi_exec_channel *dst,
906 const union tgsi_exec_channel *src0,
907 const union tgsi_exec_channel *src1 )
908 {
909 dst->f[0] = src0->f[0] - src1->f[0];
910 dst->f[1] = src0->f[1] - src1->f[1];
911 dst->f[2] = src0->f[2] - src1->f[2];
912 dst->f[3] = src0->f[3] - src1->f[3];
913 }
914
915 static void
916 micro_xor(
917 union tgsi_exec_channel *dst,
918 const union tgsi_exec_channel *src0,
919 const union tgsi_exec_channel *src1 )
920 {
921 dst->u[0] = src0->u[0] ^ src1->u[0];
922 dst->u[1] = src0->u[1] ^ src1->u[1];
923 dst->u[2] = src0->u[2] ^ src1->u[2];
924 dst->u[3] = src0->u[3] ^ src1->u[3];
925 }
926
927 static void
928 fetch_src_file_channel(
929 const struct tgsi_exec_machine *mach,
930 const uint file,
931 const uint swizzle,
932 const union tgsi_exec_channel *index,
933 union tgsi_exec_channel *chan )
934 {
935 switch( swizzle ) {
936 case TGSI_SWIZZLE_X:
937 case TGSI_SWIZZLE_Y:
938 case TGSI_SWIZZLE_Z:
939 case TGSI_SWIZZLE_W:
940 switch( file ) {
941 case TGSI_FILE_CONSTANT:
942 assert(mach->Consts);
943 if (index->i[0] < 0)
944 chan->f[0] = 0.0f;
945 else
946 chan->f[0] = mach->Consts[index->i[0]][swizzle];
947 if (index->i[1] < 0)
948 chan->f[1] = 0.0f;
949 else
950 chan->f[1] = mach->Consts[index->i[1]][swizzle];
951 if (index->i[2] < 0)
952 chan->f[2] = 0.0f;
953 else
954 chan->f[2] = mach->Consts[index->i[2]][swizzle];
955 if (index->i[3] < 0)
956 chan->f[3] = 0.0f;
957 else
958 chan->f[3] = mach->Consts[index->i[3]][swizzle];
959 break;
960
961 case TGSI_FILE_INPUT:
962 case TGSI_FILE_SYSTEM_VALUE:
963 chan->u[0] = mach->Inputs[index->i[0]].xyzw[swizzle].u[0];
964 chan->u[1] = mach->Inputs[index->i[1]].xyzw[swizzle].u[1];
965 chan->u[2] = mach->Inputs[index->i[2]].xyzw[swizzle].u[2];
966 chan->u[3] = mach->Inputs[index->i[3]].xyzw[swizzle].u[3];
967 break;
968
969 case TGSI_FILE_TEMPORARY:
970 assert(index->i[0] < TGSI_EXEC_NUM_TEMPS);
971 chan->u[0] = mach->Temps[index->i[0]].xyzw[swizzle].u[0];
972 chan->u[1] = mach->Temps[index->i[1]].xyzw[swizzle].u[1];
973 chan->u[2] = mach->Temps[index->i[2]].xyzw[swizzle].u[2];
974 chan->u[3] = mach->Temps[index->i[3]].xyzw[swizzle].u[3];
975 break;
976
977 case TGSI_FILE_IMMEDIATE:
978 assert( index->i[0] < (int) mach->ImmLimit );
979 chan->f[0] = mach->Imms[index->i[0]][swizzle];
980 assert( index->i[1] < (int) mach->ImmLimit );
981 chan->f[1] = mach->Imms[index->i[1]][swizzle];
982 assert( index->i[2] < (int) mach->ImmLimit );
983 chan->f[2] = mach->Imms[index->i[2]][swizzle];
984 assert( index->i[3] < (int) mach->ImmLimit );
985 chan->f[3] = mach->Imms[index->i[3]][swizzle];
986 break;
987
988 case TGSI_FILE_ADDRESS:
989 chan->u[0] = mach->Addrs[index->i[0]].xyzw[swizzle].u[0];
990 chan->u[1] = mach->Addrs[index->i[1]].xyzw[swizzle].u[1];
991 chan->u[2] = mach->Addrs[index->i[2]].xyzw[swizzle].u[2];
992 chan->u[3] = mach->Addrs[index->i[3]].xyzw[swizzle].u[3];
993 break;
994
995 case TGSI_FILE_PREDICATE:
996 assert(index->i[0] < TGSI_EXEC_NUM_PREDS);
997 assert(index->i[1] < TGSI_EXEC_NUM_PREDS);
998 assert(index->i[2] < TGSI_EXEC_NUM_PREDS);
999 assert(index->i[3] < TGSI_EXEC_NUM_PREDS);
1000 chan->u[0] = mach->Predicates[0].xyzw[swizzle].u[0];
1001 chan->u[1] = mach->Predicates[0].xyzw[swizzle].u[1];
1002 chan->u[2] = mach->Predicates[0].xyzw[swizzle].u[2];
1003 chan->u[3] = mach->Predicates[0].xyzw[swizzle].u[3];
1004 break;
1005
1006 case TGSI_FILE_OUTPUT:
1007 /* vertex/fragment output vars can be read too */
1008 chan->u[0] = mach->Outputs[index->i[0]].xyzw[swizzle].u[0];
1009 chan->u[1] = mach->Outputs[index->i[1]].xyzw[swizzle].u[1];
1010 chan->u[2] = mach->Outputs[index->i[2]].xyzw[swizzle].u[2];
1011 chan->u[3] = mach->Outputs[index->i[3]].xyzw[swizzle].u[3];
1012 break;
1013
1014 default:
1015 assert( 0 );
1016 }
1017 break;
1018
1019 default:
1020 assert( 0 );
1021 }
1022 }
1023
1024 static void
1025 fetch_source(
1026 const struct tgsi_exec_machine *mach,
1027 union tgsi_exec_channel *chan,
1028 const struct tgsi_full_src_register *reg,
1029 const uint chan_index )
1030 {
1031 union tgsi_exec_channel index;
1032 uint swizzle;
1033
1034 /* We start with a direct index into a register file.
1035 *
1036 * file[1],
1037 * where:
1038 * file = Register.File
1039 * [1] = Register.Index
1040 */
1041 index.i[0] =
1042 index.i[1] =
1043 index.i[2] =
1044 index.i[3] = reg->Register.Index;
1045
1046 /* There is an extra source register that indirectly subscripts
1047 * a register file. The direct index now becomes an offset
1048 * that is being added to the indirect register.
1049 *
1050 * file[ind[2].x+1],
1051 * where:
1052 * ind = Indirect.File
1053 * [2] = Indirect.Index
1054 * .x = Indirect.SwizzleX
1055 */
1056 if (reg->Register.Indirect) {
1057 union tgsi_exec_channel index2;
1058 union tgsi_exec_channel indir_index;
1059 const uint execmask = mach->ExecMask;
1060 uint i;
1061
1062 /* which address register (always zero now) */
1063 index2.i[0] =
1064 index2.i[1] =
1065 index2.i[2] =
1066 index2.i[3] = reg->Indirect.Index;
1067
1068 /* get current value of address register[swizzle] */
1069 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1070 fetch_src_file_channel(
1071 mach,
1072 reg->Indirect.File,
1073 swizzle,
1074 &index2,
1075 &indir_index );
1076
1077 /* add value of address register to the offset */
1078 index.i[0] += (int) indir_index.f[0];
1079 index.i[1] += (int) indir_index.f[1];
1080 index.i[2] += (int) indir_index.f[2];
1081 index.i[3] += (int) indir_index.f[3];
1082
1083 /* for disabled execution channels, zero-out the index to
1084 * avoid using a potential garbage value.
1085 */
1086 for (i = 0; i < QUAD_SIZE; i++) {
1087 if ((execmask & (1 << i)) == 0)
1088 index.i[i] = 0;
1089 }
1090 }
1091
1092 /* There is an extra source register that is a second
1093 * subscript to a register file. Effectively it means that
1094 * the register file is actually a 2D array of registers.
1095 *
1096 * file[1][3] == file[1*sizeof(file[1])+3],
1097 * where:
1098 * [3] = Dimension.Index
1099 */
1100 if (reg->Register.Dimension) {
1101 /* The size of the first-order array depends on the register file type.
1102 * We need to multiply the index to the first array to get an effective,
1103 * "flat" index that points to the beginning of the second-order array.
1104 */
1105 switch (reg->Register.File) {
1106 case TGSI_FILE_INPUT:
1107 case TGSI_FILE_SYSTEM_VALUE:
1108 index.i[0] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1109 index.i[1] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1110 index.i[2] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1111 index.i[3] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1112 break;
1113 case TGSI_FILE_CONSTANT:
1114 index.i[0] *= TGSI_EXEC_MAX_CONST_BUFFER;
1115 index.i[1] *= TGSI_EXEC_MAX_CONST_BUFFER;
1116 index.i[2] *= TGSI_EXEC_MAX_CONST_BUFFER;
1117 index.i[3] *= TGSI_EXEC_MAX_CONST_BUFFER;
1118 break;
1119 default:
1120 assert( 0 );
1121 }
1122
1123 index.i[0] += reg->Dimension.Index;
1124 index.i[1] += reg->Dimension.Index;
1125 index.i[2] += reg->Dimension.Index;
1126 index.i[3] += reg->Dimension.Index;
1127
1128 /* Again, the second subscript index can be addressed indirectly
1129 * identically to the first one.
1130 * Nothing stops us from indirectly addressing the indirect register,
1131 * but there is no need for that, so we won't exercise it.
1132 *
1133 * file[1][ind[4].y+3],
1134 * where:
1135 * ind = DimIndirect.File
1136 * [4] = DimIndirect.Index
1137 * .y = DimIndirect.SwizzleX
1138 */
1139 if (reg->Dimension.Indirect) {
1140 union tgsi_exec_channel index2;
1141 union tgsi_exec_channel indir_index;
1142 const uint execmask = mach->ExecMask;
1143 uint i;
1144
1145 index2.i[0] =
1146 index2.i[1] =
1147 index2.i[2] =
1148 index2.i[3] = reg->DimIndirect.Index;
1149
1150 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1151 fetch_src_file_channel(
1152 mach,
1153 reg->DimIndirect.File,
1154 swizzle,
1155 &index2,
1156 &indir_index );
1157
1158 index.i[0] += (int) indir_index.f[0];
1159 index.i[1] += (int) indir_index.f[1];
1160 index.i[2] += (int) indir_index.f[2];
1161 index.i[3] += (int) indir_index.f[3];
1162
1163 /* for disabled execution channels, zero-out the index to
1164 * avoid using a potential garbage value.
1165 */
1166 for (i = 0; i < QUAD_SIZE; i++) {
1167 if ((execmask & (1 << i)) == 0)
1168 index.i[i] = 0;
1169 }
1170 }
1171
1172 /* If by any chance there was a need for a 3D array of register
1173 * files, we would have to check whether Dimension is followed
1174 * by a dimension register and continue the saga.
1175 */
1176 }
1177
1178 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1179 fetch_src_file_channel(
1180 mach,
1181 reg->Register.File,
1182 swizzle,
1183 &index,
1184 chan );
1185
1186 switch (tgsi_util_get_full_src_register_sign_mode( reg, chan_index )) {
1187 case TGSI_UTIL_SIGN_CLEAR:
1188 micro_abs( chan, chan );
1189 break;
1190
1191 case TGSI_UTIL_SIGN_SET:
1192 micro_abs( chan, chan );
1193 micro_neg( chan, chan );
1194 break;
1195
1196 case TGSI_UTIL_SIGN_TOGGLE:
1197 micro_neg( chan, chan );
1198 break;
1199
1200 case TGSI_UTIL_SIGN_KEEP:
1201 break;
1202 }
1203 }
1204
1205 static void
1206 store_dest(
1207 struct tgsi_exec_machine *mach,
1208 const union tgsi_exec_channel *chan,
1209 const struct tgsi_full_dst_register *reg,
1210 const struct tgsi_full_instruction *inst,
1211 uint chan_index )
1212 {
1213 uint i;
1214 union tgsi_exec_channel null;
1215 union tgsi_exec_channel *dst;
1216 uint execmask = mach->ExecMask;
1217 int offset = 0; /* indirection offset */
1218 int index;
1219
1220 #ifdef DEBUG
1221 check_inf_or_nan(chan);
1222 #endif
1223
1224 /* There is an extra source register that indirectly subscripts
1225 * a register file. The direct index now becomes an offset
1226 * that is being added to the indirect register.
1227 *
1228 * file[ind[2].x+1],
1229 * where:
1230 * ind = Indirect.File
1231 * [2] = Indirect.Index
1232 * .x = Indirect.SwizzleX
1233 */
1234 if (reg->Register.Indirect) {
1235 union tgsi_exec_channel index;
1236 union tgsi_exec_channel indir_index;
1237 uint swizzle;
1238
1239 /* which address register (always zero for now) */
1240 index.i[0] =
1241 index.i[1] =
1242 index.i[2] =
1243 index.i[3] = reg->Indirect.Index;
1244
1245 /* get current value of address register[swizzle] */
1246 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1247
1248 /* fetch values from the address/indirection register */
1249 fetch_src_file_channel(
1250 mach,
1251 reg->Indirect.File,
1252 swizzle,
1253 &index,
1254 &indir_index );
1255
1256 /* save indirection offset */
1257 offset = (int) indir_index.f[0];
1258 }
1259
1260 switch (reg->Register.File) {
1261 case TGSI_FILE_NULL:
1262 dst = &null;
1263 break;
1264
1265 case TGSI_FILE_OUTPUT:
1266 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1267 + reg->Register.Index;
1268 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1269 #if 0
1270 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1271 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1272 for (i = 0; i < QUAD_SIZE; i++)
1273 if (execmask & (1 << i))
1274 fprintf(stderr, "%f, ", chan->f[i]);
1275 fprintf(stderr, ")\n");
1276 }
1277 #endif
1278 break;
1279
1280 case TGSI_FILE_TEMPORARY:
1281 index = reg->Register.Index;
1282 assert( index < TGSI_EXEC_NUM_TEMPS );
1283 dst = &mach->Temps[offset + index].xyzw[chan_index];
1284 break;
1285
1286 case TGSI_FILE_ADDRESS:
1287 index = reg->Register.Index;
1288 dst = &mach->Addrs[index].xyzw[chan_index];
1289 break;
1290
1291 case TGSI_FILE_LOOP:
1292 assert(reg->Register.Index == 0);
1293 assert(mach->LoopCounterStackTop > 0);
1294 assert(chan_index == CHAN_X);
1295 dst = &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[chan_index];
1296 break;
1297
1298 case TGSI_FILE_PREDICATE:
1299 index = reg->Register.Index;
1300 assert(index < TGSI_EXEC_NUM_PREDS);
1301 dst = &mach->Predicates[index].xyzw[chan_index];
1302 break;
1303
1304 default:
1305 assert( 0 );
1306 return;
1307 }
1308
1309 if (inst->Instruction.Predicate) {
1310 uint swizzle;
1311 union tgsi_exec_channel *pred;
1312
1313 switch (chan_index) {
1314 case CHAN_X:
1315 swizzle = inst->Predicate.SwizzleX;
1316 break;
1317 case CHAN_Y:
1318 swizzle = inst->Predicate.SwizzleY;
1319 break;
1320 case CHAN_Z:
1321 swizzle = inst->Predicate.SwizzleZ;
1322 break;
1323 case CHAN_W:
1324 swizzle = inst->Predicate.SwizzleW;
1325 break;
1326 default:
1327 assert(0);
1328 return;
1329 }
1330
1331 assert(inst->Predicate.Index == 0);
1332
1333 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1334
1335 if (inst->Predicate.Negate) {
1336 for (i = 0; i < QUAD_SIZE; i++) {
1337 if (pred->u[i]) {
1338 execmask &= ~(1 << i);
1339 }
1340 }
1341 } else {
1342 for (i = 0; i < QUAD_SIZE; i++) {
1343 if (!pred->u[i]) {
1344 execmask &= ~(1 << i);
1345 }
1346 }
1347 }
1348 }
1349
1350 switch (inst->Instruction.Saturate) {
1351 case TGSI_SAT_NONE:
1352 for (i = 0; i < QUAD_SIZE; i++)
1353 if (execmask & (1 << i))
1354 dst->i[i] = chan->i[i];
1355 break;
1356
1357 case TGSI_SAT_ZERO_ONE:
1358 for (i = 0; i < QUAD_SIZE; i++)
1359 if (execmask & (1 << i)) {
1360 if (chan->f[i] < 0.0f)
1361 dst->f[i] = 0.0f;
1362 else if (chan->f[i] > 1.0f)
1363 dst->f[i] = 1.0f;
1364 else
1365 dst->i[i] = chan->i[i];
1366 }
1367 break;
1368
1369 case TGSI_SAT_MINUS_PLUS_ONE:
1370 for (i = 0; i < QUAD_SIZE; i++)
1371 if (execmask & (1 << i)) {
1372 if (chan->f[i] < -1.0f)
1373 dst->f[i] = -1.0f;
1374 else if (chan->f[i] > 1.0f)
1375 dst->f[i] = 1.0f;
1376 else
1377 dst->i[i] = chan->i[i];
1378 }
1379 break;
1380
1381 default:
1382 assert( 0 );
1383 }
1384 }
1385
1386 #define FETCH(VAL,INDEX,CHAN)\
1387 fetch_source (mach, VAL, &inst->Src[INDEX], CHAN)
1388
1389 #define STORE(VAL,INDEX,CHAN)\
1390 store_dest (mach, VAL, &inst->Dst[INDEX], inst, CHAN )
1391
1392
1393 /**
1394 * Execute ARB-style KIL which is predicated by a src register.
1395 * Kill fragment if any of the four values is less than zero.
1396 */
1397 static void
1398 exec_kil(struct tgsi_exec_machine *mach,
1399 const struct tgsi_full_instruction *inst)
1400 {
1401 uint uniquemask;
1402 uint chan_index;
1403 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1404 union tgsi_exec_channel r[1];
1405
1406 /* This mask stores component bits that were already tested. */
1407 uniquemask = 0;
1408
1409 for (chan_index = 0; chan_index < 4; chan_index++)
1410 {
1411 uint swizzle;
1412 uint i;
1413
1414 /* unswizzle channel */
1415 swizzle = tgsi_util_get_full_src_register_swizzle (
1416 &inst->Src[0],
1417 chan_index);
1418
1419 /* check if the component has not been already tested */
1420 if (uniquemask & (1 << swizzle))
1421 continue;
1422 uniquemask |= 1 << swizzle;
1423
1424 FETCH(&r[0], 0, chan_index);
1425 for (i = 0; i < 4; i++)
1426 if (r[0].f[i] < 0.0f)
1427 kilmask |= 1 << i;
1428 }
1429
1430 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1431 }
1432
1433 /**
1434 * Execute NVIDIA-style KIL which is predicated by a condition code.
1435 * Kill fragment if the condition code is TRUE.
1436 */
1437 static void
1438 exec_kilp(struct tgsi_exec_machine *mach,
1439 const struct tgsi_full_instruction *inst)
1440 {
1441 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1442
1443 /* "unconditional" kil */
1444 kilmask = mach->ExecMask;
1445 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1446 }
1447
1448 static void
1449 emit_vertex(struct tgsi_exec_machine *mach)
1450 {
1451 /* FIXME: check for exec mask correctly
1452 unsigned i;
1453 for (i = 0; i < QUAD_SIZE; ++i) {
1454 if ((mach->ExecMask & (1 << i)))
1455 */
1456 if (mach->ExecMask) {
1457 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1458 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1459 }
1460 }
1461
1462 static void
1463 emit_primitive(struct tgsi_exec_machine *mach)
1464 {
1465 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1466 /* FIXME: check for exec mask correctly
1467 unsigned i;
1468 for (i = 0; i < QUAD_SIZE; ++i) {
1469 if ((mach->ExecMask & (1 << i)))
1470 */
1471 if (mach->ExecMask) {
1472 ++(*prim_count);
1473 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1474 mach->Primitives[*prim_count] = 0;
1475 }
1476 }
1477
1478 /*
1479 * Fetch a four texture samples using STR texture coordinates.
1480 */
1481 static void
1482 fetch_texel( struct tgsi_sampler *sampler,
1483 const union tgsi_exec_channel *s,
1484 const union tgsi_exec_channel *t,
1485 const union tgsi_exec_channel *p,
1486 float lodbias, /* XXX should be float[4] */
1487 union tgsi_exec_channel *r,
1488 union tgsi_exec_channel *g,
1489 union tgsi_exec_channel *b,
1490 union tgsi_exec_channel *a )
1491 {
1492 uint j;
1493 float rgba[NUM_CHANNELS][QUAD_SIZE];
1494
1495 sampler->get_samples(sampler, s->f, t->f, p->f, lodbias, rgba);
1496
1497 for (j = 0; j < 4; j++) {
1498 r->f[j] = rgba[0][j];
1499 g->f[j] = rgba[1][j];
1500 b->f[j] = rgba[2][j];
1501 a->f[j] = rgba[3][j];
1502 }
1503 }
1504
1505
1506 static void
1507 exec_tex(struct tgsi_exec_machine *mach,
1508 const struct tgsi_full_instruction *inst,
1509 boolean biasLod,
1510 boolean projected)
1511 {
1512 const uint unit = inst->Src[1].Register.Index;
1513 union tgsi_exec_channel r[4];
1514 uint chan_index;
1515 float lodBias;
1516
1517 /* debug_printf("Sampler %u unit %u\n", sampler, unit); */
1518
1519 switch (inst->Texture.Texture) {
1520 case TGSI_TEXTURE_1D:
1521 case TGSI_TEXTURE_SHADOW1D:
1522
1523 FETCH(&r[0], 0, CHAN_X);
1524
1525 if (projected) {
1526 FETCH(&r[1], 0, CHAN_W);
1527 micro_div( &r[0], &r[0], &r[1] );
1528 }
1529
1530 if (biasLod) {
1531 FETCH(&r[1], 0, CHAN_W);
1532 lodBias = r[2].f[0];
1533 }
1534 else
1535 lodBias = 0.0;
1536
1537 fetch_texel(mach->Samplers[unit],
1538 &r[0], &ZeroVec, &ZeroVec, lodBias, /* S, T, P, BIAS */
1539 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1540 break;
1541
1542 case TGSI_TEXTURE_2D:
1543 case TGSI_TEXTURE_RECT:
1544 case TGSI_TEXTURE_SHADOW2D:
1545 case TGSI_TEXTURE_SHADOWRECT:
1546
1547 FETCH(&r[0], 0, CHAN_X);
1548 FETCH(&r[1], 0, CHAN_Y);
1549 FETCH(&r[2], 0, CHAN_Z);
1550
1551 if (projected) {
1552 FETCH(&r[3], 0, CHAN_W);
1553 micro_div( &r[0], &r[0], &r[3] );
1554 micro_div( &r[1], &r[1], &r[3] );
1555 micro_div( &r[2], &r[2], &r[3] );
1556 }
1557
1558 if (biasLod) {
1559 FETCH(&r[3], 0, CHAN_W);
1560 lodBias = r[3].f[0];
1561 }
1562 else
1563 lodBias = 0.0;
1564
1565 fetch_texel(mach->Samplers[unit],
1566 &r[0], &r[1], &r[2], lodBias, /* inputs */
1567 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1568 break;
1569
1570 case TGSI_TEXTURE_3D:
1571 case TGSI_TEXTURE_CUBE:
1572
1573 FETCH(&r[0], 0, CHAN_X);
1574 FETCH(&r[1], 0, CHAN_Y);
1575 FETCH(&r[2], 0, CHAN_Z);
1576
1577 if (projected) {
1578 FETCH(&r[3], 0, CHAN_W);
1579 micro_div( &r[0], &r[0], &r[3] );
1580 micro_div( &r[1], &r[1], &r[3] );
1581 micro_div( &r[2], &r[2], &r[3] );
1582 }
1583
1584 if (biasLod) {
1585 FETCH(&r[3], 0, CHAN_W);
1586 lodBias = r[3].f[0];
1587 }
1588 else
1589 lodBias = 0.0;
1590
1591 fetch_texel(mach->Samplers[unit],
1592 &r[0], &r[1], &r[2], lodBias,
1593 &r[0], &r[1], &r[2], &r[3]);
1594 break;
1595
1596 default:
1597 assert (0);
1598 }
1599
1600 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1601 STORE( &r[chan_index], 0, chan_index );
1602 }
1603 }
1604
1605 static void
1606 exec_txd(struct tgsi_exec_machine *mach,
1607 const struct tgsi_full_instruction *inst)
1608 {
1609 const uint unit = inst->Src[3].Register.Index;
1610 union tgsi_exec_channel r[4];
1611 uint chan_index;
1612
1613 /*
1614 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1615 */
1616
1617 switch (inst->Texture.Texture) {
1618 case TGSI_TEXTURE_1D:
1619 case TGSI_TEXTURE_SHADOW1D:
1620
1621 FETCH(&r[0], 0, CHAN_X);
1622
1623 fetch_texel(mach->Samplers[unit],
1624 &r[0], &ZeroVec, &ZeroVec, 0.0f, /* S, T, P, BIAS */
1625 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1626 break;
1627
1628 case TGSI_TEXTURE_2D:
1629 case TGSI_TEXTURE_RECT:
1630 case TGSI_TEXTURE_SHADOW2D:
1631 case TGSI_TEXTURE_SHADOWRECT:
1632
1633 FETCH(&r[0], 0, CHAN_X);
1634 FETCH(&r[1], 0, CHAN_Y);
1635 FETCH(&r[2], 0, CHAN_Z);
1636
1637 fetch_texel(mach->Samplers[unit],
1638 &r[0], &r[1], &r[2], 0.0f, /* inputs */
1639 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1640 break;
1641
1642 case TGSI_TEXTURE_3D:
1643 case TGSI_TEXTURE_CUBE:
1644
1645 FETCH(&r[0], 0, CHAN_X);
1646 FETCH(&r[1], 0, CHAN_Y);
1647 FETCH(&r[2], 0, CHAN_Z);
1648
1649 fetch_texel(mach->Samplers[unit],
1650 &r[0], &r[1], &r[2], 0.0f,
1651 &r[0], &r[1], &r[2], &r[3]);
1652 break;
1653
1654 default:
1655 assert(0);
1656 }
1657
1658 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1659 STORE(&r[chan_index], 0, chan_index);
1660 }
1661 }
1662
1663
1664 /**
1665 * Evaluate a constant-valued coefficient at the position of the
1666 * current quad.
1667 */
1668 static void
1669 eval_constant_coef(
1670 struct tgsi_exec_machine *mach,
1671 unsigned attrib,
1672 unsigned chan )
1673 {
1674 unsigned i;
1675
1676 for( i = 0; i < QUAD_SIZE; i++ ) {
1677 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1678 }
1679 }
1680
1681 /**
1682 * Evaluate a linear-valued coefficient at the position of the
1683 * current quad.
1684 */
1685 static void
1686 eval_linear_coef(
1687 struct tgsi_exec_machine *mach,
1688 unsigned attrib,
1689 unsigned chan )
1690 {
1691 const float x = mach->QuadPos.xyzw[0].f[0];
1692 const float y = mach->QuadPos.xyzw[1].f[0];
1693 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1694 const float dady = mach->InterpCoefs[attrib].dady[chan];
1695 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1696 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1697 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1698 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1699 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1700 }
1701
1702 /**
1703 * Evaluate a perspective-valued coefficient at the position of the
1704 * current quad.
1705 */
1706 static void
1707 eval_perspective_coef(
1708 struct tgsi_exec_machine *mach,
1709 unsigned attrib,
1710 unsigned chan )
1711 {
1712 const float x = mach->QuadPos.xyzw[0].f[0];
1713 const float y = mach->QuadPos.xyzw[1].f[0];
1714 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1715 const float dady = mach->InterpCoefs[attrib].dady[chan];
1716 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1717 const float *w = mach->QuadPos.xyzw[3].f;
1718 /* divide by W here */
1719 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1720 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1721 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1722 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1723 }
1724
1725
1726 typedef void (* eval_coef_func)(
1727 struct tgsi_exec_machine *mach,
1728 unsigned attrib,
1729 unsigned chan );
1730
1731 static void
1732 exec_declaration(struct tgsi_exec_machine *mach,
1733 const struct tgsi_full_declaration *decl)
1734 {
1735 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
1736 if (decl->Declaration.File == TGSI_FILE_INPUT ||
1737 decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1738 uint first, last, mask;
1739
1740 first = decl->Range.First;
1741 last = decl->Range.Last;
1742 mask = decl->Declaration.UsageMask;
1743
1744 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
1745 assert(decl->Semantic.Index == 0);
1746 assert(first == last);
1747 assert(mask == TGSI_WRITEMASK_XYZW);
1748
1749 mach->Inputs[first] = mach->QuadPos;
1750 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1751 uint i;
1752
1753 assert(decl->Semantic.Index == 0);
1754 assert(first == last);
1755
1756 for (i = 0; i < QUAD_SIZE; i++) {
1757 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
1758 }
1759 } else {
1760 eval_coef_func eval;
1761 uint i, j;
1762
1763 switch (decl->Declaration.Interpolate) {
1764 case TGSI_INTERPOLATE_CONSTANT:
1765 eval = eval_constant_coef;
1766 break;
1767
1768 case TGSI_INTERPOLATE_LINEAR:
1769 eval = eval_linear_coef;
1770 break;
1771
1772 case TGSI_INTERPOLATE_PERSPECTIVE:
1773 eval = eval_perspective_coef;
1774 break;
1775
1776 default:
1777 assert(0);
1778 return;
1779 }
1780
1781 for (j = 0; j < NUM_CHANNELS; j++) {
1782 if (mask & (1 << j)) {
1783 for (i = first; i <= last; i++) {
1784 eval(mach, i, j);
1785 }
1786 }
1787 }
1788 }
1789 }
1790 }
1791 }
1792
1793 typedef void (* micro_op)(union tgsi_exec_channel *dst,
1794 const union tgsi_exec_channel *src);
1795
1796 static void
1797 exec_vector_unary(struct tgsi_exec_machine *mach,
1798 const struct tgsi_full_instruction *inst,
1799 micro_op op)
1800 {
1801 unsigned int chan;
1802 struct tgsi_exec_vector dst;
1803
1804 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1805 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1806 union tgsi_exec_channel src;
1807
1808 fetch_source(mach, &src, &inst->Src[0], chan);
1809 op(&dst.xyzw[chan], &src);
1810 }
1811 }
1812 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1813 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1814 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan);
1815 }
1816 }
1817 }
1818
1819 static void
1820 exec_vector_binary(struct tgsi_exec_machine *mach,
1821 const struct tgsi_full_instruction *inst,
1822 micro_op op)
1823 {
1824 unsigned int chan;
1825 struct tgsi_exec_vector dst;
1826
1827 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1828 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1829 union tgsi_exec_channel src[2];
1830
1831 fetch_source(mach, &src[0], &inst->Src[0], chan);
1832 fetch_source(mach, &src[1], &inst->Src[1], chan);
1833 op(&dst.xyzw[chan], src);
1834 }
1835 }
1836 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1837 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1838 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan);
1839 }
1840 }
1841 }
1842
1843 static void
1844 exec_vector_trinary(struct tgsi_exec_machine *mach,
1845 const struct tgsi_full_instruction *inst,
1846 micro_op op)
1847 {
1848 unsigned int chan;
1849 struct tgsi_exec_vector dst;
1850
1851 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1852 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1853 union tgsi_exec_channel src[3];
1854
1855 fetch_source(mach, &src[0], &inst->Src[0], chan);
1856 fetch_source(mach, &src[1], &inst->Src[1], chan);
1857 fetch_source(mach, &src[2], &inst->Src[2], chan);
1858 op(&dst.xyzw[chan], src);
1859 }
1860 }
1861 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1862 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1863 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan);
1864 }
1865 }
1866 }
1867
1868 static void
1869 micro_f2i(union tgsi_exec_channel *dst,
1870 const union tgsi_exec_channel *src)
1871 {
1872 dst->i[0] = (int)src->f[0];
1873 dst->i[1] = (int)src->f[1];
1874 dst->i[2] = (int)src->f[2];
1875 dst->i[3] = (int)src->f[3];
1876 }
1877
1878 static void
1879 micro_idiv(union tgsi_exec_channel *dst,
1880 const union tgsi_exec_channel *src)
1881 {
1882 dst->i[0] = src[0].i[0] / src[1].i[0];
1883 dst->i[1] = src[0].i[1] / src[1].i[1];
1884 dst->i[2] = src[0].i[2] / src[1].i[2];
1885 dst->i[3] = src[0].i[3] / src[1].i[3];
1886 }
1887
1888 static void
1889 micro_imax(union tgsi_exec_channel *dst,
1890 const union tgsi_exec_channel *src)
1891 {
1892 dst->i[0] = src[0].i[0] > src[1].i[0] ? src[0].i[0] : src[1].i[0];
1893 dst->i[1] = src[0].i[1] > src[1].i[1] ? src[0].i[1] : src[1].i[1];
1894 dst->i[2] = src[0].i[2] > src[1].i[2] ? src[0].i[2] : src[1].i[2];
1895 dst->i[3] = src[0].i[3] > src[1].i[3] ? src[0].i[3] : src[1].i[3];
1896 }
1897
1898 static void
1899 micro_imin(union tgsi_exec_channel *dst,
1900 const union tgsi_exec_channel *src)
1901 {
1902 dst->i[0] = src[0].i[0] < src[1].i[0] ? src[0].i[0] : src[1].i[0];
1903 dst->i[1] = src[0].i[1] < src[1].i[1] ? src[0].i[1] : src[1].i[1];
1904 dst->i[2] = src[0].i[2] < src[1].i[2] ? src[0].i[2] : src[1].i[2];
1905 dst->i[3] = src[0].i[3] < src[1].i[3] ? src[0].i[3] : src[1].i[3];
1906 }
1907
1908 static void
1909 micro_ineg(union tgsi_exec_channel *dst,
1910 const union tgsi_exec_channel *src)
1911 {
1912 dst->i[0] = -src->i[0];
1913 dst->i[1] = -src->i[1];
1914 dst->i[2] = -src->i[2];
1915 dst->i[3] = -src->i[3];
1916 }
1917
1918 static void
1919 micro_isge(union tgsi_exec_channel *dst,
1920 const union tgsi_exec_channel *src)
1921 {
1922 dst->i[0] = src[0].i[0] >= src[1].i[0] ? -1 : 0;
1923 dst->i[1] = src[0].i[1] >= src[1].i[1] ? -1 : 0;
1924 dst->i[2] = src[0].i[2] >= src[1].i[2] ? -1 : 0;
1925 dst->i[3] = src[0].i[3] >= src[1].i[3] ? -1 : 0;
1926 }
1927
1928 static void
1929 micro_ishr(union tgsi_exec_channel *dst,
1930 const union tgsi_exec_channel *src)
1931 {
1932 dst->i[0] = src[0].i[0] >> src[1].i[0];
1933 dst->i[1] = src[0].i[1] >> src[1].i[1];
1934 dst->i[2] = src[0].i[2] >> src[1].i[2];
1935 dst->i[3] = src[0].i[3] >> src[1].i[3];
1936 }
1937
1938 static void
1939 micro_islt(union tgsi_exec_channel *dst,
1940 const union tgsi_exec_channel *src)
1941 {
1942 dst->i[0] = src[0].i[0] < src[1].i[0] ? -1 : 0;
1943 dst->i[1] = src[0].i[1] < src[1].i[1] ? -1 : 0;
1944 dst->i[2] = src[0].i[2] < src[1].i[2] ? -1 : 0;
1945 dst->i[3] = src[0].i[3] < src[1].i[3] ? -1 : 0;
1946 }
1947
1948 static void
1949 micro_f2u(union tgsi_exec_channel *dst,
1950 const union tgsi_exec_channel *src)
1951 {
1952 dst->u[0] = (uint)src->f[0];
1953 dst->u[1] = (uint)src->f[1];
1954 dst->u[2] = (uint)src->f[2];
1955 dst->u[3] = (uint)src->f[3];
1956 }
1957
1958 static void
1959 micro_u2f(union tgsi_exec_channel *dst,
1960 const union tgsi_exec_channel *src)
1961 {
1962 dst->f[0] = (float)src->u[0];
1963 dst->f[1] = (float)src->u[1];
1964 dst->f[2] = (float)src->u[2];
1965 dst->f[3] = (float)src->u[3];
1966 }
1967
1968 static void
1969 micro_uadd(union tgsi_exec_channel *dst,
1970 const union tgsi_exec_channel *src)
1971 {
1972 dst->u[0] = src[0].u[0] + src[1].u[0];
1973 dst->u[1] = src[0].u[1] + src[1].u[1];
1974 dst->u[2] = src[0].u[2] + src[1].u[2];
1975 dst->u[3] = src[0].u[3] + src[1].u[3];
1976 }
1977
1978 static void
1979 micro_udiv(union tgsi_exec_channel *dst,
1980 const union tgsi_exec_channel *src)
1981 {
1982 dst->u[0] = src[0].u[0] / src[1].u[0];
1983 dst->u[1] = src[0].u[1] / src[1].u[1];
1984 dst->u[2] = src[0].u[2] / src[1].u[2];
1985 dst->u[3] = src[0].u[3] / src[1].u[3];
1986 }
1987
1988 static void
1989 micro_umad(union tgsi_exec_channel *dst,
1990 const union tgsi_exec_channel *src)
1991 {
1992 dst->u[0] = src[0].u[0] * src[1].u[0] + src[2].u[0];
1993 dst->u[1] = src[0].u[1] * src[1].u[1] + src[2].u[1];
1994 dst->u[2] = src[0].u[2] * src[1].u[2] + src[2].u[2];
1995 dst->u[3] = src[0].u[3] * src[1].u[3] + src[2].u[3];
1996 }
1997
1998 static void
1999 micro_umax(union tgsi_exec_channel *dst,
2000 const union tgsi_exec_channel *src)
2001 {
2002 dst->u[0] = src[0].u[0] > src[1].u[0] ? src[0].u[0] : src[1].u[0];
2003 dst->u[1] = src[0].u[1] > src[1].u[1] ? src[0].u[1] : src[1].u[1];
2004 dst->u[2] = src[0].u[2] > src[1].u[2] ? src[0].u[2] : src[1].u[2];
2005 dst->u[3] = src[0].u[3] > src[1].u[3] ? src[0].u[3] : src[1].u[3];
2006 }
2007
2008 static void
2009 micro_umin(union tgsi_exec_channel *dst,
2010 const union tgsi_exec_channel *src)
2011 {
2012 dst->u[0] = src[0].u[0] < src[1].u[0] ? src[0].u[0] : src[1].u[0];
2013 dst->u[1] = src[0].u[1] < src[1].u[1] ? src[0].u[1] : src[1].u[1];
2014 dst->u[2] = src[0].u[2] < src[1].u[2] ? src[0].u[2] : src[1].u[2];
2015 dst->u[3] = src[0].u[3] < src[1].u[3] ? src[0].u[3] : src[1].u[3];
2016 }
2017
2018 static void
2019 micro_umul(union tgsi_exec_channel *dst,
2020 const union tgsi_exec_channel *src)
2021 {
2022 dst->u[0] = src[0].u[0] * src[1].u[0];
2023 dst->u[1] = src[0].u[1] * src[1].u[1];
2024 dst->u[2] = src[0].u[2] * src[1].u[2];
2025 dst->u[3] = src[0].u[3] * src[1].u[3];
2026 }
2027
2028 static void
2029 micro_useq(union tgsi_exec_channel *dst,
2030 const union tgsi_exec_channel *src)
2031 {
2032 dst->u[0] = src[0].u[0] == src[1].u[0] ? ~0 : 0;
2033 dst->u[1] = src[0].u[1] == src[1].u[1] ? ~0 : 0;
2034 dst->u[2] = src[0].u[2] == src[1].u[2] ? ~0 : 0;
2035 dst->u[3] = src[0].u[3] == src[1].u[3] ? ~0 : 0;
2036 }
2037
2038 static void
2039 micro_usge(union tgsi_exec_channel *dst,
2040 const union tgsi_exec_channel *src)
2041 {
2042 dst->u[0] = src[0].u[0] >= src[1].u[0] ? ~0 : 0;
2043 dst->u[1] = src[0].u[1] >= src[1].u[1] ? ~0 : 0;
2044 dst->u[2] = src[0].u[2] >= src[1].u[2] ? ~0 : 0;
2045 dst->u[3] = src[0].u[3] >= src[1].u[3] ? ~0 : 0;
2046 }
2047
2048 static void
2049 micro_ushr(union tgsi_exec_channel *dst,
2050 const union tgsi_exec_channel *src)
2051 {
2052 dst->u[0] = src[0].u[0] >> src[1].u[0];
2053 dst->u[1] = src[0].u[1] >> src[1].u[1];
2054 dst->u[2] = src[0].u[2] >> src[1].u[2];
2055 dst->u[3] = src[0].u[3] >> src[1].u[3];
2056 }
2057
2058 static void
2059 micro_uslt(union tgsi_exec_channel *dst,
2060 const union tgsi_exec_channel *src)
2061 {
2062 dst->u[0] = src[0].u[0] < src[1].u[0] ? ~0 : 0;
2063 dst->u[1] = src[0].u[1] < src[1].u[1] ? ~0 : 0;
2064 dst->u[2] = src[0].u[2] < src[1].u[2] ? ~0 : 0;
2065 dst->u[3] = src[0].u[3] < src[1].u[3] ? ~0 : 0;
2066 }
2067
2068 static void
2069 micro_usne(union tgsi_exec_channel *dst,
2070 const union tgsi_exec_channel *src)
2071 {
2072 dst->u[0] = src[0].u[0] != src[1].u[0] ? ~0 : 0;
2073 dst->u[1] = src[0].u[1] != src[1].u[1] ? ~0 : 0;
2074 dst->u[2] = src[0].u[2] != src[1].u[2] ? ~0 : 0;
2075 dst->u[3] = src[0].u[3] != src[1].u[3] ? ~0 : 0;
2076 }
2077
2078 static void
2079 exec_instruction(
2080 struct tgsi_exec_machine *mach,
2081 const struct tgsi_full_instruction *inst,
2082 int *pc )
2083 {
2084 uint chan_index;
2085 union tgsi_exec_channel r[10];
2086 union tgsi_exec_channel d[8];
2087
2088 (*pc)++;
2089
2090 switch (inst->Instruction.Opcode) {
2091 case TGSI_OPCODE_ARL:
2092 case TGSI_OPCODE_FLR:
2093 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2094 FETCH( &r[0], 0, chan_index );
2095 micro_flr(&d[chan_index], &r[0]);
2096 }
2097 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2098 STORE(&d[chan_index], 0, chan_index);
2099 }
2100 break;
2101
2102 case TGSI_OPCODE_MOV:
2103 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2104 FETCH(&d[chan_index], 0, chan_index);
2105 }
2106 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2107 STORE(&d[chan_index], 0, chan_index);
2108 }
2109 break;
2110
2111 case TGSI_OPCODE_LIT:
2112 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2113 FETCH( &r[0], 0, CHAN_X );
2114 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2115 micro_max(&d[CHAN_Y], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2116 }
2117
2118 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2119 FETCH( &r[1], 0, CHAN_Y );
2120 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2121
2122 FETCH( &r[2], 0, CHAN_W );
2123 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
2124 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
2125 micro_pow( &r[1], &r[1], &r[2] );
2126 micro_lt(&d[CHAN_Z], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2127 }
2128
2129 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2130 STORE(&d[CHAN_Y], 0, CHAN_Y);
2131 }
2132 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2133 STORE(&d[CHAN_Z], 0, CHAN_Z);
2134 }
2135 }
2136 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2137 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
2138 }
2139 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2140 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2141 }
2142 break;
2143
2144 case TGSI_OPCODE_RCP:
2145 /* TGSI_OPCODE_RECIP */
2146 FETCH( &r[0], 0, CHAN_X );
2147 micro_div( &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0] );
2148 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2149 STORE( &r[0], 0, chan_index );
2150 }
2151 break;
2152
2153 case TGSI_OPCODE_RSQ:
2154 /* TGSI_OPCODE_RECIPSQRT */
2155 FETCH( &r[0], 0, CHAN_X );
2156 micro_abs( &r[0], &r[0] );
2157 micro_sqrt( &r[0], &r[0] );
2158 micro_div( &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0] );
2159 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2160 STORE( &r[0], 0, chan_index );
2161 }
2162 break;
2163
2164 case TGSI_OPCODE_EXP:
2165 FETCH( &r[0], 0, CHAN_X );
2166 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
2167 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2168 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
2169 STORE( &r[2], 0, CHAN_X ); /* store r2 */
2170 }
2171 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2172 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
2173 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
2174 }
2175 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2176 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
2177 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
2178 }
2179 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2180 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2181 }
2182 break;
2183
2184 case TGSI_OPCODE_LOG:
2185 FETCH( &r[0], 0, CHAN_X );
2186 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
2187 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
2188 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
2189 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2190 STORE( &r[0], 0, CHAN_X );
2191 }
2192 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2193 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
2194 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
2195 STORE( &r[0], 0, CHAN_Y );
2196 }
2197 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2198 STORE( &r[1], 0, CHAN_Z );
2199 }
2200 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2201 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2202 }
2203 break;
2204
2205 case TGSI_OPCODE_MUL:
2206 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2207 FETCH(&r[0], 0, chan_index);
2208 FETCH(&r[1], 1, chan_index);
2209 micro_mul(&d[chan_index], &r[0], &r[1]);
2210 }
2211 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2212 STORE(&d[chan_index], 0, chan_index);
2213 }
2214 break;
2215
2216 case TGSI_OPCODE_ADD:
2217 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2218 FETCH( &r[0], 0, chan_index );
2219 FETCH( &r[1], 1, chan_index );
2220 micro_add(&d[chan_index], &r[0], &r[1]);
2221 }
2222 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2223 STORE(&d[chan_index], 0, chan_index);
2224 }
2225 break;
2226
2227 case TGSI_OPCODE_DP3:
2228 /* TGSI_OPCODE_DOT3 */
2229 FETCH( &r[0], 0, CHAN_X );
2230 FETCH( &r[1], 1, CHAN_X );
2231 micro_mul( &r[0], &r[0], &r[1] );
2232
2233 FETCH( &r[1], 0, CHAN_Y );
2234 FETCH( &r[2], 1, CHAN_Y );
2235 micro_mul( &r[1], &r[1], &r[2] );
2236 micro_add( &r[0], &r[0], &r[1] );
2237
2238 FETCH( &r[1], 0, CHAN_Z );
2239 FETCH( &r[2], 1, CHAN_Z );
2240 micro_mul( &r[1], &r[1], &r[2] );
2241 micro_add( &r[0], &r[0], &r[1] );
2242
2243 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2244 STORE( &r[0], 0, chan_index );
2245 }
2246 break;
2247
2248 case TGSI_OPCODE_DP4:
2249 /* TGSI_OPCODE_DOT4 */
2250 FETCH(&r[0], 0, CHAN_X);
2251 FETCH(&r[1], 1, CHAN_X);
2252
2253 micro_mul( &r[0], &r[0], &r[1] );
2254
2255 FETCH(&r[1], 0, CHAN_Y);
2256 FETCH(&r[2], 1, CHAN_Y);
2257
2258 micro_mul( &r[1], &r[1], &r[2] );
2259 micro_add( &r[0], &r[0], &r[1] );
2260
2261 FETCH(&r[1], 0, CHAN_Z);
2262 FETCH(&r[2], 1, CHAN_Z);
2263
2264 micro_mul( &r[1], &r[1], &r[2] );
2265 micro_add( &r[0], &r[0], &r[1] );
2266
2267 FETCH(&r[1], 0, CHAN_W);
2268 FETCH(&r[2], 1, CHAN_W);
2269
2270 micro_mul( &r[1], &r[1], &r[2] );
2271 micro_add( &r[0], &r[0], &r[1] );
2272
2273 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2274 STORE( &r[0], 0, chan_index );
2275 }
2276 break;
2277
2278 case TGSI_OPCODE_DST:
2279 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2280 FETCH( &r[0], 0, CHAN_Y );
2281 FETCH( &r[1], 1, CHAN_Y);
2282 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2283 }
2284 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2285 FETCH(&d[CHAN_Z], 0, CHAN_Z);
2286 }
2287 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2288 FETCH(&d[CHAN_W], 1, CHAN_W);
2289 }
2290
2291 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2292 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X);
2293 }
2294 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2295 STORE(&d[CHAN_Y], 0, CHAN_Y);
2296 }
2297 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2298 STORE(&d[CHAN_Z], 0, CHAN_Z);
2299 }
2300 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2301 STORE(&d[CHAN_W], 0, CHAN_W);
2302 }
2303 break;
2304
2305 case TGSI_OPCODE_MIN:
2306 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2307 FETCH(&r[0], 0, chan_index);
2308 FETCH(&r[1], 1, chan_index);
2309
2310 /* XXX use micro_min()?? */
2311 micro_lt(&d[chan_index], &r[0], &r[1], &r[0], &r[1]);
2312 }
2313 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2314 STORE(&d[chan_index], 0, chan_index);
2315 }
2316 break;
2317
2318 case TGSI_OPCODE_MAX:
2319 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2320 FETCH(&r[0], 0, chan_index);
2321 FETCH(&r[1], 1, chan_index);
2322
2323 /* XXX use micro_max()?? */
2324 micro_lt(&d[chan_index], &r[0], &r[1], &r[1], &r[0] );
2325 }
2326 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2327 STORE(&d[chan_index], 0, chan_index);
2328 }
2329 break;
2330
2331 case TGSI_OPCODE_SLT:
2332 /* TGSI_OPCODE_SETLT */
2333 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2334 FETCH( &r[0], 0, chan_index );
2335 FETCH( &r[1], 1, chan_index );
2336 micro_lt(&d[chan_index], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2337 }
2338 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2339 STORE(&d[chan_index], 0, chan_index);
2340 }
2341 break;
2342
2343 case TGSI_OPCODE_SGE:
2344 /* TGSI_OPCODE_SETGE */
2345 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2346 FETCH( &r[0], 0, chan_index );
2347 FETCH( &r[1], 1, chan_index );
2348 micro_le(&d[chan_index], &r[1], &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2349 }
2350 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2351 STORE(&d[chan_index], 0, chan_index);
2352 }
2353 break;
2354
2355 case TGSI_OPCODE_MAD:
2356 /* TGSI_OPCODE_MADD */
2357 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2358 FETCH( &r[0], 0, chan_index );
2359 FETCH( &r[1], 1, chan_index );
2360 micro_mul( &r[0], &r[0], &r[1] );
2361 FETCH( &r[1], 2, chan_index );
2362 micro_add(&d[chan_index], &r[0], &r[1]);
2363 }
2364 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2365 STORE(&d[chan_index], 0, chan_index);
2366 }
2367 break;
2368
2369 case TGSI_OPCODE_SUB:
2370 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2371 FETCH(&r[0], 0, chan_index);
2372 FETCH(&r[1], 1, chan_index);
2373 micro_sub(&d[chan_index], &r[0], &r[1]);
2374 }
2375 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2376 STORE(&d[chan_index], 0, chan_index);
2377 }
2378 break;
2379
2380 case TGSI_OPCODE_LRP:
2381 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2382 FETCH(&r[0], 0, chan_index);
2383 FETCH(&r[1], 1, chan_index);
2384 FETCH(&r[2], 2, chan_index);
2385 micro_sub( &r[1], &r[1], &r[2] );
2386 micro_mul( &r[0], &r[0], &r[1] );
2387 micro_add(&d[chan_index], &r[0], &r[2]);
2388 }
2389 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2390 STORE(&d[chan_index], 0, chan_index);
2391 }
2392 break;
2393
2394 case TGSI_OPCODE_CND:
2395 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2396 FETCH(&r[0], 0, chan_index);
2397 FETCH(&r[1], 1, chan_index);
2398 FETCH(&r[2], 2, chan_index);
2399 micro_lt(&d[chan_index], &mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C], &r[2], &r[0], &r[1]);
2400 }
2401 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2402 STORE(&d[chan_index], 0, chan_index);
2403 }
2404 break;
2405
2406 case TGSI_OPCODE_DP2A:
2407 FETCH( &r[0], 0, CHAN_X );
2408 FETCH( &r[1], 1, CHAN_X );
2409 micro_mul( &r[0], &r[0], &r[1] );
2410
2411 FETCH( &r[1], 0, CHAN_Y );
2412 FETCH( &r[2], 1, CHAN_Y );
2413 micro_mul( &r[1], &r[1], &r[2] );
2414 micro_add( &r[0], &r[0], &r[1] );
2415
2416 FETCH( &r[2], 2, CHAN_X );
2417 micro_add( &r[0], &r[0], &r[2] );
2418
2419 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2420 STORE( &r[0], 0, chan_index );
2421 }
2422 break;
2423
2424 case TGSI_OPCODE_FRC:
2425 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2426 FETCH( &r[0], 0, chan_index );
2427 micro_frc(&d[chan_index], &r[0]);
2428 }
2429 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2430 STORE(&d[chan_index], 0, chan_index);
2431 }
2432 break;
2433
2434 case TGSI_OPCODE_CLAMP:
2435 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2436 FETCH(&r[0], 0, chan_index);
2437 FETCH(&r[1], 1, chan_index);
2438 micro_max(&r[0], &r[0], &r[1]);
2439 FETCH(&r[1], 2, chan_index);
2440 micro_min(&d[chan_index], &r[0], &r[1]);
2441 }
2442 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2443 STORE(&d[chan_index], 0, chan_index);
2444 }
2445 break;
2446
2447 case TGSI_OPCODE_ROUND:
2448 case TGSI_OPCODE_ARR:
2449 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2450 FETCH( &r[0], 0, chan_index );
2451 micro_rnd(&d[chan_index], &r[0]);
2452 }
2453 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2454 STORE(&d[chan_index], 0, chan_index);
2455 }
2456 break;
2457
2458 case TGSI_OPCODE_EX2:
2459 FETCH(&r[0], 0, CHAN_X);
2460
2461 micro_exp2( &r[0], &r[0] );
2462
2463 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2464 STORE( &r[0], 0, chan_index );
2465 }
2466 break;
2467
2468 case TGSI_OPCODE_LG2:
2469 FETCH( &r[0], 0, CHAN_X );
2470 micro_lg2( &r[0], &r[0] );
2471 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2472 STORE( &r[0], 0, chan_index );
2473 }
2474 break;
2475
2476 case TGSI_OPCODE_POW:
2477 FETCH(&r[0], 0, CHAN_X);
2478 FETCH(&r[1], 1, CHAN_X);
2479
2480 micro_pow( &r[0], &r[0], &r[1] );
2481
2482 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2483 STORE( &r[0], 0, chan_index );
2484 }
2485 break;
2486
2487 case TGSI_OPCODE_XPD:
2488 FETCH(&r[0], 0, CHAN_Y);
2489 FETCH(&r[1], 1, CHAN_Z);
2490
2491 micro_mul( &r[2], &r[0], &r[1] );
2492
2493 FETCH(&r[3], 0, CHAN_Z);
2494 FETCH(&r[4], 1, CHAN_Y);
2495
2496 micro_mul( &r[5], &r[3], &r[4] );
2497 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2498
2499 FETCH(&r[2], 1, CHAN_X);
2500
2501 micro_mul( &r[3], &r[3], &r[2] );
2502
2503 FETCH(&r[5], 0, CHAN_X);
2504
2505 micro_mul( &r[1], &r[1], &r[5] );
2506 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2507
2508 micro_mul( &r[5], &r[5], &r[4] );
2509 micro_mul( &r[0], &r[0], &r[2] );
2510 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2511
2512 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2513 STORE(&d[CHAN_X], 0, CHAN_X);
2514 }
2515 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2516 STORE(&d[CHAN_Y], 0, CHAN_Y);
2517 }
2518 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2519 STORE(&d[CHAN_Z], 0, CHAN_Z);
2520 }
2521 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2522 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2523 }
2524 break;
2525
2526 case TGSI_OPCODE_ABS:
2527 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2528 FETCH(&r[0], 0, chan_index);
2529 micro_abs(&d[chan_index], &r[0]);
2530 }
2531 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2532 STORE(&d[chan_index], 0, chan_index);
2533 }
2534 break;
2535
2536 case TGSI_OPCODE_RCC:
2537 FETCH(&r[0], 0, CHAN_X);
2538 micro_div(&r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0]);
2539 micro_float_clamp(&r[0], &r[0]);
2540 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2541 STORE(&r[0], 0, chan_index);
2542 }
2543 break;
2544
2545 case TGSI_OPCODE_DPH:
2546 FETCH(&r[0], 0, CHAN_X);
2547 FETCH(&r[1], 1, CHAN_X);
2548
2549 micro_mul( &r[0], &r[0], &r[1] );
2550
2551 FETCH(&r[1], 0, CHAN_Y);
2552 FETCH(&r[2], 1, CHAN_Y);
2553
2554 micro_mul( &r[1], &r[1], &r[2] );
2555 micro_add( &r[0], &r[0], &r[1] );
2556
2557 FETCH(&r[1], 0, CHAN_Z);
2558 FETCH(&r[2], 1, CHAN_Z);
2559
2560 micro_mul( &r[1], &r[1], &r[2] );
2561 micro_add( &r[0], &r[0], &r[1] );
2562
2563 FETCH(&r[1], 1, CHAN_W);
2564
2565 micro_add( &r[0], &r[0], &r[1] );
2566
2567 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2568 STORE( &r[0], 0, chan_index );
2569 }
2570 break;
2571
2572 case TGSI_OPCODE_COS:
2573 FETCH(&r[0], 0, CHAN_X);
2574
2575 micro_cos( &r[0], &r[0] );
2576
2577 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2578 STORE( &r[0], 0, chan_index );
2579 }
2580 break;
2581
2582 case TGSI_OPCODE_DDX:
2583 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2584 FETCH( &r[0], 0, chan_index );
2585 micro_ddx(&d[chan_index], &r[0]);
2586 }
2587 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2588 STORE(&d[chan_index], 0, chan_index);
2589 }
2590 break;
2591
2592 case TGSI_OPCODE_DDY:
2593 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2594 FETCH( &r[0], 0, chan_index );
2595 micro_ddy(&d[chan_index], &r[0]);
2596 }
2597 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2598 STORE(&d[chan_index], 0, chan_index);
2599 }
2600 break;
2601
2602 case TGSI_OPCODE_KILP:
2603 exec_kilp (mach, inst);
2604 break;
2605
2606 case TGSI_OPCODE_KIL:
2607 exec_kil (mach, inst);
2608 break;
2609
2610 case TGSI_OPCODE_PK2H:
2611 assert (0);
2612 break;
2613
2614 case TGSI_OPCODE_PK2US:
2615 assert (0);
2616 break;
2617
2618 case TGSI_OPCODE_PK4B:
2619 assert (0);
2620 break;
2621
2622 case TGSI_OPCODE_PK4UB:
2623 assert (0);
2624 break;
2625
2626 case TGSI_OPCODE_RFL:
2627 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2628 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2629 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2630 /* r0 = dp3(src0, src0) */
2631 FETCH(&r[2], 0, CHAN_X);
2632 micro_mul(&r[0], &r[2], &r[2]);
2633 FETCH(&r[4], 0, CHAN_Y);
2634 micro_mul(&r[8], &r[4], &r[4]);
2635 micro_add(&r[0], &r[0], &r[8]);
2636 FETCH(&r[6], 0, CHAN_Z);
2637 micro_mul(&r[8], &r[6], &r[6]);
2638 micro_add(&r[0], &r[0], &r[8]);
2639
2640 /* r1 = dp3(src0, src1) */
2641 FETCH(&r[3], 1, CHAN_X);
2642 micro_mul(&r[1], &r[2], &r[3]);
2643 FETCH(&r[5], 1, CHAN_Y);
2644 micro_mul(&r[8], &r[4], &r[5]);
2645 micro_add(&r[1], &r[1], &r[8]);
2646 FETCH(&r[7], 1, CHAN_Z);
2647 micro_mul(&r[8], &r[6], &r[7]);
2648 micro_add(&r[1], &r[1], &r[8]);
2649
2650 /* r1 = 2 * r1 / r0 */
2651 micro_add(&r[1], &r[1], &r[1]);
2652 micro_div(&r[1], &r[1], &r[0]);
2653
2654 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2655 micro_mul(&r[2], &r[2], &r[1]);
2656 micro_sub(&r[2], &r[2], &r[3]);
2657 STORE(&r[2], 0, CHAN_X);
2658 }
2659 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2660 micro_mul(&r[4], &r[4], &r[1]);
2661 micro_sub(&r[4], &r[4], &r[5]);
2662 STORE(&r[4], 0, CHAN_Y);
2663 }
2664 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2665 micro_mul(&r[6], &r[6], &r[1]);
2666 micro_sub(&r[6], &r[6], &r[7]);
2667 STORE(&r[6], 0, CHAN_Z);
2668 }
2669 }
2670 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2671 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
2672 }
2673 break;
2674
2675 case TGSI_OPCODE_SEQ:
2676 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2677 FETCH( &r[0], 0, chan_index );
2678 FETCH( &r[1], 1, chan_index );
2679 micro_eq(&d[chan_index], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2680 }
2681 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2682 STORE(&d[chan_index], 0, chan_index);
2683 }
2684 break;
2685
2686 case TGSI_OPCODE_SFL:
2687 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2688 STORE(&mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, chan_index);
2689 }
2690 break;
2691
2692 case TGSI_OPCODE_SGT:
2693 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2694 FETCH( &r[0], 0, chan_index );
2695 FETCH( &r[1], 1, chan_index );
2696 micro_le(&d[chan_index], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C]);
2697 }
2698 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2699 STORE(&d[chan_index], 0, chan_index);
2700 }
2701 break;
2702
2703 case TGSI_OPCODE_SIN:
2704 FETCH( &r[0], 0, CHAN_X );
2705 micro_sin( &r[0], &r[0] );
2706 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2707 STORE( &r[0], 0, chan_index );
2708 }
2709 break;
2710
2711 case TGSI_OPCODE_SLE:
2712 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2713 FETCH( &r[0], 0, chan_index );
2714 FETCH( &r[1], 1, chan_index );
2715 micro_le(&d[chan_index], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2716 }
2717 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2718 STORE(&d[chan_index], 0, chan_index);
2719 }
2720 break;
2721
2722 case TGSI_OPCODE_SNE:
2723 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2724 FETCH( &r[0], 0, chan_index );
2725 FETCH( &r[1], 1, chan_index );
2726 micro_eq(&d[chan_index], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C]);
2727 }
2728 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2729 STORE(&d[chan_index], 0, chan_index);
2730 }
2731 break;
2732
2733 case TGSI_OPCODE_STR:
2734 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2735 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, chan_index);
2736 }
2737 break;
2738
2739 case TGSI_OPCODE_TEX:
2740 /* simple texture lookup */
2741 /* src[0] = texcoord */
2742 /* src[1] = sampler unit */
2743 exec_tex(mach, inst, FALSE, FALSE);
2744 break;
2745
2746 case TGSI_OPCODE_TXB:
2747 /* Texture lookup with lod bias */
2748 /* src[0] = texcoord (src[0].w = LOD bias) */
2749 /* src[1] = sampler unit */
2750 exec_tex(mach, inst, TRUE, FALSE);
2751 break;
2752
2753 case TGSI_OPCODE_TXD:
2754 /* Texture lookup with explict partial derivatives */
2755 /* src[0] = texcoord */
2756 /* src[1] = d[strq]/dx */
2757 /* src[2] = d[strq]/dy */
2758 /* src[3] = sampler unit */
2759 exec_txd(mach, inst);
2760 break;
2761
2762 case TGSI_OPCODE_TXL:
2763 /* Texture lookup with explit LOD */
2764 /* src[0] = texcoord (src[0].w = LOD) */
2765 /* src[1] = sampler unit */
2766 exec_tex(mach, inst, TRUE, FALSE);
2767 break;
2768
2769 case TGSI_OPCODE_TXP:
2770 /* Texture lookup with projection */
2771 /* src[0] = texcoord (src[0].w = projection) */
2772 /* src[1] = sampler unit */
2773 exec_tex(mach, inst, FALSE, TRUE);
2774 break;
2775
2776 case TGSI_OPCODE_UP2H:
2777 assert (0);
2778 break;
2779
2780 case TGSI_OPCODE_UP2US:
2781 assert (0);
2782 break;
2783
2784 case TGSI_OPCODE_UP4B:
2785 assert (0);
2786 break;
2787
2788 case TGSI_OPCODE_UP4UB:
2789 assert (0);
2790 break;
2791
2792 case TGSI_OPCODE_X2D:
2793 FETCH(&r[0], 1, CHAN_X);
2794 FETCH(&r[1], 1, CHAN_Y);
2795 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2796 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2797 FETCH(&r[2], 2, CHAN_X);
2798 micro_mul(&r[2], &r[2], &r[0]);
2799 FETCH(&r[3], 2, CHAN_Y);
2800 micro_mul(&r[3], &r[3], &r[1]);
2801 micro_add(&r[2], &r[2], &r[3]);
2802 FETCH(&r[3], 0, CHAN_X);
2803 micro_add(&d[CHAN_X], &r[2], &r[3]);
2804
2805 }
2806 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2807 IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2808 FETCH(&r[2], 2, CHAN_Z);
2809 micro_mul(&r[2], &r[2], &r[0]);
2810 FETCH(&r[3], 2, CHAN_W);
2811 micro_mul(&r[3], &r[3], &r[1]);
2812 micro_add(&r[2], &r[2], &r[3]);
2813 FETCH(&r[3], 0, CHAN_Y);
2814 micro_add(&d[CHAN_Y], &r[2], &r[3]);
2815
2816 }
2817 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2818 STORE(&d[CHAN_X], 0, CHAN_X);
2819 }
2820 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2821 STORE(&d[CHAN_Y], 0, CHAN_Y);
2822 }
2823 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2824 STORE(&d[CHAN_X], 0, CHAN_Z);
2825 }
2826 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2827 STORE(&d[CHAN_Y], 0, CHAN_W);
2828 }
2829 break;
2830
2831 case TGSI_OPCODE_ARA:
2832 assert (0);
2833 break;
2834
2835 case TGSI_OPCODE_BRA:
2836 assert (0);
2837 break;
2838
2839 case TGSI_OPCODE_CAL:
2840 /* skip the call if no execution channels are enabled */
2841 if (mach->ExecMask) {
2842 /* do the call */
2843
2844 /* First, record the depths of the execution stacks.
2845 * This is important for deeply nested/looped return statements.
2846 * We have to unwind the stacks by the correct amount. For a
2847 * real code generator, we could determine the number of entries
2848 * to pop off each stack with simple static analysis and avoid
2849 * implementing this data structure at run time.
2850 */
2851 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
2852 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
2853 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
2854 /* note that PC was already incremented above */
2855 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
2856
2857 mach->CallStackTop++;
2858
2859 /* Second, push the Cond, Loop, Cont, Func stacks */
2860 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
2861 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
2862 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2863 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
2864 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2865 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
2866 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
2867 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
2868
2869 /* Finally, jump to the subroutine */
2870 *pc = inst->Label.Label;
2871 }
2872 break;
2873
2874 case TGSI_OPCODE_RET:
2875 mach->FuncMask &= ~mach->ExecMask;
2876 UPDATE_EXEC_MASK(mach);
2877
2878 if (mach->FuncMask == 0x0) {
2879 /* really return now (otherwise, keep executing */
2880
2881 if (mach->CallStackTop == 0) {
2882 /* returning from main() */
2883 *pc = -1;
2884 return;
2885 }
2886
2887 assert(mach->CallStackTop > 0);
2888 mach->CallStackTop--;
2889
2890 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
2891 mach->CondMask = mach->CondStack[mach->CondStackTop];
2892
2893 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
2894 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
2895
2896 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
2897 mach->ContMask = mach->ContStack[mach->ContStackTop];
2898
2899 assert(mach->FuncStackTop > 0);
2900 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
2901
2902 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
2903
2904 UPDATE_EXEC_MASK(mach);
2905 }
2906 break;
2907
2908 case TGSI_OPCODE_SSG:
2909 /* TGSI_OPCODE_SGN */
2910 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2911 FETCH( &r[0], 0, chan_index );
2912 micro_sgn(&d[chan_index], &r[0]);
2913 }
2914 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2915 STORE(&d[chan_index], 0, chan_index);
2916 }
2917 break;
2918
2919 case TGSI_OPCODE_CMP:
2920 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2921 FETCH(&r[0], 0, chan_index);
2922 FETCH(&r[1], 1, chan_index);
2923 FETCH(&r[2], 2, chan_index);
2924 micro_lt(&d[chan_index], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[1], &r[2]);
2925 }
2926 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2927 STORE(&d[chan_index], 0, chan_index);
2928 }
2929 break;
2930
2931 case TGSI_OPCODE_SCS:
2932 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
2933 FETCH( &r[0], 0, CHAN_X );
2934 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2935 micro_cos(&r[1], &r[0]);
2936 STORE(&r[1], 0, CHAN_X);
2937 }
2938 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2939 micro_sin(&r[1], &r[0]);
2940 STORE(&r[1], 0, CHAN_Y);
2941 }
2942 }
2943 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
2944 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
2945 }
2946 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
2947 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2948 }
2949 break;
2950
2951 case TGSI_OPCODE_NRM:
2952 /* 3-component vector normalize */
2953 if(IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2954 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2955 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2956 /* r3 = sqrt(dp3(src0, src0)) */
2957 FETCH(&r[0], 0, CHAN_X);
2958 micro_mul(&r[3], &r[0], &r[0]);
2959 FETCH(&r[1], 0, CHAN_Y);
2960 micro_mul(&r[4], &r[1], &r[1]);
2961 micro_add(&r[3], &r[3], &r[4]);
2962 FETCH(&r[2], 0, CHAN_Z);
2963 micro_mul(&r[4], &r[2], &r[2]);
2964 micro_add(&r[3], &r[3], &r[4]);
2965 micro_sqrt(&r[3], &r[3]);
2966
2967 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2968 micro_div(&r[0], &r[0], &r[3]);
2969 STORE(&r[0], 0, CHAN_X);
2970 }
2971 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2972 micro_div(&r[1], &r[1], &r[3]);
2973 STORE(&r[1], 0, CHAN_Y);
2974 }
2975 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2976 micro_div(&r[2], &r[2], &r[3]);
2977 STORE(&r[2], 0, CHAN_Z);
2978 }
2979 }
2980 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2981 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
2982 }
2983 break;
2984
2985 case TGSI_OPCODE_NRM4:
2986 /* 4-component vector normalize */
2987 {
2988 union tgsi_exec_channel tmp, dot;
2989
2990 /* tmp = dp4(src0, src0): */
2991 FETCH( &r[0], 0, CHAN_X );
2992 micro_mul( &tmp, &r[0], &r[0] );
2993
2994 FETCH( &r[1], 0, CHAN_Y );
2995 micro_mul( &dot, &r[1], &r[1] );
2996 micro_add( &tmp, &tmp, &dot );
2997
2998 FETCH( &r[2], 0, CHAN_Z );
2999 micro_mul( &dot, &r[2], &r[2] );
3000 micro_add( &tmp, &tmp, &dot );
3001
3002 FETCH( &r[3], 0, CHAN_W );
3003 micro_mul( &dot, &r[3], &r[3] );
3004 micro_add( &tmp, &tmp, &dot );
3005
3006 /* tmp = 1 / sqrt(tmp) */
3007 micro_sqrt( &tmp, &tmp );
3008 micro_div( &tmp, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &tmp );
3009
3010 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3011 /* chan = chan * tmp */
3012 micro_mul( &r[chan_index], &tmp, &r[chan_index] );
3013 STORE( &r[chan_index], 0, chan_index );
3014 }
3015 }
3016 break;
3017
3018 case TGSI_OPCODE_DIV:
3019 assert( 0 );
3020 break;
3021
3022 case TGSI_OPCODE_DP2:
3023 FETCH( &r[0], 0, CHAN_X );
3024 FETCH( &r[1], 1, CHAN_X );
3025 micro_mul( &r[0], &r[0], &r[1] );
3026
3027 FETCH( &r[1], 0, CHAN_Y );
3028 FETCH( &r[2], 1, CHAN_Y );
3029 micro_mul( &r[1], &r[1], &r[2] );
3030 micro_add( &r[0], &r[0], &r[1] );
3031
3032 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3033 STORE( &r[0], 0, chan_index );
3034 }
3035 break;
3036
3037 case TGSI_OPCODE_IF:
3038 /* push CondMask */
3039 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3040 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3041 FETCH( &r[0], 0, CHAN_X );
3042 /* update CondMask */
3043 if( ! r[0].u[0] ) {
3044 mach->CondMask &= ~0x1;
3045 }
3046 if( ! r[0].u[1] ) {
3047 mach->CondMask &= ~0x2;
3048 }
3049 if( ! r[0].u[2] ) {
3050 mach->CondMask &= ~0x4;
3051 }
3052 if( ! r[0].u[3] ) {
3053 mach->CondMask &= ~0x8;
3054 }
3055 UPDATE_EXEC_MASK(mach);
3056 /* Todo: If CondMask==0, jump to ELSE */
3057 break;
3058
3059 case TGSI_OPCODE_ELSE:
3060 /* invert CondMask wrt previous mask */
3061 {
3062 uint prevMask;
3063 assert(mach->CondStackTop > 0);
3064 prevMask = mach->CondStack[mach->CondStackTop - 1];
3065 mach->CondMask = ~mach->CondMask & prevMask;
3066 UPDATE_EXEC_MASK(mach);
3067 /* Todo: If CondMask==0, jump to ENDIF */
3068 }
3069 break;
3070
3071 case TGSI_OPCODE_ENDIF:
3072 /* pop CondMask */
3073 assert(mach->CondStackTop > 0);
3074 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3075 UPDATE_EXEC_MASK(mach);
3076 break;
3077
3078 case TGSI_OPCODE_END:
3079 /* halt execution */
3080 *pc = -1;
3081 break;
3082
3083 case TGSI_OPCODE_REP:
3084 assert (0);
3085 break;
3086
3087 case TGSI_OPCODE_ENDREP:
3088 assert (0);
3089 break;
3090
3091 case TGSI_OPCODE_PUSHA:
3092 assert (0);
3093 break;
3094
3095 case TGSI_OPCODE_POPA:
3096 assert (0);
3097 break;
3098
3099 case TGSI_OPCODE_CEIL:
3100 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3101 FETCH( &r[0], 0, chan_index );
3102 micro_ceil(&d[chan_index], &r[0]);
3103 }
3104 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3105 STORE(&d[chan_index], 0, chan_index);
3106 }
3107 break;
3108
3109 case TGSI_OPCODE_I2F:
3110 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3111 FETCH( &r[0], 0, chan_index );
3112 micro_i2f(&d[chan_index], &r[0]);
3113 }
3114 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3115 STORE(&d[chan_index], 0, chan_index);
3116 }
3117 break;
3118
3119 case TGSI_OPCODE_NOT:
3120 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3121 FETCH( &r[0], 0, chan_index );
3122 micro_not(&d[chan_index], &r[0]);
3123 }
3124 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3125 STORE(&d[chan_index], 0, chan_index);
3126 }
3127 break;
3128
3129 case TGSI_OPCODE_TRUNC:
3130 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3131 FETCH( &r[0], 0, chan_index );
3132 micro_trunc(&d[chan_index], &r[0]);
3133 }
3134 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3135 STORE(&d[chan_index], 0, chan_index);
3136 }
3137 break;
3138
3139 case TGSI_OPCODE_SHL:
3140 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3141 FETCH( &r[0], 0, chan_index );
3142 FETCH( &r[1], 1, chan_index );
3143 micro_shl(&d[chan_index], &r[0], &r[1]);
3144 }
3145 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3146 STORE(&d[chan_index], 0, chan_index);
3147 }
3148 break;
3149
3150 case TGSI_OPCODE_AND:
3151 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3152 FETCH( &r[0], 0, chan_index );
3153 FETCH( &r[1], 1, chan_index );
3154 micro_and(&d[chan_index], &r[0], &r[1]);
3155 }
3156 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3157 STORE(&d[chan_index], 0, chan_index);
3158 }
3159 break;
3160
3161 case TGSI_OPCODE_OR:
3162 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3163 FETCH( &r[0], 0, chan_index );
3164 FETCH( &r[1], 1, chan_index );
3165 micro_or(&d[chan_index], &r[0], &r[1]);
3166 }
3167 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3168 STORE(&d[chan_index], 0, chan_index);
3169 }
3170 break;
3171
3172 case TGSI_OPCODE_MOD:
3173 assert (0);
3174 break;
3175
3176 case TGSI_OPCODE_XOR:
3177 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3178 FETCH( &r[0], 0, chan_index );
3179 FETCH( &r[1], 1, chan_index );
3180 micro_xor(&d[chan_index], &r[0], &r[1]);
3181 }
3182 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3183 STORE(&d[chan_index], 0, chan_index);
3184 }
3185 break;
3186
3187 case TGSI_OPCODE_SAD:
3188 assert (0);
3189 break;
3190
3191 case TGSI_OPCODE_TXF:
3192 assert (0);
3193 break;
3194
3195 case TGSI_OPCODE_TXQ:
3196 assert (0);
3197 break;
3198
3199 case TGSI_OPCODE_EMIT:
3200 emit_vertex(mach);
3201 break;
3202
3203 case TGSI_OPCODE_ENDPRIM:
3204 emit_primitive(mach);
3205 break;
3206
3207 case TGSI_OPCODE_BGNFOR:
3208 assert(mach->LoopCounterStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3209 for (chan_index = 0; chan_index < 3; chan_index++) {
3210 FETCH( &mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[chan_index], 0, chan_index );
3211 }
3212 ++mach->LoopCounterStackTop;
3213 STORE(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X], 0, CHAN_X);
3214 /* update LoopMask */
3215 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[0] <= 0.0f) {
3216 mach->LoopMask &= ~0x1;
3217 }
3218 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[1] <= 0.0f) {
3219 mach->LoopMask &= ~0x2;
3220 }
3221 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[2] <= 0.0f) {
3222 mach->LoopMask &= ~0x4;
3223 }
3224 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[3] <= 0.0f) {
3225 mach->LoopMask &= ~0x8;
3226 }
3227 /* TODO: if mach->LoopMask == 0, jump to end of loop */
3228 UPDATE_EXEC_MASK(mach);
3229 /* fall-through (for now) */
3230 case TGSI_OPCODE_BGNLOOP:
3231 /* push LoopMask and ContMasks */
3232 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3233 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3234 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3235 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3236 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3237 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3238 break;
3239
3240 case TGSI_OPCODE_ENDFOR:
3241 assert(mach->LoopCounterStackTop > 0);
3242 micro_sub(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y],
3243 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y],
3244 &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C]);
3245 /* update LoopMask */
3246 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[0] <= 0.0f) {
3247 mach->LoopMask &= ~0x1;
3248 }
3249 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[1] <= 0.0f) {
3250 mach->LoopMask &= ~0x2;
3251 }
3252 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[2] <= 0.0f) {
3253 mach->LoopMask &= ~0x4;
3254 }
3255 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[3] <= 0.0f) {
3256 mach->LoopMask &= ~0x8;
3257 }
3258 micro_add(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X],
3259 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X],
3260 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Z]);
3261 assert(mach->LoopLabelStackTop > 0);
3262 inst = mach->Instructions + mach->LoopLabelStack[mach->LoopLabelStackTop - 1];
3263 STORE(&mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[CHAN_X], 0, CHAN_X);
3264 /* Restore ContMask, but don't pop */
3265 assert(mach->ContStackTop > 0);
3266 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3267 UPDATE_EXEC_MASK(mach);
3268 if (mach->ExecMask) {
3269 /* repeat loop: jump to instruction just past BGNLOOP */
3270 assert(mach->LoopLabelStackTop > 0);
3271 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3272 }
3273 else {
3274 /* exit loop: pop LoopMask */
3275 assert(mach->LoopStackTop > 0);
3276 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3277 /* pop ContMask */
3278 assert(mach->ContStackTop > 0);
3279 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3280 assert(mach->LoopLabelStackTop > 0);
3281 --mach->LoopLabelStackTop;
3282 assert(mach->LoopCounterStackTop > 0);
3283 --mach->LoopCounterStackTop;
3284 }
3285 UPDATE_EXEC_MASK(mach);
3286 break;
3287
3288 case TGSI_OPCODE_ENDLOOP:
3289 /* Restore ContMask, but don't pop */
3290 assert(mach->ContStackTop > 0);
3291 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3292 UPDATE_EXEC_MASK(mach);
3293 if (mach->ExecMask) {
3294 /* repeat loop: jump to instruction just past BGNLOOP */
3295 assert(mach->LoopLabelStackTop > 0);
3296 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3297 }
3298 else {
3299 /* exit loop: pop LoopMask */
3300 assert(mach->LoopStackTop > 0);
3301 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3302 /* pop ContMask */
3303 assert(mach->ContStackTop > 0);
3304 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3305 assert(mach->LoopLabelStackTop > 0);
3306 --mach->LoopLabelStackTop;
3307 }
3308 UPDATE_EXEC_MASK(mach);
3309 break;
3310
3311 case TGSI_OPCODE_BRK:
3312 /* turn off loop channels for each enabled exec channel */
3313 mach->LoopMask &= ~mach->ExecMask;
3314 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3315 UPDATE_EXEC_MASK(mach);
3316 break;
3317
3318 case TGSI_OPCODE_CONT:
3319 /* turn off cont channels for each enabled exec channel */
3320 mach->ContMask &= ~mach->ExecMask;
3321 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3322 UPDATE_EXEC_MASK(mach);
3323 break;
3324
3325 case TGSI_OPCODE_BGNSUB:
3326 /* no-op */
3327 break;
3328
3329 case TGSI_OPCODE_ENDSUB:
3330 /*
3331 * XXX: This really should be a no-op. We should never reach this opcode.
3332 */
3333
3334 assert(mach->CallStackTop > 0);
3335 mach->CallStackTop--;
3336
3337 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3338 mach->CondMask = mach->CondStack[mach->CondStackTop];
3339
3340 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3341 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3342
3343 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3344 mach->ContMask = mach->ContStack[mach->ContStackTop];
3345
3346 assert(mach->FuncStackTop > 0);
3347 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3348
3349 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3350
3351 UPDATE_EXEC_MASK(mach);
3352 break;
3353
3354 case TGSI_OPCODE_NOP:
3355 break;
3356
3357 case TGSI_OPCODE_BREAKC:
3358 FETCH(&r[0], 0, CHAN_X);
3359 /* update CondMask */
3360 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3361 mach->LoopMask &= ~0x1;
3362 }
3363 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3364 mach->LoopMask &= ~0x2;
3365 }
3366 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3367 mach->LoopMask &= ~0x4;
3368 }
3369 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3370 mach->LoopMask &= ~0x8;
3371 }
3372 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3373 UPDATE_EXEC_MASK(mach);
3374 break;
3375
3376 case TGSI_OPCODE_F2I:
3377 exec_vector_unary(mach, inst, micro_f2i);
3378 break;
3379
3380 case TGSI_OPCODE_IDIV:
3381 exec_vector_binary(mach, inst, micro_idiv);
3382 break;
3383
3384 case TGSI_OPCODE_IMAX:
3385 exec_vector_binary(mach, inst, micro_imax);
3386 break;
3387
3388 case TGSI_OPCODE_IMIN:
3389 exec_vector_binary(mach, inst, micro_imin);
3390 break;
3391
3392 case TGSI_OPCODE_INEG:
3393 exec_vector_unary(mach, inst, micro_ineg);
3394 break;
3395
3396 case TGSI_OPCODE_ISGE:
3397 exec_vector_binary(mach, inst, micro_isge);
3398 break;
3399
3400 case TGSI_OPCODE_ISHR:
3401 exec_vector_binary(mach, inst, micro_ishr);
3402 break;
3403
3404 case TGSI_OPCODE_ISLT:
3405 exec_vector_binary(mach, inst, micro_islt);
3406 break;
3407
3408 case TGSI_OPCODE_F2U:
3409 exec_vector_unary(mach, inst, micro_f2u);
3410 break;
3411
3412 case TGSI_OPCODE_U2F:
3413 exec_vector_unary(mach, inst, micro_u2f);
3414 break;
3415
3416 case TGSI_OPCODE_UADD:
3417 exec_vector_binary(mach, inst, micro_uadd);
3418 break;
3419
3420 case TGSI_OPCODE_UDIV:
3421 exec_vector_binary(mach, inst, micro_udiv);
3422 break;
3423
3424 case TGSI_OPCODE_UMAD:
3425 exec_vector_trinary(mach, inst, micro_umad);
3426 break;
3427
3428 case TGSI_OPCODE_UMAX:
3429 exec_vector_binary(mach, inst, micro_umax);
3430 break;
3431
3432 case TGSI_OPCODE_UMIN:
3433 exec_vector_binary(mach, inst, micro_umin);
3434 break;
3435
3436 case TGSI_OPCODE_UMUL:
3437 exec_vector_binary(mach, inst, micro_umul);
3438 break;
3439
3440 case TGSI_OPCODE_USEQ:
3441 exec_vector_binary(mach, inst, micro_useq);
3442 break;
3443
3444 case TGSI_OPCODE_USGE:
3445 exec_vector_binary(mach, inst, micro_usge);
3446 break;
3447
3448 case TGSI_OPCODE_USHR:
3449 exec_vector_binary(mach, inst, micro_ushr);
3450 break;
3451
3452 case TGSI_OPCODE_USLT:
3453 exec_vector_binary(mach, inst, micro_uslt);
3454 break;
3455
3456 case TGSI_OPCODE_USNE:
3457 exec_vector_binary(mach, inst, micro_usne);
3458 break;
3459
3460 default:
3461 assert( 0 );
3462 }
3463 }
3464
3465 #define DEBUG_EXECUTION 0
3466
3467
3468 /**
3469 * Run TGSI interpreter.
3470 * \return bitmask of "alive" quad components
3471 */
3472 uint
3473 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3474 {
3475 uint i;
3476 int pc = 0;
3477
3478 mach->CondMask = 0xf;
3479 mach->LoopMask = 0xf;
3480 mach->ContMask = 0xf;
3481 mach->FuncMask = 0xf;
3482 mach->ExecMask = 0xf;
3483
3484 assert(mach->CondStackTop == 0);
3485 assert(mach->LoopStackTop == 0);
3486 assert(mach->ContStackTop == 0);
3487 assert(mach->CallStackTop == 0);
3488
3489 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3490 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3491
3492 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3493 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3494 mach->Primitives[0] = 0;
3495 }
3496
3497 for (i = 0; i < QUAD_SIZE; i++) {
3498 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
3499 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
3500 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
3501 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
3502 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
3503 }
3504
3505 /* execute declarations (interpolants) */
3506 for (i = 0; i < mach->NumDeclarations; i++) {
3507 exec_declaration( mach, mach->Declarations+i );
3508 }
3509
3510 {
3511 #if DEBUG_EXECUTION
3512 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
3513 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
3514 uint inst = 1;
3515
3516 memcpy(temps, mach->Temps, sizeof(temps));
3517 memcpy(outputs, mach->Outputs, sizeof(outputs));
3518 #endif
3519
3520 /* execute instructions, until pc is set to -1 */
3521 while (pc != -1) {
3522
3523 #if DEBUG_EXECUTION
3524 uint i;
3525
3526 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
3527 #endif
3528
3529 assert(pc < (int) mach->NumInstructions);
3530 exec_instruction(mach, mach->Instructions + pc, &pc);
3531
3532 #if DEBUG_EXECUTION
3533 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
3534 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
3535 uint j;
3536
3537 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
3538 debug_printf("TEMP[%2u] = ", i);
3539 for (j = 0; j < 4; j++) {
3540 if (j > 0) {
3541 debug_printf(" ");
3542 }
3543 debug_printf("(%6f, %6f, %6f, %6f)\n",
3544 temps[i].xyzw[0].f[j],
3545 temps[i].xyzw[1].f[j],
3546 temps[i].xyzw[2].f[j],
3547 temps[i].xyzw[3].f[j]);
3548 }
3549 }
3550 }
3551 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
3552 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
3553 uint j;
3554
3555 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
3556 debug_printf("OUT[%2u] = ", i);
3557 for (j = 0; j < 4; j++) {
3558 if (j > 0) {
3559 debug_printf(" ");
3560 }
3561 debug_printf("{%6f, %6f, %6f, %6f}\n",
3562 outputs[i].xyzw[0].f[j],
3563 outputs[i].xyzw[1].f[j],
3564 outputs[i].xyzw[2].f[j],
3565 outputs[i].xyzw[3].f[j]);
3566 }
3567 }
3568 }
3569 #endif
3570 }
3571 }
3572
3573 #if 0
3574 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3575 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3576 /*
3577 * Scale back depth component.
3578 */
3579 for (i = 0; i < 4; i++)
3580 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3581 }
3582 #endif
3583
3584 assert(mach->CondStackTop == 0);
3585 assert(mach->LoopStackTop == 0);
3586 assert(mach->ContStackTop == 0);
3587 assert(mach->CallStackTop == 0);
3588
3589 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3590 }