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Merge branch 'mesa_7_7_branch'
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_cos(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src)
115 {
116 dst->f[0] = cosf(src->f[0]);
117 dst->f[1] = cosf(src->f[1]);
118 dst->f[2] = cosf(src->f[2]);
119 dst->f[3] = cosf(src->f[3]);
120 }
121
122 static void
123 micro_ddx(union tgsi_exec_channel *dst,
124 const union tgsi_exec_channel *src)
125 {
126 dst->f[0] =
127 dst->f[1] =
128 dst->f[2] =
129 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
130 }
131
132 static void
133 micro_ddy(union tgsi_exec_channel *dst,
134 const union tgsi_exec_channel *src)
135 {
136 dst->f[0] =
137 dst->f[1] =
138 dst->f[2] =
139 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
140 }
141
142 static void
143 micro_exp2(union tgsi_exec_channel *dst,
144 const union tgsi_exec_channel *src)
145 {
146 #if FAST_MATH
147 dst->f[0] = util_fast_exp2(src->f[0]);
148 dst->f[1] = util_fast_exp2(src->f[1]);
149 dst->f[2] = util_fast_exp2(src->f[2]);
150 dst->f[3] = util_fast_exp2(src->f[3]);
151 #else
152 #if DEBUG
153 /* Inf is okay for this instruction, so clamp it to silence assertions. */
154 uint i;
155 union tgsi_exec_channel clamped;
156
157 for (i = 0; i < 4; i++) {
158 if (src->f[i] > 127.99999f) {
159 clamped.f[i] = 127.99999f;
160 } else if (src->f[i] < -126.99999f) {
161 clamped.f[i] = -126.99999f;
162 } else {
163 clamped.f[i] = src->f[i];
164 }
165 }
166 src = &clamped;
167 #endif /* DEBUG */
168
169 dst->f[0] = powf(2.0f, src->f[0]);
170 dst->f[1] = powf(2.0f, src->f[1]);
171 dst->f[2] = powf(2.0f, src->f[2]);
172 dst->f[3] = powf(2.0f, src->f[3]);
173 #endif /* FAST_MATH */
174 }
175
176 static void
177 micro_flr(union tgsi_exec_channel *dst,
178 const union tgsi_exec_channel *src)
179 {
180 dst->f[0] = floorf(src->f[0]);
181 dst->f[1] = floorf(src->f[1]);
182 dst->f[2] = floorf(src->f[2]);
183 dst->f[3] = floorf(src->f[3]);
184 }
185
186 static void
187 micro_frc(union tgsi_exec_channel *dst,
188 const union tgsi_exec_channel *src)
189 {
190 dst->f[0] = src->f[0] - floorf(src->f[0]);
191 dst->f[1] = src->f[1] - floorf(src->f[1]);
192 dst->f[2] = src->f[2] - floorf(src->f[2]);
193 dst->f[3] = src->f[3] - floorf(src->f[3]);
194 }
195
196 static void
197 micro_iabs(union tgsi_exec_channel *dst,
198 const union tgsi_exec_channel *src)
199 {
200 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
201 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
202 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
203 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
204 }
205
206 static void
207 micro_ineg(union tgsi_exec_channel *dst,
208 const union tgsi_exec_channel *src)
209 {
210 dst->i[0] = -src->i[0];
211 dst->i[1] = -src->i[1];
212 dst->i[2] = -src->i[2];
213 dst->i[3] = -src->i[3];
214 }
215
216 static void
217 micro_lg2(union tgsi_exec_channel *dst,
218 const union tgsi_exec_channel *src)
219 {
220 #if FAST_MATH
221 dst->f[0] = util_fast_log2(src->f[0]);
222 dst->f[1] = util_fast_log2(src->f[1]);
223 dst->f[2] = util_fast_log2(src->f[2]);
224 dst->f[3] = util_fast_log2(src->f[3]);
225 #else
226 dst->f[0] = logf(src->f[0]) * 1.442695f;
227 dst->f[1] = logf(src->f[1]) * 1.442695f;
228 dst->f[2] = logf(src->f[2]) * 1.442695f;
229 dst->f[3] = logf(src->f[3]) * 1.442695f;
230 #endif
231 }
232
233 static void
234 micro_lrp(union tgsi_exec_channel *dst,
235 const union tgsi_exec_channel *src)
236 {
237 dst->f[0] = src[0].f[0] * (src[1].f[0] - src[2].f[0]) + src[2].f[0];
238 dst->f[1] = src[0].f[1] * (src[1].f[1] - src[2].f[1]) + src[2].f[1];
239 dst->f[2] = src[0].f[2] * (src[1].f[2] - src[2].f[2]) + src[2].f[2];
240 dst->f[3] = src[0].f[3] * (src[1].f[3] - src[2].f[3]) + src[2].f[3];
241 }
242
243 static void
244 micro_mad(union tgsi_exec_channel *dst,
245 const union tgsi_exec_channel *src)
246 {
247 dst->f[0] = src[0].f[0] * src[1].f[0] + src[2].f[0];
248 dst->f[1] = src[0].f[1] * src[1].f[1] + src[2].f[1];
249 dst->f[2] = src[0].f[2] * src[1].f[2] + src[2].f[2];
250 dst->f[3] = src[0].f[3] * src[1].f[3] + src[2].f[3];
251 }
252
253 static void
254 micro_mov(union tgsi_exec_channel *dst,
255 const union tgsi_exec_channel *src)
256 {
257 dst->u[0] = src->u[0];
258 dst->u[1] = src->u[1];
259 dst->u[2] = src->u[2];
260 dst->u[3] = src->u[3];
261 }
262
263 static void
264 micro_rcp(union tgsi_exec_channel *dst,
265 const union tgsi_exec_channel *src)
266 {
267 dst->f[0] = 1.0f / src->f[0];
268 dst->f[1] = 1.0f / src->f[1];
269 dst->f[2] = 1.0f / src->f[2];
270 dst->f[3] = 1.0f / src->f[3];
271 }
272
273 static void
274 micro_rnd(union tgsi_exec_channel *dst,
275 const union tgsi_exec_channel *src)
276 {
277 dst->f[0] = floorf(src->f[0] + 0.5f);
278 dst->f[1] = floorf(src->f[1] + 0.5f);
279 dst->f[2] = floorf(src->f[2] + 0.5f);
280 dst->f[3] = floorf(src->f[3] + 0.5f);
281 }
282
283 static void
284 micro_rsq(union tgsi_exec_channel *dst,
285 const union tgsi_exec_channel *src)
286 {
287 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
288 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
289 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
290 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
291 }
292
293 static void
294 micro_seq(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->f[0] = src[0].f[0] == src[1].f[0] ? 1.0f : 0.0f;
298 dst->f[1] = src[0].f[1] == src[1].f[1] ? 1.0f : 0.0f;
299 dst->f[2] = src[0].f[2] == src[1].f[2] ? 1.0f : 0.0f;
300 dst->f[3] = src[0].f[3] == src[1].f[3] ? 1.0f : 0.0f;
301 }
302
303 static void
304 micro_sge(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 dst->f[0] = src[0].f[0] >= src[1].f[0] ? 1.0f : 0.0f;
308 dst->f[1] = src[0].f[1] >= src[1].f[1] ? 1.0f : 0.0f;
309 dst->f[2] = src[0].f[2] >= src[1].f[2] ? 1.0f : 0.0f;
310 dst->f[3] = src[0].f[3] >= src[1].f[3] ? 1.0f : 0.0f;
311 }
312
313 static void
314 micro_sgn(union tgsi_exec_channel *dst,
315 const union tgsi_exec_channel *src)
316 {
317 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
318 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
319 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
320 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
321 }
322
323 static void
324 micro_sgt(union tgsi_exec_channel *dst,
325 const union tgsi_exec_channel *src)
326 {
327 dst->f[0] = src[0].f[0] > src[1].f[0] ? 1.0f : 0.0f;
328 dst->f[1] = src[0].f[1] > src[1].f[1] ? 1.0f : 0.0f;
329 dst->f[2] = src[0].f[2] > src[1].f[2] ? 1.0f : 0.0f;
330 dst->f[3] = src[0].f[3] > src[1].f[3] ? 1.0f : 0.0f;
331 }
332
333 static void
334 micro_sin(union tgsi_exec_channel *dst,
335 const union tgsi_exec_channel *src)
336 {
337 dst->f[0] = sinf(src->f[0]);
338 dst->f[1] = sinf(src->f[1]);
339 dst->f[2] = sinf(src->f[2]);
340 dst->f[3] = sinf(src->f[3]);
341 }
342
343 static void
344 micro_sle(union tgsi_exec_channel *dst,
345 const union tgsi_exec_channel *src)
346 {
347 dst->f[0] = src[0].f[0] <= src[1].f[0] ? 1.0f : 0.0f;
348 dst->f[1] = src[0].f[1] <= src[1].f[1] ? 1.0f : 0.0f;
349 dst->f[2] = src[0].f[2] <= src[1].f[2] ? 1.0f : 0.0f;
350 dst->f[3] = src[0].f[3] <= src[1].f[3] ? 1.0f : 0.0f;
351 }
352
353 static void
354 micro_slt(union tgsi_exec_channel *dst,
355 const union tgsi_exec_channel *src)
356 {
357 dst->f[0] = src[0].f[0] < src[1].f[0] ? 1.0f : 0.0f;
358 dst->f[1] = src[0].f[1] < src[1].f[1] ? 1.0f : 0.0f;
359 dst->f[2] = src[0].f[2] < src[1].f[2] ? 1.0f : 0.0f;
360 dst->f[3] = src[0].f[3] < src[1].f[3] ? 1.0f : 0.0f;
361 }
362
363 static void
364 micro_sne(union tgsi_exec_channel *dst,
365 const union tgsi_exec_channel *src)
366 {
367 dst->f[0] = src[0].f[0] != src[1].f[0] ? 1.0f : 0.0f;
368 dst->f[1] = src[0].f[1] != src[1].f[1] ? 1.0f : 0.0f;
369 dst->f[2] = src[0].f[2] != src[1].f[2] ? 1.0f : 0.0f;
370 dst->f[3] = src[0].f[3] != src[1].f[3] ? 1.0f : 0.0f;
371 }
372
373 static void
374 micro_trunc(union tgsi_exec_channel *dst,
375 const union tgsi_exec_channel *src)
376 {
377 dst->f[0] = (float)(int)src->f[0];
378 dst->f[1] = (float)(int)src->f[1];
379 dst->f[2] = (float)(int)src->f[2];
380 dst->f[3] = (float)(int)src->f[3];
381 }
382
383
384 #define CHAN_X 0
385 #define CHAN_Y 1
386 #define CHAN_Z 2
387 #define CHAN_W 3
388
389 enum tgsi_exec_datatype {
390 TGSI_EXEC_DATA_FLOAT,
391 TGSI_EXEC_DATA_INT,
392 TGSI_EXEC_DATA_UINT
393 };
394
395 /*
396 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
397 */
398 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
399 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
400 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
401 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
402 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
403 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
404 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
405 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
406 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
407 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
408 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
409 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
410 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
411 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
412 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
413 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
414 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
415 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
416 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
417 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
418 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
419 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
420 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
421 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
422 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
423 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
424 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
425 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
426 #define TEMP_R0 TGSI_EXEC_TEMP_R0
427 #define TEMP_P0 TGSI_EXEC_TEMP_P0
428
429 #define IS_CHANNEL_ENABLED(INST, CHAN)\
430 ((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
431
432 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
433 ((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
434
435 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
436 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
437 if (IS_CHANNEL_ENABLED( INST, CHAN ))
438
439 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
440 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
441 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
442
443
444 /** The execution mask depends on the conditional mask and the loop mask */
445 #define UPDATE_EXEC_MASK(MACH) \
446 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
447
448
449 static const union tgsi_exec_channel ZeroVec =
450 { { 0.0, 0.0, 0.0, 0.0 } };
451
452
453 #define CHECK_INF_OR_NAN(chan) do {\
454 assert(!util_is_inf_or_nan((chan)->f[0]));\
455 assert(!util_is_inf_or_nan((chan)->f[1]));\
456 assert(!util_is_inf_or_nan((chan)->f[2]));\
457 assert(!util_is_inf_or_nan((chan)->f[3]));\
458 } while (0)
459
460
461 #ifdef DEBUG
462 static void
463 print_chan(const char *msg, const union tgsi_exec_channel *chan)
464 {
465 debug_printf("%s = {%f, %f, %f, %f}\n",
466 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
467 }
468 #endif
469
470
471 #ifdef DEBUG
472 static void
473 print_temp(const struct tgsi_exec_machine *mach, uint index)
474 {
475 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
476 int i;
477 debug_printf("Temp[%u] =\n", index);
478 for (i = 0; i < 4; i++) {
479 debug_printf(" %c: { %f, %f, %f, %f }\n",
480 "XYZW"[i],
481 tmp->xyzw[i].f[0],
482 tmp->xyzw[i].f[1],
483 tmp->xyzw[i].f[2],
484 tmp->xyzw[i].f[3]);
485 }
486 }
487 #endif
488
489
490 /**
491 * Check if there's a potential src/dst register data dependency when
492 * using SOA execution.
493 * Example:
494 * MOV T, T.yxwz;
495 * This would expand into:
496 * MOV t0, t1;
497 * MOV t1, t0;
498 * MOV t2, t3;
499 * MOV t3, t2;
500 * The second instruction will have the wrong value for t0 if executed as-is.
501 */
502 boolean
503 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
504 {
505 uint i, chan;
506
507 uint writemask = inst->Dst[0].Register.WriteMask;
508 if (writemask == TGSI_WRITEMASK_X ||
509 writemask == TGSI_WRITEMASK_Y ||
510 writemask == TGSI_WRITEMASK_Z ||
511 writemask == TGSI_WRITEMASK_W ||
512 writemask == TGSI_WRITEMASK_NONE) {
513 /* no chance of data dependency */
514 return FALSE;
515 }
516
517 /* loop over src regs */
518 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
519 if ((inst->Src[i].Register.File ==
520 inst->Dst[0].Register.File) &&
521 (inst->Src[i].Register.Index ==
522 inst->Dst[0].Register.Index)) {
523 /* loop over dest channels */
524 uint channelsWritten = 0x0;
525 FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
526 /* check if we're reading a channel that's been written */
527 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
528 if (channelsWritten & (1 << swizzle)) {
529 return TRUE;
530 }
531
532 channelsWritten |= (1 << chan);
533 }
534 }
535 }
536 return FALSE;
537 }
538
539
540 /**
541 * Initialize machine state by expanding tokens to full instructions,
542 * allocating temporary storage, setting up constants, etc.
543 * After this, we can call tgsi_exec_machine_run() many times.
544 */
545 void
546 tgsi_exec_machine_bind_shader(
547 struct tgsi_exec_machine *mach,
548 const struct tgsi_token *tokens,
549 uint numSamplers,
550 struct tgsi_sampler **samplers)
551 {
552 uint k;
553 struct tgsi_parse_context parse;
554 struct tgsi_exec_labels *labels = &mach->Labels;
555 struct tgsi_full_instruction *instructions;
556 struct tgsi_full_declaration *declarations;
557 uint maxInstructions = 10, numInstructions = 0;
558 uint maxDeclarations = 10, numDeclarations = 0;
559 uint instno = 0;
560
561 #if 0
562 tgsi_dump(tokens, 0);
563 #endif
564
565 util_init_math();
566
567 mach->Tokens = tokens;
568 mach->Samplers = samplers;
569
570 k = tgsi_parse_init (&parse, mach->Tokens);
571 if (k != TGSI_PARSE_OK) {
572 debug_printf( "Problem parsing!\n" );
573 return;
574 }
575
576 mach->Processor = parse.FullHeader.Processor.Processor;
577 mach->ImmLimit = 0;
578 labels->count = 0;
579
580 declarations = (struct tgsi_full_declaration *)
581 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
582
583 if (!declarations) {
584 return;
585 }
586
587 instructions = (struct tgsi_full_instruction *)
588 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
589
590 if (!instructions) {
591 FREE( declarations );
592 return;
593 }
594
595 while( !tgsi_parse_end_of_tokens( &parse ) ) {
596 uint pointer = parse.Position;
597 uint i;
598
599 tgsi_parse_token( &parse );
600 switch( parse.FullToken.Token.Type ) {
601 case TGSI_TOKEN_TYPE_DECLARATION:
602 /* save expanded declaration */
603 if (numDeclarations == maxDeclarations) {
604 declarations = REALLOC(declarations,
605 maxDeclarations
606 * sizeof(struct tgsi_full_declaration),
607 (maxDeclarations + 10)
608 * sizeof(struct tgsi_full_declaration));
609 maxDeclarations += 10;
610 }
611 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
612 unsigned reg;
613 for (reg = parse.FullToken.FullDeclaration.Range.First;
614 reg <= parse.FullToken.FullDeclaration.Range.Last;
615 ++reg) {
616 ++mach->NumOutputs;
617 }
618 }
619 memcpy(declarations + numDeclarations,
620 &parse.FullToken.FullDeclaration,
621 sizeof(declarations[0]));
622 numDeclarations++;
623 break;
624
625 case TGSI_TOKEN_TYPE_IMMEDIATE:
626 {
627 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
628 assert( size <= 4 );
629 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
630
631 for( i = 0; i < size; i++ ) {
632 mach->Imms[mach->ImmLimit][i] =
633 parse.FullToken.FullImmediate.u[i].Float;
634 }
635 mach->ImmLimit += 1;
636 }
637 break;
638
639 case TGSI_TOKEN_TYPE_INSTRUCTION:
640 assert( labels->count < MAX_LABELS );
641
642 labels->labels[labels->count][0] = instno;
643 labels->labels[labels->count][1] = pointer;
644 labels->count++;
645
646 /* save expanded instruction */
647 if (numInstructions == maxInstructions) {
648 instructions = REALLOC(instructions,
649 maxInstructions
650 * sizeof(struct tgsi_full_instruction),
651 (maxInstructions + 10)
652 * sizeof(struct tgsi_full_instruction));
653 maxInstructions += 10;
654 }
655
656 memcpy(instructions + numInstructions,
657 &parse.FullToken.FullInstruction,
658 sizeof(instructions[0]));
659
660 numInstructions++;
661 break;
662
663 case TGSI_TOKEN_TYPE_PROPERTY:
664 break;
665
666 default:
667 assert( 0 );
668 }
669 }
670 tgsi_parse_free (&parse);
671
672 if (mach->Declarations) {
673 FREE( mach->Declarations );
674 }
675 mach->Declarations = declarations;
676 mach->NumDeclarations = numDeclarations;
677
678 if (mach->Instructions) {
679 FREE( mach->Instructions );
680 }
681 mach->Instructions = instructions;
682 mach->NumInstructions = numInstructions;
683 }
684
685
686 struct tgsi_exec_machine *
687 tgsi_exec_machine_create( void )
688 {
689 struct tgsi_exec_machine *mach;
690 uint i;
691
692 mach = align_malloc( sizeof *mach, 16 );
693 if (!mach)
694 goto fail;
695
696 memset(mach, 0, sizeof(*mach));
697
698 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
699 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
700 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
701
702 /* Setup constants. */
703 for( i = 0; i < 4; i++ ) {
704 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
705 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
706 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
707 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
708 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
709 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
710 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
711 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
712 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
713 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
714 }
715
716 #ifdef DEBUG
717 /* silence warnings */
718 (void) print_chan;
719 (void) print_temp;
720 #endif
721
722 return mach;
723
724 fail:
725 align_free(mach);
726 return NULL;
727 }
728
729
730 void
731 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
732 {
733 if (mach) {
734 FREE(mach->Instructions);
735 FREE(mach->Declarations);
736 }
737
738 align_free(mach);
739 }
740
741 static void
742 micro_add(
743 union tgsi_exec_channel *dst,
744 const union tgsi_exec_channel *src0,
745 const union tgsi_exec_channel *src1 )
746 {
747 dst->f[0] = src0->f[0] + src1->f[0];
748 dst->f[1] = src0->f[1] + src1->f[1];
749 dst->f[2] = src0->f[2] + src1->f[2];
750 dst->f[3] = src0->f[3] + src1->f[3];
751 }
752
753 static void
754 micro_div(
755 union tgsi_exec_channel *dst,
756 const union tgsi_exec_channel *src0,
757 const union tgsi_exec_channel *src1 )
758 {
759 if (src1->f[0] != 0) {
760 dst->f[0] = src0->f[0] / src1->f[0];
761 }
762 if (src1->f[1] != 0) {
763 dst->f[1] = src0->f[1] / src1->f[1];
764 }
765 if (src1->f[2] != 0) {
766 dst->f[2] = src0->f[2] / src1->f[2];
767 }
768 if (src1->f[3] != 0) {
769 dst->f[3] = src0->f[3] / src1->f[3];
770 }
771 }
772
773 static void
774 micro_float_clamp(union tgsi_exec_channel *dst,
775 const union tgsi_exec_channel *src)
776 {
777 uint i;
778
779 for (i = 0; i < 4; i++) {
780 if (src->f[i] > 0.0f) {
781 if (src->f[i] > 1.884467e+019f)
782 dst->f[i] = 1.884467e+019f;
783 else if (src->f[i] < 5.42101e-020f)
784 dst->f[i] = 5.42101e-020f;
785 else
786 dst->f[i] = src->f[i];
787 }
788 else {
789 if (src->f[i] < -1.884467e+019f)
790 dst->f[i] = -1.884467e+019f;
791 else if (src->f[i] > -5.42101e-020f)
792 dst->f[i] = -5.42101e-020f;
793 else
794 dst->f[i] = src->f[i];
795 }
796 }
797 }
798
799 static void
800 micro_lt(
801 union tgsi_exec_channel *dst,
802 const union tgsi_exec_channel *src0,
803 const union tgsi_exec_channel *src1,
804 const union tgsi_exec_channel *src2,
805 const union tgsi_exec_channel *src3 )
806 {
807 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
808 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
809 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
810 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
811 }
812
813 static void
814 micro_max(
815 union tgsi_exec_channel *dst,
816 const union tgsi_exec_channel *src0,
817 const union tgsi_exec_channel *src1 )
818 {
819 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
820 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
821 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
822 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
823 }
824
825 static void
826 micro_min(
827 union tgsi_exec_channel *dst,
828 const union tgsi_exec_channel *src0,
829 const union tgsi_exec_channel *src1 )
830 {
831 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
832 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
833 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
834 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
835 }
836
837 static void
838 micro_mul(
839 union tgsi_exec_channel *dst,
840 const union tgsi_exec_channel *src0,
841 const union tgsi_exec_channel *src1 )
842 {
843 dst->f[0] = src0->f[0] * src1->f[0];
844 dst->f[1] = src0->f[1] * src1->f[1];
845 dst->f[2] = src0->f[2] * src1->f[2];
846 dst->f[3] = src0->f[3] * src1->f[3];
847 }
848
849 #if 0
850 static void
851 micro_imul64(
852 union tgsi_exec_channel *dst0,
853 union tgsi_exec_channel *dst1,
854 const union tgsi_exec_channel *src0,
855 const union tgsi_exec_channel *src1 )
856 {
857 dst1->i[0] = src0->i[0] * src1->i[0];
858 dst1->i[1] = src0->i[1] * src1->i[1];
859 dst1->i[2] = src0->i[2] * src1->i[2];
860 dst1->i[3] = src0->i[3] * src1->i[3];
861 dst0->i[0] = 0;
862 dst0->i[1] = 0;
863 dst0->i[2] = 0;
864 dst0->i[3] = 0;
865 }
866 #endif
867
868 #if 0
869 static void
870 micro_umul64(
871 union tgsi_exec_channel *dst0,
872 union tgsi_exec_channel *dst1,
873 const union tgsi_exec_channel *src0,
874 const union tgsi_exec_channel *src1 )
875 {
876 dst1->u[0] = src0->u[0] * src1->u[0];
877 dst1->u[1] = src0->u[1] * src1->u[1];
878 dst1->u[2] = src0->u[2] * src1->u[2];
879 dst1->u[3] = src0->u[3] * src1->u[3];
880 dst0->u[0] = 0;
881 dst0->u[1] = 0;
882 dst0->u[2] = 0;
883 dst0->u[3] = 0;
884 }
885 #endif
886
887
888 #if 0
889 static void
890 micro_movc(
891 union tgsi_exec_channel *dst,
892 const union tgsi_exec_channel *src0,
893 const union tgsi_exec_channel *src1,
894 const union tgsi_exec_channel *src2 )
895 {
896 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
897 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
898 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
899 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
900 }
901 #endif
902
903 static void
904 micro_neg(
905 union tgsi_exec_channel *dst,
906 const union tgsi_exec_channel *src )
907 {
908 dst->f[0] = -src->f[0];
909 dst->f[1] = -src->f[1];
910 dst->f[2] = -src->f[2];
911 dst->f[3] = -src->f[3];
912 }
913
914 static void
915 micro_pow(
916 union tgsi_exec_channel *dst,
917 const union tgsi_exec_channel *src0,
918 const union tgsi_exec_channel *src1 )
919 {
920 #if FAST_MATH
921 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
922 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
923 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
924 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
925 #else
926 dst->f[0] = powf( src0->f[0], src1->f[0] );
927 dst->f[1] = powf( src0->f[1], src1->f[1] );
928 dst->f[2] = powf( src0->f[2], src1->f[2] );
929 dst->f[3] = powf( src0->f[3], src1->f[3] );
930 #endif
931 }
932
933 static void
934 micro_sqrt( union tgsi_exec_channel *dst,
935 const union tgsi_exec_channel *src )
936 {
937 dst->f[0] = sqrtf( src->f[0] );
938 dst->f[1] = sqrtf( src->f[1] );
939 dst->f[2] = sqrtf( src->f[2] );
940 dst->f[3] = sqrtf( src->f[3] );
941 }
942
943 static void
944 micro_sub(
945 union tgsi_exec_channel *dst,
946 const union tgsi_exec_channel *src0,
947 const union tgsi_exec_channel *src1 )
948 {
949 dst->f[0] = src0->f[0] - src1->f[0];
950 dst->f[1] = src0->f[1] - src1->f[1];
951 dst->f[2] = src0->f[2] - src1->f[2];
952 dst->f[3] = src0->f[3] - src1->f[3];
953 }
954
955 static void
956 fetch_src_file_channel(
957 const struct tgsi_exec_machine *mach,
958 const uint file,
959 const uint swizzle,
960 const union tgsi_exec_channel *index,
961 union tgsi_exec_channel *chan )
962 {
963 switch( swizzle ) {
964 case TGSI_SWIZZLE_X:
965 case TGSI_SWIZZLE_Y:
966 case TGSI_SWIZZLE_Z:
967 case TGSI_SWIZZLE_W:
968 switch( file ) {
969 case TGSI_FILE_CONSTANT:
970 assert(mach->Consts);
971 if (index->i[0] < 0)
972 chan->f[0] = 0.0f;
973 else
974 chan->f[0] = mach->Consts[index->i[0]][swizzle];
975 if (index->i[1] < 0)
976 chan->f[1] = 0.0f;
977 else
978 chan->f[1] = mach->Consts[index->i[1]][swizzle];
979 if (index->i[2] < 0)
980 chan->f[2] = 0.0f;
981 else
982 chan->f[2] = mach->Consts[index->i[2]][swizzle];
983 if (index->i[3] < 0)
984 chan->f[3] = 0.0f;
985 else
986 chan->f[3] = mach->Consts[index->i[3]][swizzle];
987 break;
988
989 case TGSI_FILE_INPUT:
990 case TGSI_FILE_SYSTEM_VALUE:
991 chan->u[0] = mach->Inputs[index->i[0]].xyzw[swizzle].u[0];
992 chan->u[1] = mach->Inputs[index->i[1]].xyzw[swizzle].u[1];
993 chan->u[2] = mach->Inputs[index->i[2]].xyzw[swizzle].u[2];
994 chan->u[3] = mach->Inputs[index->i[3]].xyzw[swizzle].u[3];
995 break;
996
997 case TGSI_FILE_TEMPORARY:
998 assert(index->i[0] < TGSI_EXEC_NUM_TEMPS);
999 chan->u[0] = mach->Temps[index->i[0]].xyzw[swizzle].u[0];
1000 chan->u[1] = mach->Temps[index->i[1]].xyzw[swizzle].u[1];
1001 chan->u[2] = mach->Temps[index->i[2]].xyzw[swizzle].u[2];
1002 chan->u[3] = mach->Temps[index->i[3]].xyzw[swizzle].u[3];
1003 break;
1004
1005 case TGSI_FILE_IMMEDIATE:
1006 assert( index->i[0] < (int) mach->ImmLimit );
1007 chan->f[0] = mach->Imms[index->i[0]][swizzle];
1008 assert( index->i[1] < (int) mach->ImmLimit );
1009 chan->f[1] = mach->Imms[index->i[1]][swizzle];
1010 assert( index->i[2] < (int) mach->ImmLimit );
1011 chan->f[2] = mach->Imms[index->i[2]][swizzle];
1012 assert( index->i[3] < (int) mach->ImmLimit );
1013 chan->f[3] = mach->Imms[index->i[3]][swizzle];
1014 break;
1015
1016 case TGSI_FILE_ADDRESS:
1017 chan->u[0] = mach->Addrs[index->i[0]].xyzw[swizzle].u[0];
1018 chan->u[1] = mach->Addrs[index->i[1]].xyzw[swizzle].u[1];
1019 chan->u[2] = mach->Addrs[index->i[2]].xyzw[swizzle].u[2];
1020 chan->u[3] = mach->Addrs[index->i[3]].xyzw[swizzle].u[3];
1021 break;
1022
1023 case TGSI_FILE_PREDICATE:
1024 assert(index->i[0] < TGSI_EXEC_NUM_PREDS);
1025 assert(index->i[1] < TGSI_EXEC_NUM_PREDS);
1026 assert(index->i[2] < TGSI_EXEC_NUM_PREDS);
1027 assert(index->i[3] < TGSI_EXEC_NUM_PREDS);
1028 chan->u[0] = mach->Predicates[0].xyzw[swizzle].u[0];
1029 chan->u[1] = mach->Predicates[0].xyzw[swizzle].u[1];
1030 chan->u[2] = mach->Predicates[0].xyzw[swizzle].u[2];
1031 chan->u[3] = mach->Predicates[0].xyzw[swizzle].u[3];
1032 break;
1033
1034 case TGSI_FILE_OUTPUT:
1035 /* vertex/fragment output vars can be read too */
1036 chan->u[0] = mach->Outputs[index->i[0]].xyzw[swizzle].u[0];
1037 chan->u[1] = mach->Outputs[index->i[1]].xyzw[swizzle].u[1];
1038 chan->u[2] = mach->Outputs[index->i[2]].xyzw[swizzle].u[2];
1039 chan->u[3] = mach->Outputs[index->i[3]].xyzw[swizzle].u[3];
1040 break;
1041
1042 default:
1043 assert( 0 );
1044 }
1045 break;
1046
1047 default:
1048 assert( 0 );
1049 }
1050 }
1051
1052 static void
1053 fetch_source(const struct tgsi_exec_machine *mach,
1054 union tgsi_exec_channel *chan,
1055 const struct tgsi_full_src_register *reg,
1056 const uint chan_index,
1057 enum tgsi_exec_datatype src_datatype)
1058 {
1059 union tgsi_exec_channel index;
1060 uint swizzle;
1061
1062 /* We start with a direct index into a register file.
1063 *
1064 * file[1],
1065 * where:
1066 * file = Register.File
1067 * [1] = Register.Index
1068 */
1069 index.i[0] =
1070 index.i[1] =
1071 index.i[2] =
1072 index.i[3] = reg->Register.Index;
1073
1074 /* There is an extra source register that indirectly subscripts
1075 * a register file. The direct index now becomes an offset
1076 * that is being added to the indirect register.
1077 *
1078 * file[ind[2].x+1],
1079 * where:
1080 * ind = Indirect.File
1081 * [2] = Indirect.Index
1082 * .x = Indirect.SwizzleX
1083 */
1084 if (reg->Register.Indirect) {
1085 union tgsi_exec_channel index2;
1086 union tgsi_exec_channel indir_index;
1087 const uint execmask = mach->ExecMask;
1088 uint i;
1089
1090 /* which address register (always zero now) */
1091 index2.i[0] =
1092 index2.i[1] =
1093 index2.i[2] =
1094 index2.i[3] = reg->Indirect.Index;
1095
1096 /* get current value of address register[swizzle] */
1097 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1098 fetch_src_file_channel(
1099 mach,
1100 reg->Indirect.File,
1101 swizzle,
1102 &index2,
1103 &indir_index );
1104
1105 /* add value of address register to the offset */
1106 index.i[0] += indir_index.i[0];
1107 index.i[1] += indir_index.i[1];
1108 index.i[2] += indir_index.i[2];
1109 index.i[3] += indir_index.i[3];
1110
1111 /* for disabled execution channels, zero-out the index to
1112 * avoid using a potential garbage value.
1113 */
1114 for (i = 0; i < QUAD_SIZE; i++) {
1115 if ((execmask & (1 << i)) == 0)
1116 index.i[i] = 0;
1117 }
1118 }
1119
1120 /* There is an extra source register that is a second
1121 * subscript to a register file. Effectively it means that
1122 * the register file is actually a 2D array of registers.
1123 *
1124 * file[1][3] == file[1*sizeof(file[1])+3],
1125 * where:
1126 * [3] = Dimension.Index
1127 */
1128 if (reg->Register.Dimension) {
1129 /* The size of the first-order array depends on the register file type.
1130 * We need to multiply the index to the first array to get an effective,
1131 * "flat" index that points to the beginning of the second-order array.
1132 */
1133 switch (reg->Register.File) {
1134 case TGSI_FILE_INPUT:
1135 case TGSI_FILE_SYSTEM_VALUE:
1136 index.i[0] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1137 index.i[1] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1138 index.i[2] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1139 index.i[3] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1140 break;
1141 case TGSI_FILE_CONSTANT:
1142 index.i[0] *= TGSI_EXEC_MAX_CONST_BUFFER;
1143 index.i[1] *= TGSI_EXEC_MAX_CONST_BUFFER;
1144 index.i[2] *= TGSI_EXEC_MAX_CONST_BUFFER;
1145 index.i[3] *= TGSI_EXEC_MAX_CONST_BUFFER;
1146 break;
1147 default:
1148 assert( 0 );
1149 }
1150
1151 index.i[0] += reg->Dimension.Index;
1152 index.i[1] += reg->Dimension.Index;
1153 index.i[2] += reg->Dimension.Index;
1154 index.i[3] += reg->Dimension.Index;
1155
1156 /* Again, the second subscript index can be addressed indirectly
1157 * identically to the first one.
1158 * Nothing stops us from indirectly addressing the indirect register,
1159 * but there is no need for that, so we won't exercise it.
1160 *
1161 * file[1][ind[4].y+3],
1162 * where:
1163 * ind = DimIndirect.File
1164 * [4] = DimIndirect.Index
1165 * .y = DimIndirect.SwizzleX
1166 */
1167 if (reg->Dimension.Indirect) {
1168 union tgsi_exec_channel index2;
1169 union tgsi_exec_channel indir_index;
1170 const uint execmask = mach->ExecMask;
1171 uint i;
1172
1173 index2.i[0] =
1174 index2.i[1] =
1175 index2.i[2] =
1176 index2.i[3] = reg->DimIndirect.Index;
1177
1178 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1179 fetch_src_file_channel(
1180 mach,
1181 reg->DimIndirect.File,
1182 swizzle,
1183 &index2,
1184 &indir_index );
1185
1186 index.i[0] += indir_index.i[0];
1187 index.i[1] += indir_index.i[1];
1188 index.i[2] += indir_index.i[2];
1189 index.i[3] += indir_index.i[3];
1190
1191 /* for disabled execution channels, zero-out the index to
1192 * avoid using a potential garbage value.
1193 */
1194 for (i = 0; i < QUAD_SIZE; i++) {
1195 if ((execmask & (1 << i)) == 0)
1196 index.i[i] = 0;
1197 }
1198 }
1199
1200 /* If by any chance there was a need for a 3D array of register
1201 * files, we would have to check whether Dimension is followed
1202 * by a dimension register and continue the saga.
1203 */
1204 }
1205
1206 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1207 fetch_src_file_channel(
1208 mach,
1209 reg->Register.File,
1210 swizzle,
1211 &index,
1212 chan );
1213
1214 if (reg->Register.Absolute) {
1215 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1216 micro_abs(chan, chan);
1217 } else {
1218 micro_iabs(chan, chan);
1219 }
1220 }
1221
1222 if (reg->Register.Negate) {
1223 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1224 micro_neg(chan, chan);
1225 } else {
1226 micro_ineg(chan, chan);
1227 }
1228 }
1229 }
1230
1231 static void
1232 store_dest(struct tgsi_exec_machine *mach,
1233 const union tgsi_exec_channel *chan,
1234 const struct tgsi_full_dst_register *reg,
1235 const struct tgsi_full_instruction *inst,
1236 uint chan_index,
1237 enum tgsi_exec_datatype dst_datatype)
1238 {
1239 uint i;
1240 union tgsi_exec_channel null;
1241 union tgsi_exec_channel *dst;
1242 uint execmask = mach->ExecMask;
1243 int offset = 0; /* indirection offset */
1244 int index;
1245
1246 if (dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1247 CHECK_INF_OR_NAN(chan);
1248 }
1249
1250 /* There is an extra source register that indirectly subscripts
1251 * a register file. The direct index now becomes an offset
1252 * that is being added to the indirect register.
1253 *
1254 * file[ind[2].x+1],
1255 * where:
1256 * ind = Indirect.File
1257 * [2] = Indirect.Index
1258 * .x = Indirect.SwizzleX
1259 */
1260 if (reg->Register.Indirect) {
1261 union tgsi_exec_channel index;
1262 union tgsi_exec_channel indir_index;
1263 uint swizzle;
1264
1265 /* which address register (always zero for now) */
1266 index.i[0] =
1267 index.i[1] =
1268 index.i[2] =
1269 index.i[3] = reg->Indirect.Index;
1270
1271 /* get current value of address register[swizzle] */
1272 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1273
1274 /* fetch values from the address/indirection register */
1275 fetch_src_file_channel(
1276 mach,
1277 reg->Indirect.File,
1278 swizzle,
1279 &index,
1280 &indir_index );
1281
1282 /* save indirection offset */
1283 offset = indir_index.i[0];
1284 }
1285
1286 switch (reg->Register.File) {
1287 case TGSI_FILE_NULL:
1288 dst = &null;
1289 break;
1290
1291 case TGSI_FILE_OUTPUT:
1292 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1293 + reg->Register.Index;
1294 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1295 #if 0
1296 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1297 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1298 for (i = 0; i < QUAD_SIZE; i++)
1299 if (execmask & (1 << i))
1300 fprintf(stderr, "%f, ", chan->f[i]);
1301 fprintf(stderr, ")\n");
1302 }
1303 #endif
1304 break;
1305
1306 case TGSI_FILE_TEMPORARY:
1307 index = reg->Register.Index;
1308 assert( index < TGSI_EXEC_NUM_TEMPS );
1309 dst = &mach->Temps[offset + index].xyzw[chan_index];
1310 break;
1311
1312 case TGSI_FILE_ADDRESS:
1313 index = reg->Register.Index;
1314 dst = &mach->Addrs[index].xyzw[chan_index];
1315 break;
1316
1317 case TGSI_FILE_LOOP:
1318 assert(reg->Register.Index == 0);
1319 assert(mach->LoopCounterStackTop > 0);
1320 assert(chan_index == CHAN_X);
1321 dst = &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[chan_index];
1322 break;
1323
1324 case TGSI_FILE_PREDICATE:
1325 index = reg->Register.Index;
1326 assert(index < TGSI_EXEC_NUM_PREDS);
1327 dst = &mach->Predicates[index].xyzw[chan_index];
1328 break;
1329
1330 default:
1331 assert( 0 );
1332 return;
1333 }
1334
1335 if (inst->Instruction.Predicate) {
1336 uint swizzle;
1337 union tgsi_exec_channel *pred;
1338
1339 switch (chan_index) {
1340 case CHAN_X:
1341 swizzle = inst->Predicate.SwizzleX;
1342 break;
1343 case CHAN_Y:
1344 swizzle = inst->Predicate.SwizzleY;
1345 break;
1346 case CHAN_Z:
1347 swizzle = inst->Predicate.SwizzleZ;
1348 break;
1349 case CHAN_W:
1350 swizzle = inst->Predicate.SwizzleW;
1351 break;
1352 default:
1353 assert(0);
1354 return;
1355 }
1356
1357 assert(inst->Predicate.Index == 0);
1358
1359 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1360
1361 if (inst->Predicate.Negate) {
1362 for (i = 0; i < QUAD_SIZE; i++) {
1363 if (pred->u[i]) {
1364 execmask &= ~(1 << i);
1365 }
1366 }
1367 } else {
1368 for (i = 0; i < QUAD_SIZE; i++) {
1369 if (!pred->u[i]) {
1370 execmask &= ~(1 << i);
1371 }
1372 }
1373 }
1374 }
1375
1376 switch (inst->Instruction.Saturate) {
1377 case TGSI_SAT_NONE:
1378 for (i = 0; i < QUAD_SIZE; i++)
1379 if (execmask & (1 << i))
1380 dst->i[i] = chan->i[i];
1381 break;
1382
1383 case TGSI_SAT_ZERO_ONE:
1384 for (i = 0; i < QUAD_SIZE; i++)
1385 if (execmask & (1 << i)) {
1386 if (chan->f[i] < 0.0f)
1387 dst->f[i] = 0.0f;
1388 else if (chan->f[i] > 1.0f)
1389 dst->f[i] = 1.0f;
1390 else
1391 dst->i[i] = chan->i[i];
1392 }
1393 break;
1394
1395 case TGSI_SAT_MINUS_PLUS_ONE:
1396 for (i = 0; i < QUAD_SIZE; i++)
1397 if (execmask & (1 << i)) {
1398 if (chan->f[i] < -1.0f)
1399 dst->f[i] = -1.0f;
1400 else if (chan->f[i] > 1.0f)
1401 dst->f[i] = 1.0f;
1402 else
1403 dst->i[i] = chan->i[i];
1404 }
1405 break;
1406
1407 default:
1408 assert( 0 );
1409 }
1410 }
1411
1412 #define FETCH(VAL,INDEX,CHAN)\
1413 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1414
1415 #define STORE(VAL,INDEX,CHAN)\
1416 store_dest(mach, VAL, &inst->Dst[INDEX], inst, CHAN, TGSI_EXEC_DATA_FLOAT)
1417
1418
1419 /**
1420 * Execute ARB-style KIL which is predicated by a src register.
1421 * Kill fragment if any of the four values is less than zero.
1422 */
1423 static void
1424 exec_kil(struct tgsi_exec_machine *mach,
1425 const struct tgsi_full_instruction *inst)
1426 {
1427 uint uniquemask;
1428 uint chan_index;
1429 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1430 union tgsi_exec_channel r[1];
1431
1432 /* This mask stores component bits that were already tested. */
1433 uniquemask = 0;
1434
1435 for (chan_index = 0; chan_index < 4; chan_index++)
1436 {
1437 uint swizzle;
1438 uint i;
1439
1440 /* unswizzle channel */
1441 swizzle = tgsi_util_get_full_src_register_swizzle (
1442 &inst->Src[0],
1443 chan_index);
1444
1445 /* check if the component has not been already tested */
1446 if (uniquemask & (1 << swizzle))
1447 continue;
1448 uniquemask |= 1 << swizzle;
1449
1450 FETCH(&r[0], 0, chan_index);
1451 for (i = 0; i < 4; i++)
1452 if (r[0].f[i] < 0.0f)
1453 kilmask |= 1 << i;
1454 }
1455
1456 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1457 }
1458
1459 /**
1460 * Execute NVIDIA-style KIL which is predicated by a condition code.
1461 * Kill fragment if the condition code is TRUE.
1462 */
1463 static void
1464 exec_kilp(struct tgsi_exec_machine *mach,
1465 const struct tgsi_full_instruction *inst)
1466 {
1467 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1468
1469 /* "unconditional" kil */
1470 kilmask = mach->ExecMask;
1471 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1472 }
1473
1474 static void
1475 emit_vertex(struct tgsi_exec_machine *mach)
1476 {
1477 /* FIXME: check for exec mask correctly
1478 unsigned i;
1479 for (i = 0; i < QUAD_SIZE; ++i) {
1480 if ((mach->ExecMask & (1 << i)))
1481 */
1482 if (mach->ExecMask) {
1483 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1484 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1485 }
1486 }
1487
1488 static void
1489 emit_primitive(struct tgsi_exec_machine *mach)
1490 {
1491 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1492 /* FIXME: check for exec mask correctly
1493 unsigned i;
1494 for (i = 0; i < QUAD_SIZE; ++i) {
1495 if ((mach->ExecMask & (1 << i)))
1496 */
1497 if (mach->ExecMask) {
1498 ++(*prim_count);
1499 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1500 mach->Primitives[*prim_count] = 0;
1501 }
1502 }
1503
1504 /*
1505 * Fetch a four texture samples using STR texture coordinates.
1506 */
1507 static void
1508 fetch_texel( struct tgsi_sampler *sampler,
1509 const union tgsi_exec_channel *s,
1510 const union tgsi_exec_channel *t,
1511 const union tgsi_exec_channel *p,
1512 const union tgsi_exec_channel *c0,
1513 enum tgsi_sampler_control control,
1514 union tgsi_exec_channel *r,
1515 union tgsi_exec_channel *g,
1516 union tgsi_exec_channel *b,
1517 union tgsi_exec_channel *a )
1518 {
1519 uint j;
1520 float rgba[NUM_CHANNELS][QUAD_SIZE];
1521
1522 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1523
1524 for (j = 0; j < 4; j++) {
1525 r->f[j] = rgba[0][j];
1526 g->f[j] = rgba[1][j];
1527 b->f[j] = rgba[2][j];
1528 a->f[j] = rgba[3][j];
1529 }
1530 }
1531
1532
1533 #define TEX_MODIFIER_NONE 0
1534 #define TEX_MODIFIER_PROJECTED 1
1535 #define TEX_MODIFIER_LOD_BIAS 2
1536 #define TEX_MODIFIER_EXPLICIT_LOD 3
1537
1538
1539 static void
1540 exec_tex(struct tgsi_exec_machine *mach,
1541 const struct tgsi_full_instruction *inst,
1542 uint modifier)
1543 {
1544 const uint unit = inst->Src[1].Register.Index;
1545 union tgsi_exec_channel r[4];
1546 const union tgsi_exec_channel *lod = &ZeroVec;
1547 enum tgsi_sampler_control control;
1548 uint chan_index;
1549
1550 if (modifier != TEX_MODIFIER_NONE) {
1551 FETCH(&r[3], 0, CHAN_W);
1552 if (modifier != TEX_MODIFIER_PROJECTED) {
1553 lod = &r[3];
1554 }
1555 }
1556
1557 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1558 control = tgsi_sampler_lod_explicit;
1559 } else {
1560 control = tgsi_sampler_lod_bias;
1561 }
1562
1563 switch (inst->Texture.Texture) {
1564 case TGSI_TEXTURE_1D:
1565 case TGSI_TEXTURE_SHADOW1D:
1566 FETCH(&r[0], 0, CHAN_X);
1567
1568 if (modifier == TEX_MODIFIER_PROJECTED) {
1569 micro_div(&r[0], &r[0], &r[3]);
1570 }
1571
1572 fetch_texel(mach->Samplers[unit],
1573 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1574 control,
1575 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1576 break;
1577
1578 case TGSI_TEXTURE_2D:
1579 case TGSI_TEXTURE_RECT:
1580 case TGSI_TEXTURE_SHADOW2D:
1581 case TGSI_TEXTURE_SHADOWRECT:
1582 FETCH(&r[0], 0, CHAN_X);
1583 FETCH(&r[1], 0, CHAN_Y);
1584 FETCH(&r[2], 0, CHAN_Z);
1585
1586 if (modifier == TEX_MODIFIER_PROJECTED) {
1587 micro_div(&r[0], &r[0], &r[3]);
1588 micro_div(&r[1], &r[1], &r[3]);
1589 micro_div(&r[2], &r[2], &r[3]);
1590 }
1591
1592 fetch_texel(mach->Samplers[unit],
1593 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1594 control,
1595 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1596 break;
1597
1598 case TGSI_TEXTURE_3D:
1599 case TGSI_TEXTURE_CUBE:
1600 FETCH(&r[0], 0, CHAN_X);
1601 FETCH(&r[1], 0, CHAN_Y);
1602 FETCH(&r[2], 0, CHAN_Z);
1603
1604 if (modifier == TEX_MODIFIER_PROJECTED) {
1605 micro_div(&r[0], &r[0], &r[3]);
1606 micro_div(&r[1], &r[1], &r[3]);
1607 micro_div(&r[2], &r[2], &r[3]);
1608 }
1609
1610 fetch_texel(mach->Samplers[unit],
1611 &r[0], &r[1], &r[2], lod,
1612 control,
1613 &r[0], &r[1], &r[2], &r[3]);
1614 break;
1615
1616 default:
1617 assert(0);
1618 }
1619
1620 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1621 STORE(&r[chan_index], 0, chan_index);
1622 }
1623 }
1624
1625 static void
1626 exec_txd(struct tgsi_exec_machine *mach,
1627 const struct tgsi_full_instruction *inst)
1628 {
1629 const uint unit = inst->Src[3].Register.Index;
1630 union tgsi_exec_channel r[4];
1631 uint chan_index;
1632
1633 /*
1634 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1635 */
1636
1637 switch (inst->Texture.Texture) {
1638 case TGSI_TEXTURE_1D:
1639 case TGSI_TEXTURE_SHADOW1D:
1640
1641 FETCH(&r[0], 0, CHAN_X);
1642
1643 fetch_texel(mach->Samplers[unit],
1644 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1645 tgsi_sampler_lod_bias,
1646 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1647 break;
1648
1649 case TGSI_TEXTURE_2D:
1650 case TGSI_TEXTURE_RECT:
1651 case TGSI_TEXTURE_SHADOW2D:
1652 case TGSI_TEXTURE_SHADOWRECT:
1653
1654 FETCH(&r[0], 0, CHAN_X);
1655 FETCH(&r[1], 0, CHAN_Y);
1656 FETCH(&r[2], 0, CHAN_Z);
1657
1658 fetch_texel(mach->Samplers[unit],
1659 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1660 tgsi_sampler_lod_bias,
1661 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1662 break;
1663
1664 case TGSI_TEXTURE_3D:
1665 case TGSI_TEXTURE_CUBE:
1666
1667 FETCH(&r[0], 0, CHAN_X);
1668 FETCH(&r[1], 0, CHAN_Y);
1669 FETCH(&r[2], 0, CHAN_Z);
1670
1671 fetch_texel(mach->Samplers[unit],
1672 &r[0], &r[1], &r[2], &ZeroVec,
1673 tgsi_sampler_lod_bias,
1674 &r[0], &r[1], &r[2], &r[3]);
1675 break;
1676
1677 default:
1678 assert(0);
1679 }
1680
1681 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1682 STORE(&r[chan_index], 0, chan_index);
1683 }
1684 }
1685
1686
1687 /**
1688 * Evaluate a constant-valued coefficient at the position of the
1689 * current quad.
1690 */
1691 static void
1692 eval_constant_coef(
1693 struct tgsi_exec_machine *mach,
1694 unsigned attrib,
1695 unsigned chan )
1696 {
1697 unsigned i;
1698
1699 for( i = 0; i < QUAD_SIZE; i++ ) {
1700 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1701 }
1702 }
1703
1704 /**
1705 * Evaluate a linear-valued coefficient at the position of the
1706 * current quad.
1707 */
1708 static void
1709 eval_linear_coef(
1710 struct tgsi_exec_machine *mach,
1711 unsigned attrib,
1712 unsigned chan )
1713 {
1714 const float x = mach->QuadPos.xyzw[0].f[0];
1715 const float y = mach->QuadPos.xyzw[1].f[0];
1716 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1717 const float dady = mach->InterpCoefs[attrib].dady[chan];
1718 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1719 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1720 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1721 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1722 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1723 }
1724
1725 /**
1726 * Evaluate a perspective-valued coefficient at the position of the
1727 * current quad.
1728 */
1729 static void
1730 eval_perspective_coef(
1731 struct tgsi_exec_machine *mach,
1732 unsigned attrib,
1733 unsigned chan )
1734 {
1735 const float x = mach->QuadPos.xyzw[0].f[0];
1736 const float y = mach->QuadPos.xyzw[1].f[0];
1737 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1738 const float dady = mach->InterpCoefs[attrib].dady[chan];
1739 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1740 const float *w = mach->QuadPos.xyzw[3].f;
1741 /* divide by W here */
1742 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1743 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1744 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1745 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1746 }
1747
1748
1749 typedef void (* eval_coef_func)(
1750 struct tgsi_exec_machine *mach,
1751 unsigned attrib,
1752 unsigned chan );
1753
1754 static void
1755 exec_declaration(struct tgsi_exec_machine *mach,
1756 const struct tgsi_full_declaration *decl)
1757 {
1758 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
1759 if (decl->Declaration.File == TGSI_FILE_INPUT ||
1760 decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1761 uint first, last, mask;
1762
1763 first = decl->Range.First;
1764 last = decl->Range.Last;
1765 mask = decl->Declaration.UsageMask;
1766
1767 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
1768 assert(decl->Semantic.Index == 0);
1769 assert(first == last);
1770 assert(mask == TGSI_WRITEMASK_XYZW);
1771
1772 mach->Inputs[first] = mach->QuadPos;
1773 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1774 uint i;
1775
1776 assert(decl->Semantic.Index == 0);
1777 assert(first == last);
1778
1779 for (i = 0; i < QUAD_SIZE; i++) {
1780 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
1781 }
1782 } else {
1783 eval_coef_func eval;
1784 uint i, j;
1785
1786 switch (decl->Declaration.Interpolate) {
1787 case TGSI_INTERPOLATE_CONSTANT:
1788 eval = eval_constant_coef;
1789 break;
1790
1791 case TGSI_INTERPOLATE_LINEAR:
1792 eval = eval_linear_coef;
1793 break;
1794
1795 case TGSI_INTERPOLATE_PERSPECTIVE:
1796 eval = eval_perspective_coef;
1797 break;
1798
1799 default:
1800 assert(0);
1801 return;
1802 }
1803
1804 for (j = 0; j < NUM_CHANNELS; j++) {
1805 if (mask & (1 << j)) {
1806 for (i = first; i <= last; i++) {
1807 eval(mach, i, j);
1808 }
1809 }
1810 }
1811 }
1812 }
1813 }
1814 }
1815
1816 typedef void (* micro_op)(union tgsi_exec_channel *dst,
1817 const union tgsi_exec_channel *src);
1818
1819 static void
1820 exec_scalar_unary(struct tgsi_exec_machine *mach,
1821 const struct tgsi_full_instruction *inst,
1822 micro_op op,
1823 enum tgsi_exec_datatype dst_datatype,
1824 enum tgsi_exec_datatype src_datatype)
1825 {
1826 unsigned int chan;
1827 union tgsi_exec_channel src;
1828 union tgsi_exec_channel dst;
1829
1830 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
1831 op(&dst, &src);
1832 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1833 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1834 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
1835 }
1836 }
1837 }
1838
1839 static void
1840 exec_vector_unary(struct tgsi_exec_machine *mach,
1841 const struct tgsi_full_instruction *inst,
1842 micro_op op,
1843 enum tgsi_exec_datatype dst_datatype,
1844 enum tgsi_exec_datatype src_datatype)
1845 {
1846 unsigned int chan;
1847 struct tgsi_exec_vector dst;
1848
1849 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1850 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1851 union tgsi_exec_channel src;
1852
1853 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
1854 op(&dst.xyzw[chan], &src);
1855 }
1856 }
1857 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1858 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1859 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1860 }
1861 }
1862 }
1863
1864 static void
1865 exec_vector_binary(struct tgsi_exec_machine *mach,
1866 const struct tgsi_full_instruction *inst,
1867 micro_op op,
1868 enum tgsi_exec_datatype dst_datatype,
1869 enum tgsi_exec_datatype src_datatype)
1870 {
1871 unsigned int chan;
1872 struct tgsi_exec_vector dst;
1873
1874 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1875 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1876 union tgsi_exec_channel src[2];
1877
1878 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
1879 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
1880 op(&dst.xyzw[chan], src);
1881 }
1882 }
1883 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1884 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1885 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1886 }
1887 }
1888 }
1889
1890 static void
1891 exec_vector_trinary(struct tgsi_exec_machine *mach,
1892 const struct tgsi_full_instruction *inst,
1893 micro_op op,
1894 enum tgsi_exec_datatype dst_datatype,
1895 enum tgsi_exec_datatype src_datatype)
1896 {
1897 unsigned int chan;
1898 struct tgsi_exec_vector dst;
1899
1900 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1901 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1902 union tgsi_exec_channel src[3];
1903
1904 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
1905 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
1906 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
1907 op(&dst.xyzw[chan], src);
1908 }
1909 }
1910 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1911 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1912 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1913 }
1914 }
1915 }
1916
1917 static void
1918 exec_dp3(struct tgsi_exec_machine *mach,
1919 const struct tgsi_full_instruction *inst)
1920 {
1921 unsigned int chan;
1922 union tgsi_exec_channel arg[3];
1923
1924 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1925 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1926 micro_mul(&arg[2], &arg[0], &arg[1]);
1927
1928 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
1929 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
1930 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
1931 micro_mad(&arg[2], arg);
1932 }
1933
1934 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1935 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1936 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1937 }
1938 }
1939 }
1940
1941 static void
1942 exec_dp4(struct tgsi_exec_machine *mach,
1943 const struct tgsi_full_instruction *inst)
1944 {
1945 unsigned int chan;
1946 union tgsi_exec_channel arg[3];
1947
1948 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1949 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1950 micro_mul(&arg[2], &arg[0], &arg[1]);
1951
1952 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
1953 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
1954 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
1955 micro_mad(&arg[2], arg);
1956 }
1957
1958 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1959 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1960 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1961 }
1962 }
1963 }
1964
1965 static void
1966 exec_dp2a(struct tgsi_exec_machine *mach,
1967 const struct tgsi_full_instruction *inst)
1968 {
1969 unsigned int chan;
1970 union tgsi_exec_channel arg[3];
1971
1972 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1973 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1974 micro_mul(&arg[2], &arg[0], &arg[1]);
1975
1976 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
1977 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
1978 micro_mad(&arg[0], arg);
1979
1980 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1981 micro_add(&arg[0], &arg[0], &arg[1]);
1982
1983 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1984 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1985 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1986 }
1987 }
1988 }
1989
1990 static void
1991 exec_dph(struct tgsi_exec_machine *mach,
1992 const struct tgsi_full_instruction *inst)
1993 {
1994 unsigned int chan;
1995 union tgsi_exec_channel arg[3];
1996
1997 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1998 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1999 micro_mul(&arg[2], &arg[0], &arg[1]);
2000
2001 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2002 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2003 micro_mad(&arg[2], arg);
2004
2005 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2006 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2007 micro_mad(&arg[0], arg);
2008
2009 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2010 micro_add(&arg[0], &arg[0], &arg[1]);
2011
2012 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2013 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2014 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2015 }
2016 }
2017 }
2018
2019 static void
2020 exec_dp2(struct tgsi_exec_machine *mach,
2021 const struct tgsi_full_instruction *inst)
2022 {
2023 unsigned int chan;
2024 union tgsi_exec_channel arg[3];
2025
2026 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2027 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2028 micro_mul(&arg[2], &arg[0], &arg[1]);
2029
2030 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2031 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2032 micro_mad(&arg[2], arg);
2033
2034 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2035 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2036 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2037 }
2038 }
2039 }
2040
2041 static void
2042 exec_break(struct tgsi_exec_machine *mach)
2043 {
2044 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2045 /* turn off loop channels for each enabled exec channel */
2046 mach->LoopMask &= ~mach->ExecMask;
2047 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2048 UPDATE_EXEC_MASK(mach);
2049 } else {
2050 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2051
2052 mach->Switch.mask = 0x0;
2053
2054 UPDATE_EXEC_MASK(mach);
2055 }
2056 }
2057
2058 static void
2059 exec_switch(struct tgsi_exec_machine *mach,
2060 const struct tgsi_full_instruction *inst)
2061 {
2062 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2063 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2064
2065 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2066 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2067 mach->Switch.mask = 0x0;
2068 mach->Switch.defaultMask = 0x0;
2069
2070 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2071 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2072
2073 UPDATE_EXEC_MASK(mach);
2074 }
2075
2076 static void
2077 exec_case(struct tgsi_exec_machine *mach,
2078 const struct tgsi_full_instruction *inst)
2079 {
2080 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2081 union tgsi_exec_channel src;
2082 uint mask = 0;
2083
2084 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2085
2086 if (mach->Switch.selector.u[0] == src.u[0]) {
2087 mask |= 0x1;
2088 }
2089 if (mach->Switch.selector.u[1] == src.u[1]) {
2090 mask |= 0x2;
2091 }
2092 if (mach->Switch.selector.u[2] == src.u[2]) {
2093 mask |= 0x4;
2094 }
2095 if (mach->Switch.selector.u[3] == src.u[3]) {
2096 mask |= 0x8;
2097 }
2098
2099 mach->Switch.defaultMask |= mask;
2100
2101 mach->Switch.mask |= mask & prevMask;
2102
2103 UPDATE_EXEC_MASK(mach);
2104 }
2105
2106 static void
2107 exec_default(struct tgsi_exec_machine *mach)
2108 {
2109 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2110
2111 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2112
2113 UPDATE_EXEC_MASK(mach);
2114 }
2115
2116 static void
2117 exec_endswitch(struct tgsi_exec_machine *mach)
2118 {
2119 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2120 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2121
2122 UPDATE_EXEC_MASK(mach);
2123 }
2124
2125 static void
2126 micro_i2f(union tgsi_exec_channel *dst,
2127 const union tgsi_exec_channel *src)
2128 {
2129 dst->f[0] = (float)src->i[0];
2130 dst->f[1] = (float)src->i[1];
2131 dst->f[2] = (float)src->i[2];
2132 dst->f[3] = (float)src->i[3];
2133 }
2134
2135 static void
2136 micro_not(union tgsi_exec_channel *dst,
2137 const union tgsi_exec_channel *src)
2138 {
2139 dst->u[0] = ~src->u[0];
2140 dst->u[1] = ~src->u[1];
2141 dst->u[2] = ~src->u[2];
2142 dst->u[3] = ~src->u[3];
2143 }
2144
2145 static void
2146 micro_shl(union tgsi_exec_channel *dst,
2147 const union tgsi_exec_channel *src)
2148 {
2149 dst->u[0] = src[0].u[0] << src[1].u[0];
2150 dst->u[1] = src[0].u[1] << src[1].u[1];
2151 dst->u[2] = src[0].u[2] << src[1].u[2];
2152 dst->u[3] = src[0].u[3] << src[1].u[3];
2153 }
2154
2155 static void
2156 micro_and(union tgsi_exec_channel *dst,
2157 const union tgsi_exec_channel *src)
2158 {
2159 dst->u[0] = src[0].u[0] & src[1].u[0];
2160 dst->u[1] = src[0].u[1] & src[1].u[1];
2161 dst->u[2] = src[0].u[2] & src[1].u[2];
2162 dst->u[3] = src[0].u[3] & src[1].u[3];
2163 }
2164
2165 static void
2166 micro_or(union tgsi_exec_channel *dst,
2167 const union tgsi_exec_channel *src)
2168 {
2169 dst->u[0] = src[0].u[0] | src[1].u[0];
2170 dst->u[1] = src[0].u[1] | src[1].u[1];
2171 dst->u[2] = src[0].u[2] | src[1].u[2];
2172 dst->u[3] = src[0].u[3] | src[1].u[3];
2173 }
2174
2175 static void
2176 micro_xor(union tgsi_exec_channel *dst,
2177 const union tgsi_exec_channel *src)
2178 {
2179 dst->u[0] = src[0].u[0] ^ src[1].u[0];
2180 dst->u[1] = src[0].u[1] ^ src[1].u[1];
2181 dst->u[2] = src[0].u[2] ^ src[1].u[2];
2182 dst->u[3] = src[0].u[3] ^ src[1].u[3];
2183 }
2184
2185 static void
2186 micro_f2i(union tgsi_exec_channel *dst,
2187 const union tgsi_exec_channel *src)
2188 {
2189 dst->i[0] = (int)src->f[0];
2190 dst->i[1] = (int)src->f[1];
2191 dst->i[2] = (int)src->f[2];
2192 dst->i[3] = (int)src->f[3];
2193 }
2194
2195 static void
2196 micro_idiv(union tgsi_exec_channel *dst,
2197 const union tgsi_exec_channel *src)
2198 {
2199 dst->i[0] = src[0].i[0] / src[1].i[0];
2200 dst->i[1] = src[0].i[1] / src[1].i[1];
2201 dst->i[2] = src[0].i[2] / src[1].i[2];
2202 dst->i[3] = src[0].i[3] / src[1].i[3];
2203 }
2204
2205 static void
2206 micro_imax(union tgsi_exec_channel *dst,
2207 const union tgsi_exec_channel *src)
2208 {
2209 dst->i[0] = src[0].i[0] > src[1].i[0] ? src[0].i[0] : src[1].i[0];
2210 dst->i[1] = src[0].i[1] > src[1].i[1] ? src[0].i[1] : src[1].i[1];
2211 dst->i[2] = src[0].i[2] > src[1].i[2] ? src[0].i[2] : src[1].i[2];
2212 dst->i[3] = src[0].i[3] > src[1].i[3] ? src[0].i[3] : src[1].i[3];
2213 }
2214
2215 static void
2216 micro_imin(union tgsi_exec_channel *dst,
2217 const union tgsi_exec_channel *src)
2218 {
2219 dst->i[0] = src[0].i[0] < src[1].i[0] ? src[0].i[0] : src[1].i[0];
2220 dst->i[1] = src[0].i[1] < src[1].i[1] ? src[0].i[1] : src[1].i[1];
2221 dst->i[2] = src[0].i[2] < src[1].i[2] ? src[0].i[2] : src[1].i[2];
2222 dst->i[3] = src[0].i[3] < src[1].i[3] ? src[0].i[3] : src[1].i[3];
2223 }
2224
2225 static void
2226 micro_isge(union tgsi_exec_channel *dst,
2227 const union tgsi_exec_channel *src)
2228 {
2229 dst->i[0] = src[0].i[0] >= src[1].i[0] ? -1 : 0;
2230 dst->i[1] = src[0].i[1] >= src[1].i[1] ? -1 : 0;
2231 dst->i[2] = src[0].i[2] >= src[1].i[2] ? -1 : 0;
2232 dst->i[3] = src[0].i[3] >= src[1].i[3] ? -1 : 0;
2233 }
2234
2235 static void
2236 micro_ishr(union tgsi_exec_channel *dst,
2237 const union tgsi_exec_channel *src)
2238 {
2239 dst->i[0] = src[0].i[0] >> src[1].i[0];
2240 dst->i[1] = src[0].i[1] >> src[1].i[1];
2241 dst->i[2] = src[0].i[2] >> src[1].i[2];
2242 dst->i[3] = src[0].i[3] >> src[1].i[3];
2243 }
2244
2245 static void
2246 micro_islt(union tgsi_exec_channel *dst,
2247 const union tgsi_exec_channel *src)
2248 {
2249 dst->i[0] = src[0].i[0] < src[1].i[0] ? -1 : 0;
2250 dst->i[1] = src[0].i[1] < src[1].i[1] ? -1 : 0;
2251 dst->i[2] = src[0].i[2] < src[1].i[2] ? -1 : 0;
2252 dst->i[3] = src[0].i[3] < src[1].i[3] ? -1 : 0;
2253 }
2254
2255 static void
2256 micro_f2u(union tgsi_exec_channel *dst,
2257 const union tgsi_exec_channel *src)
2258 {
2259 dst->u[0] = (uint)src->f[0];
2260 dst->u[1] = (uint)src->f[1];
2261 dst->u[2] = (uint)src->f[2];
2262 dst->u[3] = (uint)src->f[3];
2263 }
2264
2265 static void
2266 micro_u2f(union tgsi_exec_channel *dst,
2267 const union tgsi_exec_channel *src)
2268 {
2269 dst->f[0] = (float)src->u[0];
2270 dst->f[1] = (float)src->u[1];
2271 dst->f[2] = (float)src->u[2];
2272 dst->f[3] = (float)src->u[3];
2273 }
2274
2275 static void
2276 micro_uadd(union tgsi_exec_channel *dst,
2277 const union tgsi_exec_channel *src)
2278 {
2279 dst->u[0] = src[0].u[0] + src[1].u[0];
2280 dst->u[1] = src[0].u[1] + src[1].u[1];
2281 dst->u[2] = src[0].u[2] + src[1].u[2];
2282 dst->u[3] = src[0].u[3] + src[1].u[3];
2283 }
2284
2285 static void
2286 micro_udiv(union tgsi_exec_channel *dst,
2287 const union tgsi_exec_channel *src)
2288 {
2289 dst->u[0] = src[0].u[0] / src[1].u[0];
2290 dst->u[1] = src[0].u[1] / src[1].u[1];
2291 dst->u[2] = src[0].u[2] / src[1].u[2];
2292 dst->u[3] = src[0].u[3] / src[1].u[3];
2293 }
2294
2295 static void
2296 micro_umad(union tgsi_exec_channel *dst,
2297 const union tgsi_exec_channel *src)
2298 {
2299 dst->u[0] = src[0].u[0] * src[1].u[0] + src[2].u[0];
2300 dst->u[1] = src[0].u[1] * src[1].u[1] + src[2].u[1];
2301 dst->u[2] = src[0].u[2] * src[1].u[2] + src[2].u[2];
2302 dst->u[3] = src[0].u[3] * src[1].u[3] + src[2].u[3];
2303 }
2304
2305 static void
2306 micro_umax(union tgsi_exec_channel *dst,
2307 const union tgsi_exec_channel *src)
2308 {
2309 dst->u[0] = src[0].u[0] > src[1].u[0] ? src[0].u[0] : src[1].u[0];
2310 dst->u[1] = src[0].u[1] > src[1].u[1] ? src[0].u[1] : src[1].u[1];
2311 dst->u[2] = src[0].u[2] > src[1].u[2] ? src[0].u[2] : src[1].u[2];
2312 dst->u[3] = src[0].u[3] > src[1].u[3] ? src[0].u[3] : src[1].u[3];
2313 }
2314
2315 static void
2316 micro_umin(union tgsi_exec_channel *dst,
2317 const union tgsi_exec_channel *src)
2318 {
2319 dst->u[0] = src[0].u[0] < src[1].u[0] ? src[0].u[0] : src[1].u[0];
2320 dst->u[1] = src[0].u[1] < src[1].u[1] ? src[0].u[1] : src[1].u[1];
2321 dst->u[2] = src[0].u[2] < src[1].u[2] ? src[0].u[2] : src[1].u[2];
2322 dst->u[3] = src[0].u[3] < src[1].u[3] ? src[0].u[3] : src[1].u[3];
2323 }
2324
2325 static void
2326 micro_umod(union tgsi_exec_channel *dst,
2327 const union tgsi_exec_channel *src)
2328 {
2329 dst->u[0] = src[0].u[0] % src[1].u[0];
2330 dst->u[1] = src[0].u[1] % src[1].u[1];
2331 dst->u[2] = src[0].u[2] % src[1].u[2];
2332 dst->u[3] = src[0].u[3] % src[1].u[3];
2333 }
2334
2335 static void
2336 micro_umul(union tgsi_exec_channel *dst,
2337 const union tgsi_exec_channel *src)
2338 {
2339 dst->u[0] = src[0].u[0] * src[1].u[0];
2340 dst->u[1] = src[0].u[1] * src[1].u[1];
2341 dst->u[2] = src[0].u[2] * src[1].u[2];
2342 dst->u[3] = src[0].u[3] * src[1].u[3];
2343 }
2344
2345 static void
2346 micro_useq(union tgsi_exec_channel *dst,
2347 const union tgsi_exec_channel *src)
2348 {
2349 dst->u[0] = src[0].u[0] == src[1].u[0] ? ~0 : 0;
2350 dst->u[1] = src[0].u[1] == src[1].u[1] ? ~0 : 0;
2351 dst->u[2] = src[0].u[2] == src[1].u[2] ? ~0 : 0;
2352 dst->u[3] = src[0].u[3] == src[1].u[3] ? ~0 : 0;
2353 }
2354
2355 static void
2356 micro_usge(union tgsi_exec_channel *dst,
2357 const union tgsi_exec_channel *src)
2358 {
2359 dst->u[0] = src[0].u[0] >= src[1].u[0] ? ~0 : 0;
2360 dst->u[1] = src[0].u[1] >= src[1].u[1] ? ~0 : 0;
2361 dst->u[2] = src[0].u[2] >= src[1].u[2] ? ~0 : 0;
2362 dst->u[3] = src[0].u[3] >= src[1].u[3] ? ~0 : 0;
2363 }
2364
2365 static void
2366 micro_ushr(union tgsi_exec_channel *dst,
2367 const union tgsi_exec_channel *src)
2368 {
2369 dst->u[0] = src[0].u[0] >> src[1].u[0];
2370 dst->u[1] = src[0].u[1] >> src[1].u[1];
2371 dst->u[2] = src[0].u[2] >> src[1].u[2];
2372 dst->u[3] = src[0].u[3] >> src[1].u[3];
2373 }
2374
2375 static void
2376 micro_uslt(union tgsi_exec_channel *dst,
2377 const union tgsi_exec_channel *src)
2378 {
2379 dst->u[0] = src[0].u[0] < src[1].u[0] ? ~0 : 0;
2380 dst->u[1] = src[0].u[1] < src[1].u[1] ? ~0 : 0;
2381 dst->u[2] = src[0].u[2] < src[1].u[2] ? ~0 : 0;
2382 dst->u[3] = src[0].u[3] < src[1].u[3] ? ~0 : 0;
2383 }
2384
2385 static void
2386 micro_usne(union tgsi_exec_channel *dst,
2387 const union tgsi_exec_channel *src)
2388 {
2389 dst->u[0] = src[0].u[0] != src[1].u[0] ? ~0 : 0;
2390 dst->u[1] = src[0].u[1] != src[1].u[1] ? ~0 : 0;
2391 dst->u[2] = src[0].u[2] != src[1].u[2] ? ~0 : 0;
2392 dst->u[3] = src[0].u[3] != src[1].u[3] ? ~0 : 0;
2393 }
2394
2395 static void
2396 exec_instruction(
2397 struct tgsi_exec_machine *mach,
2398 const struct tgsi_full_instruction *inst,
2399 int *pc )
2400 {
2401 uint chan_index;
2402 union tgsi_exec_channel r[10];
2403 union tgsi_exec_channel d[8];
2404
2405 (*pc)++;
2406
2407 switch (inst->Instruction.Opcode) {
2408 case TGSI_OPCODE_ARL:
2409 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2410 break;
2411
2412 case TGSI_OPCODE_MOV:
2413 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
2414 break;
2415
2416 case TGSI_OPCODE_LIT:
2417 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2418 FETCH( &r[0], 0, CHAN_X );
2419 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2420 micro_max(&d[CHAN_Y], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2421 }
2422
2423 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2424 FETCH( &r[1], 0, CHAN_Y );
2425 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2426
2427 FETCH( &r[2], 0, CHAN_W );
2428 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
2429 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
2430 micro_pow( &r[1], &r[1], &r[2] );
2431 micro_lt(&d[CHAN_Z], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2432 }
2433
2434 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2435 STORE(&d[CHAN_Y], 0, CHAN_Y);
2436 }
2437 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2438 STORE(&d[CHAN_Z], 0, CHAN_Z);
2439 }
2440 }
2441 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2442 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
2443 }
2444 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2445 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2446 }
2447 break;
2448
2449 case TGSI_OPCODE_RCP:
2450 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2451 break;
2452
2453 case TGSI_OPCODE_RSQ:
2454 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2455 break;
2456
2457 case TGSI_OPCODE_EXP:
2458 FETCH( &r[0], 0, CHAN_X );
2459 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
2460 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2461 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
2462 STORE( &r[2], 0, CHAN_X ); /* store r2 */
2463 }
2464 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2465 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
2466 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
2467 }
2468 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2469 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
2470 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
2471 }
2472 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2473 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2474 }
2475 break;
2476
2477 case TGSI_OPCODE_LOG:
2478 FETCH( &r[0], 0, CHAN_X );
2479 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
2480 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
2481 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
2482 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2483 STORE( &r[0], 0, CHAN_X );
2484 }
2485 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2486 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
2487 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
2488 STORE( &r[0], 0, CHAN_Y );
2489 }
2490 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2491 STORE( &r[1], 0, CHAN_Z );
2492 }
2493 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2494 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2495 }
2496 break;
2497
2498 case TGSI_OPCODE_MUL:
2499 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2500 FETCH(&r[0], 0, chan_index);
2501 FETCH(&r[1], 1, chan_index);
2502 micro_mul(&d[chan_index], &r[0], &r[1]);
2503 }
2504 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2505 STORE(&d[chan_index], 0, chan_index);
2506 }
2507 break;
2508
2509 case TGSI_OPCODE_ADD:
2510 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2511 FETCH( &r[0], 0, chan_index );
2512 FETCH( &r[1], 1, chan_index );
2513 micro_add(&d[chan_index], &r[0], &r[1]);
2514 }
2515 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2516 STORE(&d[chan_index], 0, chan_index);
2517 }
2518 break;
2519
2520 case TGSI_OPCODE_DP3:
2521 exec_dp3(mach, inst);
2522 break;
2523
2524 case TGSI_OPCODE_DP4:
2525 exec_dp4(mach, inst);
2526 break;
2527
2528 case TGSI_OPCODE_DST:
2529 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2530 FETCH( &r[0], 0, CHAN_Y );
2531 FETCH( &r[1], 1, CHAN_Y);
2532 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2533 }
2534 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2535 FETCH(&d[CHAN_Z], 0, CHAN_Z);
2536 }
2537 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2538 FETCH(&d[CHAN_W], 1, CHAN_W);
2539 }
2540
2541 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2542 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X);
2543 }
2544 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2545 STORE(&d[CHAN_Y], 0, CHAN_Y);
2546 }
2547 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2548 STORE(&d[CHAN_Z], 0, CHAN_Z);
2549 }
2550 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2551 STORE(&d[CHAN_W], 0, CHAN_W);
2552 }
2553 break;
2554
2555 case TGSI_OPCODE_MIN:
2556 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2557 FETCH(&r[0], 0, chan_index);
2558 FETCH(&r[1], 1, chan_index);
2559
2560 /* XXX use micro_min()?? */
2561 micro_lt(&d[chan_index], &r[0], &r[1], &r[0], &r[1]);
2562 }
2563 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2564 STORE(&d[chan_index], 0, chan_index);
2565 }
2566 break;
2567
2568 case TGSI_OPCODE_MAX:
2569 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2570 FETCH(&r[0], 0, chan_index);
2571 FETCH(&r[1], 1, chan_index);
2572
2573 /* XXX use micro_max()?? */
2574 micro_lt(&d[chan_index], &r[0], &r[1], &r[1], &r[0] );
2575 }
2576 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2577 STORE(&d[chan_index], 0, chan_index);
2578 }
2579 break;
2580
2581 case TGSI_OPCODE_SLT:
2582 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2583 break;
2584
2585 case TGSI_OPCODE_SGE:
2586 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2587 break;
2588
2589 case TGSI_OPCODE_MAD:
2590 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2591 break;
2592
2593 case TGSI_OPCODE_SUB:
2594 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2595 FETCH(&r[0], 0, chan_index);
2596 FETCH(&r[1], 1, chan_index);
2597 micro_sub(&d[chan_index], &r[0], &r[1]);
2598 }
2599 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2600 STORE(&d[chan_index], 0, chan_index);
2601 }
2602 break;
2603
2604 case TGSI_OPCODE_LRP:
2605 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2606 break;
2607
2608 case TGSI_OPCODE_CND:
2609 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2610 FETCH(&r[0], 0, chan_index);
2611 FETCH(&r[1], 1, chan_index);
2612 FETCH(&r[2], 2, chan_index);
2613 micro_lt(&d[chan_index], &mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C], &r[2], &r[0], &r[1]);
2614 }
2615 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2616 STORE(&d[chan_index], 0, chan_index);
2617 }
2618 break;
2619
2620 case TGSI_OPCODE_DP2A:
2621 exec_dp2a(mach, inst);
2622 break;
2623
2624 case TGSI_OPCODE_FRC:
2625 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2626 break;
2627
2628 case TGSI_OPCODE_CLAMP:
2629 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2630 FETCH(&r[0], 0, chan_index);
2631 FETCH(&r[1], 1, chan_index);
2632 micro_max(&r[0], &r[0], &r[1]);
2633 FETCH(&r[1], 2, chan_index);
2634 micro_min(&d[chan_index], &r[0], &r[1]);
2635 }
2636 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2637 STORE(&d[chan_index], 0, chan_index);
2638 }
2639 break;
2640
2641 case TGSI_OPCODE_FLR:
2642 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2643 break;
2644
2645 case TGSI_OPCODE_ROUND:
2646 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2647 break;
2648
2649 case TGSI_OPCODE_EX2:
2650 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2651 break;
2652
2653 case TGSI_OPCODE_LG2:
2654 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2655 break;
2656
2657 case TGSI_OPCODE_POW:
2658 FETCH(&r[0], 0, CHAN_X);
2659 FETCH(&r[1], 1, CHAN_X);
2660
2661 micro_pow( &r[0], &r[0], &r[1] );
2662
2663 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2664 STORE( &r[0], 0, chan_index );
2665 }
2666 break;
2667
2668 case TGSI_OPCODE_XPD:
2669 FETCH(&r[0], 0, CHAN_Y);
2670 FETCH(&r[1], 1, CHAN_Z);
2671
2672 micro_mul( &r[2], &r[0], &r[1] );
2673
2674 FETCH(&r[3], 0, CHAN_Z);
2675 FETCH(&r[4], 1, CHAN_Y);
2676
2677 micro_mul( &r[5], &r[3], &r[4] );
2678 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2679
2680 FETCH(&r[2], 1, CHAN_X);
2681
2682 micro_mul( &r[3], &r[3], &r[2] );
2683
2684 FETCH(&r[5], 0, CHAN_X);
2685
2686 micro_mul( &r[1], &r[1], &r[5] );
2687 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2688
2689 micro_mul( &r[5], &r[5], &r[4] );
2690 micro_mul( &r[0], &r[0], &r[2] );
2691 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2692
2693 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2694 STORE(&d[CHAN_X], 0, CHAN_X);
2695 }
2696 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2697 STORE(&d[CHAN_Y], 0, CHAN_Y);
2698 }
2699 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2700 STORE(&d[CHAN_Z], 0, CHAN_Z);
2701 }
2702 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2703 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2704 }
2705 break;
2706
2707 case TGSI_OPCODE_ABS:
2708 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2709 break;
2710
2711 case TGSI_OPCODE_RCC:
2712 FETCH(&r[0], 0, CHAN_X);
2713 micro_div(&r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0]);
2714 micro_float_clamp(&r[0], &r[0]);
2715 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2716 STORE(&r[0], 0, chan_index);
2717 }
2718 break;
2719
2720 case TGSI_OPCODE_DPH:
2721 exec_dph(mach, inst);
2722 break;
2723
2724 case TGSI_OPCODE_COS:
2725 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2726 break;
2727
2728 case TGSI_OPCODE_DDX:
2729 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2730 break;
2731
2732 case TGSI_OPCODE_DDY:
2733 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2734 break;
2735
2736 case TGSI_OPCODE_KILP:
2737 exec_kilp (mach, inst);
2738 break;
2739
2740 case TGSI_OPCODE_KIL:
2741 exec_kil (mach, inst);
2742 break;
2743
2744 case TGSI_OPCODE_PK2H:
2745 assert (0);
2746 break;
2747
2748 case TGSI_OPCODE_PK2US:
2749 assert (0);
2750 break;
2751
2752 case TGSI_OPCODE_PK4B:
2753 assert (0);
2754 break;
2755
2756 case TGSI_OPCODE_PK4UB:
2757 assert (0);
2758 break;
2759
2760 case TGSI_OPCODE_RFL:
2761 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2762 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2763 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2764 /* r0 = dp3(src0, src0) */
2765 FETCH(&r[2], 0, CHAN_X);
2766 micro_mul(&r[0], &r[2], &r[2]);
2767 FETCH(&r[4], 0, CHAN_Y);
2768 micro_mul(&r[8], &r[4], &r[4]);
2769 micro_add(&r[0], &r[0], &r[8]);
2770 FETCH(&r[6], 0, CHAN_Z);
2771 micro_mul(&r[8], &r[6], &r[6]);
2772 micro_add(&r[0], &r[0], &r[8]);
2773
2774 /* r1 = dp3(src0, src1) */
2775 FETCH(&r[3], 1, CHAN_X);
2776 micro_mul(&r[1], &r[2], &r[3]);
2777 FETCH(&r[5], 1, CHAN_Y);
2778 micro_mul(&r[8], &r[4], &r[5]);
2779 micro_add(&r[1], &r[1], &r[8]);
2780 FETCH(&r[7], 1, CHAN_Z);
2781 micro_mul(&r[8], &r[6], &r[7]);
2782 micro_add(&r[1], &r[1], &r[8]);
2783
2784 /* r1 = 2 * r1 / r0 */
2785 micro_add(&r[1], &r[1], &r[1]);
2786 micro_div(&r[1], &r[1], &r[0]);
2787
2788 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2789 micro_mul(&r[2], &r[2], &r[1]);
2790 micro_sub(&r[2], &r[2], &r[3]);
2791 STORE(&r[2], 0, CHAN_X);
2792 }
2793 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2794 micro_mul(&r[4], &r[4], &r[1]);
2795 micro_sub(&r[4], &r[4], &r[5]);
2796 STORE(&r[4], 0, CHAN_Y);
2797 }
2798 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2799 micro_mul(&r[6], &r[6], &r[1]);
2800 micro_sub(&r[6], &r[6], &r[7]);
2801 STORE(&r[6], 0, CHAN_Z);
2802 }
2803 }
2804 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2805 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
2806 }
2807 break;
2808
2809 case TGSI_OPCODE_SEQ:
2810 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2811 break;
2812
2813 case TGSI_OPCODE_SFL:
2814 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2815 STORE(&mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, chan_index);
2816 }
2817 break;
2818
2819 case TGSI_OPCODE_SGT:
2820 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2821 break;
2822
2823 case TGSI_OPCODE_SIN:
2824 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2825 break;
2826
2827 case TGSI_OPCODE_SLE:
2828 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2829 break;
2830
2831 case TGSI_OPCODE_SNE:
2832 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2833 break;
2834
2835 case TGSI_OPCODE_STR:
2836 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2837 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, chan_index);
2838 }
2839 break;
2840
2841 case TGSI_OPCODE_TEX:
2842 /* simple texture lookup */
2843 /* src[0] = texcoord */
2844 /* src[1] = sampler unit */
2845 exec_tex(mach, inst, TEX_MODIFIER_NONE);
2846 break;
2847
2848 case TGSI_OPCODE_TXB:
2849 /* Texture lookup with lod bias */
2850 /* src[0] = texcoord (src[0].w = LOD bias) */
2851 /* src[1] = sampler unit */
2852 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
2853 break;
2854
2855 case TGSI_OPCODE_TXD:
2856 /* Texture lookup with explict partial derivatives */
2857 /* src[0] = texcoord */
2858 /* src[1] = d[strq]/dx */
2859 /* src[2] = d[strq]/dy */
2860 /* src[3] = sampler unit */
2861 exec_txd(mach, inst);
2862 break;
2863
2864 case TGSI_OPCODE_TXL:
2865 /* Texture lookup with explit LOD */
2866 /* src[0] = texcoord (src[0].w = LOD) */
2867 /* src[1] = sampler unit */
2868 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
2869 break;
2870
2871 case TGSI_OPCODE_TXP:
2872 /* Texture lookup with projection */
2873 /* src[0] = texcoord (src[0].w = projection) */
2874 /* src[1] = sampler unit */
2875 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
2876 break;
2877
2878 case TGSI_OPCODE_UP2H:
2879 assert (0);
2880 break;
2881
2882 case TGSI_OPCODE_UP2US:
2883 assert (0);
2884 break;
2885
2886 case TGSI_OPCODE_UP4B:
2887 assert (0);
2888 break;
2889
2890 case TGSI_OPCODE_UP4UB:
2891 assert (0);
2892 break;
2893
2894 case TGSI_OPCODE_X2D:
2895 FETCH(&r[0], 1, CHAN_X);
2896 FETCH(&r[1], 1, CHAN_Y);
2897 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2898 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2899 FETCH(&r[2], 2, CHAN_X);
2900 micro_mul(&r[2], &r[2], &r[0]);
2901 FETCH(&r[3], 2, CHAN_Y);
2902 micro_mul(&r[3], &r[3], &r[1]);
2903 micro_add(&r[2], &r[2], &r[3]);
2904 FETCH(&r[3], 0, CHAN_X);
2905 micro_add(&d[CHAN_X], &r[2], &r[3]);
2906
2907 }
2908 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2909 IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2910 FETCH(&r[2], 2, CHAN_Z);
2911 micro_mul(&r[2], &r[2], &r[0]);
2912 FETCH(&r[3], 2, CHAN_W);
2913 micro_mul(&r[3], &r[3], &r[1]);
2914 micro_add(&r[2], &r[2], &r[3]);
2915 FETCH(&r[3], 0, CHAN_Y);
2916 micro_add(&d[CHAN_Y], &r[2], &r[3]);
2917
2918 }
2919 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2920 STORE(&d[CHAN_X], 0, CHAN_X);
2921 }
2922 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2923 STORE(&d[CHAN_Y], 0, CHAN_Y);
2924 }
2925 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2926 STORE(&d[CHAN_X], 0, CHAN_Z);
2927 }
2928 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2929 STORE(&d[CHAN_Y], 0, CHAN_W);
2930 }
2931 break;
2932
2933 case TGSI_OPCODE_ARA:
2934 assert (0);
2935 break;
2936
2937 case TGSI_OPCODE_ARR:
2938 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2939 break;
2940
2941 case TGSI_OPCODE_BRA:
2942 assert (0);
2943 break;
2944
2945 case TGSI_OPCODE_CAL:
2946 /* skip the call if no execution channels are enabled */
2947 if (mach->ExecMask) {
2948 /* do the call */
2949
2950 /* First, record the depths of the execution stacks.
2951 * This is important for deeply nested/looped return statements.
2952 * We have to unwind the stacks by the correct amount. For a
2953 * real code generator, we could determine the number of entries
2954 * to pop off each stack with simple static analysis and avoid
2955 * implementing this data structure at run time.
2956 */
2957 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
2958 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
2959 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
2960 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
2961 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
2962 /* note that PC was already incremented above */
2963 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
2964
2965 mach->CallStackTop++;
2966
2967 /* Second, push the Cond, Loop, Cont, Func stacks */
2968 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
2969 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2970 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2971 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2972 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2973 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
2974
2975 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
2976 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
2977 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
2978 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2979 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2980 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
2981
2982 /* Finally, jump to the subroutine */
2983 *pc = inst->Label.Label;
2984 }
2985 break;
2986
2987 case TGSI_OPCODE_RET:
2988 mach->FuncMask &= ~mach->ExecMask;
2989 UPDATE_EXEC_MASK(mach);
2990
2991 if (mach->FuncMask == 0x0) {
2992 /* really return now (otherwise, keep executing */
2993
2994 if (mach->CallStackTop == 0) {
2995 /* returning from main() */
2996 *pc = -1;
2997 return;
2998 }
2999
3000 assert(mach->CallStackTop > 0);
3001 mach->CallStackTop--;
3002
3003 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3004 mach->CondMask = mach->CondStack[mach->CondStackTop];
3005
3006 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3007 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3008
3009 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3010 mach->ContMask = mach->ContStack[mach->ContStackTop];
3011
3012 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3013 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3014
3015 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3016 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3017
3018 assert(mach->FuncStackTop > 0);
3019 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3020
3021 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3022
3023 UPDATE_EXEC_MASK(mach);
3024 }
3025 break;
3026
3027 case TGSI_OPCODE_SSG:
3028 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3029 break;
3030
3031 case TGSI_OPCODE_CMP:
3032 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3033 FETCH(&r[0], 0, chan_index);
3034 FETCH(&r[1], 1, chan_index);
3035 FETCH(&r[2], 2, chan_index);
3036 micro_lt(&d[chan_index], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[1], &r[2]);
3037 }
3038 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3039 STORE(&d[chan_index], 0, chan_index);
3040 }
3041 break;
3042
3043 case TGSI_OPCODE_SCS:
3044 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
3045 FETCH( &r[0], 0, CHAN_X );
3046 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3047 micro_cos(&r[1], &r[0]);
3048 STORE(&r[1], 0, CHAN_X);
3049 }
3050 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3051 micro_sin(&r[1], &r[0]);
3052 STORE(&r[1], 0, CHAN_Y);
3053 }
3054 }
3055 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
3056 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
3057 }
3058 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
3059 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
3060 }
3061 break;
3062
3063 case TGSI_OPCODE_NRM:
3064 /* 3-component vector normalize */
3065 if(IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
3066 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
3067 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3068 /* r3 = sqrt(dp3(src0, src0)) */
3069 FETCH(&r[0], 0, CHAN_X);
3070 micro_mul(&r[3], &r[0], &r[0]);
3071 FETCH(&r[1], 0, CHAN_Y);
3072 micro_mul(&r[4], &r[1], &r[1]);
3073 micro_add(&r[3], &r[3], &r[4]);
3074 FETCH(&r[2], 0, CHAN_Z);
3075 micro_mul(&r[4], &r[2], &r[2]);
3076 micro_add(&r[3], &r[3], &r[4]);
3077 micro_sqrt(&r[3], &r[3]);
3078
3079 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3080 micro_div(&r[0], &r[0], &r[3]);
3081 STORE(&r[0], 0, CHAN_X);
3082 }
3083 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3084 micro_div(&r[1], &r[1], &r[3]);
3085 STORE(&r[1], 0, CHAN_Y);
3086 }
3087 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
3088 micro_div(&r[2], &r[2], &r[3]);
3089 STORE(&r[2], 0, CHAN_Z);
3090 }
3091 }
3092 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
3093 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
3094 }
3095 break;
3096
3097 case TGSI_OPCODE_NRM4:
3098 /* 4-component vector normalize */
3099 {
3100 union tgsi_exec_channel tmp, dot;
3101
3102 /* tmp = dp4(src0, src0): */
3103 FETCH( &r[0], 0, CHAN_X );
3104 micro_mul( &tmp, &r[0], &r[0] );
3105
3106 FETCH( &r[1], 0, CHAN_Y );
3107 micro_mul( &dot, &r[1], &r[1] );
3108 micro_add( &tmp, &tmp, &dot );
3109
3110 FETCH( &r[2], 0, CHAN_Z );
3111 micro_mul( &dot, &r[2], &r[2] );
3112 micro_add( &tmp, &tmp, &dot );
3113
3114 FETCH( &r[3], 0, CHAN_W );
3115 micro_mul( &dot, &r[3], &r[3] );
3116 micro_add( &tmp, &tmp, &dot );
3117
3118 /* tmp = 1 / sqrt(tmp) */
3119 micro_sqrt( &tmp, &tmp );
3120 micro_div( &tmp, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &tmp );
3121
3122 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3123 /* chan = chan * tmp */
3124 micro_mul( &r[chan_index], &tmp, &r[chan_index] );
3125 STORE( &r[chan_index], 0, chan_index );
3126 }
3127 }
3128 break;
3129
3130 case TGSI_OPCODE_DIV:
3131 assert( 0 );
3132 break;
3133
3134 case TGSI_OPCODE_DP2:
3135 exec_dp2(mach, inst);
3136 break;
3137
3138 case TGSI_OPCODE_IF:
3139 /* push CondMask */
3140 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3141 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3142 FETCH( &r[0], 0, CHAN_X );
3143 /* update CondMask */
3144 if( ! r[0].u[0] ) {
3145 mach->CondMask &= ~0x1;
3146 }
3147 if( ! r[0].u[1] ) {
3148 mach->CondMask &= ~0x2;
3149 }
3150 if( ! r[0].u[2] ) {
3151 mach->CondMask &= ~0x4;
3152 }
3153 if( ! r[0].u[3] ) {
3154 mach->CondMask &= ~0x8;
3155 }
3156 UPDATE_EXEC_MASK(mach);
3157 /* Todo: If CondMask==0, jump to ELSE */
3158 break;
3159
3160 case TGSI_OPCODE_ELSE:
3161 /* invert CondMask wrt previous mask */
3162 {
3163 uint prevMask;
3164 assert(mach->CondStackTop > 0);
3165 prevMask = mach->CondStack[mach->CondStackTop - 1];
3166 mach->CondMask = ~mach->CondMask & prevMask;
3167 UPDATE_EXEC_MASK(mach);
3168 /* Todo: If CondMask==0, jump to ENDIF */
3169 }
3170 break;
3171
3172 case TGSI_OPCODE_ENDIF:
3173 /* pop CondMask */
3174 assert(mach->CondStackTop > 0);
3175 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3176 UPDATE_EXEC_MASK(mach);
3177 break;
3178
3179 case TGSI_OPCODE_END:
3180 /* halt execution */
3181 *pc = -1;
3182 break;
3183
3184 case TGSI_OPCODE_REP:
3185 assert (0);
3186 break;
3187
3188 case TGSI_OPCODE_ENDREP:
3189 assert (0);
3190 break;
3191
3192 case TGSI_OPCODE_PUSHA:
3193 assert (0);
3194 break;
3195
3196 case TGSI_OPCODE_POPA:
3197 assert (0);
3198 break;
3199
3200 case TGSI_OPCODE_CEIL:
3201 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3202 break;
3203
3204 case TGSI_OPCODE_I2F:
3205 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3206 break;
3207
3208 case TGSI_OPCODE_NOT:
3209 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3210 break;
3211
3212 case TGSI_OPCODE_TRUNC:
3213 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3214 break;
3215
3216 case TGSI_OPCODE_SHL:
3217 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3218 break;
3219
3220 case TGSI_OPCODE_AND:
3221 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3222 break;
3223
3224 case TGSI_OPCODE_OR:
3225 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3226 break;
3227
3228 case TGSI_OPCODE_MOD:
3229 assert (0);
3230 break;
3231
3232 case TGSI_OPCODE_XOR:
3233 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3234 break;
3235
3236 case TGSI_OPCODE_SAD:
3237 assert (0);
3238 break;
3239
3240 case TGSI_OPCODE_TXF:
3241 assert (0);
3242 break;
3243
3244 case TGSI_OPCODE_TXQ:
3245 assert (0);
3246 break;
3247
3248 case TGSI_OPCODE_EMIT:
3249 emit_vertex(mach);
3250 break;
3251
3252 case TGSI_OPCODE_ENDPRIM:
3253 emit_primitive(mach);
3254 break;
3255
3256 case TGSI_OPCODE_BGNFOR:
3257 assert(mach->LoopCounterStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3258 for (chan_index = 0; chan_index < 3; chan_index++) {
3259 FETCH( &mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[chan_index], 0, chan_index );
3260 }
3261 ++mach->LoopCounterStackTop;
3262 STORE(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X], 0, CHAN_X);
3263 /* update LoopMask */
3264 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[0] <= 0.0f) {
3265 mach->LoopMask &= ~0x1;
3266 }
3267 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[1] <= 0.0f) {
3268 mach->LoopMask &= ~0x2;
3269 }
3270 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[2] <= 0.0f) {
3271 mach->LoopMask &= ~0x4;
3272 }
3273 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[3] <= 0.0f) {
3274 mach->LoopMask &= ~0x8;
3275 }
3276 /* TODO: if mach->LoopMask == 0, jump to end of loop */
3277 UPDATE_EXEC_MASK(mach);
3278 /* fall-through (for now) */
3279 case TGSI_OPCODE_BGNLOOP:
3280 /* push LoopMask and ContMasks */
3281 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3282 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3283 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3284 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3285
3286 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3287 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3288 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3289 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3290 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3291 break;
3292
3293 case TGSI_OPCODE_ENDFOR:
3294 assert(mach->LoopCounterStackTop > 0);
3295 micro_sub(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y],
3296 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y],
3297 &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C]);
3298 /* update LoopMask */
3299 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[0] <= 0.0f) {
3300 mach->LoopMask &= ~0x1;
3301 }
3302 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[1] <= 0.0f) {
3303 mach->LoopMask &= ~0x2;
3304 }
3305 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[2] <= 0.0f) {
3306 mach->LoopMask &= ~0x4;
3307 }
3308 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[3] <= 0.0f) {
3309 mach->LoopMask &= ~0x8;
3310 }
3311 micro_add(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X],
3312 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X],
3313 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Z]);
3314 assert(mach->LoopLabelStackTop > 0);
3315 inst = mach->Instructions + mach->LoopLabelStack[mach->LoopLabelStackTop - 1];
3316 STORE(&mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[CHAN_X], 0, CHAN_X);
3317 /* Restore ContMask, but don't pop */
3318 assert(mach->ContStackTop > 0);
3319 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3320 UPDATE_EXEC_MASK(mach);
3321 if (mach->ExecMask) {
3322 /* repeat loop: jump to instruction just past BGNLOOP */
3323 assert(mach->LoopLabelStackTop > 0);
3324 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3325 }
3326 else {
3327 /* exit loop: pop LoopMask */
3328 assert(mach->LoopStackTop > 0);
3329 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3330 /* pop ContMask */
3331 assert(mach->ContStackTop > 0);
3332 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3333 assert(mach->LoopLabelStackTop > 0);
3334 --mach->LoopLabelStackTop;
3335 assert(mach->LoopCounterStackTop > 0);
3336 --mach->LoopCounterStackTop;
3337
3338 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3339 }
3340 UPDATE_EXEC_MASK(mach);
3341 break;
3342
3343 case TGSI_OPCODE_ENDLOOP:
3344 /* Restore ContMask, but don't pop */
3345 assert(mach->ContStackTop > 0);
3346 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3347 UPDATE_EXEC_MASK(mach);
3348 if (mach->ExecMask) {
3349 /* repeat loop: jump to instruction just past BGNLOOP */
3350 assert(mach->LoopLabelStackTop > 0);
3351 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3352 }
3353 else {
3354 /* exit loop: pop LoopMask */
3355 assert(mach->LoopStackTop > 0);
3356 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3357 /* pop ContMask */
3358 assert(mach->ContStackTop > 0);
3359 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3360 assert(mach->LoopLabelStackTop > 0);
3361 --mach->LoopLabelStackTop;
3362
3363 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3364 }
3365 UPDATE_EXEC_MASK(mach);
3366 break;
3367
3368 case TGSI_OPCODE_BRK:
3369 exec_break(mach);
3370 break;
3371
3372 case TGSI_OPCODE_CONT:
3373 /* turn off cont channels for each enabled exec channel */
3374 mach->ContMask &= ~mach->ExecMask;
3375 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3376 UPDATE_EXEC_MASK(mach);
3377 break;
3378
3379 case TGSI_OPCODE_BGNSUB:
3380 /* no-op */
3381 break;
3382
3383 case TGSI_OPCODE_ENDSUB:
3384 /*
3385 * XXX: This really should be a no-op. We should never reach this opcode.
3386 */
3387
3388 assert(mach->CallStackTop > 0);
3389 mach->CallStackTop--;
3390
3391 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3392 mach->CondMask = mach->CondStack[mach->CondStackTop];
3393
3394 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3395 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3396
3397 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3398 mach->ContMask = mach->ContStack[mach->ContStackTop];
3399
3400 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3401 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3402
3403 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3404 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3405
3406 assert(mach->FuncStackTop > 0);
3407 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3408
3409 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3410
3411 UPDATE_EXEC_MASK(mach);
3412 break;
3413
3414 case TGSI_OPCODE_NOP:
3415 break;
3416
3417 case TGSI_OPCODE_BREAKC:
3418 FETCH(&r[0], 0, CHAN_X);
3419 /* update CondMask */
3420 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3421 mach->LoopMask &= ~0x1;
3422 }
3423 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3424 mach->LoopMask &= ~0x2;
3425 }
3426 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3427 mach->LoopMask &= ~0x4;
3428 }
3429 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3430 mach->LoopMask &= ~0x8;
3431 }
3432 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3433 UPDATE_EXEC_MASK(mach);
3434 break;
3435
3436 case TGSI_OPCODE_F2I:
3437 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3438 break;
3439
3440 case TGSI_OPCODE_IDIV:
3441 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3442 break;
3443
3444 case TGSI_OPCODE_IMAX:
3445 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3446 break;
3447
3448 case TGSI_OPCODE_IMIN:
3449 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3450 break;
3451
3452 case TGSI_OPCODE_INEG:
3453 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3454 break;
3455
3456 case TGSI_OPCODE_ISGE:
3457 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3458 break;
3459
3460 case TGSI_OPCODE_ISHR:
3461 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3462 break;
3463
3464 case TGSI_OPCODE_ISLT:
3465 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3466 break;
3467
3468 case TGSI_OPCODE_F2U:
3469 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3470 break;
3471
3472 case TGSI_OPCODE_U2F:
3473 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
3474 break;
3475
3476 case TGSI_OPCODE_UADD:
3477 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3478 break;
3479
3480 case TGSI_OPCODE_UDIV:
3481 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3482 break;
3483
3484 case TGSI_OPCODE_UMAD:
3485 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3486 break;
3487
3488 case TGSI_OPCODE_UMAX:
3489 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3490 break;
3491
3492 case TGSI_OPCODE_UMIN:
3493 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3494 break;
3495
3496 case TGSI_OPCODE_UMOD:
3497 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3498 break;
3499
3500 case TGSI_OPCODE_UMUL:
3501 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3502 break;
3503
3504 case TGSI_OPCODE_USEQ:
3505 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3506 break;
3507
3508 case TGSI_OPCODE_USGE:
3509 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3510 break;
3511
3512 case TGSI_OPCODE_USHR:
3513 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3514 break;
3515
3516 case TGSI_OPCODE_USLT:
3517 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3518 break;
3519
3520 case TGSI_OPCODE_USNE:
3521 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3522 break;
3523
3524 case TGSI_OPCODE_SWITCH:
3525 exec_switch(mach, inst);
3526 break;
3527
3528 case TGSI_OPCODE_CASE:
3529 exec_case(mach, inst);
3530 break;
3531
3532 case TGSI_OPCODE_DEFAULT:
3533 exec_default(mach);
3534 break;
3535
3536 case TGSI_OPCODE_ENDSWITCH:
3537 exec_endswitch(mach);
3538 break;
3539
3540 default:
3541 assert( 0 );
3542 }
3543 }
3544
3545
3546 #define DEBUG_EXECUTION 0
3547
3548
3549 /**
3550 * Run TGSI interpreter.
3551 * \return bitmask of "alive" quad components
3552 */
3553 uint
3554 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3555 {
3556 uint i;
3557 int pc = 0;
3558
3559 mach->CondMask = 0xf;
3560 mach->LoopMask = 0xf;
3561 mach->ContMask = 0xf;
3562 mach->FuncMask = 0xf;
3563 mach->ExecMask = 0xf;
3564
3565 mach->Switch.mask = 0xf;
3566
3567 assert(mach->CondStackTop == 0);
3568 assert(mach->LoopStackTop == 0);
3569 assert(mach->ContStackTop == 0);
3570 assert(mach->SwitchStackTop == 0);
3571 assert(mach->BreakStackTop == 0);
3572 assert(mach->CallStackTop == 0);
3573
3574 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3575 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3576
3577 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3578 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3579 mach->Primitives[0] = 0;
3580 }
3581
3582 for (i = 0; i < QUAD_SIZE; i++) {
3583 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
3584 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
3585 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
3586 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
3587 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
3588 }
3589
3590 /* execute declarations (interpolants) */
3591 for (i = 0; i < mach->NumDeclarations; i++) {
3592 exec_declaration( mach, mach->Declarations+i );
3593 }
3594
3595 {
3596 #if DEBUG_EXECUTION
3597 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
3598 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
3599 uint inst = 1;
3600
3601 memcpy(temps, mach->Temps, sizeof(temps));
3602 memcpy(outputs, mach->Outputs, sizeof(outputs));
3603 #endif
3604
3605 /* execute instructions, until pc is set to -1 */
3606 while (pc != -1) {
3607
3608 #if DEBUG_EXECUTION
3609 uint i;
3610
3611 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
3612 #endif
3613
3614 assert(pc < (int) mach->NumInstructions);
3615 exec_instruction(mach, mach->Instructions + pc, &pc);
3616
3617 #if DEBUG_EXECUTION
3618 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
3619 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
3620 uint j;
3621
3622 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
3623 debug_printf("TEMP[%2u] = ", i);
3624 for (j = 0; j < 4; j++) {
3625 if (j > 0) {
3626 debug_printf(" ");
3627 }
3628 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3629 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
3630 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
3631 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
3632 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
3633 }
3634 }
3635 }
3636 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
3637 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
3638 uint j;
3639
3640 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
3641 debug_printf("OUT[%2u] = ", i);
3642 for (j = 0; j < 4; j++) {
3643 if (j > 0) {
3644 debug_printf(" ");
3645 }
3646 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3647 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
3648 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
3649 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
3650 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
3651 }
3652 }
3653 }
3654 #endif
3655 }
3656 }
3657
3658 #if 0
3659 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3660 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3661 /*
3662 * Scale back depth component.
3663 */
3664 for (i = 0; i < 4; i++)
3665 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3666 }
3667 #endif
3668
3669 assert(mach->CondStackTop == 0);
3670 assert(mach->LoopStackTop == 0);
3671 assert(mach->ContStackTop == 0);
3672 assert(mach->SwitchStackTop == 0);
3673 assert(mach->BreakStackTop == 0);
3674 assert(mach->CallStackTop == 0);
3675
3676 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3677 }