2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "tgsi/tgsi_transform.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_dump.h"
31 #include "util/u_debug.h"
32 #include "util/u_math.h"
34 #include "tgsi_lowering.h"
36 struct tgsi_lowering_context
{
37 struct tgsi_transform_context base
;
38 const struct tgsi_lowering_config
*config
;
39 struct tgsi_shader_info
*info
;
40 unsigned two_side_colors
;
41 unsigned two_side_idx
[PIPE_MAX_SHADER_INPUTS
];
42 unsigned color_base
; /* base register for chosen COLOR/BCOLOR's */
46 struct tgsi_full_src_register src
;
47 struct tgsi_full_dst_register dst
;
51 struct tgsi_full_src_register imm
;
56 static inline struct tgsi_lowering_context
*
57 tgsi_lowering_context(struct tgsi_transform_context
*tctx
)
59 return (struct tgsi_lowering_context
*)tctx
;
67 reg_dst(struct tgsi_full_dst_register
*dst
,
68 const struct tgsi_full_dst_register
*orig_dst
, unsigned wrmask
)
71 dst
->Register
.WriteMask
&= wrmask
;
72 assert(dst
->Register
.WriteMask
);
76 get_swiz(unsigned *swiz
, const struct tgsi_src_register
*src
)
78 swiz
[0] = src
->SwizzleX
;
79 swiz
[1] = src
->SwizzleY
;
80 swiz
[2] = src
->SwizzleZ
;
81 swiz
[3] = src
->SwizzleW
;
85 reg_src(struct tgsi_full_src_register
*src
,
86 const struct tgsi_full_src_register
*orig_src
,
87 unsigned sx
, unsigned sy
, unsigned sz
, unsigned sw
)
90 get_swiz(swiz
, &orig_src
->Register
);
92 src
->Register
.SwizzleX
= swiz
[sx
];
93 src
->Register
.SwizzleY
= swiz
[sy
];
94 src
->Register
.SwizzleZ
= swiz
[sz
];
95 src
->Register
.SwizzleW
= swiz
[sw
];
98 #define TGSI_SWIZZLE__ TGSI_SWIZZLE_X /* don't-care value! */
99 #define SWIZ(x,y,z,w) TGSI_SWIZZLE_ ## x, TGSI_SWIZZLE_ ## y, \
100 TGSI_SWIZZLE_ ## z, TGSI_SWIZZLE_ ## w
103 * if (dst.x aliases src.x) {
109 * MOV dst.zw, imm{0.0, 1.0}
112 aliases(const struct tgsi_full_dst_register
*dst
, unsigned dst_mask
,
113 const struct tgsi_full_src_register
*src
, unsigned src_mask
)
115 if ((dst
->Register
.File
== src
->Register
.File
) &&
116 (dst
->Register
.Index
== src
->Register
.Index
)) {
117 unsigned i
, actual_mask
= 0;
119 get_swiz(swiz
, &src
->Register
);
120 for (i
= 0; i
< 4; i
++)
121 if (src_mask
& (1 << i
))
122 actual_mask
|= (1 << swiz
[i
]);
123 if (actual_mask
& dst_mask
)
130 create_mov(struct tgsi_transform_context
*tctx
,
131 const struct tgsi_full_dst_register
*dst
,
132 const struct tgsi_full_src_register
*src
,
133 unsigned mask
, unsigned saturate
)
135 struct tgsi_full_instruction new_inst
;
137 new_inst
= tgsi_default_full_instruction();
138 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
139 new_inst
.Instruction
.Saturate
= saturate
;
140 new_inst
.Instruction
.NumDstRegs
= 1;
141 reg_dst(&new_inst
.Dst
[0], dst
, mask
);
142 new_inst
.Instruction
.NumSrcRegs
= 1;
143 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, Y
, Z
, W
));
144 tctx
->emit_instruction(tctx
, &new_inst
);
147 /* to help calculate # of tgsi tokens for a lowering.. we assume
148 * the worst case, ie. removed instructions don't have ADDR[] or
149 * anything which increases the # of tokens per src/dst and the
150 * inserted instructions do.
152 * OINST() - old instruction
153 * 1 : instruction itself
157 * NINST() - new instruction
158 * 1 : instruction itself
163 #define OINST(nargs) (1 + 1 + 1 * (nargs))
164 #define NINST(nargs) (1 + 2 + 2 * (nargs))
167 * Lowering Translators:
170 /* DST - Distance Vector
172 * dst.y = src0.y \times src1.y
176 * ; note: could be more clever and use just a single temp
177 * ; if I was clever enough to re-write the swizzles.
178 * ; needs: 2 tmp, imm{1.0}
179 * if (dst.y aliases src0.z) {
180 * MOV tmpA.yz, src0.yz
183 * if (dst.yz aliases src1.w) {
184 * MOV tmpB.yw, src1.yw
187 * MUL dst.y, src0.y, src1.y
190 * MOV dst.x, imm{1.0}
192 #define DST_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1) + \
193 NINST(1) + NINST(1) - OINST(2))
196 transform_dst(struct tgsi_transform_context
*tctx
,
197 struct tgsi_full_instruction
*inst
)
199 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
200 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
201 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
202 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
203 struct tgsi_full_instruction new_inst
;
205 if (aliases(dst
, TGSI_WRITEMASK_Y
, src0
, TGSI_WRITEMASK_Z
)) {
206 create_mov(tctx
, &ctx
->tmp
[A
].dst
, src0
, TGSI_WRITEMASK_YZ
, 0);
207 src0
= &ctx
->tmp
[A
].src
;
210 if (aliases(dst
, TGSI_WRITEMASK_YZ
, src1
, TGSI_WRITEMASK_W
)) {
211 create_mov(tctx
, &ctx
->tmp
[B
].dst
, src1
, TGSI_WRITEMASK_YW
, 0);
212 src1
= &ctx
->tmp
[B
].src
;
215 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
216 /* MUL dst.y, src0.y, src1.y */
217 new_inst
= tgsi_default_full_instruction();
218 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
219 new_inst
.Instruction
.NumDstRegs
= 1;
220 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Y
);
221 new_inst
.Instruction
.NumSrcRegs
= 2;
222 reg_src(&new_inst
.Src
[0], src0
, SWIZ(_
, Y
, _
, _
));
223 reg_src(&new_inst
.Src
[1], src1
, SWIZ(_
, Y
, _
, _
));
224 tctx
->emit_instruction(tctx
, &new_inst
);
227 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
228 /* MOV dst.z, src0.z */
229 new_inst
= tgsi_default_full_instruction();
230 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
231 new_inst
.Instruction
.NumDstRegs
= 1;
232 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Z
);
233 new_inst
.Instruction
.NumSrcRegs
= 1;
234 reg_src(&new_inst
.Src
[0], src0
, SWIZ(_
, _
, Z
, _
));
235 tctx
->emit_instruction(tctx
, &new_inst
);
238 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_W
) {
239 /* MOV dst.w, src1.w */
240 new_inst
= tgsi_default_full_instruction();
241 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
242 new_inst
.Instruction
.NumDstRegs
= 1;
243 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_W
);
244 new_inst
.Instruction
.NumSrcRegs
= 1;
245 reg_src(&new_inst
.Src
[0], src1
, SWIZ(_
, _
, _
, W
));
246 tctx
->emit_instruction(tctx
, &new_inst
);
249 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_X
) {
250 /* MOV dst.x, imm{1.0} */
251 new_inst
= tgsi_default_full_instruction();
252 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
253 new_inst
.Instruction
.NumDstRegs
= 1;
254 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_X
);
255 new_inst
.Instruction
.NumSrcRegs
= 1;
256 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(Y
, _
, _
, _
));
257 tctx
->emit_instruction(tctx
, &new_inst
);
261 /* XPD - Cross Product
262 * dst.x = src0.y \times src1.z - src1.y \times src0.z
263 * dst.y = src0.z \times src1.x - src1.z \times src0.x
264 * dst.z = src0.x \times src1.y - src1.x \times src0.y
267 * ; needs: 1 tmp, imm{1.0}
268 * MUL tmpA.xyz, src1.yzx, src0.zxy
269 * MAD dst.xyz, src0.yzx, src1.zxy, -tmpA.xyz
270 * MOV dst.w, imm{1.0}
272 #define XPD_GROW (NINST(2) + NINST(3) + NINST(1) - OINST(2))
275 transform_xpd(struct tgsi_transform_context
*tctx
,
276 struct tgsi_full_instruction
*inst
)
278 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
279 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
280 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
281 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
282 struct tgsi_full_instruction new_inst
;
284 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
285 /* MUL tmpA.xyz, src1.yzx, src0.zxy */
286 new_inst
= tgsi_default_full_instruction();
287 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
288 new_inst
.Instruction
.NumDstRegs
= 1;
289 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZ
);
290 new_inst
.Instruction
.NumSrcRegs
= 2;
291 reg_src(&new_inst
.Src
[0], src1
, SWIZ(Y
, Z
, X
, _
));
292 reg_src(&new_inst
.Src
[1], src0
, SWIZ(Z
, X
, Y
, _
));
293 tctx
->emit_instruction(tctx
, &new_inst
);
295 /* MAD dst.xyz, src0.yzx, src1.zxy, -tmpA.xyz */
296 new_inst
= tgsi_default_full_instruction();
297 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
298 new_inst
.Instruction
.NumDstRegs
= 1;
299 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZ
);
300 new_inst
.Instruction
.NumSrcRegs
= 3;
301 reg_src(&new_inst
.Src
[0], src0
, SWIZ(Y
, Z
, X
, _
));
302 reg_src(&new_inst
.Src
[1], src1
, SWIZ(Z
, X
, Y
, _
));
303 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, _
));
304 new_inst
.Src
[2].Register
.Negate
= true;
305 tctx
->emit_instruction(tctx
, &new_inst
);
308 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_W
) {
309 /* MOV dst.w, imm{1.0} */
310 new_inst
= tgsi_default_full_instruction();
311 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
312 new_inst
.Instruction
.NumDstRegs
= 1;
313 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_W
);
314 new_inst
.Instruction
.NumSrcRegs
= 1;
315 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(_
, _
, _
, Y
));
316 tctx
->emit_instruction(tctx
, &new_inst
);
321 * dst.x = \cos{src.x}
322 * dst.y = \sin{src.x}
326 * ; needs: 1 tmp, imm{0.0, 1.0}
327 * if (dst.x aliases src.x) {
333 * MOV dst.zw, imm{0.0, 1.0}
335 #define SCS_GROW (NINST(1) + NINST(1) + NINST(1) + NINST(1) - OINST(1))
338 transform_scs(struct tgsi_transform_context
*tctx
,
339 struct tgsi_full_instruction
*inst
)
341 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
342 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
343 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
344 struct tgsi_full_instruction new_inst
;
346 if (aliases(dst
, TGSI_WRITEMASK_X
, src
, TGSI_WRITEMASK_X
)) {
347 create_mov(tctx
, &ctx
->tmp
[A
].dst
, src
, TGSI_WRITEMASK_X
, 0);
348 src
= &ctx
->tmp
[A
].src
;
351 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_X
) {
352 /* COS dst.x, src.x */
353 new_inst
= tgsi_default_full_instruction();
354 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_COS
;
355 new_inst
.Instruction
.NumDstRegs
= 1;
356 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_X
);
357 new_inst
.Instruction
.NumSrcRegs
= 1;
358 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
359 tctx
->emit_instruction(tctx
, &new_inst
);
362 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
363 /* SIN dst.y, src.x */
364 new_inst
= tgsi_default_full_instruction();
365 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SIN
;
366 new_inst
.Instruction
.NumDstRegs
= 1;
367 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Y
);
368 new_inst
.Instruction
.NumSrcRegs
= 1;
369 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
370 tctx
->emit_instruction(tctx
, &new_inst
);
373 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_ZW
) {
374 /* MOV dst.zw, imm{0.0, 1.0} */
375 new_inst
= tgsi_default_full_instruction();
376 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
377 new_inst
.Instruction
.NumDstRegs
= 1;
378 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_ZW
);
379 new_inst
.Instruction
.NumSrcRegs
= 1;
380 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(_
, _
, X
, Y
));
381 tctx
->emit_instruction(tctx
, &new_inst
);
385 /* LRP - Linear Interpolate
386 * dst.x = src0.x \times src1.x + (1.0 - src0.x) \times src2.x
387 * dst.y = src0.y \times src1.y + (1.0 - src0.y) \times src2.y
388 * dst.z = src0.z \times src1.z + (1.0 - src0.z) \times src2.z
389 * dst.w = src0.w \times src1.w + (1.0 - src0.w) \times src2.w
391 * This becomes: src0 \times src1 + src2 - src0 \times src2, which
392 * can then become: src0 \times src1 - (src0 \times src2 - src2)
395 * MAD tmpA, src0, src2, -src2
396 * MAD dst, src0, src1, -tmpA
398 #define LRP_GROW (NINST(3) + NINST(3) - OINST(3))
401 transform_lrp(struct tgsi_transform_context
*tctx
,
402 struct tgsi_full_instruction
*inst
)
404 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
405 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
406 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
407 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
408 struct tgsi_full_src_register
*src2
= &inst
->Src
[2];
409 struct tgsi_full_instruction new_inst
;
411 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
412 /* MAD tmpA, src0, src2, -src2 */
413 new_inst
= tgsi_default_full_instruction();
414 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
415 new_inst
.Instruction
.NumDstRegs
= 1;
416 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
417 new_inst
.Instruction
.NumSrcRegs
= 3;
418 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
419 reg_src(&new_inst
.Src
[1], src2
, SWIZ(X
, Y
, Z
, W
));
420 reg_src(&new_inst
.Src
[2], src2
, SWIZ(X
, Y
, Z
, W
));
421 new_inst
.Src
[2].Register
.Negate
= !new_inst
.Src
[2].Register
.Negate
;
422 tctx
->emit_instruction(tctx
, &new_inst
);
424 /* MAD dst, src0, src1, -tmpA */
425 new_inst
= tgsi_default_full_instruction();
426 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
427 new_inst
.Instruction
.NumDstRegs
= 1;
428 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
429 new_inst
.Instruction
.NumSrcRegs
= 3;
430 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
431 reg_src(&new_inst
.Src
[1], src1
, SWIZ(X
, Y
, Z
, W
));
432 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
433 new_inst
.Src
[2].Register
.Negate
= true;
434 tctx
->emit_instruction(tctx
, &new_inst
);
439 * dst.x = src.x - \lfloor src.x\rfloor
440 * dst.y = src.y - \lfloor src.y\rfloor
441 * dst.z = src.z - \lfloor src.z\rfloor
442 * dst.w = src.w - \lfloor src.w\rfloor
448 #define FRC_GROW (NINST(1) + NINST(2) - OINST(1))
451 transform_frc(struct tgsi_transform_context
*tctx
,
452 struct tgsi_full_instruction
*inst
)
454 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
455 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
456 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
457 struct tgsi_full_instruction new_inst
;
459 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
461 new_inst
= tgsi_default_full_instruction();
462 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FLR
;
463 new_inst
.Instruction
.NumDstRegs
= 1;
464 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
465 new_inst
.Instruction
.NumSrcRegs
= 1;
466 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, Y
, Z
, W
));
467 tctx
->emit_instruction(tctx
, &new_inst
);
469 /* SUB dst, src, tmpA */
470 new_inst
= tgsi_default_full_instruction();
471 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
472 new_inst
.Instruction
.NumDstRegs
= 1;
473 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
474 new_inst
.Instruction
.NumSrcRegs
= 2;
475 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, Y
, Z
, W
));
476 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
477 tctx
->emit_instruction(tctx
, &new_inst
);
482 * dst.x = src0.x^{src1.x}
483 * dst.y = src0.x^{src1.x}
484 * dst.z = src0.x^{src1.x}
485 * dst.w = src0.x^{src1.x}
489 * MUL tmpA.x, src1.x, tmpA.x
492 #define POW_GROW (NINST(1) + NINST(2) + NINST(1) - OINST(2))
495 transform_pow(struct tgsi_transform_context
*tctx
,
496 struct tgsi_full_instruction
*inst
)
498 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
499 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
500 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
501 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
502 struct tgsi_full_instruction new_inst
;
504 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
505 /* LG2 tmpA.x, src0.x */
506 new_inst
= tgsi_default_full_instruction();
507 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_LG2
;
508 new_inst
.Instruction
.NumDstRegs
= 1;
509 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
510 new_inst
.Instruction
.NumSrcRegs
= 1;
511 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, _
, _
, _
));
512 tctx
->emit_instruction(tctx
, &new_inst
);
514 /* MUL tmpA.x, src1.x, tmpA.x */
515 new_inst
= tgsi_default_full_instruction();
516 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
517 new_inst
.Instruction
.NumDstRegs
= 1;
518 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
519 new_inst
.Instruction
.NumSrcRegs
= 2;
520 reg_src(&new_inst
.Src
[0], src1
, SWIZ(X
, _
, _
, _
));
521 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, _
, _
, _
));
522 tctx
->emit_instruction(tctx
, &new_inst
);
524 /* EX2 dst, tmpA.x */
525 new_inst
= tgsi_default_full_instruction();
526 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
527 new_inst
.Instruction
.NumDstRegs
= 1;
528 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
529 new_inst
.Instruction
.NumSrcRegs
= 1;
530 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(X
, _
, _
, _
));
531 tctx
->emit_instruction(tctx
, &new_inst
);
535 /* LIT - Light Coefficients
537 * dst.y = max(src.x, 0.0)
538 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
541 * ; needs: 1 tmp, imm{0.0}, imm{1.0}, imm{128.0}
542 * MAX tmpA.xy, src.xy, imm{0.0}
543 * CLAMP tmpA.z, src.w, -imm{128.0}, imm{128.0}
545 * MUL tmpA.y, tmpA.z, tmpA.y
547 * CMP tmpA.y, -src.x, tmpA.y, imm{0.0}
548 * MOV dst.yz, tmpA.xy
549 * MOV dst.xw, imm{1.0}
551 #define LIT_GROW (NINST(1) + NINST(3) + NINST(1) + NINST(2) + \
552 NINST(1) + NINST(3) + NINST(1) + NINST(1) - OINST(1))
555 transform_lit(struct tgsi_transform_context
*tctx
,
556 struct tgsi_full_instruction
*inst
)
558 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
559 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
560 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
561 struct tgsi_full_instruction new_inst
;
563 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
564 /* MAX tmpA.xy, src.xy, imm{0.0} */
565 new_inst
= tgsi_default_full_instruction();
566 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAX
;
567 new_inst
.Instruction
.NumDstRegs
= 1;
568 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XY
);
569 new_inst
.Instruction
.NumSrcRegs
= 2;
570 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, Y
, _
, _
));
571 reg_src(&new_inst
.Src
[1], &ctx
->imm
, SWIZ(X
, X
, _
, _
));
572 tctx
->emit_instruction(tctx
, &new_inst
);
574 /* CLAMP tmpA.z, src.w, -imm{128.0}, imm{128.0} */
575 new_inst
= tgsi_default_full_instruction();
576 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_CLAMP
;
577 new_inst
.Instruction
.NumDstRegs
= 1;
578 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Z
);
579 new_inst
.Instruction
.NumSrcRegs
= 3;
580 reg_src(&new_inst
.Src
[0], src
, SWIZ(_
, _
, W
, _
));
581 reg_src(&new_inst
.Src
[1], &ctx
->imm
, SWIZ(_
, _
, Z
, _
));
582 new_inst
.Src
[1].Register
.Negate
= true;
583 reg_src(&new_inst
.Src
[2], &ctx
->imm
, SWIZ(_
, _
, Z
, _
));
584 tctx
->emit_instruction(tctx
, &new_inst
);
586 /* LG2 tmpA.y, tmpA.y */
587 new_inst
= tgsi_default_full_instruction();
588 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_LG2
;
589 new_inst
.Instruction
.NumDstRegs
= 1;
590 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
591 new_inst
.Instruction
.NumSrcRegs
= 1;
592 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Y
, _
, _
, _
));
593 tctx
->emit_instruction(tctx
, &new_inst
);
595 /* MUL tmpA.y, tmpA.z, tmpA.y */
596 new_inst
= tgsi_default_full_instruction();
597 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
598 new_inst
.Instruction
.NumDstRegs
= 1;
599 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
600 new_inst
.Instruction
.NumSrcRegs
= 2;
601 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, Z
, _
, _
));
602 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, Y
, _
, _
));
603 tctx
->emit_instruction(tctx
, &new_inst
);
605 /* EX2 tmpA.y, tmpA.y */
606 new_inst
= tgsi_default_full_instruction();
607 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
608 new_inst
.Instruction
.NumDstRegs
= 1;
609 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
610 new_inst
.Instruction
.NumSrcRegs
= 1;
611 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Y
, _
, _
, _
));
612 tctx
->emit_instruction(tctx
, &new_inst
);
614 /* CMP tmpA.y, -src.x, tmpA.y, imm{0.0} */
615 new_inst
= tgsi_default_full_instruction();
616 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_CMP
;
617 new_inst
.Instruction
.NumDstRegs
= 1;
618 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
619 new_inst
.Instruction
.NumSrcRegs
= 3;
620 reg_src(&new_inst
.Src
[0], src
, SWIZ(_
, X
, _
, _
));
621 new_inst
.Src
[0].Register
.Negate
= true;
622 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, Y
, _
, _
));
623 reg_src(&new_inst
.Src
[2], &ctx
->imm
, SWIZ(_
, X
, _
, _
));
624 tctx
->emit_instruction(tctx
, &new_inst
);
626 /* MOV dst.yz, tmpA.xy */
627 new_inst
= tgsi_default_full_instruction();
628 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
629 new_inst
.Instruction
.NumDstRegs
= 1;
630 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_YZ
);
631 new_inst
.Instruction
.NumSrcRegs
= 1;
632 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, Y
, _
));
633 tctx
->emit_instruction(tctx
, &new_inst
);
636 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XW
) {
637 /* MOV dst.xw, imm{1.0} */
638 new_inst
= tgsi_default_full_instruction();
639 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
640 new_inst
.Instruction
.NumDstRegs
= 1;
641 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XW
);
642 new_inst
.Instruction
.NumSrcRegs
= 1;
643 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(Y
, _
, _
, Y
));
644 tctx
->emit_instruction(tctx
, &new_inst
);
648 /* EXP - Approximate Exponential Base 2
649 * dst.x = 2^{\lfloor src.x\rfloor}
650 * dst.y = src.x - \lfloor src.x\rfloor
654 * ; needs: 1 tmp, imm{1.0}
655 * if (lowering FLR) {
657 * SUB tmpA.x, src.x, tmpA.x
662 * SUB dst.y, src.x, tmpA.x
665 * MOV dst.w, imm{1.0}
667 #define EXP_GROW (NINST(1) + NINST(2) + NINST(1) + NINST(2) + NINST(1) + \
668 NINST(1)+ NINST(1) - OINST(1))
671 transform_exp(struct tgsi_transform_context
*tctx
,
672 struct tgsi_full_instruction
*inst
)
674 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
675 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
676 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
677 struct tgsi_full_instruction new_inst
;
679 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
680 if (ctx
->config
->lower_FLR
) {
681 /* FRC tmpA.x, src.x */
682 new_inst
= tgsi_default_full_instruction();
683 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FRC
;
684 new_inst
.Instruction
.NumDstRegs
= 1;
685 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
686 new_inst
.Instruction
.NumSrcRegs
= 1;
687 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
688 tctx
->emit_instruction(tctx
, &new_inst
);
690 /* SUB tmpA.x, src.x, tmpA.x */
691 new_inst
= tgsi_default_full_instruction();
692 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
693 new_inst
.Instruction
.NumDstRegs
= 1;
694 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
695 new_inst
.Instruction
.NumSrcRegs
= 2;
696 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
697 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, _
, _
, _
));
698 tctx
->emit_instruction(tctx
, &new_inst
);
700 /* FLR tmpA.x, src.x */
701 new_inst
= tgsi_default_full_instruction();
702 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FLR
;
703 new_inst
.Instruction
.NumDstRegs
= 1;
704 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
705 new_inst
.Instruction
.NumSrcRegs
= 1;
706 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
707 tctx
->emit_instruction(tctx
, &new_inst
);
711 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
712 /* EX2 tmpA.y, src.x */
713 new_inst
= tgsi_default_full_instruction();
714 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
715 new_inst
.Instruction
.NumDstRegs
= 1;
716 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
717 new_inst
.Instruction
.NumSrcRegs
= 1;
718 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
719 tctx
->emit_instruction(tctx
, &new_inst
);
722 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
723 /* SUB dst.y, src.x, tmpA.x */
724 new_inst
= tgsi_default_full_instruction();
725 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
726 new_inst
.Instruction
.NumDstRegs
= 1;
727 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Y
);
728 new_inst
.Instruction
.NumSrcRegs
= 2;
729 reg_src(&new_inst
.Src
[0], src
, SWIZ(_
, X
, _
, _
));
730 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, _
, _
));
731 tctx
->emit_instruction(tctx
, &new_inst
);
734 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_X
) {
735 /* EX2 dst.x, tmpA.x */
736 new_inst
= tgsi_default_full_instruction();
737 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
738 new_inst
.Instruction
.NumDstRegs
= 1;
739 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_X
);
740 new_inst
.Instruction
.NumSrcRegs
= 1;
741 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(X
, _
, _
, _
));
742 tctx
->emit_instruction(tctx
, &new_inst
);
745 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
746 /* MOV dst.z, tmpA.y */
747 new_inst
= tgsi_default_full_instruction();
748 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
749 new_inst
.Instruction
.NumDstRegs
= 1;
750 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Z
);
751 new_inst
.Instruction
.NumSrcRegs
= 1;
752 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, _
, Y
, _
));
753 tctx
->emit_instruction(tctx
, &new_inst
);
756 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_W
) {
757 /* MOV dst.w, imm{1.0} */
758 new_inst
= tgsi_default_full_instruction();
759 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
760 new_inst
.Instruction
.NumDstRegs
= 1;
761 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_W
);
762 new_inst
.Instruction
.NumSrcRegs
= 1;
763 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(_
, _
, _
, Y
));
764 tctx
->emit_instruction(tctx
, &new_inst
);
768 /* LOG - Approximate Logarithm Base 2
769 * dst.x = \lfloor\log_2{|src.x|}\rfloor
770 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
771 * dst.z = \log_2{|src.x|}
774 * ; needs: 1 tmp, imm{1.0}
775 * LG2 tmpA.x, |src.x|
776 * if (lowering FLR) {
778 * SUB tmpA.y, tmpA.x, tmpA.y
784 * MUL dst.y, |src.x|, tmpA.z
785 * MOV dst.xz, tmpA.yx
786 * MOV dst.w, imm{1.0}
788 #define LOG_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1) + NINST(1) + \
789 NINST(2) + NINST(1) + NINST(1) - OINST(1))
792 transform_log(struct tgsi_transform_context
*tctx
,
793 struct tgsi_full_instruction
*inst
)
795 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
796 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
797 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
798 struct tgsi_full_instruction new_inst
;
800 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
801 /* LG2 tmpA.x, |src.x| */
802 new_inst
= tgsi_default_full_instruction();
803 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_LG2
;
804 new_inst
.Instruction
.NumDstRegs
= 1;
805 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
806 new_inst
.Instruction
.NumSrcRegs
= 1;
807 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
808 new_inst
.Src
[0].Register
.Absolute
= true;
809 tctx
->emit_instruction(tctx
, &new_inst
);
812 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
813 if (ctx
->config
->lower_FLR
) {
814 /* FRC tmpA.y, tmpA.x */
815 new_inst
= tgsi_default_full_instruction();
816 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FRC
;
817 new_inst
.Instruction
.NumDstRegs
= 1;
818 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
819 new_inst
.Instruction
.NumSrcRegs
= 1;
820 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, _
, _
));
821 tctx
->emit_instruction(tctx
, &new_inst
);
823 /* SUB tmpA.y, tmpA.x, tmpA.y */
824 new_inst
= tgsi_default_full_instruction();
825 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
826 new_inst
.Instruction
.NumDstRegs
= 1;
827 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
828 new_inst
.Instruction
.NumSrcRegs
= 2;
829 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, _
, _
));
830 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, Y
, _
, _
));
831 tctx
->emit_instruction(tctx
, &new_inst
);
833 /* FLR tmpA.y, tmpA.x */
834 new_inst
= tgsi_default_full_instruction();
835 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FLR
;
836 new_inst
.Instruction
.NumDstRegs
= 1;
837 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
838 new_inst
.Instruction
.NumSrcRegs
= 1;
839 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, _
, _
));
840 tctx
->emit_instruction(tctx
, &new_inst
);
844 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
845 /* EX2 tmpA.z, tmpA.y */
846 new_inst
= tgsi_default_full_instruction();
847 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
848 new_inst
.Instruction
.NumDstRegs
= 1;
849 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Z
);
850 new_inst
.Instruction
.NumSrcRegs
= 1;
851 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Y
, _
, _
, _
));
852 tctx
->emit_instruction(tctx
, &new_inst
);
854 /* RCP tmpA.z, tmpA.z */
855 new_inst
= tgsi_default_full_instruction();
856 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_RCP
;
857 new_inst
.Instruction
.NumDstRegs
= 1;
858 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Z
);
859 new_inst
.Instruction
.NumSrcRegs
= 1;
860 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Z
, _
, _
, _
));
861 tctx
->emit_instruction(tctx
, &new_inst
);
863 /* MUL dst.y, |src.x|, tmpA.z */
864 new_inst
= tgsi_default_full_instruction();
865 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
866 new_inst
.Instruction
.NumDstRegs
= 1;
867 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Y
);
868 new_inst
.Instruction
.NumSrcRegs
= 2;
869 reg_src(&new_inst
.Src
[0], src
, SWIZ(_
, X
, _
, _
));
870 new_inst
.Src
[0].Register
.Absolute
= true;
871 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, Z
, _
, _
));
872 tctx
->emit_instruction(tctx
, &new_inst
);
875 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XZ
) {
876 /* MOV dst.xz, tmpA.yx */
877 new_inst
= tgsi_default_full_instruction();
878 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
879 new_inst
.Instruction
.NumDstRegs
= 1;
880 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XZ
);
881 new_inst
.Instruction
.NumSrcRegs
= 1;
882 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Y
, _
, X
, _
));
883 tctx
->emit_instruction(tctx
, &new_inst
);
886 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_W
) {
887 /* MOV dst.w, imm{1.0} */
888 new_inst
= tgsi_default_full_instruction();
889 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
890 new_inst
.Instruction
.NumDstRegs
= 1;
891 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_W
);
892 new_inst
.Instruction
.NumSrcRegs
= 1;
893 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(_
, _
, _
, Y
));
894 tctx
->emit_instruction(tctx
, &new_inst
);
898 /* DP4 - 4-component Dot Product
899 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z + src0.w \times src1.w
901 * DP3 - 3-component Dot Product
902 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z
904 * DPH - Homogeneous Dot Product
905 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z + src1.w
907 * DP2 - 2-component Dot Product
908 * dst = src0.x \times src1.x + src0.y \times src1.y
910 * DP2A - 2-component Dot Product And Add
911 * dst = src0.x \times src1.x + src0.y \times src1.y + src2.x
913 * NOTE: these are translated into sequence of MUL/MAD(/ADD) scalar
914 * operations, which is what you'd prefer for a ISA that is natively
915 * scalar. Probably a native vector ISA would at least already have
916 * DP4/DP3 instructions, but perhaps there is room for an alternative
917 * translation for DPH/DP2/DP2A using vector instructions.
920 * MUL tmpA.x, src0.x, src1.x
921 * MAD tmpA.x, src0.y, src1.y, tmpA.x
922 * if (DPH || DP3 || DP4) {
923 * MAD tmpA.x, src0.z, src1.z, tmpA.x
925 * ADD tmpA.x, src1.w, tmpA.x
927 * MAD tmpA.x, src0.w, src1.w, tmpA.x
930 * ADD tmpA.x, src2.x, tmpA.x
932 * ; fixup last instruction to replicate into dst
934 #define DP4_GROW (NINST(2) + NINST(3) + NINST(3) + NINST(3) - OINST(2))
935 #define DP3_GROW (NINST(2) + NINST(3) + NINST(3) - OINST(2))
936 #define DPH_GROW (NINST(2) + NINST(3) + NINST(3) + NINST(2) - OINST(2))
937 #define DP2_GROW (NINST(2) + NINST(3) - OINST(2))
938 #define DP2A_GROW (NINST(2) + NINST(3) + NINST(2) - OINST(3))
941 transform_dotp(struct tgsi_transform_context
*tctx
,
942 struct tgsi_full_instruction
*inst
)
944 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
945 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
946 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
947 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
948 struct tgsi_full_src_register
*src2
= &inst
->Src
[2]; /* only DP2A */
949 struct tgsi_full_instruction new_inst
;
950 unsigned opcode
= inst
->Instruction
.Opcode
;
952 /* NOTE: any potential last instruction must replicate src on all
953 * components (since it could be re-written to write to final dst)
956 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
957 /* MUL tmpA.x, src0.x, src1.x */
958 new_inst
= tgsi_default_full_instruction();
959 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
960 new_inst
.Instruction
.NumDstRegs
= 1;
961 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
962 new_inst
.Instruction
.NumSrcRegs
= 2;
963 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, _
, _
, _
));
964 reg_src(&new_inst
.Src
[1], src1
, SWIZ(X
, _
, _
, _
));
965 tctx
->emit_instruction(tctx
, &new_inst
);
967 /* MAD tmpA.x, src0.y, src1.y, tmpA.x */
968 new_inst
= tgsi_default_full_instruction();
969 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
970 new_inst
.Instruction
.NumDstRegs
= 1;
971 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
972 new_inst
.Instruction
.NumSrcRegs
= 3;
973 reg_src(&new_inst
.Src
[0], src0
, SWIZ(Y
, Y
, Y
, Y
));
974 reg_src(&new_inst
.Src
[1], src1
, SWIZ(Y
, Y
, Y
, Y
));
975 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
977 if ((opcode
== TGSI_OPCODE_DPH
) ||
978 (opcode
== TGSI_OPCODE_DP3
) ||
979 (opcode
== TGSI_OPCODE_DP4
)) {
980 tctx
->emit_instruction(tctx
, &new_inst
);
982 /* MAD tmpA.x, src0.z, src1.z, tmpA.x */
983 new_inst
= tgsi_default_full_instruction();
984 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
985 new_inst
.Instruction
.NumDstRegs
= 1;
986 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
987 new_inst
.Instruction
.NumSrcRegs
= 3;
988 reg_src(&new_inst
.Src
[0], src0
, SWIZ(Z
, Z
, Z
, Z
));
989 reg_src(&new_inst
.Src
[1], src1
, SWIZ(Z
, Z
, Z
, Z
));
990 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
992 if (opcode
== TGSI_OPCODE_DPH
) {
993 tctx
->emit_instruction(tctx
, &new_inst
);
995 /* ADD tmpA.x, src1.w, tmpA.x */
996 new_inst
= tgsi_default_full_instruction();
997 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_ADD
;
998 new_inst
.Instruction
.NumDstRegs
= 1;
999 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
1000 new_inst
.Instruction
.NumSrcRegs
= 2;
1001 reg_src(&new_inst
.Src
[0], src1
, SWIZ(W
, W
, W
, W
));
1002 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
1003 } else if (opcode
== TGSI_OPCODE_DP4
) {
1004 tctx
->emit_instruction(tctx
, &new_inst
);
1006 /* MAD tmpA.x, src0.w, src1.w, tmpA.x */
1007 new_inst
= tgsi_default_full_instruction();
1008 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
1009 new_inst
.Instruction
.NumDstRegs
= 1;
1010 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
1011 new_inst
.Instruction
.NumSrcRegs
= 3;
1012 reg_src(&new_inst
.Src
[0], src0
, SWIZ(W
, W
, W
, W
));
1013 reg_src(&new_inst
.Src
[1], src1
, SWIZ(W
, W
, W
, W
));
1014 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
1016 } else if (opcode
== TGSI_OPCODE_DP2A
) {
1017 tctx
->emit_instruction(tctx
, &new_inst
);
1019 /* ADD tmpA.x, src2.x, tmpA.x */
1020 new_inst
= tgsi_default_full_instruction();
1021 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_ADD
;
1022 new_inst
.Instruction
.NumDstRegs
= 1;
1023 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
1024 new_inst
.Instruction
.NumSrcRegs
= 2;
1025 reg_src(&new_inst
.Src
[0], src2
, SWIZ(X
, X
, X
, X
));
1026 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
1029 /* fixup last instruction to write to dst: */
1030 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
1032 tctx
->emit_instruction(tctx
, &new_inst
);
1036 /* FLR - floor, CEIL - ceil
1040 * ADD dst, src, tmpA
1043 * SUB dst, src, tmpA
1046 #define FLR_GROW (NINST(1) + NINST(2) - OINST(1))
1047 #define CEIL_GROW (NINST(1) + NINST(2) - OINST(1))
1051 transform_flr_ceil(struct tgsi_transform_context
*tctx
,
1052 struct tgsi_full_instruction
*inst
)
1054 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1055 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
1056 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
1057 struct tgsi_full_instruction new_inst
;
1058 unsigned opcode
= inst
->Instruction
.Opcode
;
1060 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
1061 /* FLR: FRC tmpA, src CEIL: FRC tmpA, -src */
1062 new_inst
= tgsi_default_full_instruction();
1063 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FRC
;
1064 new_inst
.Instruction
.NumDstRegs
= 1;
1065 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
1066 new_inst
.Instruction
.NumSrcRegs
= 1;
1067 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
1069 if (opcode
== TGSI_OPCODE_CEIL
)
1070 new_inst
.Src
[0].Register
.Negate
= !new_inst
.Src
[0].Register
.Negate
;
1071 tctx
->emit_instruction(tctx
, &new_inst
);
1073 /* FLR: SUB dst, src, tmpA CEIL: ADD dst, src, tmpA */
1074 new_inst
= tgsi_default_full_instruction();
1075 if (opcode
== TGSI_OPCODE_CEIL
)
1076 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_ADD
;
1078 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
1079 new_inst
.Instruction
.NumDstRegs
= 1;
1080 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
1081 new_inst
.Instruction
.NumSrcRegs
= 2;
1082 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
1083 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
1084 tctx
->emit_instruction(tctx
, &new_inst
);
1088 /* TRUNC - truncate off fractional part
1089 * dst.x = trunc(src.x)
1090 * dst.y = trunc(src.y)
1091 * dst.z = trunc(src.z)
1092 * dst.w = trunc(src.w)
1097 * SUB tmpA, |src|, tmpA
1101 * CMP dst, src, -tmpA, tmpA
1103 #define TRUNC_GROW (NINST(1) + NINST(2) + NINST(3) - OINST(1))
1106 transform_trunc(struct tgsi_transform_context
*tctx
,
1107 struct tgsi_full_instruction
*inst
)
1109 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1110 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
1111 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
1112 struct tgsi_full_instruction new_inst
;
1114 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
1115 if (ctx
->config
->lower_FLR
) {
1116 new_inst
= tgsi_default_full_instruction();
1117 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FRC
;
1118 new_inst
.Instruction
.NumDstRegs
= 1;
1119 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
1120 new_inst
.Instruction
.NumSrcRegs
= 1;
1121 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
1122 new_inst
.Src
[0].Register
.Absolute
= true;
1123 new_inst
.Src
[0].Register
.Negate
= false;
1124 tctx
->emit_instruction(tctx
, &new_inst
);
1126 new_inst
= tgsi_default_full_instruction();
1127 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
1128 new_inst
.Instruction
.NumDstRegs
= 1;
1129 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
1130 new_inst
.Instruction
.NumSrcRegs
= 2;
1131 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
1132 new_inst
.Src
[0].Register
.Absolute
= true;
1133 new_inst
.Src
[0].Register
.Negate
= false;
1134 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
1135 tctx
->emit_instruction(tctx
, &new_inst
);
1137 new_inst
= tgsi_default_full_instruction();
1138 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FLR
;
1139 new_inst
.Instruction
.NumDstRegs
= 1;
1140 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
1141 new_inst
.Instruction
.NumSrcRegs
= 1;
1142 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
1143 new_inst
.Src
[0].Register
.Absolute
= true;
1144 new_inst
.Src
[0].Register
.Negate
= false;
1145 tctx
->emit_instruction(tctx
, &new_inst
);
1148 new_inst
= tgsi_default_full_instruction();
1149 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_CMP
;
1150 new_inst
.Instruction
.NumDstRegs
= 1;
1151 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
1152 new_inst
.Instruction
.NumSrcRegs
= 3;
1153 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
1154 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
1155 new_inst
.Src
[1].Register
.Negate
= true;
1156 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
1157 tctx
->emit_instruction(tctx
, &new_inst
);
1161 /* Inserts a MOV_SAT for the needed components of tex coord. Note that
1162 * in the case of TXP, the clamping must happen *after* projection, so
1163 * we need to lower TXP to TEX.
1167 * ; do perspective division manually before clamping:
1169 * MUL tmpB.<pmask>, tmpA, tmpB.xxxx
1172 * MOV_SAT tmpA.<mask>, tmpA ; <mask> is the clamped s/t/r coords
1173 * <opc> dst, tmpA, ...
1175 #define SAMP_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1))
1178 transform_samp(struct tgsi_transform_context
*tctx
,
1179 struct tgsi_full_instruction
*inst
)
1181 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1182 struct tgsi_full_src_register
*coord
= &inst
->Src
[0];
1183 struct tgsi_full_src_register
*samp
;
1184 struct tgsi_full_instruction new_inst
;
1185 /* mask is clamped coords, pmask is all coords (for projection): */
1186 unsigned mask
= 0, pmask
= 0, smask
;
1187 unsigned tex
= inst
->Texture
.Texture
;
1188 unsigned opcode
= inst
->Instruction
.Opcode
;
1189 bool lower_txp
= (opcode
== TGSI_OPCODE_TXP
) &&
1190 (ctx
->config
->lower_TXP
& (1 << tex
));
1192 if (opcode
== TGSI_OPCODE_TXB2
) {
1193 samp
= &inst
->Src
[2];
1195 samp
= &inst
->Src
[1];
1198 /* convert sampler # to bitmask to test: */
1199 smask
= 1 << samp
->Register
.Index
;
1201 /* check if we actually need to lower this one: */
1202 if (!(ctx
->saturate
& smask
) && !lower_txp
)
1205 /* figure out which coordinates need saturating:
1206 * - RECT textures should not get saturated
1207 * - array index coords should not get saturated
1210 case TGSI_TEXTURE_3D
:
1211 case TGSI_TEXTURE_CUBE
:
1212 case TGSI_TEXTURE_CUBE_ARRAY
:
1213 case TGSI_TEXTURE_SHADOWCUBE
:
1214 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1215 if (ctx
->config
->saturate_r
& smask
)
1216 mask
|= TGSI_WRITEMASK_Z
;
1217 pmask
|= TGSI_WRITEMASK_Z
;
1220 case TGSI_TEXTURE_2D
:
1221 case TGSI_TEXTURE_2D_ARRAY
:
1222 case TGSI_TEXTURE_SHADOW2D
:
1223 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1224 case TGSI_TEXTURE_2D_MSAA
:
1225 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
1226 if (ctx
->config
->saturate_t
& smask
)
1227 mask
|= TGSI_WRITEMASK_Y
;
1228 pmask
|= TGSI_WRITEMASK_Y
;
1231 case TGSI_TEXTURE_1D
:
1232 case TGSI_TEXTURE_1D_ARRAY
:
1233 case TGSI_TEXTURE_SHADOW1D
:
1234 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1235 if (ctx
->config
->saturate_s
& smask
)
1236 mask
|= TGSI_WRITEMASK_X
;
1237 pmask
|= TGSI_WRITEMASK_X
;
1240 case TGSI_TEXTURE_RECT
:
1241 case TGSI_TEXTURE_SHADOWRECT
:
1242 /* we don't saturate, but in case of lower_txp we
1243 * still need to do the perspective divide:
1245 pmask
= TGSI_WRITEMASK_XY
;
1249 /* sanity check.. driver could be asking to saturate a non-
1250 * existent coordinate component:
1252 if (!mask
&& !lower_txp
)
1255 /* MOV tmpA, src0 */
1256 create_mov(tctx
, &ctx
->tmp
[A
].dst
, coord
, TGSI_WRITEMASK_XYZW
, 0);
1258 /* This is a bit sad.. we need to clamp *after* the coords
1259 * are projected, which means lowering TXP to TEX and doing
1260 * the projection ourself. But since I haven't figured out
1261 * how to make the lowering code deliver an electric shock
1262 * to anyone using GL_CLAMP, we must do this instead:
1264 if (opcode
== TGSI_OPCODE_TXP
) {
1265 /* RCP tmpB.x tmpA.w */
1266 new_inst
= tgsi_default_full_instruction();
1267 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_RCP
;
1268 new_inst
.Instruction
.NumDstRegs
= 1;
1269 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[B
].dst
, TGSI_WRITEMASK_X
);
1270 new_inst
.Instruction
.NumSrcRegs
= 1;
1271 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(W
, _
, _
, _
));
1272 tctx
->emit_instruction(tctx
, &new_inst
);
1274 /* MUL tmpA.mask, tmpA, tmpB.xxxx */
1275 new_inst
= tgsi_default_full_instruction();
1276 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
1277 new_inst
.Instruction
.NumDstRegs
= 1;
1278 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, pmask
);
1279 new_inst
.Instruction
.NumSrcRegs
= 2;
1280 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
1281 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[B
].src
, SWIZ(X
, X
, X
, X
));
1282 tctx
->emit_instruction(tctx
, &new_inst
);
1284 opcode
= TGSI_OPCODE_TEX
;
1287 /* MOV_SAT tmpA.<mask>, tmpA */
1289 create_mov(tctx
, &ctx
->tmp
[A
].dst
, &ctx
->tmp
[A
].src
, mask
, 1);
1292 /* modify the texture samp instruction to take fixed up coord: */
1294 new_inst
.Instruction
.Opcode
= opcode
;
1295 new_inst
.Src
[0] = ctx
->tmp
[A
].src
;
1296 tctx
->emit_instruction(tctx
, &new_inst
);
1301 /* Two-sided color emulation:
1302 * For each COLOR input, create a corresponding BCOLOR input, plus
1303 * CMP instruction to select front or back color based on FACE
1305 #define TWOSIDE_GROW(n) ( \
1307 ((n) * 3) + /* IN[], BCOLOR[n], <intrp> */\
1308 ((n) * 1) + /* TEMP[] */ \
1309 ((n) * NINST(3)) /* CMP instr */ \
1313 emit_twoside(struct tgsi_transform_context
*tctx
)
1315 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1316 struct tgsi_shader_info
*info
= ctx
->info
;
1317 struct tgsi_full_declaration decl
;
1318 struct tgsi_full_instruction new_inst
;
1319 unsigned inbase
, tmpbase
;
1322 inbase
= info
->file_max
[TGSI_FILE_INPUT
] + 1;
1323 tmpbase
= info
->file_max
[TGSI_FILE_TEMPORARY
] + 1;
1325 /* additional inputs for BCOLOR's */
1326 for (i
= 0; i
< ctx
->two_side_colors
; i
++) {
1327 unsigned in_idx
= ctx
->two_side_idx
[i
];
1328 decl
= tgsi_default_full_declaration();
1329 decl
.Declaration
.File
= TGSI_FILE_INPUT
;
1330 decl
.Declaration
.Semantic
= true;
1331 decl
.Range
.First
= decl
.Range
.Last
= inbase
+ i
;
1332 decl
.Semantic
.Name
= TGSI_SEMANTIC_BCOLOR
;
1333 decl
.Semantic
.Index
= info
->input_semantic_index
[in_idx
];
1334 decl
.Declaration
.Interpolate
= true;
1335 decl
.Interp
.Interpolate
= info
->input_interpolate
[in_idx
];
1336 decl
.Interp
.Location
= info
->input_interpolate_loc
[in_idx
];
1337 decl
.Interp
.CylindricalWrap
= info
->input_cylindrical_wrap
[in_idx
];
1338 tctx
->emit_declaration(tctx
, &decl
);
1341 /* additional input for FACE */
1342 if (ctx
->two_side_colors
&& (ctx
->face_idx
== -1)) {
1343 decl
= tgsi_default_full_declaration();
1344 decl
.Declaration
.File
= TGSI_FILE_INPUT
;
1345 decl
.Declaration
.Semantic
= true;
1346 decl
.Range
.First
= decl
.Range
.Last
= inbase
+ ctx
->two_side_colors
;
1347 decl
.Semantic
.Name
= TGSI_SEMANTIC_FACE
;
1348 decl
.Semantic
.Index
= 0;
1349 tctx
->emit_declaration(tctx
, &decl
);
1351 ctx
->face_idx
= decl
.Range
.First
;
1354 /* additional temps for COLOR/BCOLOR selection: */
1355 for (i
= 0; i
< ctx
->two_side_colors
; i
++) {
1356 decl
= tgsi_default_full_declaration();
1357 decl
.Declaration
.File
= TGSI_FILE_TEMPORARY
;
1358 decl
.Range
.First
= decl
.Range
.Last
= tmpbase
+ ctx
->numtmp
+ i
;
1359 tctx
->emit_declaration(tctx
, &decl
);
1362 /* and finally additional instructions to select COLOR/BCOLOR: */
1363 for (i
= 0; i
< ctx
->two_side_colors
; i
++) {
1364 new_inst
= tgsi_default_full_instruction();
1365 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_CMP
;
1367 new_inst
.Instruction
.NumDstRegs
= 1;
1368 new_inst
.Dst
[0].Register
.File
= TGSI_FILE_TEMPORARY
;
1369 new_inst
.Dst
[0].Register
.Index
= tmpbase
+ ctx
->numtmp
+ i
;
1370 new_inst
.Dst
[0].Register
.WriteMask
= TGSI_WRITEMASK_XYZW
;
1372 new_inst
.Instruction
.NumSrcRegs
= 3;
1373 new_inst
.Src
[0].Register
.File
= TGSI_FILE_INPUT
;
1374 new_inst
.Src
[0].Register
.Index
= ctx
->face_idx
;
1375 new_inst
.Src
[0].Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1376 new_inst
.Src
[0].Register
.SwizzleY
= TGSI_SWIZZLE_X
;
1377 new_inst
.Src
[0].Register
.SwizzleZ
= TGSI_SWIZZLE_X
;
1378 new_inst
.Src
[0].Register
.SwizzleW
= TGSI_SWIZZLE_X
;
1379 new_inst
.Src
[1].Register
.File
= TGSI_FILE_INPUT
;
1380 new_inst
.Src
[1].Register
.Index
= inbase
+ i
;
1381 new_inst
.Src
[1].Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1382 new_inst
.Src
[1].Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1383 new_inst
.Src
[1].Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1384 new_inst
.Src
[1].Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1385 new_inst
.Src
[2].Register
.File
= TGSI_FILE_INPUT
;
1386 new_inst
.Src
[2].Register
.Index
= ctx
->two_side_idx
[i
];
1387 new_inst
.Src
[2].Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1388 new_inst
.Src
[2].Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1389 new_inst
.Src
[2].Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1390 new_inst
.Src
[2].Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1392 tctx
->emit_instruction(tctx
, &new_inst
);
1397 emit_decls(struct tgsi_transform_context
*tctx
)
1399 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1400 struct tgsi_shader_info
*info
= ctx
->info
;
1401 struct tgsi_full_declaration decl
;
1402 struct tgsi_full_immediate immed
;
1406 tmpbase
= info
->file_max
[TGSI_FILE_TEMPORARY
] + 1;
1408 ctx
->color_base
= tmpbase
+ ctx
->numtmp
;
1410 /* declare immediate: */
1411 immed
= tgsi_default_full_immediate();
1412 immed
.Immediate
.NrTokens
= 1 + 4; /* one for the token itself */
1413 immed
.u
[0].Float
= 0.0;
1414 immed
.u
[1].Float
= 1.0;
1415 immed
.u
[2].Float
= 128.0;
1416 immed
.u
[3].Float
= 0.0;
1417 tctx
->emit_immediate(tctx
, &immed
);
1419 ctx
->imm
.Register
.File
= TGSI_FILE_IMMEDIATE
;
1420 ctx
->imm
.Register
.Index
= info
->immediate_count
;
1421 ctx
->imm
.Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1422 ctx
->imm
.Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1423 ctx
->imm
.Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1424 ctx
->imm
.Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1426 /* declare temp regs: */
1427 for (i
= 0; i
< ctx
->numtmp
; i
++) {
1428 decl
= tgsi_default_full_declaration();
1429 decl
.Declaration
.File
= TGSI_FILE_TEMPORARY
;
1430 decl
.Range
.First
= decl
.Range
.Last
= tmpbase
+ i
;
1431 tctx
->emit_declaration(tctx
, &decl
);
1433 ctx
->tmp
[i
].src
.Register
.File
= TGSI_FILE_TEMPORARY
;
1434 ctx
->tmp
[i
].src
.Register
.Index
= tmpbase
+ i
;
1435 ctx
->tmp
[i
].src
.Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1436 ctx
->tmp
[i
].src
.Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1437 ctx
->tmp
[i
].src
.Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1438 ctx
->tmp
[i
].src
.Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1440 ctx
->tmp
[i
].dst
.Register
.File
= TGSI_FILE_TEMPORARY
;
1441 ctx
->tmp
[i
].dst
.Register
.Index
= tmpbase
+ i
;
1442 ctx
->tmp
[i
].dst
.Register
.WriteMask
= TGSI_WRITEMASK_XYZW
;
1445 if (ctx
->two_side_colors
)
1450 rename_color_inputs(struct tgsi_lowering_context
*ctx
,
1451 struct tgsi_full_instruction
*inst
)
1454 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1455 struct tgsi_src_register
*src
= &inst
->Src
[i
].Register
;
1456 if (src
->File
== TGSI_FILE_INPUT
) {
1457 for (j
= 0; j
< ctx
->two_side_colors
; j
++) {
1458 if (src
->Index
== ctx
->two_side_idx
[j
]) {
1459 src
->File
= TGSI_FILE_TEMPORARY
;
1460 src
->Index
= ctx
->color_base
+ j
;
1470 transform_instr(struct tgsi_transform_context
*tctx
,
1471 struct tgsi_full_instruction
*inst
)
1473 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1475 if (!ctx
->emitted_decls
) {
1477 ctx
->emitted_decls
= 1;
1480 /* if emulating two-sided-color, we need to re-write some
1483 if (ctx
->two_side_colors
)
1484 rename_color_inputs(ctx
, inst
);
1486 switch (inst
->Instruction
.Opcode
) {
1487 case TGSI_OPCODE_DST
:
1488 if (!ctx
->config
->lower_DST
)
1490 transform_dst(tctx
, inst
);
1492 case TGSI_OPCODE_XPD
:
1493 if (!ctx
->config
->lower_XPD
)
1495 transform_xpd(tctx
, inst
);
1497 case TGSI_OPCODE_SCS
:
1498 if (!ctx
->config
->lower_SCS
)
1500 transform_scs(tctx
, inst
);
1502 case TGSI_OPCODE_LRP
:
1503 if (!ctx
->config
->lower_LRP
)
1505 transform_lrp(tctx
, inst
);
1507 case TGSI_OPCODE_FRC
:
1508 if (!ctx
->config
->lower_FRC
)
1510 transform_frc(tctx
, inst
);
1512 case TGSI_OPCODE_POW
:
1513 if (!ctx
->config
->lower_POW
)
1515 transform_pow(tctx
, inst
);
1517 case TGSI_OPCODE_LIT
:
1518 if (!ctx
->config
->lower_LIT
)
1520 transform_lit(tctx
, inst
);
1522 case TGSI_OPCODE_EXP
:
1523 if (!ctx
->config
->lower_EXP
)
1525 transform_exp(tctx
, inst
);
1527 case TGSI_OPCODE_LOG
:
1528 if (!ctx
->config
->lower_LOG
)
1530 transform_log(tctx
, inst
);
1532 case TGSI_OPCODE_DP4
:
1533 if (!ctx
->config
->lower_DP4
)
1535 transform_dotp(tctx
, inst
);
1537 case TGSI_OPCODE_DP3
:
1538 if (!ctx
->config
->lower_DP3
)
1540 transform_dotp(tctx
, inst
);
1542 case TGSI_OPCODE_DPH
:
1543 if (!ctx
->config
->lower_DPH
)
1545 transform_dotp(tctx
, inst
);
1547 case TGSI_OPCODE_DP2
:
1548 if (!ctx
->config
->lower_DP2
)
1550 transform_dotp(tctx
, inst
);
1552 case TGSI_OPCODE_DP2A
:
1553 if (!ctx
->config
->lower_DP2A
)
1555 transform_dotp(tctx
, inst
);
1557 case TGSI_OPCODE_FLR
:
1558 if (!ctx
->config
->lower_FLR
)
1560 transform_flr_ceil(tctx
, inst
);
1562 case TGSI_OPCODE_CEIL
:
1563 if (!ctx
->config
->lower_CEIL
)
1565 transform_flr_ceil(tctx
, inst
);
1567 case TGSI_OPCODE_TRUNC
:
1568 if (!ctx
->config
->lower_TRUNC
)
1570 transform_trunc(tctx
, inst
);
1572 case TGSI_OPCODE_TEX
:
1573 case TGSI_OPCODE_TXP
:
1574 case TGSI_OPCODE_TXB
:
1575 case TGSI_OPCODE_TXB2
:
1576 case TGSI_OPCODE_TXL
:
1577 if (transform_samp(tctx
, inst
))
1582 tctx
->emit_instruction(tctx
, inst
);
1587 /* returns NULL if no lowering required, else returns the new
1588 * tokens (which caller is required to free()). In either case
1589 * returns the current info.
1591 const struct tgsi_token
*
1592 tgsi_transform_lowering(const struct tgsi_lowering_config
*config
,
1593 const struct tgsi_token
*tokens
,
1594 struct tgsi_shader_info
*info
)
1596 struct tgsi_lowering_context ctx
;
1597 struct tgsi_token
*newtoks
;
1600 /* sanity check in case limit is ever increased: */
1601 STATIC_ASSERT((sizeof(config
->saturate_s
) * 8) >= PIPE_MAX_SAMPLERS
);
1603 /* sanity check the lowering */
1604 assert(!(config
->lower_FRC
&& (config
->lower_FLR
|| config
->lower_CEIL
)));
1605 assert(!(config
->lower_FRC
&& config
->lower_TRUNC
));
1607 memset(&ctx
, 0, sizeof(ctx
));
1608 ctx
.base
.transform_instruction
= transform_instr
;
1610 ctx
.config
= config
;
1612 tgsi_scan_shader(tokens
, info
);
1614 /* if we are adding fragment shader support to emulate two-sided
1615 * color, then figure out the number of additional inputs we need
1616 * to create for BCOLOR's..
1618 if ((info
->processor
== PIPE_SHADER_FRAGMENT
) &&
1619 config
->color_two_side
) {
1622 for (i
= 0; i
<= info
->file_max
[TGSI_FILE_INPUT
]; i
++) {
1623 if (info
->input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
)
1624 ctx
.two_side_idx
[ctx
.two_side_colors
++] = i
;
1625 if (info
->input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
1630 ctx
.saturate
= config
->saturate_r
| config
->saturate_s
| config
->saturate_t
;
1632 #define OPCS(x) ((config->lower_ ## x) ? info->opcode_count[TGSI_OPCODE_ ## x] : 0)
1633 /* if there are no instructions to lower, then we are done: */
1652 ctx
.two_side_colors
||
1657 _debug_printf("BEFORE:");
1658 tgsi_dump(tokens
, 0);
1662 newlen
= tgsi_num_tokens(tokens
);
1664 newlen
+= DST_GROW
* OPCS(DST
);
1665 numtmp
= MAX2(numtmp
, DST_TMP
);
1668 newlen
+= XPD_GROW
* OPCS(XPD
);
1669 numtmp
= MAX2(numtmp
, XPD_TMP
);
1672 newlen
+= SCS_GROW
* OPCS(SCS
);
1673 numtmp
= MAX2(numtmp
, SCS_TMP
);
1676 newlen
+= LRP_GROW
* OPCS(LRP
);
1677 numtmp
= MAX2(numtmp
, LRP_TMP
);
1680 newlen
+= FRC_GROW
* OPCS(FRC
);
1681 numtmp
= MAX2(numtmp
, FRC_TMP
);
1684 newlen
+= POW_GROW
* OPCS(POW
);
1685 numtmp
= MAX2(numtmp
, POW_TMP
);
1688 newlen
+= LIT_GROW
* OPCS(LIT
);
1689 numtmp
= MAX2(numtmp
, LIT_TMP
);
1692 newlen
+= EXP_GROW
* OPCS(EXP
);
1693 numtmp
= MAX2(numtmp
, EXP_TMP
);
1696 newlen
+= LOG_GROW
* OPCS(LOG
);
1697 numtmp
= MAX2(numtmp
, LOG_TMP
);
1700 newlen
+= DP4_GROW
* OPCS(DP4
);
1701 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1704 newlen
+= DP3_GROW
* OPCS(DP3
);
1705 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1708 newlen
+= DPH_GROW
* OPCS(DPH
);
1709 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1712 newlen
+= DP2_GROW
* OPCS(DP2
);
1713 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1716 newlen
+= DP2A_GROW
* OPCS(DP2A
);
1717 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1720 newlen
+= FLR_GROW
* OPCS(FLR
);
1721 numtmp
= MAX2(numtmp
, FLR_TMP
);
1724 newlen
+= CEIL_GROW
* OPCS(CEIL
);
1725 numtmp
= MAX2(numtmp
, CEIL_TMP
);
1728 newlen
+= TRUNC_GROW
* OPCS(TRUNC
);
1729 numtmp
= MAX2(numtmp
, TRUNC_TMP
);
1731 if (ctx
.saturate
|| config
->lower_TXP
) {
1735 n
= info
->opcode_count
[TGSI_OPCODE_TEX
] +
1736 info
->opcode_count
[TGSI_OPCODE_TXP
] +
1737 info
->opcode_count
[TGSI_OPCODE_TXB
] +
1738 info
->opcode_count
[TGSI_OPCODE_TXB2
] +
1739 info
->opcode_count
[TGSI_OPCODE_TXL
];
1740 } else if (config
->lower_TXP
) {
1741 n
= info
->opcode_count
[TGSI_OPCODE_TXP
];
1744 newlen
+= SAMP_GROW
* n
;
1745 numtmp
= MAX2(numtmp
, SAMP_TMP
);
1748 /* specifically don't include two_side_colors temps in the count: */
1749 ctx
.numtmp
= numtmp
;
1751 if (ctx
.two_side_colors
) {
1752 newlen
+= TWOSIDE_GROW(ctx
.two_side_colors
);
1753 /* note: we permanently consume temp regs, re-writing references
1754 * to IN.COLOR[n] to TEMP[m] (holding the output of of the CMP
1755 * instruction that selects which varying to use):
1757 numtmp
+= ctx
.two_side_colors
;
1760 newlen
+= 2 * numtmp
;
1761 newlen
+= 5; /* immediate */
1763 newtoks
= tgsi_alloc_tokens(newlen
);
1767 tgsi_transform_shader(tokens
, newtoks
, newlen
, &ctx
.base
);
1769 tgsi_scan_shader(newtoks
, info
);
1772 _debug_printf("AFTER:");
1773 tgsi_dump(newtoks
, 0);