2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "tgsi/tgsi_transform.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_dump.h"
31 #include "util/u_debug.h"
32 #include "util/u_math.h"
34 #include "tgsi_lowering.h"
36 struct tgsi_lowering_context
{
37 struct tgsi_transform_context base
;
38 const struct tgsi_lowering_config
*config
;
39 struct tgsi_shader_info
*info
;
40 unsigned two_side_colors
;
41 unsigned two_side_idx
[PIPE_MAX_SHADER_INPUTS
];
42 unsigned color_base
; /* base register for chosen COLOR/BCOLOR's */
46 struct tgsi_full_src_register src
;
47 struct tgsi_full_dst_register dst
;
51 struct tgsi_full_src_register imm
;
56 static inline struct tgsi_lowering_context
*
57 tgsi_lowering_context(struct tgsi_transform_context
*tctx
)
59 return (struct tgsi_lowering_context
*)tctx
;
67 reg_dst(struct tgsi_full_dst_register
*dst
,
68 const struct tgsi_full_dst_register
*orig_dst
, unsigned wrmask
)
71 dst
->Register
.WriteMask
&= wrmask
;
72 assert(dst
->Register
.WriteMask
);
76 get_swiz(unsigned *swiz
, const struct tgsi_src_register
*src
)
78 swiz
[0] = src
->SwizzleX
;
79 swiz
[1] = src
->SwizzleY
;
80 swiz
[2] = src
->SwizzleZ
;
81 swiz
[3] = src
->SwizzleW
;
85 reg_src(struct tgsi_full_src_register
*src
,
86 const struct tgsi_full_src_register
*orig_src
,
87 unsigned sx
, unsigned sy
, unsigned sz
, unsigned sw
)
90 get_swiz(swiz
, &orig_src
->Register
);
92 src
->Register
.SwizzleX
= swiz
[sx
];
93 src
->Register
.SwizzleY
= swiz
[sy
];
94 src
->Register
.SwizzleZ
= swiz
[sz
];
95 src
->Register
.SwizzleW
= swiz
[sw
];
98 #define TGSI_SWIZZLE__ TGSI_SWIZZLE_X /* don't-care value! */
99 #define SWIZ(x,y,z,w) TGSI_SWIZZLE_ ## x, TGSI_SWIZZLE_ ## y, \
100 TGSI_SWIZZLE_ ## z, TGSI_SWIZZLE_ ## w
103 * if (dst.x aliases src.x) {
109 * MOV dst.zw, imm{0.0, 1.0}
112 aliases(const struct tgsi_full_dst_register
*dst
, unsigned dst_mask
,
113 const struct tgsi_full_src_register
*src
, unsigned src_mask
)
115 if ((dst
->Register
.File
== src
->Register
.File
) &&
116 (dst
->Register
.Index
== src
->Register
.Index
)) {
117 unsigned i
, actual_mask
= 0;
119 get_swiz(swiz
, &src
->Register
);
120 for (i
= 0; i
< 4; i
++)
121 if (src_mask
& (1 << i
))
122 actual_mask
|= (1 << swiz
[i
]);
123 if (actual_mask
& dst_mask
)
130 create_mov(struct tgsi_transform_context
*tctx
,
131 const struct tgsi_full_dst_register
*dst
,
132 const struct tgsi_full_src_register
*src
,
133 unsigned mask
, unsigned saturate
)
135 struct tgsi_full_instruction new_inst
;
137 new_inst
= tgsi_default_full_instruction();
138 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
139 new_inst
.Instruction
.Saturate
= saturate
;
140 new_inst
.Instruction
.NumDstRegs
= 1;
141 reg_dst(&new_inst
.Dst
[0], dst
, mask
);
142 new_inst
.Instruction
.NumSrcRegs
= 1;
143 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, Y
, Z
, W
));
144 tctx
->emit_instruction(tctx
, &new_inst
);
147 /* to help calculate # of tgsi tokens for a lowering.. we assume
148 * the worst case, ie. removed instructions don't have ADDR[] or
149 * anything which increases the # of tokens per src/dst and the
150 * inserted instructions do.
152 * OINST() - old instruction
153 * 1 : instruction itself
157 * NINST() - new instruction
158 * 1 : instruction itself
163 #define OINST(nargs) (1 + 1 + 1 * (nargs))
164 #define NINST(nargs) (1 + 2 + 2 * (nargs))
167 * Lowering Translators:
170 /* DST - Distance Vector
172 * dst.y = src0.y \times src1.y
176 * ; note: could be more clever and use just a single temp
177 * ; if I was clever enough to re-write the swizzles.
178 * ; needs: 2 tmp, imm{1.0}
179 * if (dst.y aliases src0.z) {
180 * MOV tmpA.yz, src0.yz
183 * if (dst.yz aliases src1.w) {
184 * MOV tmpB.yw, src1.yw
187 * MUL dst.y, src0.y, src1.y
190 * MOV dst.x, imm{1.0}
192 #define DST_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1) + \
193 NINST(1) + NINST(1) - OINST(2))
196 transform_dst(struct tgsi_transform_context
*tctx
,
197 struct tgsi_full_instruction
*inst
)
199 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
200 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
201 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
202 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
203 struct tgsi_full_instruction new_inst
;
205 if (aliases(dst
, TGSI_WRITEMASK_Y
, src0
, TGSI_WRITEMASK_Z
)) {
206 create_mov(tctx
, &ctx
->tmp
[A
].dst
, src0
, TGSI_WRITEMASK_YZ
, 0);
207 src0
= &ctx
->tmp
[A
].src
;
210 if (aliases(dst
, TGSI_WRITEMASK_YZ
, src1
, TGSI_WRITEMASK_W
)) {
211 create_mov(tctx
, &ctx
->tmp
[B
].dst
, src1
, TGSI_WRITEMASK_YW
, 0);
212 src1
= &ctx
->tmp
[B
].src
;
215 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
216 /* MUL dst.y, src0.y, src1.y */
217 new_inst
= tgsi_default_full_instruction();
218 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
219 new_inst
.Instruction
.NumDstRegs
= 1;
220 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Y
);
221 new_inst
.Instruction
.NumSrcRegs
= 2;
222 reg_src(&new_inst
.Src
[0], src0
, SWIZ(_
, Y
, _
, _
));
223 reg_src(&new_inst
.Src
[1], src1
, SWIZ(_
, Y
, _
, _
));
224 tctx
->emit_instruction(tctx
, &new_inst
);
227 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
228 /* MOV dst.z, src0.z */
229 new_inst
= tgsi_default_full_instruction();
230 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
231 new_inst
.Instruction
.NumDstRegs
= 1;
232 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Z
);
233 new_inst
.Instruction
.NumSrcRegs
= 1;
234 reg_src(&new_inst
.Src
[0], src0
, SWIZ(_
, _
, Z
, _
));
235 tctx
->emit_instruction(tctx
, &new_inst
);
238 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_W
) {
239 /* MOV dst.w, src1.w */
240 new_inst
= tgsi_default_full_instruction();
241 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
242 new_inst
.Instruction
.NumDstRegs
= 1;
243 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_W
);
244 new_inst
.Instruction
.NumSrcRegs
= 1;
245 reg_src(&new_inst
.Src
[0], src1
, SWIZ(_
, _
, _
, W
));
246 tctx
->emit_instruction(tctx
, &new_inst
);
249 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_X
) {
250 /* MOV dst.x, imm{1.0} */
251 new_inst
= tgsi_default_full_instruction();
252 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
253 new_inst
.Instruction
.NumDstRegs
= 1;
254 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_X
);
255 new_inst
.Instruction
.NumSrcRegs
= 1;
256 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(Y
, _
, _
, _
));
257 tctx
->emit_instruction(tctx
, &new_inst
);
261 /* XPD - Cross Product
262 * dst.x = src0.y \times src1.z - src1.y \times src0.z
263 * dst.y = src0.z \times src1.x - src1.z \times src0.x
264 * dst.z = src0.x \times src1.y - src1.x \times src0.y
267 * ; needs: 2 tmp, imm{1.0}
268 * MUL tmpA.xyz, src0.yzx, src1.zxy
269 * MUL tmpB.xyz, src1.yzx, src0.zxy
270 * SUB dst.xyz, tmpA.xyz, tmpB.xyz
271 * MOV dst.w, imm{1.0}
273 #define XPD_GROW (NINST(2) + NINST(2) + NINST(2) + NINST(1) - OINST(2))
276 transform_xpd(struct tgsi_transform_context
*tctx
,
277 struct tgsi_full_instruction
*inst
)
279 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
280 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
281 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
282 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
283 struct tgsi_full_instruction new_inst
;
285 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
286 /* MUL tmpA.xyz, src0.yzx, src1.zxy */
287 new_inst
= tgsi_default_full_instruction();
288 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
289 new_inst
.Instruction
.NumDstRegs
= 1;
290 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZ
);
291 new_inst
.Instruction
.NumSrcRegs
= 2;
292 reg_src(&new_inst
.Src
[0], src0
, SWIZ(Y
, Z
, X
, _
));
293 reg_src(&new_inst
.Src
[1], src1
, SWIZ(Z
, X
, Y
, _
));
294 tctx
->emit_instruction(tctx
, &new_inst
);
296 /* MUL tmpB.xyz, src1.yzx, src0.zxy */
297 new_inst
= tgsi_default_full_instruction();
298 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
299 new_inst
.Instruction
.NumDstRegs
= 1;
300 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[B
].dst
, TGSI_WRITEMASK_XYZ
);
301 new_inst
.Instruction
.NumSrcRegs
= 2;
302 reg_src(&new_inst
.Src
[0], src1
, SWIZ(Y
, Z
, X
, _
));
303 reg_src(&new_inst
.Src
[1], src0
, SWIZ(Z
, X
, Y
, _
));
304 tctx
->emit_instruction(tctx
, &new_inst
);
306 /* SUB dst.xyz, tmpA.xyz, tmpB.xyz */
307 new_inst
= tgsi_default_full_instruction();
308 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
309 new_inst
.Instruction
.NumDstRegs
= 1;
310 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZ
);
311 new_inst
.Instruction
.NumSrcRegs
= 2;
312 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, _
));
313 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[B
].src
, SWIZ(X
, Y
, Z
, _
));
314 tctx
->emit_instruction(tctx
, &new_inst
);
317 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_W
) {
318 /* MOV dst.w, imm{1.0} */
319 new_inst
= tgsi_default_full_instruction();
320 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
321 new_inst
.Instruction
.NumDstRegs
= 1;
322 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_W
);
323 new_inst
.Instruction
.NumSrcRegs
= 1;
324 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(_
, _
, _
, Y
));
325 tctx
->emit_instruction(tctx
, &new_inst
);
330 * dst.x = \cos{src.x}
331 * dst.y = \sin{src.x}
335 * ; needs: 1 tmp, imm{0.0, 1.0}
336 * if (dst.x aliases src.x) {
342 * MOV dst.zw, imm{0.0, 1.0}
344 #define SCS_GROW (NINST(1) + NINST(1) + NINST(1) + NINST(1) - OINST(1))
347 transform_scs(struct tgsi_transform_context
*tctx
,
348 struct tgsi_full_instruction
*inst
)
350 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
351 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
352 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
353 struct tgsi_full_instruction new_inst
;
355 if (aliases(dst
, TGSI_WRITEMASK_X
, src
, TGSI_WRITEMASK_X
)) {
356 create_mov(tctx
, &ctx
->tmp
[A
].dst
, src
, TGSI_WRITEMASK_X
, 0);
357 src
= &ctx
->tmp
[A
].src
;
360 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_X
) {
361 /* COS dst.x, src.x */
362 new_inst
= tgsi_default_full_instruction();
363 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_COS
;
364 new_inst
.Instruction
.NumDstRegs
= 1;
365 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_X
);
366 new_inst
.Instruction
.NumSrcRegs
= 1;
367 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
368 tctx
->emit_instruction(tctx
, &new_inst
);
371 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
372 /* SIN dst.y, src.x */
373 new_inst
= tgsi_default_full_instruction();
374 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SIN
;
375 new_inst
.Instruction
.NumDstRegs
= 1;
376 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Y
);
377 new_inst
.Instruction
.NumSrcRegs
= 1;
378 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
379 tctx
->emit_instruction(tctx
, &new_inst
);
382 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_ZW
) {
383 /* MOV dst.zw, imm{0.0, 1.0} */
384 new_inst
= tgsi_default_full_instruction();
385 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
386 new_inst
.Instruction
.NumDstRegs
= 1;
387 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_ZW
);
388 new_inst
.Instruction
.NumSrcRegs
= 1;
389 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(_
, _
, X
, Y
));
390 tctx
->emit_instruction(tctx
, &new_inst
);
394 /* LRP - Linear Interpolate
395 * dst.x = src0.x \times src1.x + (1.0 - src0.x) \times src2.x
396 * dst.y = src0.y \times src1.y + (1.0 - src0.y) \times src2.y
397 * dst.z = src0.z \times src1.z + (1.0 - src0.z) \times src2.z
398 * dst.w = src0.w \times src1.w + (1.0 - src0.w) \times src2.w
400 * ; needs: 2 tmp, imm{1.0}
401 * MUL tmpA, src0, src1
402 * SUB tmpB, imm{1.0}, src0
403 * MUL tmpB, tmpB, src2
404 * ADD dst, tmpA, tmpB
406 #define LRP_GROW (NINST(2) + NINST(2) + NINST(2) + NINST(2) - OINST(3))
409 transform_lrp(struct tgsi_transform_context
*tctx
,
410 struct tgsi_full_instruction
*inst
)
412 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
413 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
414 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
415 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
416 struct tgsi_full_src_register
*src2
= &inst
->Src
[2];
417 struct tgsi_full_instruction new_inst
;
419 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
420 /* MUL tmpA, src0, src1 */
421 new_inst
= tgsi_default_full_instruction();
422 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
423 new_inst
.Instruction
.NumDstRegs
= 1;
424 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
425 new_inst
.Instruction
.NumSrcRegs
= 2;
426 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
427 reg_src(&new_inst
.Src
[1], src1
, SWIZ(X
, Y
, Z
, W
));
428 tctx
->emit_instruction(tctx
, &new_inst
);
430 /* SUB tmpB, imm{1.0}, src0 */
431 new_inst
= tgsi_default_full_instruction();
432 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
433 new_inst
.Instruction
.NumDstRegs
= 1;
434 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[B
].dst
, TGSI_WRITEMASK_XYZW
);
435 new_inst
.Instruction
.NumSrcRegs
= 2;
436 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(Y
, Y
, Y
, Y
));
437 reg_src(&new_inst
.Src
[1], src0
, SWIZ(X
, Y
, Z
, W
));
438 tctx
->emit_instruction(tctx
, &new_inst
);
440 /* MUL tmpB, tmpB, src2 */
441 new_inst
= tgsi_default_full_instruction();
442 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
443 new_inst
.Instruction
.NumDstRegs
= 1;
444 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[B
].dst
, TGSI_WRITEMASK_XYZW
);
445 new_inst
.Instruction
.NumSrcRegs
= 2;
446 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[B
].src
, SWIZ(X
, Y
, Z
, W
));
447 reg_src(&new_inst
.Src
[1], src2
, SWIZ(X
, Y
, Z
, W
));
448 tctx
->emit_instruction(tctx
, &new_inst
);
450 /* ADD dst, tmpA, tmpB */
451 new_inst
= tgsi_default_full_instruction();
452 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_ADD
;
453 new_inst
.Instruction
.NumDstRegs
= 1;
454 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
455 new_inst
.Instruction
.NumSrcRegs
= 2;
456 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
457 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[B
].src
, SWIZ(X
, Y
, Z
, W
));
458 tctx
->emit_instruction(tctx
, &new_inst
);
463 * dst.x = src.x - \lfloor src.x\rfloor
464 * dst.y = src.y - \lfloor src.y\rfloor
465 * dst.z = src.z - \lfloor src.z\rfloor
466 * dst.w = src.w - \lfloor src.w\rfloor
472 #define FRC_GROW (NINST(1) + NINST(2) - OINST(1))
475 transform_frc(struct tgsi_transform_context
*tctx
,
476 struct tgsi_full_instruction
*inst
)
478 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
479 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
480 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
481 struct tgsi_full_instruction new_inst
;
483 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
485 new_inst
= tgsi_default_full_instruction();
486 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FLR
;
487 new_inst
.Instruction
.NumDstRegs
= 1;
488 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
489 new_inst
.Instruction
.NumSrcRegs
= 1;
490 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, Y
, Z
, W
));
491 tctx
->emit_instruction(tctx
, &new_inst
);
493 /* SUB dst, src, tmpA */
494 new_inst
= tgsi_default_full_instruction();
495 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
496 new_inst
.Instruction
.NumDstRegs
= 1;
497 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
498 new_inst
.Instruction
.NumSrcRegs
= 2;
499 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, Y
, Z
, W
));
500 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
501 tctx
->emit_instruction(tctx
, &new_inst
);
506 * dst.x = src0.x^{src1.x}
507 * dst.y = src0.x^{src1.x}
508 * dst.z = src0.x^{src1.x}
509 * dst.w = src0.x^{src1.x}
513 * MUL tmpA.x, src1.x, tmpA.x
516 #define POW_GROW (NINST(1) + NINST(2) + NINST(1) - OINST(2))
519 transform_pow(struct tgsi_transform_context
*tctx
,
520 struct tgsi_full_instruction
*inst
)
522 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
523 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
524 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
525 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
526 struct tgsi_full_instruction new_inst
;
528 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
529 /* LG2 tmpA.x, src0.x */
530 new_inst
= tgsi_default_full_instruction();
531 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_LG2
;
532 new_inst
.Instruction
.NumDstRegs
= 1;
533 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
534 new_inst
.Instruction
.NumSrcRegs
= 1;
535 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, _
, _
, _
));
536 tctx
->emit_instruction(tctx
, &new_inst
);
538 /* MUL tmpA.x, src1.x, tmpA.x */
539 new_inst
= tgsi_default_full_instruction();
540 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
541 new_inst
.Instruction
.NumDstRegs
= 1;
542 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
543 new_inst
.Instruction
.NumSrcRegs
= 2;
544 reg_src(&new_inst
.Src
[0], src1
, SWIZ(X
, _
, _
, _
));
545 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, _
, _
, _
));
546 tctx
->emit_instruction(tctx
, &new_inst
);
548 /* EX2 dst, tmpA.x */
549 new_inst
= tgsi_default_full_instruction();
550 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
551 new_inst
.Instruction
.NumDstRegs
= 1;
552 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
553 new_inst
.Instruction
.NumSrcRegs
= 1;
554 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(X
, _
, _
, _
));
555 tctx
->emit_instruction(tctx
, &new_inst
);
559 /* LIT - Light Coefficients
561 * dst.y = max(src.x, 0.0)
562 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
565 * ; needs: 1 tmp, imm{0.0}, imm{1.0}, imm{128.0}
566 * MAX tmpA.xy, src.xy, imm{0.0}
567 * CLAMP tmpA.z, src.w, -imm{128.0}, imm{128.0}
569 * MUL tmpA.y, tmpA.z, tmpA.y
571 * CMP tmpA.y, -src.x, tmpA.y, imm{0.0}
572 * MOV dst.yz, tmpA.xy
573 * MOV dst.xw, imm{1.0}
575 #define LIT_GROW (NINST(1) + NINST(3) + NINST(1) + NINST(2) + \
576 NINST(1) + NINST(3) + NINST(1) + NINST(1) - OINST(1))
579 transform_lit(struct tgsi_transform_context
*tctx
,
580 struct tgsi_full_instruction
*inst
)
582 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
583 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
584 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
585 struct tgsi_full_instruction new_inst
;
587 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
588 /* MAX tmpA.xy, src.xy, imm{0.0} */
589 new_inst
= tgsi_default_full_instruction();
590 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAX
;
591 new_inst
.Instruction
.NumDstRegs
= 1;
592 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XY
);
593 new_inst
.Instruction
.NumSrcRegs
= 2;
594 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, Y
, _
, _
));
595 reg_src(&new_inst
.Src
[1], &ctx
->imm
, SWIZ(X
, X
, _
, _
));
596 tctx
->emit_instruction(tctx
, &new_inst
);
598 /* CLAMP tmpA.z, src.w, -imm{128.0}, imm{128.0} */
599 new_inst
= tgsi_default_full_instruction();
600 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_CLAMP
;
601 new_inst
.Instruction
.NumDstRegs
= 1;
602 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Z
);
603 new_inst
.Instruction
.NumSrcRegs
= 3;
604 reg_src(&new_inst
.Src
[0], src
, SWIZ(_
, _
, W
, _
));
605 reg_src(&new_inst
.Src
[1], &ctx
->imm
, SWIZ(_
, _
, Z
, _
));
606 new_inst
.Src
[1].Register
.Negate
= true;
607 reg_src(&new_inst
.Src
[2], &ctx
->imm
, SWIZ(_
, _
, Z
, _
));
608 tctx
->emit_instruction(tctx
, &new_inst
);
610 /* LG2 tmpA.y, tmpA.y */
611 new_inst
= tgsi_default_full_instruction();
612 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_LG2
;
613 new_inst
.Instruction
.NumDstRegs
= 1;
614 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
615 new_inst
.Instruction
.NumSrcRegs
= 1;
616 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Y
, _
, _
, _
));
617 tctx
->emit_instruction(tctx
, &new_inst
);
619 /* MUL tmpA.y, tmpA.z, tmpA.y */
620 new_inst
= tgsi_default_full_instruction();
621 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
622 new_inst
.Instruction
.NumDstRegs
= 1;
623 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
624 new_inst
.Instruction
.NumSrcRegs
= 2;
625 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, Z
, _
, _
));
626 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, Y
, _
, _
));
627 tctx
->emit_instruction(tctx
, &new_inst
);
629 /* EX2 tmpA.y, tmpA.y */
630 new_inst
= tgsi_default_full_instruction();
631 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
632 new_inst
.Instruction
.NumDstRegs
= 1;
633 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
634 new_inst
.Instruction
.NumSrcRegs
= 1;
635 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Y
, _
, _
, _
));
636 tctx
->emit_instruction(tctx
, &new_inst
);
638 /* CMP tmpA.y, -src.x, tmpA.y, imm{0.0} */
639 new_inst
= tgsi_default_full_instruction();
640 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_CMP
;
641 new_inst
.Instruction
.NumDstRegs
= 1;
642 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
643 new_inst
.Instruction
.NumSrcRegs
= 3;
644 reg_src(&new_inst
.Src
[0], src
, SWIZ(_
, X
, _
, _
));
645 new_inst
.Src
[0].Register
.Negate
= true;
646 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, Y
, _
, _
));
647 reg_src(&new_inst
.Src
[2], &ctx
->imm
, SWIZ(_
, X
, _
, _
));
648 tctx
->emit_instruction(tctx
, &new_inst
);
650 /* MOV dst.yz, tmpA.xy */
651 new_inst
= tgsi_default_full_instruction();
652 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
653 new_inst
.Instruction
.NumDstRegs
= 1;
654 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_YZ
);
655 new_inst
.Instruction
.NumSrcRegs
= 1;
656 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, Y
, _
));
657 tctx
->emit_instruction(tctx
, &new_inst
);
660 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XW
) {
661 /* MOV dst.xw, imm{1.0} */
662 new_inst
= tgsi_default_full_instruction();
663 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
664 new_inst
.Instruction
.NumDstRegs
= 1;
665 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XW
);
666 new_inst
.Instruction
.NumSrcRegs
= 1;
667 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(Y
, _
, _
, Y
));
668 tctx
->emit_instruction(tctx
, &new_inst
);
672 /* EXP - Approximate Exponential Base 2
673 * dst.x = 2^{\lfloor src.x\rfloor}
674 * dst.y = src.x - \lfloor src.x\rfloor
678 * ; needs: 1 tmp, imm{1.0}
679 * if (lowering FLR) {
681 * SUB tmpA.x, src.x, tmpA.x
686 * SUB dst.y, src.x, tmpA.x
689 * MOV dst.w, imm{1.0}
691 #define EXP_GROW (NINST(1) + NINST(2) + NINST(1) + NINST(2) + NINST(1) + \
692 NINST(1)+ NINST(1) - OINST(1))
695 transform_exp(struct tgsi_transform_context
*tctx
,
696 struct tgsi_full_instruction
*inst
)
698 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
699 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
700 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
701 struct tgsi_full_instruction new_inst
;
703 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
704 if (ctx
->config
->lower_FLR
) {
705 /* FRC tmpA.x, src.x */
706 new_inst
= tgsi_default_full_instruction();
707 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FRC
;
708 new_inst
.Instruction
.NumDstRegs
= 1;
709 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
710 new_inst
.Instruction
.NumSrcRegs
= 1;
711 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
712 tctx
->emit_instruction(tctx
, &new_inst
);
714 /* SUB tmpA.x, src.x, tmpA.x */
715 new_inst
= tgsi_default_full_instruction();
716 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
717 new_inst
.Instruction
.NumDstRegs
= 1;
718 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
719 new_inst
.Instruction
.NumSrcRegs
= 2;
720 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
721 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, _
, _
, _
));
722 tctx
->emit_instruction(tctx
, &new_inst
);
724 /* FLR tmpA.x, src.x */
725 new_inst
= tgsi_default_full_instruction();
726 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FLR
;
727 new_inst
.Instruction
.NumDstRegs
= 1;
728 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
729 new_inst
.Instruction
.NumSrcRegs
= 1;
730 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
731 tctx
->emit_instruction(tctx
, &new_inst
);
735 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
736 /* EX2 tmpA.y, src.x */
737 new_inst
= tgsi_default_full_instruction();
738 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
739 new_inst
.Instruction
.NumDstRegs
= 1;
740 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
741 new_inst
.Instruction
.NumSrcRegs
= 1;
742 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
743 tctx
->emit_instruction(tctx
, &new_inst
);
746 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
747 /* SUB dst.y, src.x, tmpA.x */
748 new_inst
= tgsi_default_full_instruction();
749 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
750 new_inst
.Instruction
.NumDstRegs
= 1;
751 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Y
);
752 new_inst
.Instruction
.NumSrcRegs
= 2;
753 reg_src(&new_inst
.Src
[0], src
, SWIZ(_
, X
, _
, _
));
754 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, _
, _
));
755 tctx
->emit_instruction(tctx
, &new_inst
);
758 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_X
) {
759 /* EX2 dst.x, tmpA.x */
760 new_inst
= tgsi_default_full_instruction();
761 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
762 new_inst
.Instruction
.NumDstRegs
= 1;
763 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_X
);
764 new_inst
.Instruction
.NumSrcRegs
= 1;
765 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(X
, _
, _
, _
));
766 tctx
->emit_instruction(tctx
, &new_inst
);
769 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
770 /* MOV dst.z, tmpA.y */
771 new_inst
= tgsi_default_full_instruction();
772 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
773 new_inst
.Instruction
.NumDstRegs
= 1;
774 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Z
);
775 new_inst
.Instruction
.NumSrcRegs
= 1;
776 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, _
, Y
, _
));
777 tctx
->emit_instruction(tctx
, &new_inst
);
780 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_W
) {
781 /* MOV dst.w, imm{1.0} */
782 new_inst
= tgsi_default_full_instruction();
783 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
784 new_inst
.Instruction
.NumDstRegs
= 1;
785 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_W
);
786 new_inst
.Instruction
.NumSrcRegs
= 1;
787 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(_
, _
, _
, Y
));
788 tctx
->emit_instruction(tctx
, &new_inst
);
792 /* LOG - Approximate Logarithm Base 2
793 * dst.x = \lfloor\log_2{|src.x|}\rfloor
794 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
795 * dst.z = \log_2{|src.x|}
798 * ; needs: 1 tmp, imm{1.0}
799 * LG2 tmpA.x, |src.x|
800 * if (lowering FLR) {
802 * SUB tmpA.y, tmpA.x, tmpA.y
808 * MUL dst.y, |src.x|, tmpA.z
809 * MOV dst.xz, tmpA.yx
810 * MOV dst.w, imm{1.0}
812 #define LOG_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1) + NINST(1) + \
813 NINST(2) + NINST(1) + NINST(1) - OINST(1))
816 transform_log(struct tgsi_transform_context
*tctx
,
817 struct tgsi_full_instruction
*inst
)
819 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
820 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
821 struct tgsi_full_src_register
*src
= &inst
->Src
[0];
822 struct tgsi_full_instruction new_inst
;
824 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
825 /* LG2 tmpA.x, |src.x| */
826 new_inst
= tgsi_default_full_instruction();
827 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_LG2
;
828 new_inst
.Instruction
.NumDstRegs
= 1;
829 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
830 new_inst
.Instruction
.NumSrcRegs
= 1;
831 reg_src(&new_inst
.Src
[0], src
, SWIZ(X
, _
, _
, _
));
832 new_inst
.Src
[0].Register
.Absolute
= true;
833 tctx
->emit_instruction(tctx
, &new_inst
);
836 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
837 if (ctx
->config
->lower_FLR
) {
838 /* FRC tmpA.y, tmpA.x */
839 new_inst
= tgsi_default_full_instruction();
840 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FRC
;
841 new_inst
.Instruction
.NumDstRegs
= 1;
842 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
843 new_inst
.Instruction
.NumSrcRegs
= 1;
844 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, _
, _
));
845 tctx
->emit_instruction(tctx
, &new_inst
);
847 /* SUB tmpA.y, tmpA.x, tmpA.y */
848 new_inst
= tgsi_default_full_instruction();
849 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
850 new_inst
.Instruction
.NumDstRegs
= 1;
851 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
852 new_inst
.Instruction
.NumSrcRegs
= 2;
853 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, _
, _
));
854 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, Y
, _
, _
));
855 tctx
->emit_instruction(tctx
, &new_inst
);
857 /* FLR tmpA.y, tmpA.x */
858 new_inst
= tgsi_default_full_instruction();
859 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FLR
;
860 new_inst
.Instruction
.NumDstRegs
= 1;
861 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Y
);
862 new_inst
.Instruction
.NumSrcRegs
= 1;
863 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(_
, X
, _
, _
));
864 tctx
->emit_instruction(tctx
, &new_inst
);
868 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
869 /* EX2 tmpA.z, tmpA.y */
870 new_inst
= tgsi_default_full_instruction();
871 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_EX2
;
872 new_inst
.Instruction
.NumDstRegs
= 1;
873 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Z
);
874 new_inst
.Instruction
.NumSrcRegs
= 1;
875 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Y
, _
, _
, _
));
876 tctx
->emit_instruction(tctx
, &new_inst
);
878 /* RCP tmpA.z, tmpA.z */
879 new_inst
= tgsi_default_full_instruction();
880 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_RCP
;
881 new_inst
.Instruction
.NumDstRegs
= 1;
882 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_Z
);
883 new_inst
.Instruction
.NumSrcRegs
= 1;
884 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Z
, _
, _
, _
));
885 tctx
->emit_instruction(tctx
, &new_inst
);
887 /* MUL dst.y, |src.x|, tmpA.z */
888 new_inst
= tgsi_default_full_instruction();
889 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
890 new_inst
.Instruction
.NumDstRegs
= 1;
891 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_Y
);
892 new_inst
.Instruction
.NumSrcRegs
= 2;
893 reg_src(&new_inst
.Src
[0], src
, SWIZ(_
, X
, _
, _
));
894 new_inst
.Src
[0].Register
.Absolute
= true;
895 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(_
, Z
, _
, _
));
896 tctx
->emit_instruction(tctx
, &new_inst
);
899 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XZ
) {
900 /* MOV dst.xz, tmpA.yx */
901 new_inst
= tgsi_default_full_instruction();
902 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
903 new_inst
.Instruction
.NumDstRegs
= 1;
904 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XZ
);
905 new_inst
.Instruction
.NumSrcRegs
= 1;
906 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(Y
, _
, X
, _
));
907 tctx
->emit_instruction(tctx
, &new_inst
);
910 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_W
) {
911 /* MOV dst.w, imm{1.0} */
912 new_inst
= tgsi_default_full_instruction();
913 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MOV
;
914 new_inst
.Instruction
.NumDstRegs
= 1;
915 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_W
);
916 new_inst
.Instruction
.NumSrcRegs
= 1;
917 reg_src(&new_inst
.Src
[0], &ctx
->imm
, SWIZ(_
, _
, _
, Y
));
918 tctx
->emit_instruction(tctx
, &new_inst
);
922 /* DP4 - 4-component Dot Product
923 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z + src0.w \times src1.w
925 * DP3 - 3-component Dot Product
926 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z
928 * DPH - Homogeneous Dot Product
929 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z + src1.w
931 * DP2 - 2-component Dot Product
932 * dst = src0.x \times src1.x + src0.y \times src1.y
934 * DP2A - 2-component Dot Product And Add
935 * dst = src0.x \times src1.x + src0.y \times src1.y + src2.x
937 * NOTE: these are translated into sequence of MUL/MAD(/ADD) scalar
938 * operations, which is what you'd prefer for a ISA that is natively
939 * scalar. Probably a native vector ISA would at least already have
940 * DP4/DP3 instructions, but perhaps there is room for an alternative
941 * translation for DPH/DP2/DP2A using vector instructions.
944 * MUL tmpA.x, src0.x, src1.x
945 * MAD tmpA.x, src0.y, src1.y, tmpA.x
946 * if (DPH || DP3 || DP4) {
947 * MAD tmpA.x, src0.z, src1.z, tmpA.x
949 * ADD tmpA.x, src1.w, tmpA.x
951 * MAD tmpA.x, src0.w, src1.w, tmpA.x
954 * ADD tmpA.x, src2.x, tmpA.x
956 * ; fixup last instruction to replicate into dst
958 #define DP4_GROW (NINST(2) + NINST(3) + NINST(3) + NINST(3) - OINST(2))
959 #define DP3_GROW (NINST(2) + NINST(3) + NINST(3) - OINST(2))
960 #define DPH_GROW (NINST(2) + NINST(3) + NINST(3) + NINST(2) - OINST(2))
961 #define DP2_GROW (NINST(2) + NINST(3) - OINST(2))
962 #define DP2A_GROW (NINST(2) + NINST(3) + NINST(2) - OINST(3))
965 transform_dotp(struct tgsi_transform_context
*tctx
,
966 struct tgsi_full_instruction
*inst
)
968 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
969 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
970 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
971 struct tgsi_full_src_register
*src1
= &inst
->Src
[1];
972 struct tgsi_full_src_register
*src2
= &inst
->Src
[2]; /* only DP2A */
973 struct tgsi_full_instruction new_inst
;
974 unsigned opcode
= inst
->Instruction
.Opcode
;
976 /* NOTE: any potential last instruction must replicate src on all
977 * components (since it could be re-written to write to final dst)
980 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
981 /* MUL tmpA.x, src0.x, src1.x */
982 new_inst
= tgsi_default_full_instruction();
983 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
984 new_inst
.Instruction
.NumDstRegs
= 1;
985 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
986 new_inst
.Instruction
.NumSrcRegs
= 2;
987 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, _
, _
, _
));
988 reg_src(&new_inst
.Src
[1], src1
, SWIZ(X
, _
, _
, _
));
989 tctx
->emit_instruction(tctx
, &new_inst
);
991 /* MAD tmpA.x, src0.y, src1.y, tmpA.x */
992 new_inst
= tgsi_default_full_instruction();
993 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
994 new_inst
.Instruction
.NumDstRegs
= 1;
995 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
996 new_inst
.Instruction
.NumSrcRegs
= 3;
997 reg_src(&new_inst
.Src
[0], src0
, SWIZ(Y
, Y
, Y
, Y
));
998 reg_src(&new_inst
.Src
[1], src1
, SWIZ(Y
, Y
, Y
, Y
));
999 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
1001 if ((opcode
== TGSI_OPCODE_DPH
) ||
1002 (opcode
== TGSI_OPCODE_DP3
) ||
1003 (opcode
== TGSI_OPCODE_DP4
)) {
1004 tctx
->emit_instruction(tctx
, &new_inst
);
1006 /* MAD tmpA.x, src0.z, src1.z, tmpA.x */
1007 new_inst
= tgsi_default_full_instruction();
1008 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
1009 new_inst
.Instruction
.NumDstRegs
= 1;
1010 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
1011 new_inst
.Instruction
.NumSrcRegs
= 3;
1012 reg_src(&new_inst
.Src
[0], src0
, SWIZ(Z
, Z
, Z
, Z
));
1013 reg_src(&new_inst
.Src
[1], src1
, SWIZ(Z
, Z
, Z
, Z
));
1014 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
1016 if (opcode
== TGSI_OPCODE_DPH
) {
1017 tctx
->emit_instruction(tctx
, &new_inst
);
1019 /* ADD tmpA.x, src1.w, tmpA.x */
1020 new_inst
= tgsi_default_full_instruction();
1021 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_ADD
;
1022 new_inst
.Instruction
.NumDstRegs
= 1;
1023 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
1024 new_inst
.Instruction
.NumSrcRegs
= 2;
1025 reg_src(&new_inst
.Src
[0], src1
, SWIZ(W
, W
, W
, W
));
1026 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
1027 } else if (opcode
== TGSI_OPCODE_DP4
) {
1028 tctx
->emit_instruction(tctx
, &new_inst
);
1030 /* MAD tmpA.x, src0.w, src1.w, tmpA.x */
1031 new_inst
= tgsi_default_full_instruction();
1032 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MAD
;
1033 new_inst
.Instruction
.NumDstRegs
= 1;
1034 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
1035 new_inst
.Instruction
.NumSrcRegs
= 3;
1036 reg_src(&new_inst
.Src
[0], src0
, SWIZ(W
, W
, W
, W
));
1037 reg_src(&new_inst
.Src
[1], src1
, SWIZ(W
, W
, W
, W
));
1038 reg_src(&new_inst
.Src
[2], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
1040 } else if (opcode
== TGSI_OPCODE_DP2A
) {
1041 tctx
->emit_instruction(tctx
, &new_inst
);
1043 /* ADD tmpA.x, src2.x, tmpA.x */
1044 new_inst
= tgsi_default_full_instruction();
1045 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_ADD
;
1046 new_inst
.Instruction
.NumDstRegs
= 1;
1047 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_X
);
1048 new_inst
.Instruction
.NumSrcRegs
= 2;
1049 reg_src(&new_inst
.Src
[0], src2
, SWIZ(X
, X
, X
, X
));
1050 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, X
, X
, X
));
1053 /* fixup last instruction to write to dst: */
1054 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
1056 tctx
->emit_instruction(tctx
, &new_inst
);
1060 /* FLR - floor, CEIL - ceil
1064 * ADD dst, src, tmpA
1067 * SUB dst, src, tmpA
1070 #define FLR_GROW (NINST(1) + NINST(2) - OINST(1))
1071 #define CEIL_GROW (NINST(1) + NINST(2) - OINST(1))
1075 transform_flr_ceil(struct tgsi_transform_context
*tctx
,
1076 struct tgsi_full_instruction
*inst
)
1078 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1079 struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
1080 struct tgsi_full_src_register
*src0
= &inst
->Src
[0];
1081 struct tgsi_full_instruction new_inst
;
1082 unsigned opcode
= inst
->Instruction
.Opcode
;
1084 if (dst
->Register
.WriteMask
& TGSI_WRITEMASK_XYZW
) {
1085 /* FLR: FRC tmpA, src CEIL: FRC tmpA, -src */
1086 new_inst
= tgsi_default_full_instruction();
1087 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_FRC
;
1088 new_inst
.Instruction
.NumDstRegs
= 1;
1089 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, TGSI_WRITEMASK_XYZW
);
1090 new_inst
.Instruction
.NumSrcRegs
= 1;
1091 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
1093 if (opcode
== TGSI_OPCODE_CEIL
)
1094 new_inst
.Src
[0].Register
.Negate
= !new_inst
.Src
[0].Register
.Negate
;
1095 tctx
->emit_instruction(tctx
, &new_inst
);
1097 /* FLR: SUB dst, src, tmpA CEIL: ADD dst, src, tmpA */
1098 new_inst
= tgsi_default_full_instruction();
1099 if (opcode
== TGSI_OPCODE_CEIL
)
1100 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_ADD
;
1102 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_SUB
;
1103 new_inst
.Instruction
.NumDstRegs
= 1;
1104 reg_dst(&new_inst
.Dst
[0], dst
, TGSI_WRITEMASK_XYZW
);
1105 new_inst
.Instruction
.NumSrcRegs
= 2;
1106 reg_src(&new_inst
.Src
[0], src0
, SWIZ(X
, Y
, Z
, W
));
1107 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
1108 tctx
->emit_instruction(tctx
, &new_inst
);
1112 /* Inserts a MOV_SAT for the needed components of tex coord. Note that
1113 * in the case of TXP, the clamping must happen *after* projection, so
1114 * we need to lower TXP to TEX.
1118 * ; do perspective division manually before clamping:
1120 * MUL tmpB.<pmask>, tmpA, tmpB.xxxx
1123 * MOV_SAT tmpA.<mask>, tmpA ; <mask> is the clamped s/t/r coords
1124 * <opc> dst, tmpA, ...
1126 #define SAMP_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1))
1129 transform_samp(struct tgsi_transform_context
*tctx
,
1130 struct tgsi_full_instruction
*inst
)
1132 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1133 struct tgsi_full_src_register
*coord
= &inst
->Src
[0];
1134 struct tgsi_full_src_register
*samp
;
1135 struct tgsi_full_instruction new_inst
;
1136 /* mask is clamped coords, pmask is all coords (for projection): */
1137 unsigned mask
= 0, pmask
= 0, smask
;
1138 unsigned tex
= inst
->Texture
.Texture
;
1139 unsigned opcode
= inst
->Instruction
.Opcode
;
1140 bool lower_txp
= (opcode
== TGSI_OPCODE_TXP
) &&
1141 (ctx
->config
->lower_TXP
& (1 << tex
));
1143 if (opcode
== TGSI_OPCODE_TXB2
) {
1144 samp
= &inst
->Src
[2];
1146 samp
= &inst
->Src
[1];
1149 /* convert sampler # to bitmask to test: */
1150 smask
= 1 << samp
->Register
.Index
;
1152 /* check if we actually need to lower this one: */
1153 if (!(ctx
->saturate
& smask
) && !lower_txp
)
1156 /* figure out which coordinates need saturating:
1157 * - RECT textures should not get saturated
1158 * - array index coords should not get saturated
1161 case TGSI_TEXTURE_3D
:
1162 case TGSI_TEXTURE_CUBE
:
1163 case TGSI_TEXTURE_CUBE_ARRAY
:
1164 case TGSI_TEXTURE_SHADOWCUBE
:
1165 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1166 if (ctx
->config
->saturate_r
& smask
)
1167 mask
|= TGSI_WRITEMASK_Z
;
1168 pmask
|= TGSI_WRITEMASK_Z
;
1171 case TGSI_TEXTURE_2D
:
1172 case TGSI_TEXTURE_2D_ARRAY
:
1173 case TGSI_TEXTURE_SHADOW2D
:
1174 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1175 case TGSI_TEXTURE_2D_MSAA
:
1176 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
1177 if (ctx
->config
->saturate_t
& smask
)
1178 mask
|= TGSI_WRITEMASK_Y
;
1179 pmask
|= TGSI_WRITEMASK_Y
;
1182 case TGSI_TEXTURE_1D
:
1183 case TGSI_TEXTURE_1D_ARRAY
:
1184 case TGSI_TEXTURE_SHADOW1D
:
1185 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1186 if (ctx
->config
->saturate_s
& smask
)
1187 mask
|= TGSI_WRITEMASK_X
;
1188 pmask
|= TGSI_WRITEMASK_X
;
1191 case TGSI_TEXTURE_RECT
:
1192 case TGSI_TEXTURE_SHADOWRECT
:
1193 /* we don't saturate, but in case of lower_txp we
1194 * still need to do the perspective divide:
1196 pmask
= TGSI_WRITEMASK_XY
;
1200 /* sanity check.. driver could be asking to saturate a non-
1201 * existent coordinate component:
1203 if (!mask
&& !lower_txp
)
1206 /* MOV tmpA, src0 */
1207 create_mov(tctx
, &ctx
->tmp
[A
].dst
, coord
, TGSI_WRITEMASK_XYZW
, 0);
1209 /* This is a bit sad.. we need to clamp *after* the coords
1210 * are projected, which means lowering TXP to TEX and doing
1211 * the projection ourself. But since I haven't figured out
1212 * how to make the lowering code deliver an electric shock
1213 * to anyone using GL_CLAMP, we must do this instead:
1215 if (opcode
== TGSI_OPCODE_TXP
) {
1216 /* RCP tmpB.x tmpA.w */
1217 new_inst
= tgsi_default_full_instruction();
1218 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_RCP
;
1219 new_inst
.Instruction
.NumDstRegs
= 1;
1220 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[B
].dst
, TGSI_WRITEMASK_X
);
1221 new_inst
.Instruction
.NumSrcRegs
= 1;
1222 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(W
, _
, _
, _
));
1223 tctx
->emit_instruction(tctx
, &new_inst
);
1225 /* MUL tmpA.mask, tmpA, tmpB.xxxx */
1226 new_inst
= tgsi_default_full_instruction();
1227 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_MUL
;
1228 new_inst
.Instruction
.NumDstRegs
= 1;
1229 reg_dst(&new_inst
.Dst
[0], &ctx
->tmp
[A
].dst
, pmask
);
1230 new_inst
.Instruction
.NumSrcRegs
= 2;
1231 reg_src(&new_inst
.Src
[0], &ctx
->tmp
[A
].src
, SWIZ(X
, Y
, Z
, W
));
1232 reg_src(&new_inst
.Src
[1], &ctx
->tmp
[B
].src
, SWIZ(X
, X
, X
, X
));
1233 tctx
->emit_instruction(tctx
, &new_inst
);
1235 opcode
= TGSI_OPCODE_TEX
;
1238 /* MOV_SAT tmpA.<mask>, tmpA */
1240 create_mov(tctx
, &ctx
->tmp
[A
].dst
, &ctx
->tmp
[A
].src
, mask
, 1);
1243 /* modify the texture samp instruction to take fixed up coord: */
1245 new_inst
.Instruction
.Opcode
= opcode
;
1246 new_inst
.Src
[0] = ctx
->tmp
[A
].src
;
1247 tctx
->emit_instruction(tctx
, &new_inst
);
1252 /* Two-sided color emulation:
1253 * For each COLOR input, create a corresponding BCOLOR input, plus
1254 * CMP instruction to select front or back color based on FACE
1256 #define TWOSIDE_GROW(n) ( \
1258 ((n) * 3) + /* IN[], BCOLOR[n], <intrp> */\
1259 ((n) * 1) + /* TEMP[] */ \
1260 ((n) * NINST(3)) /* CMP instr */ \
1264 emit_twoside(struct tgsi_transform_context
*tctx
)
1266 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1267 struct tgsi_shader_info
*info
= ctx
->info
;
1268 struct tgsi_full_declaration decl
;
1269 struct tgsi_full_instruction new_inst
;
1270 unsigned inbase
, tmpbase
;
1273 inbase
= info
->file_max
[TGSI_FILE_INPUT
] + 1;
1274 tmpbase
= info
->file_max
[TGSI_FILE_TEMPORARY
] + 1;
1276 /* additional inputs for BCOLOR's */
1277 for (i
= 0; i
< ctx
->two_side_colors
; i
++) {
1278 unsigned in_idx
= ctx
->two_side_idx
[i
];
1279 decl
= tgsi_default_full_declaration();
1280 decl
.Declaration
.File
= TGSI_FILE_INPUT
;
1281 decl
.Declaration
.Semantic
= true;
1282 decl
.Range
.First
= decl
.Range
.Last
= inbase
+ i
;
1283 decl
.Semantic
.Name
= TGSI_SEMANTIC_BCOLOR
;
1284 decl
.Semantic
.Index
= info
->input_semantic_index
[in_idx
];
1285 decl
.Declaration
.Interpolate
= true;
1286 decl
.Interp
.Interpolate
= info
->input_interpolate
[in_idx
];
1287 decl
.Interp
.Location
= info
->input_interpolate_loc
[in_idx
];
1288 decl
.Interp
.CylindricalWrap
= info
->input_cylindrical_wrap
[in_idx
];
1289 tctx
->emit_declaration(tctx
, &decl
);
1292 /* additional input for FACE */
1293 if (ctx
->two_side_colors
&& (ctx
->face_idx
== -1)) {
1294 decl
= tgsi_default_full_declaration();
1295 decl
.Declaration
.File
= TGSI_FILE_INPUT
;
1296 decl
.Declaration
.Semantic
= true;
1297 decl
.Range
.First
= decl
.Range
.Last
= inbase
+ ctx
->two_side_colors
;
1298 decl
.Semantic
.Name
= TGSI_SEMANTIC_FACE
;
1299 decl
.Semantic
.Index
= 0;
1300 tctx
->emit_declaration(tctx
, &decl
);
1302 ctx
->face_idx
= decl
.Range
.First
;
1305 /* additional temps for COLOR/BCOLOR selection: */
1306 for (i
= 0; i
< ctx
->two_side_colors
; i
++) {
1307 decl
= tgsi_default_full_declaration();
1308 decl
.Declaration
.File
= TGSI_FILE_TEMPORARY
;
1309 decl
.Range
.First
= decl
.Range
.Last
= tmpbase
+ ctx
->numtmp
+ i
;
1310 tctx
->emit_declaration(tctx
, &decl
);
1313 /* and finally additional instructions to select COLOR/BCOLOR: */
1314 for (i
= 0; i
< ctx
->two_side_colors
; i
++) {
1315 new_inst
= tgsi_default_full_instruction();
1316 new_inst
.Instruction
.Opcode
= TGSI_OPCODE_CMP
;
1318 new_inst
.Instruction
.NumDstRegs
= 1;
1319 new_inst
.Dst
[0].Register
.File
= TGSI_FILE_TEMPORARY
;
1320 new_inst
.Dst
[0].Register
.Index
= tmpbase
+ ctx
->numtmp
+ i
;
1321 new_inst
.Dst
[0].Register
.WriteMask
= TGSI_WRITEMASK_XYZW
;
1323 new_inst
.Instruction
.NumSrcRegs
= 3;
1324 new_inst
.Src
[0].Register
.File
= TGSI_FILE_INPUT
;
1325 new_inst
.Src
[0].Register
.Index
= ctx
->face_idx
;
1326 new_inst
.Src
[0].Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1327 new_inst
.Src
[0].Register
.SwizzleY
= TGSI_SWIZZLE_X
;
1328 new_inst
.Src
[0].Register
.SwizzleZ
= TGSI_SWIZZLE_X
;
1329 new_inst
.Src
[0].Register
.SwizzleW
= TGSI_SWIZZLE_X
;
1330 new_inst
.Src
[1].Register
.File
= TGSI_FILE_INPUT
;
1331 new_inst
.Src
[1].Register
.Index
= inbase
+ i
;
1332 new_inst
.Src
[1].Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1333 new_inst
.Src
[1].Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1334 new_inst
.Src
[1].Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1335 new_inst
.Src
[1].Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1336 new_inst
.Src
[2].Register
.File
= TGSI_FILE_INPUT
;
1337 new_inst
.Src
[2].Register
.Index
= ctx
->two_side_idx
[i
];
1338 new_inst
.Src
[2].Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1339 new_inst
.Src
[2].Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1340 new_inst
.Src
[2].Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1341 new_inst
.Src
[2].Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1343 tctx
->emit_instruction(tctx
, &new_inst
);
1348 emit_decls(struct tgsi_transform_context
*tctx
)
1350 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1351 struct tgsi_shader_info
*info
= ctx
->info
;
1352 struct tgsi_full_declaration decl
;
1353 struct tgsi_full_immediate immed
;
1357 tmpbase
= info
->file_max
[TGSI_FILE_TEMPORARY
] + 1;
1359 ctx
->color_base
= tmpbase
+ ctx
->numtmp
;
1361 /* declare immediate: */
1362 immed
= tgsi_default_full_immediate();
1363 immed
.Immediate
.NrTokens
= 1 + 4; /* one for the token itself */
1364 immed
.u
[0].Float
= 0.0;
1365 immed
.u
[1].Float
= 1.0;
1366 immed
.u
[2].Float
= 128.0;
1367 immed
.u
[3].Float
= 0.0;
1368 tctx
->emit_immediate(tctx
, &immed
);
1370 ctx
->imm
.Register
.File
= TGSI_FILE_IMMEDIATE
;
1371 ctx
->imm
.Register
.Index
= info
->immediate_count
;
1372 ctx
->imm
.Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1373 ctx
->imm
.Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1374 ctx
->imm
.Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1375 ctx
->imm
.Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1377 /* declare temp regs: */
1378 for (i
= 0; i
< ctx
->numtmp
; i
++) {
1379 decl
= tgsi_default_full_declaration();
1380 decl
.Declaration
.File
= TGSI_FILE_TEMPORARY
;
1381 decl
.Range
.First
= decl
.Range
.Last
= tmpbase
+ i
;
1382 tctx
->emit_declaration(tctx
, &decl
);
1384 ctx
->tmp
[i
].src
.Register
.File
= TGSI_FILE_TEMPORARY
;
1385 ctx
->tmp
[i
].src
.Register
.Index
= tmpbase
+ i
;
1386 ctx
->tmp
[i
].src
.Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1387 ctx
->tmp
[i
].src
.Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1388 ctx
->tmp
[i
].src
.Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1389 ctx
->tmp
[i
].src
.Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1391 ctx
->tmp
[i
].dst
.Register
.File
= TGSI_FILE_TEMPORARY
;
1392 ctx
->tmp
[i
].dst
.Register
.Index
= tmpbase
+ i
;
1393 ctx
->tmp
[i
].dst
.Register
.WriteMask
= TGSI_WRITEMASK_XYZW
;
1396 if (ctx
->two_side_colors
)
1401 rename_color_inputs(struct tgsi_lowering_context
*ctx
,
1402 struct tgsi_full_instruction
*inst
)
1405 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1406 struct tgsi_src_register
*src
= &inst
->Src
[i
].Register
;
1407 if (src
->File
== TGSI_FILE_INPUT
) {
1408 for (j
= 0; j
< ctx
->two_side_colors
; j
++) {
1409 if (src
->Index
== ctx
->two_side_idx
[j
]) {
1410 src
->File
= TGSI_FILE_TEMPORARY
;
1411 src
->Index
= ctx
->color_base
+ j
;
1421 transform_instr(struct tgsi_transform_context
*tctx
,
1422 struct tgsi_full_instruction
*inst
)
1424 struct tgsi_lowering_context
*ctx
= tgsi_lowering_context(tctx
);
1426 if (!ctx
->emitted_decls
) {
1428 ctx
->emitted_decls
= 1;
1431 /* if emulating two-sided-color, we need to re-write some
1434 if (ctx
->two_side_colors
)
1435 rename_color_inputs(ctx
, inst
);
1437 switch (inst
->Instruction
.Opcode
) {
1438 case TGSI_OPCODE_DST
:
1439 if (!ctx
->config
->lower_DST
)
1441 transform_dst(tctx
, inst
);
1443 case TGSI_OPCODE_XPD
:
1444 if (!ctx
->config
->lower_XPD
)
1446 transform_xpd(tctx
, inst
);
1448 case TGSI_OPCODE_SCS
:
1449 if (!ctx
->config
->lower_SCS
)
1451 transform_scs(tctx
, inst
);
1453 case TGSI_OPCODE_LRP
:
1454 if (!ctx
->config
->lower_LRP
)
1456 transform_lrp(tctx
, inst
);
1458 case TGSI_OPCODE_FRC
:
1459 if (!ctx
->config
->lower_FRC
)
1461 transform_frc(tctx
, inst
);
1463 case TGSI_OPCODE_POW
:
1464 if (!ctx
->config
->lower_POW
)
1466 transform_pow(tctx
, inst
);
1468 case TGSI_OPCODE_LIT
:
1469 if (!ctx
->config
->lower_LIT
)
1471 transform_lit(tctx
, inst
);
1473 case TGSI_OPCODE_EXP
:
1474 if (!ctx
->config
->lower_EXP
)
1476 transform_exp(tctx
, inst
);
1478 case TGSI_OPCODE_LOG
:
1479 if (!ctx
->config
->lower_LOG
)
1481 transform_log(tctx
, inst
);
1483 case TGSI_OPCODE_DP4
:
1484 if (!ctx
->config
->lower_DP4
)
1486 transform_dotp(tctx
, inst
);
1488 case TGSI_OPCODE_DP3
:
1489 if (!ctx
->config
->lower_DP3
)
1491 transform_dotp(tctx
, inst
);
1493 case TGSI_OPCODE_DPH
:
1494 if (!ctx
->config
->lower_DPH
)
1496 transform_dotp(tctx
, inst
);
1498 case TGSI_OPCODE_DP2
:
1499 if (!ctx
->config
->lower_DP2
)
1501 transform_dotp(tctx
, inst
);
1503 case TGSI_OPCODE_DP2A
:
1504 if (!ctx
->config
->lower_DP2A
)
1506 transform_dotp(tctx
, inst
);
1508 case TGSI_OPCODE_FLR
:
1509 if (!ctx
->config
->lower_FLR
)
1511 transform_flr_ceil(tctx
, inst
);
1513 case TGSI_OPCODE_CEIL
:
1514 if (!ctx
->config
->lower_CEIL
)
1516 transform_flr_ceil(tctx
, inst
);
1518 case TGSI_OPCODE_TEX
:
1519 case TGSI_OPCODE_TXP
:
1520 case TGSI_OPCODE_TXB
:
1521 case TGSI_OPCODE_TXB2
:
1522 case TGSI_OPCODE_TXL
:
1523 if (transform_samp(tctx
, inst
))
1528 tctx
->emit_instruction(tctx
, inst
);
1533 /* returns NULL if no lowering required, else returns the new
1534 * tokens (which caller is required to free()). In either case
1535 * returns the current info.
1537 const struct tgsi_token
*
1538 tgsi_transform_lowering(const struct tgsi_lowering_config
*config
,
1539 const struct tgsi_token
*tokens
,
1540 struct tgsi_shader_info
*info
)
1542 struct tgsi_lowering_context ctx
;
1543 struct tgsi_token
*newtoks
;
1546 /* sanity check in case limit is ever increased: */
1547 STATIC_ASSERT((sizeof(config
->saturate_s
) * 8) >= PIPE_MAX_SAMPLERS
);
1549 /* sanity check the lowering */
1550 assert(!(config
->lower_FRC
&& (config
->lower_FLR
|| config
->lower_CEIL
)));
1552 memset(&ctx
, 0, sizeof(ctx
));
1553 ctx
.base
.transform_instruction
= transform_instr
;
1555 ctx
.config
= config
;
1557 tgsi_scan_shader(tokens
, info
);
1559 /* if we are adding fragment shader support to emulate two-sided
1560 * color, then figure out the number of additional inputs we need
1561 * to create for BCOLOR's..
1563 if ((info
->processor
== TGSI_PROCESSOR_FRAGMENT
) &&
1564 config
->color_two_side
) {
1567 for (i
= 0; i
<= info
->file_max
[TGSI_FILE_INPUT
]; i
++) {
1568 if (info
->input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
)
1569 ctx
.two_side_idx
[ctx
.two_side_colors
++] = i
;
1570 if (info
->input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
1575 ctx
.saturate
= config
->saturate_r
| config
->saturate_s
| config
->saturate_t
;
1577 #define OPCS(x) ((config->lower_ ## x) ? info->opcode_count[TGSI_OPCODE_ ## x] : 0)
1578 /* if there are no instructions to lower, then we are done: */
1596 ctx
.two_side_colors
||
1601 _debug_printf("BEFORE:");
1602 tgsi_dump(tokens
, 0);
1606 newlen
= tgsi_num_tokens(tokens
);
1608 newlen
+= DST_GROW
* OPCS(DST
);
1609 numtmp
= MAX2(numtmp
, DST_TMP
);
1612 newlen
+= XPD_GROW
* OPCS(XPD
);
1613 numtmp
= MAX2(numtmp
, XPD_TMP
);
1616 newlen
+= SCS_GROW
* OPCS(SCS
);
1617 numtmp
= MAX2(numtmp
, SCS_TMP
);
1620 newlen
+= LRP_GROW
* OPCS(LRP
);
1621 numtmp
= MAX2(numtmp
, LRP_TMP
);
1624 newlen
+= FRC_GROW
* OPCS(FRC
);
1625 numtmp
= MAX2(numtmp
, FRC_TMP
);
1628 newlen
+= POW_GROW
* OPCS(POW
);
1629 numtmp
= MAX2(numtmp
, POW_TMP
);
1632 newlen
+= LIT_GROW
* OPCS(LIT
);
1633 numtmp
= MAX2(numtmp
, LIT_TMP
);
1636 newlen
+= EXP_GROW
* OPCS(EXP
);
1637 numtmp
= MAX2(numtmp
, EXP_TMP
);
1640 newlen
+= LOG_GROW
* OPCS(LOG
);
1641 numtmp
= MAX2(numtmp
, LOG_TMP
);
1644 newlen
+= DP4_GROW
* OPCS(DP4
);
1645 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1648 newlen
+= DP3_GROW
* OPCS(DP3
);
1649 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1652 newlen
+= DPH_GROW
* OPCS(DPH
);
1653 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1656 newlen
+= DP2_GROW
* OPCS(DP2
);
1657 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1660 newlen
+= DP2A_GROW
* OPCS(DP2A
);
1661 numtmp
= MAX2(numtmp
, DOTP_TMP
);
1664 newlen
+= FLR_GROW
* OPCS(FLR
);
1665 numtmp
= MAX2(numtmp
, FLR_TMP
);
1668 newlen
+= CEIL_GROW
* OPCS(CEIL
);
1669 numtmp
= MAX2(numtmp
, CEIL_TMP
);
1671 if (ctx
.saturate
|| config
->lower_TXP
) {
1675 n
= info
->opcode_count
[TGSI_OPCODE_TEX
] +
1676 info
->opcode_count
[TGSI_OPCODE_TXP
] +
1677 info
->opcode_count
[TGSI_OPCODE_TXB
] +
1678 info
->opcode_count
[TGSI_OPCODE_TXB2
] +
1679 info
->opcode_count
[TGSI_OPCODE_TXL
];
1680 } else if (config
->lower_TXP
) {
1681 n
= info
->opcode_count
[TGSI_OPCODE_TXP
];
1684 newlen
+= SAMP_GROW
* n
;
1685 numtmp
= MAX2(numtmp
, SAMP_TMP
);
1688 /* specifically don't include two_side_colors temps in the count: */
1689 ctx
.numtmp
= numtmp
;
1691 if (ctx
.two_side_colors
) {
1692 newlen
+= TWOSIDE_GROW(ctx
.two_side_colors
);
1693 /* note: we permanently consume temp regs, re-writing references
1694 * to IN.COLOR[n] to TEMP[m] (holding the output of of the CMP
1695 * instruction that selects which varying to use):
1697 numtmp
+= ctx
.two_side_colors
;
1700 newlen
+= 2 * numtmp
;
1701 newlen
+= 5; /* immediate */
1703 newtoks
= tgsi_alloc_tokens(newlen
);
1707 tgsi_transform_shader(tokens
, newtoks
, newlen
, &ctx
.base
);
1709 tgsi_scan_shader(newtoks
, info
);
1712 _debug_printf("AFTER:");
1713 tgsi_dump(newtoks
, 0);