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gallium: remove TGSI opcode DP2A
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_lowering.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "tgsi/tgsi_transform.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_dump.h"
30
31 #include "util/u_debug.h"
32 #include "util/u_math.h"
33
34 #include "tgsi_lowering.h"
35
36 struct tgsi_lowering_context {
37 struct tgsi_transform_context base;
38 const struct tgsi_lowering_config *config;
39 struct tgsi_shader_info *info;
40 unsigned two_side_colors;
41 unsigned two_side_idx[PIPE_MAX_SHADER_INPUTS];
42 unsigned color_base; /* base register for chosen COLOR/BCOLOR's */
43 int face_idx;
44 unsigned numtmp;
45 struct {
46 struct tgsi_full_src_register src;
47 struct tgsi_full_dst_register dst;
48 } tmp[2];
49 #define A 0
50 #define B 1
51 struct tgsi_full_src_register imm;
52 int emitted_decls;
53 unsigned saturate;
54 };
55
56 static inline struct tgsi_lowering_context *
57 tgsi_lowering_context(struct tgsi_transform_context *tctx)
58 {
59 return (struct tgsi_lowering_context *)tctx;
60 }
61
62 /*
63 * Utility helpers:
64 */
65
66 static void
67 reg_dst(struct tgsi_full_dst_register *dst,
68 const struct tgsi_full_dst_register *orig_dst, unsigned wrmask)
69 {
70 *dst = *orig_dst;
71 dst->Register.WriteMask &= wrmask;
72 assert(dst->Register.WriteMask);
73 }
74
75 static inline void
76 get_swiz(unsigned *swiz, const struct tgsi_src_register *src)
77 {
78 swiz[0] = src->SwizzleX;
79 swiz[1] = src->SwizzleY;
80 swiz[2] = src->SwizzleZ;
81 swiz[3] = src->SwizzleW;
82 }
83
84 static void
85 reg_src(struct tgsi_full_src_register *src,
86 const struct tgsi_full_src_register *orig_src,
87 unsigned sx, unsigned sy, unsigned sz, unsigned sw)
88 {
89 unsigned swiz[4];
90 get_swiz(swiz, &orig_src->Register);
91 *src = *orig_src;
92 src->Register.SwizzleX = swiz[sx];
93 src->Register.SwizzleY = swiz[sy];
94 src->Register.SwizzleZ = swiz[sz];
95 src->Register.SwizzleW = swiz[sw];
96 }
97
98 #define TGSI_SWIZZLE__ TGSI_SWIZZLE_X /* don't-care value! */
99 #define SWIZ(x,y,z,w) TGSI_SWIZZLE_ ## x, TGSI_SWIZZLE_ ## y, \
100 TGSI_SWIZZLE_ ## z, TGSI_SWIZZLE_ ## w
101
102 /*
103 * if (dst.x aliases src.x) {
104 * MOV tmpA.x, src.x
105 * src = tmpA
106 * }
107 * COS dst.x, src.x
108 * SIN dst.y, src.x
109 * MOV dst.zw, imm{0.0, 1.0}
110 */
111 static bool
112 aliases(const struct tgsi_full_dst_register *dst, unsigned dst_mask,
113 const struct tgsi_full_src_register *src, unsigned src_mask)
114 {
115 if ((dst->Register.File == src->Register.File) &&
116 (dst->Register.Index == src->Register.Index)) {
117 unsigned i, actual_mask = 0;
118 unsigned swiz[4];
119 get_swiz(swiz, &src->Register);
120 for (i = 0; i < 4; i++)
121 if (src_mask & (1 << i))
122 actual_mask |= (1 << swiz[i]);
123 if (actual_mask & dst_mask)
124 return true;
125 }
126 return false;
127 }
128
129 static void
130 create_mov(struct tgsi_transform_context *tctx,
131 const struct tgsi_full_dst_register *dst,
132 const struct tgsi_full_src_register *src,
133 unsigned mask, unsigned saturate)
134 {
135 struct tgsi_full_instruction new_inst;
136
137 new_inst = tgsi_default_full_instruction();
138 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
139 new_inst.Instruction.Saturate = saturate;
140 new_inst.Instruction.NumDstRegs = 1;
141 reg_dst(&new_inst.Dst[0], dst, mask);
142 new_inst.Instruction.NumSrcRegs = 1;
143 reg_src(&new_inst.Src[0], src, SWIZ(X, Y, Z, W));
144 tctx->emit_instruction(tctx, &new_inst);
145 }
146
147 /* to help calculate # of tgsi tokens for a lowering.. we assume
148 * the worst case, ie. removed instructions don't have ADDR[] or
149 * anything which increases the # of tokens per src/dst and the
150 * inserted instructions do.
151 *
152 * OINST() - old instruction
153 * 1 : instruction itself
154 * 1 : dst
155 * 1 * nargs : srcN
156 *
157 * NINST() - new instruction
158 * 1 : instruction itself
159 * 2 : dst
160 * 2 * nargs : srcN
161 */
162
163 #define OINST(nargs) (1 + 1 + 1 * (nargs))
164 #define NINST(nargs) (1 + 2 + 2 * (nargs))
165
166 /*
167 * Lowering Translators:
168 */
169
170 /* DST - Distance Vector
171 * dst.x = 1.0
172 * dst.y = src0.y \times src1.y
173 * dst.z = src0.z
174 * dst.w = src1.w
175 *
176 * ; note: could be more clever and use just a single temp
177 * ; if I was clever enough to re-write the swizzles.
178 * ; needs: 2 tmp, imm{1.0}
179 * if (dst.y aliases src0.z) {
180 * MOV tmpA.yz, src0.yz
181 * src0 = tmpA
182 * }
183 * if (dst.yz aliases src1.w) {
184 * MOV tmpB.yw, src1.yw
185 * src1 = tmpB
186 * }
187 * MUL dst.y, src0.y, src1.y
188 * MOV dst.z, src0.z
189 * MOV dst.w, src1.w
190 * MOV dst.x, imm{1.0}
191 */
192 #define DST_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1) + \
193 NINST(1) + NINST(1) - OINST(2))
194 #define DST_TMP 2
195 static void
196 transform_dst(struct tgsi_transform_context *tctx,
197 struct tgsi_full_instruction *inst)
198 {
199 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
200 struct tgsi_full_dst_register *dst = &inst->Dst[0];
201 struct tgsi_full_src_register *src0 = &inst->Src[0];
202 struct tgsi_full_src_register *src1 = &inst->Src[1];
203 struct tgsi_full_instruction new_inst;
204
205 if (aliases(dst, TGSI_WRITEMASK_Y, src0, TGSI_WRITEMASK_Z)) {
206 create_mov(tctx, &ctx->tmp[A].dst, src0, TGSI_WRITEMASK_YZ, 0);
207 src0 = &ctx->tmp[A].src;
208 }
209
210 if (aliases(dst, TGSI_WRITEMASK_YZ, src1, TGSI_WRITEMASK_W)) {
211 create_mov(tctx, &ctx->tmp[B].dst, src1, TGSI_WRITEMASK_YW, 0);
212 src1 = &ctx->tmp[B].src;
213 }
214
215 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) {
216 /* MUL dst.y, src0.y, src1.y */
217 new_inst = tgsi_default_full_instruction();
218 new_inst.Instruction.Opcode = TGSI_OPCODE_MUL;
219 new_inst.Instruction.NumDstRegs = 1;
220 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_Y);
221 new_inst.Instruction.NumSrcRegs = 2;
222 reg_src(&new_inst.Src[0], src0, SWIZ(_, Y, _, _));
223 reg_src(&new_inst.Src[1], src1, SWIZ(_, Y, _, _));
224 tctx->emit_instruction(tctx, &new_inst);
225 }
226
227 if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) {
228 /* MOV dst.z, src0.z */
229 new_inst = tgsi_default_full_instruction();
230 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
231 new_inst.Instruction.NumDstRegs = 1;
232 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_Z);
233 new_inst.Instruction.NumSrcRegs = 1;
234 reg_src(&new_inst.Src[0], src0, SWIZ(_, _, Z, _));
235 tctx->emit_instruction(tctx, &new_inst);
236 }
237
238 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) {
239 /* MOV dst.w, src1.w */
240 new_inst = tgsi_default_full_instruction();
241 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
242 new_inst.Instruction.NumDstRegs = 1;
243 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_W);
244 new_inst.Instruction.NumSrcRegs = 1;
245 reg_src(&new_inst.Src[0], src1, SWIZ(_, _, _, W));
246 tctx->emit_instruction(tctx, &new_inst);
247 }
248
249 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
250 /* MOV dst.x, imm{1.0} */
251 new_inst = tgsi_default_full_instruction();
252 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
253 new_inst.Instruction.NumDstRegs = 1;
254 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_X);
255 new_inst.Instruction.NumSrcRegs = 1;
256 reg_src(&new_inst.Src[0], &ctx->imm, SWIZ(Y, _, _, _));
257 tctx->emit_instruction(tctx, &new_inst);
258 }
259 }
260
261 /* XPD - Cross Product
262 * dst.x = src0.y \times src1.z - src1.y \times src0.z
263 * dst.y = src0.z \times src1.x - src1.z \times src0.x
264 * dst.z = src0.x \times src1.y - src1.x \times src0.y
265 * dst.w = 1.0
266 *
267 * ; needs: 1 tmp, imm{1.0}
268 * MUL tmpA.xyz, src1.yzx, src0.zxy
269 * MAD dst.xyz, src0.yzx, src1.zxy, -tmpA.xyz
270 * MOV dst.w, imm{1.0}
271 */
272 #define XPD_GROW (NINST(2) + NINST(3) + NINST(1) - OINST(2))
273 #define XPD_TMP 1
274 static void
275 transform_xpd(struct tgsi_transform_context *tctx,
276 struct tgsi_full_instruction *inst)
277 {
278 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
279 struct tgsi_full_dst_register *dst = &inst->Dst[0];
280 struct tgsi_full_src_register *src0 = &inst->Src[0];
281 struct tgsi_full_src_register *src1 = &inst->Src[1];
282 struct tgsi_full_instruction new_inst;
283
284 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZ) {
285 /* MUL tmpA.xyz, src1.yzx, src0.zxy */
286 new_inst = tgsi_default_full_instruction();
287 new_inst.Instruction.Opcode = TGSI_OPCODE_MUL;
288 new_inst.Instruction.NumDstRegs = 1;
289 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZ);
290 new_inst.Instruction.NumSrcRegs = 2;
291 reg_src(&new_inst.Src[0], src1, SWIZ(Y, Z, X, _));
292 reg_src(&new_inst.Src[1], src0, SWIZ(Z, X, Y, _));
293 tctx->emit_instruction(tctx, &new_inst);
294
295 /* MAD dst.xyz, src0.yzx, src1.zxy, -tmpA.xyz */
296 new_inst = tgsi_default_full_instruction();
297 new_inst.Instruction.Opcode = TGSI_OPCODE_MAD;
298 new_inst.Instruction.NumDstRegs = 1;
299 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZ);
300 new_inst.Instruction.NumSrcRegs = 3;
301 reg_src(&new_inst.Src[0], src0, SWIZ(Y, Z, X, _));
302 reg_src(&new_inst.Src[1], src1, SWIZ(Z, X, Y, _));
303 reg_src(&new_inst.Src[2], &ctx->tmp[A].src, SWIZ(X, Y, Z, _));
304 new_inst.Src[2].Register.Negate = true;
305 tctx->emit_instruction(tctx, &new_inst);
306 }
307
308 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) {
309 /* MOV dst.w, imm{1.0} */
310 new_inst = tgsi_default_full_instruction();
311 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
312 new_inst.Instruction.NumDstRegs = 1;
313 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_W);
314 new_inst.Instruction.NumSrcRegs = 1;
315 reg_src(&new_inst.Src[0], &ctx->imm, SWIZ(_, _, _, Y));
316 tctx->emit_instruction(tctx, &new_inst);
317 }
318 }
319
320 /* SCS - Sine Cosine
321 * dst.x = \cos{src.x}
322 * dst.y = \sin{src.x}
323 * dst.z = 0.0
324 * dst.w = 1.0
325 *
326 * ; needs: 1 tmp, imm{0.0, 1.0}
327 * if (dst.x aliases src.x) {
328 * MOV tmpA.x, src.x
329 * src = tmpA
330 * }
331 * COS dst.x, src.x
332 * SIN dst.y, src.x
333 * MOV dst.zw, imm{0.0, 1.0}
334 */
335 #define SCS_GROW (NINST(1) + NINST(1) + NINST(1) + NINST(1) - OINST(1))
336 #define SCS_TMP 1
337 static void
338 transform_scs(struct tgsi_transform_context *tctx,
339 struct tgsi_full_instruction *inst)
340 {
341 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
342 struct tgsi_full_dst_register *dst = &inst->Dst[0];
343 struct tgsi_full_src_register *src = &inst->Src[0];
344 struct tgsi_full_instruction new_inst;
345
346 if (aliases(dst, TGSI_WRITEMASK_X, src, TGSI_WRITEMASK_X)) {
347 create_mov(tctx, &ctx->tmp[A].dst, src, TGSI_WRITEMASK_X, 0);
348 src = &ctx->tmp[A].src;
349 }
350
351 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
352 /* COS dst.x, src.x */
353 new_inst = tgsi_default_full_instruction();
354 new_inst.Instruction.Opcode = TGSI_OPCODE_COS;
355 new_inst.Instruction.NumDstRegs = 1;
356 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_X);
357 new_inst.Instruction.NumSrcRegs = 1;
358 reg_src(&new_inst.Src[0], src, SWIZ(X, _, _, _));
359 tctx->emit_instruction(tctx, &new_inst);
360 }
361
362 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) {
363 /* SIN dst.y, src.x */
364 new_inst = tgsi_default_full_instruction();
365 new_inst.Instruction.Opcode = TGSI_OPCODE_SIN;
366 new_inst.Instruction.NumDstRegs = 1;
367 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_Y);
368 new_inst.Instruction.NumSrcRegs = 1;
369 reg_src(&new_inst.Src[0], src, SWIZ(X, _, _, _));
370 tctx->emit_instruction(tctx, &new_inst);
371 }
372
373 if (dst->Register.WriteMask & TGSI_WRITEMASK_ZW) {
374 /* MOV dst.zw, imm{0.0, 1.0} */
375 new_inst = tgsi_default_full_instruction();
376 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
377 new_inst.Instruction.NumDstRegs = 1;
378 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_ZW);
379 new_inst.Instruction.NumSrcRegs = 1;
380 reg_src(&new_inst.Src[0], &ctx->imm, SWIZ(_, _, X, Y));
381 tctx->emit_instruction(tctx, &new_inst);
382 }
383 }
384
385 /* LRP - Linear Interpolate
386 * dst.x = src0.x \times src1.x + (1.0 - src0.x) \times src2.x
387 * dst.y = src0.y \times src1.y + (1.0 - src0.y) \times src2.y
388 * dst.z = src0.z \times src1.z + (1.0 - src0.z) \times src2.z
389 * dst.w = src0.w \times src1.w + (1.0 - src0.w) \times src2.w
390 *
391 * This becomes: src0 \times src1 + src2 - src0 \times src2, which
392 * can then become: src0 \times src1 - (src0 \times src2 - src2)
393 *
394 * ; needs: 1 tmp
395 * MAD tmpA, src0, src2, -src2
396 * MAD dst, src0, src1, -tmpA
397 */
398 #define LRP_GROW (NINST(3) + NINST(3) - OINST(3))
399 #define LRP_TMP 1
400 static void
401 transform_lrp(struct tgsi_transform_context *tctx,
402 struct tgsi_full_instruction *inst)
403 {
404 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
405 struct tgsi_full_dst_register *dst = &inst->Dst[0];
406 struct tgsi_full_src_register *src0 = &inst->Src[0];
407 struct tgsi_full_src_register *src1 = &inst->Src[1];
408 struct tgsi_full_src_register *src2 = &inst->Src[2];
409 struct tgsi_full_instruction new_inst;
410
411 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
412 /* MAD tmpA, src0, src2, -src2 */
413 new_inst = tgsi_default_full_instruction();
414 new_inst.Instruction.Opcode = TGSI_OPCODE_MAD;
415 new_inst.Instruction.NumDstRegs = 1;
416 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW);
417 new_inst.Instruction.NumSrcRegs = 3;
418 reg_src(&new_inst.Src[0], src0, SWIZ(X, Y, Z, W));
419 reg_src(&new_inst.Src[1], src2, SWIZ(X, Y, Z, W));
420 reg_src(&new_inst.Src[2], src2, SWIZ(X, Y, Z, W));
421 new_inst.Src[2].Register.Negate = !new_inst.Src[2].Register.Negate;
422 tctx->emit_instruction(tctx, &new_inst);
423
424 /* MAD dst, src0, src1, -tmpA */
425 new_inst = tgsi_default_full_instruction();
426 new_inst.Instruction.Opcode = TGSI_OPCODE_MAD;
427 new_inst.Instruction.NumDstRegs = 1;
428 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
429 new_inst.Instruction.NumSrcRegs = 3;
430 reg_src(&new_inst.Src[0], src0, SWIZ(X, Y, Z, W));
431 reg_src(&new_inst.Src[1], src1, SWIZ(X, Y, Z, W));
432 reg_src(&new_inst.Src[2], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
433 new_inst.Src[2].Register.Negate = true;
434 tctx->emit_instruction(tctx, &new_inst);
435 }
436 }
437
438 /* FRC - Fraction
439 * dst.x = src.x - \lfloor src.x\rfloor
440 * dst.y = src.y - \lfloor src.y\rfloor
441 * dst.z = src.z - \lfloor src.z\rfloor
442 * dst.w = src.w - \lfloor src.w\rfloor
443 *
444 * ; needs: 1 tmp
445 * FLR tmpA, src
446 * SUB dst, src, tmpA
447 */
448 #define FRC_GROW (NINST(1) + NINST(2) - OINST(1))
449 #define FRC_TMP 1
450 static void
451 transform_frc(struct tgsi_transform_context *tctx,
452 struct tgsi_full_instruction *inst)
453 {
454 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
455 struct tgsi_full_dst_register *dst = &inst->Dst[0];
456 struct tgsi_full_src_register *src = &inst->Src[0];
457 struct tgsi_full_instruction new_inst;
458
459 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
460 /* FLR tmpA, src */
461 new_inst = tgsi_default_full_instruction();
462 new_inst.Instruction.Opcode = TGSI_OPCODE_FLR;
463 new_inst.Instruction.NumDstRegs = 1;
464 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW);
465 new_inst.Instruction.NumSrcRegs = 1;
466 reg_src(&new_inst.Src[0], src, SWIZ(X, Y, Z, W));
467 tctx->emit_instruction(tctx, &new_inst);
468
469 /* SUB dst, src, tmpA */
470 new_inst = tgsi_default_full_instruction();
471 new_inst.Instruction.Opcode = TGSI_OPCODE_ADD;
472 new_inst.Instruction.NumDstRegs = 1;
473 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
474 new_inst.Instruction.NumSrcRegs = 2;
475 reg_src(&new_inst.Src[0], src, SWIZ(X, Y, Z, W));
476 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
477 new_inst.Src[1].Register.Negate = 1;
478 tctx->emit_instruction(tctx, &new_inst);
479 }
480 }
481
482 /* POW - Power
483 * dst.x = src0.x^{src1.x}
484 * dst.y = src0.x^{src1.x}
485 * dst.z = src0.x^{src1.x}
486 * dst.w = src0.x^{src1.x}
487 *
488 * ; needs: 1 tmp
489 * LG2 tmpA.x, src0.x
490 * MUL tmpA.x, src1.x, tmpA.x
491 * EX2 dst, tmpA.x
492 */
493 #define POW_GROW (NINST(1) + NINST(2) + NINST(1) - OINST(2))
494 #define POW_TMP 1
495 static void
496 transform_pow(struct tgsi_transform_context *tctx,
497 struct tgsi_full_instruction *inst)
498 {
499 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
500 struct tgsi_full_dst_register *dst = &inst->Dst[0];
501 struct tgsi_full_src_register *src0 = &inst->Src[0];
502 struct tgsi_full_src_register *src1 = &inst->Src[1];
503 struct tgsi_full_instruction new_inst;
504
505 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
506 /* LG2 tmpA.x, src0.x */
507 new_inst = tgsi_default_full_instruction();
508 new_inst.Instruction.Opcode = TGSI_OPCODE_LG2;
509 new_inst.Instruction.NumDstRegs = 1;
510 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
511 new_inst.Instruction.NumSrcRegs = 1;
512 reg_src(&new_inst.Src[0], src0, SWIZ(X, _, _, _));
513 tctx->emit_instruction(tctx, &new_inst);
514
515 /* MUL tmpA.x, src1.x, tmpA.x */
516 new_inst = tgsi_default_full_instruction();
517 new_inst.Instruction.Opcode = TGSI_OPCODE_MUL;
518 new_inst.Instruction.NumDstRegs = 1;
519 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
520 new_inst.Instruction.NumSrcRegs = 2;
521 reg_src(&new_inst.Src[0], src1, SWIZ(X, _, _, _));
522 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(X, _, _, _));
523 tctx->emit_instruction(tctx, &new_inst);
524
525 /* EX2 dst, tmpA.x */
526 new_inst = tgsi_default_full_instruction();
527 new_inst.Instruction.Opcode = TGSI_OPCODE_EX2;
528 new_inst.Instruction.NumDstRegs = 1;
529 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
530 new_inst.Instruction.NumSrcRegs = 1;
531 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(X, _, _, _));
532 tctx->emit_instruction(tctx, &new_inst);
533 }
534 }
535
536 /* LIT - Light Coefficients
537 * dst.x = 1.0
538 * dst.y = max(src.x, 0.0)
539 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
540 * dst.w = 1.0
541 *
542 * ; needs: 1 tmp, imm{0.0}, imm{1.0}, imm{128.0}
543 * MAX tmpA.xy, src.xy, imm{0.0}
544 * CLAMP tmpA.z, src.w, -imm{128.0}, imm{128.0}
545 * LG2 tmpA.y, tmpA.y
546 * MUL tmpA.y, tmpA.z, tmpA.y
547 * EX2 tmpA.y, tmpA.y
548 * CMP tmpA.y, -src.x, tmpA.y, imm{0.0}
549 * MOV dst.yz, tmpA.xy
550 * MOV dst.xw, imm{1.0}
551 */
552 #define LIT_GROW (NINST(1) + NINST(3) + NINST(1) + NINST(2) + \
553 NINST(1) + NINST(3) + NINST(1) + NINST(1) - OINST(1))
554 #define LIT_TMP 1
555 static void
556 transform_lit(struct tgsi_transform_context *tctx,
557 struct tgsi_full_instruction *inst)
558 {
559 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
560 struct tgsi_full_dst_register *dst = &inst->Dst[0];
561 struct tgsi_full_src_register *src = &inst->Src[0];
562 struct tgsi_full_instruction new_inst;
563
564 if (dst->Register.WriteMask & TGSI_WRITEMASK_YZ) {
565 /* MAX tmpA.xy, src.xy, imm{0.0} */
566 new_inst = tgsi_default_full_instruction();
567 new_inst.Instruction.Opcode = TGSI_OPCODE_MAX;
568 new_inst.Instruction.NumDstRegs = 1;
569 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XY);
570 new_inst.Instruction.NumSrcRegs = 2;
571 reg_src(&new_inst.Src[0], src, SWIZ(X, Y, _, _));
572 reg_src(&new_inst.Src[1], &ctx->imm, SWIZ(X, X, _, _));
573 tctx->emit_instruction(tctx, &new_inst);
574
575 /* MIN tmpA.z, src.w, imm{128.0} */
576 new_inst = tgsi_default_full_instruction();
577 new_inst.Instruction.Opcode = TGSI_OPCODE_MIN;
578 new_inst.Instruction.NumDstRegs = 1;
579 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Z);
580 new_inst.Instruction.NumSrcRegs = 2;
581 reg_src(&new_inst.Src[0], src, SWIZ(_, _, W, _));
582 reg_src(&new_inst.Src[1], &ctx->imm, SWIZ(_, _, Z, _));
583 tctx->emit_instruction(tctx, &new_inst);
584
585 /* MAX tmpA.z, tmpA.z, -imm{128.0} */
586 new_inst = tgsi_default_full_instruction();
587 new_inst.Instruction.Opcode = TGSI_OPCODE_MAX;
588 new_inst.Instruction.NumDstRegs = 1;
589 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Z);
590 new_inst.Instruction.NumSrcRegs = 2;
591 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(_, _, Z, _));
592 reg_src(&new_inst.Src[1], &ctx->imm, SWIZ(_, _, Z, _));
593 new_inst.Src[1].Register.Negate = true;
594 tctx->emit_instruction(tctx, &new_inst);
595
596 /* LG2 tmpA.y, tmpA.y */
597 new_inst = tgsi_default_full_instruction();
598 new_inst.Instruction.Opcode = TGSI_OPCODE_LG2;
599 new_inst.Instruction.NumDstRegs = 1;
600 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Y);
601 new_inst.Instruction.NumSrcRegs = 1;
602 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(Y, _, _, _));
603 tctx->emit_instruction(tctx, &new_inst);
604
605 /* MUL tmpA.y, tmpA.z, tmpA.y */
606 new_inst = tgsi_default_full_instruction();
607 new_inst.Instruction.Opcode = TGSI_OPCODE_MUL;
608 new_inst.Instruction.NumDstRegs = 1;
609 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Y);
610 new_inst.Instruction.NumSrcRegs = 2;
611 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(_, Z, _, _));
612 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(_, Y, _, _));
613 tctx->emit_instruction(tctx, &new_inst);
614
615 /* EX2 tmpA.y, tmpA.y */
616 new_inst = tgsi_default_full_instruction();
617 new_inst.Instruction.Opcode = TGSI_OPCODE_EX2;
618 new_inst.Instruction.NumDstRegs = 1;
619 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Y);
620 new_inst.Instruction.NumSrcRegs = 1;
621 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(Y, _, _, _));
622 tctx->emit_instruction(tctx, &new_inst);
623
624 /* CMP tmpA.y, -src.x, tmpA.y, imm{0.0} */
625 new_inst = tgsi_default_full_instruction();
626 new_inst.Instruction.Opcode = TGSI_OPCODE_CMP;
627 new_inst.Instruction.NumDstRegs = 1;
628 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Y);
629 new_inst.Instruction.NumSrcRegs = 3;
630 reg_src(&new_inst.Src[0], src, SWIZ(_, X, _, _));
631 new_inst.Src[0].Register.Negate = true;
632 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(_, Y, _, _));
633 reg_src(&new_inst.Src[2], &ctx->imm, SWIZ(_, X, _, _));
634 tctx->emit_instruction(tctx, &new_inst);
635
636 /* MOV dst.yz, tmpA.xy */
637 new_inst = tgsi_default_full_instruction();
638 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
639 new_inst.Instruction.NumDstRegs = 1;
640 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_YZ);
641 new_inst.Instruction.NumSrcRegs = 1;
642 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(_, X, Y, _));
643 tctx->emit_instruction(tctx, &new_inst);
644 }
645
646 if (dst->Register.WriteMask & TGSI_WRITEMASK_XW) {
647 /* MOV dst.xw, imm{1.0} */
648 new_inst = tgsi_default_full_instruction();
649 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
650 new_inst.Instruction.NumDstRegs = 1;
651 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XW);
652 new_inst.Instruction.NumSrcRegs = 1;
653 reg_src(&new_inst.Src[0], &ctx->imm, SWIZ(Y, _, _, Y));
654 tctx->emit_instruction(tctx, &new_inst);
655 }
656 }
657
658 /* EXP - Approximate Exponential Base 2
659 * dst.x = 2^{\lfloor src.x\rfloor}
660 * dst.y = src.x - \lfloor src.x\rfloor
661 * dst.z = 2^{src.x}
662 * dst.w = 1.0
663 *
664 * ; needs: 1 tmp, imm{1.0}
665 * if (lowering FLR) {
666 * FRC tmpA.x, src.x
667 * SUB tmpA.x, src.x, tmpA.x
668 * } else {
669 * FLR tmpA.x, src.x
670 * }
671 * EX2 tmpA.y, src.x
672 * SUB dst.y, src.x, tmpA.x
673 * EX2 dst.x, tmpA.x
674 * MOV dst.z, tmpA.y
675 * MOV dst.w, imm{1.0}
676 */
677 #define EXP_GROW (NINST(1) + NINST(2) + NINST(1) + NINST(2) + NINST(1) + \
678 NINST(1)+ NINST(1) - OINST(1))
679 #define EXP_TMP 1
680 static void
681 transform_exp(struct tgsi_transform_context *tctx,
682 struct tgsi_full_instruction *inst)
683 {
684 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
685 struct tgsi_full_dst_register *dst = &inst->Dst[0];
686 struct tgsi_full_src_register *src = &inst->Src[0];
687 struct tgsi_full_instruction new_inst;
688
689 if (dst->Register.WriteMask & TGSI_WRITEMASK_XY) {
690 if (ctx->config->lower_FLR) {
691 /* FRC tmpA.x, src.x */
692 new_inst = tgsi_default_full_instruction();
693 new_inst.Instruction.Opcode = TGSI_OPCODE_FRC;
694 new_inst.Instruction.NumDstRegs = 1;
695 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
696 new_inst.Instruction.NumSrcRegs = 1;
697 reg_src(&new_inst.Src[0], src, SWIZ(X, _, _, _));
698 tctx->emit_instruction(tctx, &new_inst);
699
700 /* SUB tmpA.x, src.x, tmpA.x */
701 new_inst = tgsi_default_full_instruction();
702 new_inst.Instruction.Opcode = TGSI_OPCODE_ADD;
703 new_inst.Instruction.NumDstRegs = 1;
704 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
705 new_inst.Instruction.NumSrcRegs = 2;
706 reg_src(&new_inst.Src[0], src, SWIZ(X, _, _, _));
707 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(X, _, _, _));
708 new_inst.Src[1].Register.Negate = 1;
709 tctx->emit_instruction(tctx, &new_inst);
710 } else {
711 /* FLR tmpA.x, src.x */
712 new_inst = tgsi_default_full_instruction();
713 new_inst.Instruction.Opcode = TGSI_OPCODE_FLR;
714 new_inst.Instruction.NumDstRegs = 1;
715 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
716 new_inst.Instruction.NumSrcRegs = 1;
717 reg_src(&new_inst.Src[0], src, SWIZ(X, _, _, _));
718 tctx->emit_instruction(tctx, &new_inst);
719 }
720 }
721
722 if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) {
723 /* EX2 tmpA.y, src.x */
724 new_inst = tgsi_default_full_instruction();
725 new_inst.Instruction.Opcode = TGSI_OPCODE_EX2;
726 new_inst.Instruction.NumDstRegs = 1;
727 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Y);
728 new_inst.Instruction.NumSrcRegs = 1;
729 reg_src(&new_inst.Src[0], src, SWIZ(X, _, _, _));
730 tctx->emit_instruction(tctx, &new_inst);
731 }
732
733 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) {
734 /* SUB dst.y, src.x, tmpA.x */
735 new_inst = tgsi_default_full_instruction();
736 new_inst.Instruction.Opcode = TGSI_OPCODE_ADD;
737 new_inst.Instruction.NumDstRegs = 1;
738 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_Y);
739 new_inst.Instruction.NumSrcRegs = 2;
740 reg_src(&new_inst.Src[0], src, SWIZ(_, X, _, _));
741 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(_, X, _, _));
742 new_inst.Src[1].Register.Negate = 1;
743 tctx->emit_instruction(tctx, &new_inst);
744 }
745
746 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
747 /* EX2 dst.x, tmpA.x */
748 new_inst = tgsi_default_full_instruction();
749 new_inst.Instruction.Opcode = TGSI_OPCODE_EX2;
750 new_inst.Instruction.NumDstRegs = 1;
751 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_X);
752 new_inst.Instruction.NumSrcRegs = 1;
753 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(X, _, _, _));
754 tctx->emit_instruction(tctx, &new_inst);
755 }
756
757 if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) {
758 /* MOV dst.z, tmpA.y */
759 new_inst = tgsi_default_full_instruction();
760 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
761 new_inst.Instruction.NumDstRegs = 1;
762 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_Z);
763 new_inst.Instruction.NumSrcRegs = 1;
764 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(_, _, Y, _));
765 tctx->emit_instruction(tctx, &new_inst);
766 }
767
768 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) {
769 /* MOV dst.w, imm{1.0} */
770 new_inst = tgsi_default_full_instruction();
771 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
772 new_inst.Instruction.NumDstRegs = 1;
773 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_W);
774 new_inst.Instruction.NumSrcRegs = 1;
775 reg_src(&new_inst.Src[0], &ctx->imm, SWIZ(_, _, _, Y));
776 tctx->emit_instruction(tctx, &new_inst);
777 }
778 }
779
780 /* LOG - Approximate Logarithm Base 2
781 * dst.x = \lfloor\log_2{|src.x|}\rfloor
782 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
783 * dst.z = \log_2{|src.x|}
784 * dst.w = 1.0
785 *
786 * ; needs: 1 tmp, imm{1.0}
787 * LG2 tmpA.x, |src.x|
788 * if (lowering FLR) {
789 * FRC tmpA.y, tmpA.x
790 * SUB tmpA.y, tmpA.x, tmpA.y
791 * } else {
792 * FLR tmpA.y, tmpA.x
793 * }
794 * EX2 tmpA.z, tmpA.y
795 * RCP tmpA.z, tmpA.z
796 * MUL dst.y, |src.x|, tmpA.z
797 * MOV dst.xz, tmpA.yx
798 * MOV dst.w, imm{1.0}
799 */
800 #define LOG_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1) + NINST(1) + \
801 NINST(2) + NINST(1) + NINST(1) - OINST(1))
802 #define LOG_TMP 1
803 static void
804 transform_log(struct tgsi_transform_context *tctx,
805 struct tgsi_full_instruction *inst)
806 {
807 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
808 struct tgsi_full_dst_register *dst = &inst->Dst[0];
809 struct tgsi_full_src_register *src = &inst->Src[0];
810 struct tgsi_full_instruction new_inst;
811
812 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZ) {
813 /* LG2 tmpA.x, |src.x| */
814 new_inst = tgsi_default_full_instruction();
815 new_inst.Instruction.Opcode = TGSI_OPCODE_LG2;
816 new_inst.Instruction.NumDstRegs = 1;
817 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
818 new_inst.Instruction.NumSrcRegs = 1;
819 reg_src(&new_inst.Src[0], src, SWIZ(X, _, _, _));
820 new_inst.Src[0].Register.Absolute = true;
821 tctx->emit_instruction(tctx, &new_inst);
822 }
823
824 if (dst->Register.WriteMask & TGSI_WRITEMASK_XY) {
825 if (ctx->config->lower_FLR) {
826 /* FRC tmpA.y, tmpA.x */
827 new_inst = tgsi_default_full_instruction();
828 new_inst.Instruction.Opcode = TGSI_OPCODE_FRC;
829 new_inst.Instruction.NumDstRegs = 1;
830 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Y);
831 new_inst.Instruction.NumSrcRegs = 1;
832 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(_, X, _, _));
833 tctx->emit_instruction(tctx, &new_inst);
834
835 /* SUB tmpA.y, tmpA.x, tmpA.y */
836 new_inst = tgsi_default_full_instruction();
837 new_inst.Instruction.Opcode = TGSI_OPCODE_ADD;
838 new_inst.Instruction.NumDstRegs = 1;
839 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Y);
840 new_inst.Instruction.NumSrcRegs = 2;
841 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(_, X, _, _));
842 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(_, Y, _, _));
843 new_inst.Src[1].Register.Negate = 1;
844 tctx->emit_instruction(tctx, &new_inst);
845 } else {
846 /* FLR tmpA.y, tmpA.x */
847 new_inst = tgsi_default_full_instruction();
848 new_inst.Instruction.Opcode = TGSI_OPCODE_FLR;
849 new_inst.Instruction.NumDstRegs = 1;
850 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Y);
851 new_inst.Instruction.NumSrcRegs = 1;
852 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(_, X, _, _));
853 tctx->emit_instruction(tctx, &new_inst);
854 }
855 }
856
857 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) {
858 /* EX2 tmpA.z, tmpA.y */
859 new_inst = tgsi_default_full_instruction();
860 new_inst.Instruction.Opcode = TGSI_OPCODE_EX2;
861 new_inst.Instruction.NumDstRegs = 1;
862 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Z);
863 new_inst.Instruction.NumSrcRegs = 1;
864 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(Y, _, _, _));
865 tctx->emit_instruction(tctx, &new_inst);
866
867 /* RCP tmpA.z, tmpA.z */
868 new_inst = tgsi_default_full_instruction();
869 new_inst.Instruction.Opcode = TGSI_OPCODE_RCP;
870 new_inst.Instruction.NumDstRegs = 1;
871 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_Z);
872 new_inst.Instruction.NumSrcRegs = 1;
873 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(Z, _, _, _));
874 tctx->emit_instruction(tctx, &new_inst);
875
876 /* MUL dst.y, |src.x|, tmpA.z */
877 new_inst = tgsi_default_full_instruction();
878 new_inst.Instruction.Opcode = TGSI_OPCODE_MUL;
879 new_inst.Instruction.NumDstRegs = 1;
880 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_Y);
881 new_inst.Instruction.NumSrcRegs = 2;
882 reg_src(&new_inst.Src[0], src, SWIZ(_, X, _, _));
883 new_inst.Src[0].Register.Absolute = true;
884 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(_, Z, _, _));
885 tctx->emit_instruction(tctx, &new_inst);
886 }
887
888 if (dst->Register.WriteMask & TGSI_WRITEMASK_XZ) {
889 /* MOV dst.xz, tmpA.yx */
890 new_inst = tgsi_default_full_instruction();
891 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
892 new_inst.Instruction.NumDstRegs = 1;
893 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XZ);
894 new_inst.Instruction.NumSrcRegs = 1;
895 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(Y, _, X, _));
896 tctx->emit_instruction(tctx, &new_inst);
897 }
898
899 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) {
900 /* MOV dst.w, imm{1.0} */
901 new_inst = tgsi_default_full_instruction();
902 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
903 new_inst.Instruction.NumDstRegs = 1;
904 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_W);
905 new_inst.Instruction.NumSrcRegs = 1;
906 reg_src(&new_inst.Src[0], &ctx->imm, SWIZ(_, _, _, Y));
907 tctx->emit_instruction(tctx, &new_inst);
908 }
909 }
910
911 /* DP4 - 4-component Dot Product
912 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z + src0.w \times src1.w
913 *
914 * DP3 - 3-component Dot Product
915 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z
916 *
917 * DPH - Homogeneous Dot Product
918 * dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z + src1.w
919 *
920 * DP2 - 2-component Dot Product
921 * dst = src0.x \times src1.x + src0.y \times src1.y
922 *
923 * NOTE: these are translated into sequence of MUL/MAD(/ADD) scalar
924 * operations, which is what you'd prefer for a ISA that is natively
925 * scalar. Probably a native vector ISA would at least already have
926 * DP4/DP3 instructions, but perhaps there is room for an alternative
927 * translation for DPH/DP2 using vector instructions.
928 *
929 * ; needs: 1 tmp
930 * MUL tmpA.x, src0.x, src1.x
931 * MAD tmpA.x, src0.y, src1.y, tmpA.x
932 * if (DPH || DP3 || DP4) {
933 * MAD tmpA.x, src0.z, src1.z, tmpA.x
934 * if (DPH) {
935 * ADD tmpA.x, src1.w, tmpA.x
936 * } else if (DP4) {
937 * MAD tmpA.x, src0.w, src1.w, tmpA.x
938 * }
939 * }
940 * ; fixup last instruction to replicate into dst
941 */
942 #define DP4_GROW (NINST(2) + NINST(3) + NINST(3) + NINST(3) - OINST(2))
943 #define DP3_GROW (NINST(2) + NINST(3) + NINST(3) - OINST(2))
944 #define DPH_GROW (NINST(2) + NINST(3) + NINST(3) + NINST(2) - OINST(2))
945 #define DP2_GROW (NINST(2) + NINST(3) - OINST(2))
946 #define DOTP_TMP 1
947 static void
948 transform_dotp(struct tgsi_transform_context *tctx,
949 struct tgsi_full_instruction *inst)
950 {
951 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
952 struct tgsi_full_dst_register *dst = &inst->Dst[0];
953 struct tgsi_full_src_register *src0 = &inst->Src[0];
954 struct tgsi_full_src_register *src1 = &inst->Src[1];
955 struct tgsi_full_instruction new_inst;
956 unsigned opcode = inst->Instruction.Opcode;
957
958 /* NOTE: any potential last instruction must replicate src on all
959 * components (since it could be re-written to write to final dst)
960 */
961
962 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
963 /* MUL tmpA.x, src0.x, src1.x */
964 new_inst = tgsi_default_full_instruction();
965 new_inst.Instruction.Opcode = TGSI_OPCODE_MUL;
966 new_inst.Instruction.NumDstRegs = 1;
967 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
968 new_inst.Instruction.NumSrcRegs = 2;
969 reg_src(&new_inst.Src[0], src0, SWIZ(X, _, _, _));
970 reg_src(&new_inst.Src[1], src1, SWIZ(X, _, _, _));
971 tctx->emit_instruction(tctx, &new_inst);
972
973 /* MAD tmpA.x, src0.y, src1.y, tmpA.x */
974 new_inst = tgsi_default_full_instruction();
975 new_inst.Instruction.Opcode = TGSI_OPCODE_MAD;
976 new_inst.Instruction.NumDstRegs = 1;
977 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
978 new_inst.Instruction.NumSrcRegs = 3;
979 reg_src(&new_inst.Src[0], src0, SWIZ(Y, Y, Y, Y));
980 reg_src(&new_inst.Src[1], src1, SWIZ(Y, Y, Y, Y));
981 reg_src(&new_inst.Src[2], &ctx->tmp[A].src, SWIZ(X, X, X, X));
982
983 if ((opcode == TGSI_OPCODE_DPH) ||
984 (opcode == TGSI_OPCODE_DP3) ||
985 (opcode == TGSI_OPCODE_DP4)) {
986 tctx->emit_instruction(tctx, &new_inst);
987
988 /* MAD tmpA.x, src0.z, src1.z, tmpA.x */
989 new_inst = tgsi_default_full_instruction();
990 new_inst.Instruction.Opcode = TGSI_OPCODE_MAD;
991 new_inst.Instruction.NumDstRegs = 1;
992 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
993 new_inst.Instruction.NumSrcRegs = 3;
994 reg_src(&new_inst.Src[0], src0, SWIZ(Z, Z, Z, Z));
995 reg_src(&new_inst.Src[1], src1, SWIZ(Z, Z, Z, Z));
996 reg_src(&new_inst.Src[2], &ctx->tmp[A].src, SWIZ(X, X, X, X));
997
998 if (opcode == TGSI_OPCODE_DPH) {
999 tctx->emit_instruction(tctx, &new_inst);
1000
1001 /* ADD tmpA.x, src1.w, tmpA.x */
1002 new_inst = tgsi_default_full_instruction();
1003 new_inst.Instruction.Opcode = TGSI_OPCODE_ADD;
1004 new_inst.Instruction.NumDstRegs = 1;
1005 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
1006 new_inst.Instruction.NumSrcRegs = 2;
1007 reg_src(&new_inst.Src[0], src1, SWIZ(W, W, W, W));
1008 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(X, X, X, X));
1009 } else if (opcode == TGSI_OPCODE_DP4) {
1010 tctx->emit_instruction(tctx, &new_inst);
1011
1012 /* MAD tmpA.x, src0.w, src1.w, tmpA.x */
1013 new_inst = tgsi_default_full_instruction();
1014 new_inst.Instruction.Opcode = TGSI_OPCODE_MAD;
1015 new_inst.Instruction.NumDstRegs = 1;
1016 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
1017 new_inst.Instruction.NumSrcRegs = 3;
1018 reg_src(&new_inst.Src[0], src0, SWIZ(W, W, W, W));
1019 reg_src(&new_inst.Src[1], src1, SWIZ(W, W, W, W));
1020 reg_src(&new_inst.Src[2], &ctx->tmp[A].src, SWIZ(X, X, X, X));
1021 }
1022 }
1023
1024 /* fixup last instruction to write to dst: */
1025 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
1026
1027 tctx->emit_instruction(tctx, &new_inst);
1028 }
1029 }
1030
1031 /* FLR - floor, CEIL - ceil
1032 * ; needs: 1 tmp
1033 * if (CEIL) {
1034 * FRC tmpA, -src
1035 * ADD dst, src, tmpA
1036 * } else {
1037 * FRC tmpA, src
1038 * SUB dst, src, tmpA
1039 * }
1040 */
1041 #define FLR_GROW (NINST(1) + NINST(2) - OINST(1))
1042 #define CEIL_GROW (NINST(1) + NINST(2) - OINST(1))
1043 #define FLR_TMP 1
1044 #define CEIL_TMP 1
1045 static void
1046 transform_flr_ceil(struct tgsi_transform_context *tctx,
1047 struct tgsi_full_instruction *inst)
1048 {
1049 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
1050 struct tgsi_full_dst_register *dst = &inst->Dst[0];
1051 struct tgsi_full_src_register *src0 = &inst->Src[0];
1052 struct tgsi_full_instruction new_inst;
1053 unsigned opcode = inst->Instruction.Opcode;
1054
1055 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
1056 /* FLR: FRC tmpA, src CEIL: FRC tmpA, -src */
1057 new_inst = tgsi_default_full_instruction();
1058 new_inst.Instruction.Opcode = TGSI_OPCODE_FRC;
1059 new_inst.Instruction.NumDstRegs = 1;
1060 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW);
1061 new_inst.Instruction.NumSrcRegs = 1;
1062 reg_src(&new_inst.Src[0], src0, SWIZ(X, Y, Z, W));
1063
1064 if (opcode == TGSI_OPCODE_CEIL)
1065 new_inst.Src[0].Register.Negate = !new_inst.Src[0].Register.Negate;
1066 tctx->emit_instruction(tctx, &new_inst);
1067
1068 /* FLR: SUB dst, src, tmpA CEIL: ADD dst, src, tmpA */
1069 new_inst = tgsi_default_full_instruction();
1070 new_inst.Instruction.Opcode = TGSI_OPCODE_ADD;
1071 new_inst.Instruction.NumDstRegs = 1;
1072 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
1073 new_inst.Instruction.NumSrcRegs = 2;
1074 reg_src(&new_inst.Src[0], src0, SWIZ(X, Y, Z, W));
1075 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
1076 if (opcode == TGSI_OPCODE_FLR)
1077 new_inst.Src[1].Register.Negate = 1;
1078 tctx->emit_instruction(tctx, &new_inst);
1079 }
1080 }
1081
1082 /* TRUNC - truncate off fractional part
1083 * dst.x = trunc(src.x)
1084 * dst.y = trunc(src.y)
1085 * dst.z = trunc(src.z)
1086 * dst.w = trunc(src.w)
1087 *
1088 * ; needs: 1 tmp
1089 * if (lower FLR) {
1090 * FRC tmpA, |src|
1091 * SUB tmpA, |src|, tmpA
1092 * } else {
1093 * FLR tmpA, |src|
1094 * }
1095 * CMP dst, src, -tmpA, tmpA
1096 */
1097 #define TRUNC_GROW (NINST(1) + NINST(2) + NINST(3) - OINST(1))
1098 #define TRUNC_TMP 1
1099 static void
1100 transform_trunc(struct tgsi_transform_context *tctx,
1101 struct tgsi_full_instruction *inst)
1102 {
1103 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
1104 struct tgsi_full_dst_register *dst = &inst->Dst[0];
1105 struct tgsi_full_src_register *src0 = &inst->Src[0];
1106 struct tgsi_full_instruction new_inst;
1107
1108 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
1109 if (ctx->config->lower_FLR) {
1110 new_inst = tgsi_default_full_instruction();
1111 new_inst.Instruction.Opcode = TGSI_OPCODE_FRC;
1112 new_inst.Instruction.NumDstRegs = 1;
1113 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW);
1114 new_inst.Instruction.NumSrcRegs = 1;
1115 reg_src(&new_inst.Src[0], src0, SWIZ(X, Y, Z, W));
1116 new_inst.Src[0].Register.Absolute = true;
1117 new_inst.Src[0].Register.Negate = false;
1118 tctx->emit_instruction(tctx, &new_inst);
1119
1120 new_inst = tgsi_default_full_instruction();
1121 new_inst.Instruction.Opcode = TGSI_OPCODE_ADD;
1122 new_inst.Instruction.NumDstRegs = 1;
1123 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW);
1124 new_inst.Instruction.NumSrcRegs = 2;
1125 reg_src(&new_inst.Src[0], src0, SWIZ(X, Y, Z, W));
1126 new_inst.Src[0].Register.Absolute = true;
1127 new_inst.Src[0].Register.Negate = false;
1128 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
1129 new_inst.Src[1].Register.Negate = 1;
1130 tctx->emit_instruction(tctx, &new_inst);
1131 } else {
1132 new_inst = tgsi_default_full_instruction();
1133 new_inst.Instruction.Opcode = TGSI_OPCODE_FLR;
1134 new_inst.Instruction.NumDstRegs = 1;
1135 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW);
1136 new_inst.Instruction.NumSrcRegs = 1;
1137 reg_src(&new_inst.Src[0], src0, SWIZ(X, Y, Z, W));
1138 new_inst.Src[0].Register.Absolute = true;
1139 new_inst.Src[0].Register.Negate = false;
1140 tctx->emit_instruction(tctx, &new_inst);
1141 }
1142
1143 new_inst = tgsi_default_full_instruction();
1144 new_inst.Instruction.Opcode = TGSI_OPCODE_CMP;
1145 new_inst.Instruction.NumDstRegs = 1;
1146 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
1147 new_inst.Instruction.NumSrcRegs = 3;
1148 reg_src(&new_inst.Src[0], src0, SWIZ(X, Y, Z, W));
1149 reg_src(&new_inst.Src[1], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
1150 new_inst.Src[1].Register.Negate = true;
1151 reg_src(&new_inst.Src[2], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
1152 tctx->emit_instruction(tctx, &new_inst);
1153 }
1154 }
1155
1156 /* Inserts a MOV_SAT for the needed components of tex coord. Note that
1157 * in the case of TXP, the clamping must happen *after* projection, so
1158 * we need to lower TXP to TEX.
1159 *
1160 * MOV tmpA, src0
1161 * if (opc == TXP) {
1162 * ; do perspective division manually before clamping:
1163 * RCP tmpB, tmpA.w
1164 * MUL tmpB.<pmask>, tmpA, tmpB.xxxx
1165 * opc = TEX;
1166 * }
1167 * MOV_SAT tmpA.<mask>, tmpA ; <mask> is the clamped s/t/r coords
1168 * <opc> dst, tmpA, ...
1169 */
1170 #define SAMP_GROW (NINST(1) + NINST(1) + NINST(2) + NINST(1))
1171 #define SAMP_TMP 2
1172 static int
1173 transform_samp(struct tgsi_transform_context *tctx,
1174 struct tgsi_full_instruction *inst)
1175 {
1176 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
1177 struct tgsi_full_src_register *coord = &inst->Src[0];
1178 struct tgsi_full_src_register *samp;
1179 struct tgsi_full_instruction new_inst;
1180 /* mask is clamped coords, pmask is all coords (for projection): */
1181 unsigned mask = 0, pmask = 0, smask;
1182 unsigned tex = inst->Texture.Texture;
1183 unsigned opcode = inst->Instruction.Opcode;
1184 bool lower_txp = (opcode == TGSI_OPCODE_TXP) &&
1185 (ctx->config->lower_TXP & (1 << tex));
1186
1187 if (opcode == TGSI_OPCODE_TXB2) {
1188 samp = &inst->Src[2];
1189 } else {
1190 samp = &inst->Src[1];
1191 }
1192
1193 /* convert sampler # to bitmask to test: */
1194 smask = 1 << samp->Register.Index;
1195
1196 /* check if we actually need to lower this one: */
1197 if (!(ctx->saturate & smask) && !lower_txp)
1198 return -1;
1199
1200 /* figure out which coordinates need saturating:
1201 * - RECT textures should not get saturated
1202 * - array index coords should not get saturated
1203 */
1204 switch (tex) {
1205 case TGSI_TEXTURE_3D:
1206 case TGSI_TEXTURE_CUBE:
1207 case TGSI_TEXTURE_CUBE_ARRAY:
1208 case TGSI_TEXTURE_SHADOWCUBE:
1209 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1210 if (ctx->config->saturate_r & smask)
1211 mask |= TGSI_WRITEMASK_Z;
1212 pmask |= TGSI_WRITEMASK_Z;
1213 /* fallthrough */
1214
1215 case TGSI_TEXTURE_2D:
1216 case TGSI_TEXTURE_2D_ARRAY:
1217 case TGSI_TEXTURE_SHADOW2D:
1218 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1219 case TGSI_TEXTURE_2D_MSAA:
1220 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1221 if (ctx->config->saturate_t & smask)
1222 mask |= TGSI_WRITEMASK_Y;
1223 pmask |= TGSI_WRITEMASK_Y;
1224 /* fallthrough */
1225
1226 case TGSI_TEXTURE_1D:
1227 case TGSI_TEXTURE_1D_ARRAY:
1228 case TGSI_TEXTURE_SHADOW1D:
1229 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1230 if (ctx->config->saturate_s & smask)
1231 mask |= TGSI_WRITEMASK_X;
1232 pmask |= TGSI_WRITEMASK_X;
1233 break;
1234
1235 case TGSI_TEXTURE_RECT:
1236 case TGSI_TEXTURE_SHADOWRECT:
1237 /* we don't saturate, but in case of lower_txp we
1238 * still need to do the perspective divide:
1239 */
1240 pmask = TGSI_WRITEMASK_XY;
1241 break;
1242 }
1243
1244 /* sanity check.. driver could be asking to saturate a non-
1245 * existent coordinate component:
1246 */
1247 if (!mask && !lower_txp)
1248 return -1;
1249
1250 /* MOV tmpA, src0 */
1251 create_mov(tctx, &ctx->tmp[A].dst, coord, TGSI_WRITEMASK_XYZW, 0);
1252
1253 /* This is a bit sad.. we need to clamp *after* the coords
1254 * are projected, which means lowering TXP to TEX and doing
1255 * the projection ourself. But since I haven't figured out
1256 * how to make the lowering code deliver an electric shock
1257 * to anyone using GL_CLAMP, we must do this instead:
1258 */
1259 if (opcode == TGSI_OPCODE_TXP) {
1260 /* RCP tmpB.x tmpA.w */
1261 new_inst = tgsi_default_full_instruction();
1262 new_inst.Instruction.Opcode = TGSI_OPCODE_RCP;
1263 new_inst.Instruction.NumDstRegs = 1;
1264 reg_dst(&new_inst.Dst[0], &ctx->tmp[B].dst, TGSI_WRITEMASK_X);
1265 new_inst.Instruction.NumSrcRegs = 1;
1266 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(W, _, _, _));
1267 tctx->emit_instruction(tctx, &new_inst);
1268
1269 /* MUL tmpA.mask, tmpA, tmpB.xxxx */
1270 new_inst = tgsi_default_full_instruction();
1271 new_inst.Instruction.Opcode = TGSI_OPCODE_MUL;
1272 new_inst.Instruction.NumDstRegs = 1;
1273 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, pmask);
1274 new_inst.Instruction.NumSrcRegs = 2;
1275 reg_src(&new_inst.Src[0], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
1276 reg_src(&new_inst.Src[1], &ctx->tmp[B].src, SWIZ(X, X, X, X));
1277 tctx->emit_instruction(tctx, &new_inst);
1278
1279 opcode = TGSI_OPCODE_TEX;
1280 }
1281
1282 /* MOV_SAT tmpA.<mask>, tmpA */
1283 if (mask) {
1284 create_mov(tctx, &ctx->tmp[A].dst, &ctx->tmp[A].src, mask, 1);
1285 }
1286
1287 /* modify the texture samp instruction to take fixed up coord: */
1288 new_inst = *inst;
1289 new_inst.Instruction.Opcode = opcode;
1290 new_inst.Src[0] = ctx->tmp[A].src;
1291 tctx->emit_instruction(tctx, &new_inst);
1292
1293 return 0;
1294 }
1295
1296 /* Two-sided color emulation:
1297 * For each COLOR input, create a corresponding BCOLOR input, plus
1298 * CMP instruction to select front or back color based on FACE
1299 */
1300 #define TWOSIDE_GROW(n) ( \
1301 2 + /* FACE */ \
1302 ((n) * 3) + /* IN[], BCOLOR[n], <intrp> */\
1303 ((n) * 1) + /* TEMP[] */ \
1304 ((n) * NINST(3)) /* CMP instr */ \
1305 )
1306
1307 static void
1308 emit_twoside(struct tgsi_transform_context *tctx)
1309 {
1310 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
1311 struct tgsi_shader_info *info = ctx->info;
1312 struct tgsi_full_declaration decl;
1313 struct tgsi_full_instruction new_inst;
1314 unsigned inbase, tmpbase;
1315 int i;
1316
1317 inbase = info->file_max[TGSI_FILE_INPUT] + 1;
1318 tmpbase = info->file_max[TGSI_FILE_TEMPORARY] + 1;
1319
1320 /* additional inputs for BCOLOR's */
1321 for (i = 0; i < ctx->two_side_colors; i++) {
1322 unsigned in_idx = ctx->two_side_idx[i];
1323 decl = tgsi_default_full_declaration();
1324 decl.Declaration.File = TGSI_FILE_INPUT;
1325 decl.Declaration.Semantic = true;
1326 decl.Range.First = decl.Range.Last = inbase + i;
1327 decl.Semantic.Name = TGSI_SEMANTIC_BCOLOR;
1328 decl.Semantic.Index = info->input_semantic_index[in_idx];
1329 decl.Declaration.Interpolate = true;
1330 decl.Interp.Interpolate = info->input_interpolate[in_idx];
1331 decl.Interp.Location = info->input_interpolate_loc[in_idx];
1332 decl.Interp.CylindricalWrap = info->input_cylindrical_wrap[in_idx];
1333 tctx->emit_declaration(tctx, &decl);
1334 }
1335
1336 /* additional input for FACE */
1337 if (ctx->two_side_colors && (ctx->face_idx == -1)) {
1338 decl = tgsi_default_full_declaration();
1339 decl.Declaration.File = TGSI_FILE_INPUT;
1340 decl.Declaration.Semantic = true;
1341 decl.Range.First = decl.Range.Last = inbase + ctx->two_side_colors;
1342 decl.Semantic.Name = TGSI_SEMANTIC_FACE;
1343 decl.Semantic.Index = 0;
1344 tctx->emit_declaration(tctx, &decl);
1345
1346 ctx->face_idx = decl.Range.First;
1347 }
1348
1349 /* additional temps for COLOR/BCOLOR selection: */
1350 for (i = 0; i < ctx->two_side_colors; i++) {
1351 decl = tgsi_default_full_declaration();
1352 decl.Declaration.File = TGSI_FILE_TEMPORARY;
1353 decl.Range.First = decl.Range.Last = tmpbase + ctx->numtmp + i;
1354 tctx->emit_declaration(tctx, &decl);
1355 }
1356
1357 /* and finally additional instructions to select COLOR/BCOLOR: */
1358 for (i = 0; i < ctx->two_side_colors; i++) {
1359 new_inst = tgsi_default_full_instruction();
1360 new_inst.Instruction.Opcode = TGSI_OPCODE_CMP;
1361
1362 new_inst.Instruction.NumDstRegs = 1;
1363 new_inst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
1364 new_inst.Dst[0].Register.Index = tmpbase + ctx->numtmp + i;
1365 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
1366
1367 new_inst.Instruction.NumSrcRegs = 3;
1368 new_inst.Src[0].Register.File = TGSI_FILE_INPUT;
1369 new_inst.Src[0].Register.Index = ctx->face_idx;
1370 new_inst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_X;
1371 new_inst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_X;
1372 new_inst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_X;
1373 new_inst.Src[0].Register.SwizzleW = TGSI_SWIZZLE_X;
1374 new_inst.Src[1].Register.File = TGSI_FILE_INPUT;
1375 new_inst.Src[1].Register.Index = inbase + i;
1376 new_inst.Src[1].Register.SwizzleX = TGSI_SWIZZLE_X;
1377 new_inst.Src[1].Register.SwizzleY = TGSI_SWIZZLE_Y;
1378 new_inst.Src[1].Register.SwizzleZ = TGSI_SWIZZLE_Z;
1379 new_inst.Src[1].Register.SwizzleW = TGSI_SWIZZLE_W;
1380 new_inst.Src[2].Register.File = TGSI_FILE_INPUT;
1381 new_inst.Src[2].Register.Index = ctx->two_side_idx[i];
1382 new_inst.Src[2].Register.SwizzleX = TGSI_SWIZZLE_X;
1383 new_inst.Src[2].Register.SwizzleY = TGSI_SWIZZLE_Y;
1384 new_inst.Src[2].Register.SwizzleZ = TGSI_SWIZZLE_Z;
1385 new_inst.Src[2].Register.SwizzleW = TGSI_SWIZZLE_W;
1386
1387 tctx->emit_instruction(tctx, &new_inst);
1388 }
1389 }
1390
1391 static void
1392 emit_decls(struct tgsi_transform_context *tctx)
1393 {
1394 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
1395 struct tgsi_shader_info *info = ctx->info;
1396 struct tgsi_full_declaration decl;
1397 struct tgsi_full_immediate immed;
1398 unsigned tmpbase;
1399 int i;
1400
1401 tmpbase = info->file_max[TGSI_FILE_TEMPORARY] + 1;
1402
1403 ctx->color_base = tmpbase + ctx->numtmp;
1404
1405 /* declare immediate: */
1406 immed = tgsi_default_full_immediate();
1407 immed.Immediate.NrTokens = 1 + 4; /* one for the token itself */
1408 immed.u[0].Float = 0.0;
1409 immed.u[1].Float = 1.0;
1410 immed.u[2].Float = 128.0;
1411 immed.u[3].Float = 0.0;
1412 tctx->emit_immediate(tctx, &immed);
1413
1414 ctx->imm.Register.File = TGSI_FILE_IMMEDIATE;
1415 ctx->imm.Register.Index = info->immediate_count;
1416 ctx->imm.Register.SwizzleX = TGSI_SWIZZLE_X;
1417 ctx->imm.Register.SwizzleY = TGSI_SWIZZLE_Y;
1418 ctx->imm.Register.SwizzleZ = TGSI_SWIZZLE_Z;
1419 ctx->imm.Register.SwizzleW = TGSI_SWIZZLE_W;
1420
1421 /* declare temp regs: */
1422 for (i = 0; i < ctx->numtmp; i++) {
1423 decl = tgsi_default_full_declaration();
1424 decl.Declaration.File = TGSI_FILE_TEMPORARY;
1425 decl.Range.First = decl.Range.Last = tmpbase + i;
1426 tctx->emit_declaration(tctx, &decl);
1427
1428 ctx->tmp[i].src.Register.File = TGSI_FILE_TEMPORARY;
1429 ctx->tmp[i].src.Register.Index = tmpbase + i;
1430 ctx->tmp[i].src.Register.SwizzleX = TGSI_SWIZZLE_X;
1431 ctx->tmp[i].src.Register.SwizzleY = TGSI_SWIZZLE_Y;
1432 ctx->tmp[i].src.Register.SwizzleZ = TGSI_SWIZZLE_Z;
1433 ctx->tmp[i].src.Register.SwizzleW = TGSI_SWIZZLE_W;
1434
1435 ctx->tmp[i].dst.Register.File = TGSI_FILE_TEMPORARY;
1436 ctx->tmp[i].dst.Register.Index = tmpbase + i;
1437 ctx->tmp[i].dst.Register.WriteMask = TGSI_WRITEMASK_XYZW;
1438 }
1439
1440 if (ctx->two_side_colors)
1441 emit_twoside(tctx);
1442 }
1443
1444 static void
1445 rename_color_inputs(struct tgsi_lowering_context *ctx,
1446 struct tgsi_full_instruction *inst)
1447 {
1448 unsigned i, j;
1449 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1450 struct tgsi_src_register *src = &inst->Src[i].Register;
1451 if (src->File == TGSI_FILE_INPUT) {
1452 for (j = 0; j < ctx->two_side_colors; j++) {
1453 if (src->Index == ctx->two_side_idx[j]) {
1454 src->File = TGSI_FILE_TEMPORARY;
1455 src->Index = ctx->color_base + j;
1456 break;
1457 }
1458 }
1459 }
1460 }
1461
1462 }
1463
1464 static void
1465 transform_instr(struct tgsi_transform_context *tctx,
1466 struct tgsi_full_instruction *inst)
1467 {
1468 struct tgsi_lowering_context *ctx = tgsi_lowering_context(tctx);
1469
1470 if (!ctx->emitted_decls) {
1471 emit_decls(tctx);
1472 ctx->emitted_decls = 1;
1473 }
1474
1475 /* if emulating two-sided-color, we need to re-write some
1476 * src registers:
1477 */
1478 if (ctx->two_side_colors)
1479 rename_color_inputs(ctx, inst);
1480
1481 switch (inst->Instruction.Opcode) {
1482 case TGSI_OPCODE_DST:
1483 if (!ctx->config->lower_DST)
1484 goto skip;
1485 transform_dst(tctx, inst);
1486 break;
1487 case TGSI_OPCODE_XPD:
1488 if (!ctx->config->lower_XPD)
1489 goto skip;
1490 transform_xpd(tctx, inst);
1491 break;
1492 case TGSI_OPCODE_SCS:
1493 if (!ctx->config->lower_SCS)
1494 goto skip;
1495 transform_scs(tctx, inst);
1496 break;
1497 case TGSI_OPCODE_LRP:
1498 if (!ctx->config->lower_LRP)
1499 goto skip;
1500 transform_lrp(tctx, inst);
1501 break;
1502 case TGSI_OPCODE_FRC:
1503 if (!ctx->config->lower_FRC)
1504 goto skip;
1505 transform_frc(tctx, inst);
1506 break;
1507 case TGSI_OPCODE_POW:
1508 if (!ctx->config->lower_POW)
1509 goto skip;
1510 transform_pow(tctx, inst);
1511 break;
1512 case TGSI_OPCODE_LIT:
1513 if (!ctx->config->lower_LIT)
1514 goto skip;
1515 transform_lit(tctx, inst);
1516 break;
1517 case TGSI_OPCODE_EXP:
1518 if (!ctx->config->lower_EXP)
1519 goto skip;
1520 transform_exp(tctx, inst);
1521 break;
1522 case TGSI_OPCODE_LOG:
1523 if (!ctx->config->lower_LOG)
1524 goto skip;
1525 transform_log(tctx, inst);
1526 break;
1527 case TGSI_OPCODE_DP4:
1528 if (!ctx->config->lower_DP4)
1529 goto skip;
1530 transform_dotp(tctx, inst);
1531 break;
1532 case TGSI_OPCODE_DP3:
1533 if (!ctx->config->lower_DP3)
1534 goto skip;
1535 transform_dotp(tctx, inst);
1536 break;
1537 case TGSI_OPCODE_DPH:
1538 if (!ctx->config->lower_DPH)
1539 goto skip;
1540 transform_dotp(tctx, inst);
1541 break;
1542 case TGSI_OPCODE_DP2:
1543 if (!ctx->config->lower_DP2)
1544 goto skip;
1545 transform_dotp(tctx, inst);
1546 break;
1547 case TGSI_OPCODE_FLR:
1548 if (!ctx->config->lower_FLR)
1549 goto skip;
1550 transform_flr_ceil(tctx, inst);
1551 break;
1552 case TGSI_OPCODE_CEIL:
1553 if (!ctx->config->lower_CEIL)
1554 goto skip;
1555 transform_flr_ceil(tctx, inst);
1556 break;
1557 case TGSI_OPCODE_TRUNC:
1558 if (!ctx->config->lower_TRUNC)
1559 goto skip;
1560 transform_trunc(tctx, inst);
1561 break;
1562 case TGSI_OPCODE_TEX:
1563 case TGSI_OPCODE_TXP:
1564 case TGSI_OPCODE_TXB:
1565 case TGSI_OPCODE_TXB2:
1566 case TGSI_OPCODE_TXL:
1567 if (transform_samp(tctx, inst))
1568 goto skip;
1569 break;
1570 default:
1571 skip:
1572 tctx->emit_instruction(tctx, inst);
1573 break;
1574 }
1575 }
1576
1577 /* returns NULL if no lowering required, else returns the new
1578 * tokens (which caller is required to free()). In either case
1579 * returns the current info.
1580 */
1581 const struct tgsi_token *
1582 tgsi_transform_lowering(const struct tgsi_lowering_config *config,
1583 const struct tgsi_token *tokens,
1584 struct tgsi_shader_info *info)
1585 {
1586 struct tgsi_lowering_context ctx;
1587 struct tgsi_token *newtoks;
1588 int newlen, numtmp;
1589
1590 /* sanity check in case limit is ever increased: */
1591 STATIC_ASSERT((sizeof(config->saturate_s) * 8) >= PIPE_MAX_SAMPLERS);
1592
1593 /* sanity check the lowering */
1594 assert(!(config->lower_FRC && (config->lower_FLR || config->lower_CEIL)));
1595 assert(!(config->lower_FRC && config->lower_TRUNC));
1596
1597 memset(&ctx, 0, sizeof(ctx));
1598 ctx.base.transform_instruction = transform_instr;
1599 ctx.info = info;
1600 ctx.config = config;
1601
1602 tgsi_scan_shader(tokens, info);
1603
1604 /* if we are adding fragment shader support to emulate two-sided
1605 * color, then figure out the number of additional inputs we need
1606 * to create for BCOLOR's..
1607 */
1608 if ((info->processor == PIPE_SHADER_FRAGMENT) &&
1609 config->color_two_side) {
1610 int i;
1611 ctx.face_idx = -1;
1612 for (i = 0; i <= info->file_max[TGSI_FILE_INPUT]; i++) {
1613 if (info->input_semantic_name[i] == TGSI_SEMANTIC_COLOR)
1614 ctx.two_side_idx[ctx.two_side_colors++] = i;
1615 if (info->input_semantic_name[i] == TGSI_SEMANTIC_FACE)
1616 ctx.face_idx = i;
1617 }
1618 }
1619
1620 ctx.saturate = config->saturate_r | config->saturate_s | config->saturate_t;
1621
1622 #define OPCS(x) ((config->lower_ ## x) ? info->opcode_count[TGSI_OPCODE_ ## x] : 0)
1623 /* if there are no instructions to lower, then we are done: */
1624 if (!(OPCS(DST) ||
1625 OPCS(XPD) ||
1626 OPCS(SCS) ||
1627 OPCS(LRP) ||
1628 OPCS(FRC) ||
1629 OPCS(POW) ||
1630 OPCS(LIT) ||
1631 OPCS(EXP) ||
1632 OPCS(LOG) ||
1633 OPCS(DP4) ||
1634 OPCS(DP3) ||
1635 OPCS(DPH) ||
1636 OPCS(DP2) ||
1637 OPCS(FLR) ||
1638 OPCS(CEIL) ||
1639 OPCS(TRUNC) ||
1640 OPCS(TXP) ||
1641 ctx.two_side_colors ||
1642 ctx.saturate))
1643 return NULL;
1644
1645 #if 0 /* debug */
1646 _debug_printf("BEFORE:");
1647 tgsi_dump(tokens, 0);
1648 #endif
1649
1650 numtmp = 0;
1651 newlen = tgsi_num_tokens(tokens);
1652 if (OPCS(DST)) {
1653 newlen += DST_GROW * OPCS(DST);
1654 numtmp = MAX2(numtmp, DST_TMP);
1655 }
1656 if (OPCS(XPD)) {
1657 newlen += XPD_GROW * OPCS(XPD);
1658 numtmp = MAX2(numtmp, XPD_TMP);
1659 }
1660 if (OPCS(SCS)) {
1661 newlen += SCS_GROW * OPCS(SCS);
1662 numtmp = MAX2(numtmp, SCS_TMP);
1663 }
1664 if (OPCS(LRP)) {
1665 newlen += LRP_GROW * OPCS(LRP);
1666 numtmp = MAX2(numtmp, LRP_TMP);
1667 }
1668 if (OPCS(FRC)) {
1669 newlen += FRC_GROW * OPCS(FRC);
1670 numtmp = MAX2(numtmp, FRC_TMP);
1671 }
1672 if (OPCS(POW)) {
1673 newlen += POW_GROW * OPCS(POW);
1674 numtmp = MAX2(numtmp, POW_TMP);
1675 }
1676 if (OPCS(LIT)) {
1677 newlen += LIT_GROW * OPCS(LIT);
1678 numtmp = MAX2(numtmp, LIT_TMP);
1679 }
1680 if (OPCS(EXP)) {
1681 newlen += EXP_GROW * OPCS(EXP);
1682 numtmp = MAX2(numtmp, EXP_TMP);
1683 }
1684 if (OPCS(LOG)) {
1685 newlen += LOG_GROW * OPCS(LOG);
1686 numtmp = MAX2(numtmp, LOG_TMP);
1687 }
1688 if (OPCS(DP4)) {
1689 newlen += DP4_GROW * OPCS(DP4);
1690 numtmp = MAX2(numtmp, DOTP_TMP);
1691 }
1692 if (OPCS(DP3)) {
1693 newlen += DP3_GROW * OPCS(DP3);
1694 numtmp = MAX2(numtmp, DOTP_TMP);
1695 }
1696 if (OPCS(DPH)) {
1697 newlen += DPH_GROW * OPCS(DPH);
1698 numtmp = MAX2(numtmp, DOTP_TMP);
1699 }
1700 if (OPCS(DP2)) {
1701 newlen += DP2_GROW * OPCS(DP2);
1702 numtmp = MAX2(numtmp, DOTP_TMP);
1703 }
1704 if (OPCS(FLR)) {
1705 newlen += FLR_GROW * OPCS(FLR);
1706 numtmp = MAX2(numtmp, FLR_TMP);
1707 }
1708 if (OPCS(CEIL)) {
1709 newlen += CEIL_GROW * OPCS(CEIL);
1710 numtmp = MAX2(numtmp, CEIL_TMP);
1711 }
1712 if (OPCS(TRUNC)) {
1713 newlen += TRUNC_GROW * OPCS(TRUNC);
1714 numtmp = MAX2(numtmp, TRUNC_TMP);
1715 }
1716 if (ctx.saturate || config->lower_TXP) {
1717 int n = 0;
1718
1719 if (ctx.saturate) {
1720 n = info->opcode_count[TGSI_OPCODE_TEX] +
1721 info->opcode_count[TGSI_OPCODE_TXP] +
1722 info->opcode_count[TGSI_OPCODE_TXB] +
1723 info->opcode_count[TGSI_OPCODE_TXB2] +
1724 info->opcode_count[TGSI_OPCODE_TXL];
1725 } else if (config->lower_TXP) {
1726 n = info->opcode_count[TGSI_OPCODE_TXP];
1727 }
1728
1729 newlen += SAMP_GROW * n;
1730 numtmp = MAX2(numtmp, SAMP_TMP);
1731 }
1732
1733 /* specifically don't include two_side_colors temps in the count: */
1734 ctx.numtmp = numtmp;
1735
1736 if (ctx.two_side_colors) {
1737 newlen += TWOSIDE_GROW(ctx.two_side_colors);
1738 /* note: we permanently consume temp regs, re-writing references
1739 * to IN.COLOR[n] to TEMP[m] (holding the output of of the CMP
1740 * instruction that selects which varying to use):
1741 */
1742 numtmp += ctx.two_side_colors;
1743 }
1744
1745 newlen += 2 * numtmp;
1746 newlen += 5; /* immediate */
1747
1748 newtoks = tgsi_alloc_tokens(newlen);
1749 if (!newtoks)
1750 return NULL;
1751
1752 tgsi_transform_shader(tokens, newtoks, newlen, &ctx.base);
1753
1754 tgsi_scan_shader(newtoks, info);
1755
1756 #if 0 /* debug */
1757 _debug_printf("AFTER:");
1758 tgsi_dump(newtoks, 0);
1759 #endif
1760
1761 return newtoks;
1762 }