1 /**************************************************************************
3 * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 * TGSI to PowerPC code generation.
32 #include "pipe/p_config.h"
34 #if defined(PIPE_ARCH_PPC)
36 #include "util/u_debug.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "util/u_math.h"
39 #include "util/u_memory.h"
40 #include "util/u_sse.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_util.h"
43 #include "tgsi_dump.h"
44 #include "tgsi_exec.h"
46 #include "rtasm/rtasm_ppc.h"
50 * Since it's pretty much impossible to form PPC vector immediates, load
51 * them from memory here:
53 const float ppc_builtin_constants
[] ALIGN16_ATTRIB
= {
54 1.0f
, -128.0f
, 128.0, 0.0
58 #define FOR_EACH_CHANNEL( CHAN )\
59 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
61 #define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
62 ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
64 #define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
65 if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
67 #define FOR_EACH_DST0_ENABLED_CHANNEL( INST, CHAN )\
68 FOR_EACH_CHANNEL( CHAN )\
69 IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )
78 * How many TGSI temps should be implemented with real PPC vector registers
81 #define MAX_PPC_TEMPS 3
85 * Context/state used during code gen.
89 struct ppc_function
*f
;
90 int inputs_reg
; /**< GP register pointing to input params */
91 int outputs_reg
; /**< GP register pointing to output params */
92 int temps_reg
; /**< GP register pointing to temporary "registers" */
93 int immed_reg
; /**< GP register pointing to immediates buffer */
94 int const_reg
; /**< GP register pointing to constants buffer */
95 int builtins_reg
; /**< GP register pointint to built-in constants */
97 int offset_reg
; /**< used to reduce redundant li instructions */
100 int one_vec
; /**< vector register with {1.0, 1.0, 1.0, 1.0} */
101 int bit31_vec
; /**< vector register with {1<<31, 1<<31, 1<<31, 1<<31} */
104 * Map TGSI temps to PPC vector temps.
105 * We have 32 PPC vector regs. Use 16 of them for storing 4 TGSI temps.
106 * XXX currently only do this for TGSI temps [0..MAX_PPC_TEMPS-1].
108 int temps_map
[MAX_PPC_TEMPS
][4];
111 * Cache of src registers.
112 * This is used to avoid redundant load instructions.
115 struct tgsi_full_src_register src
;
118 } regs
[12]; /* 3 src regs, 4 channels */
124 * Initialize code generation context.
127 init_gen_context(struct gen_context
*gen
, struct ppc_function
*func
)
131 memset(gen
, 0, sizeof(*gen
));
133 gen
->inputs_reg
= ppc_reserve_register(func
, 3); /* first function param */
134 gen
->outputs_reg
= ppc_reserve_register(func
, 4); /* second function param */
135 gen
->temps_reg
= ppc_reserve_register(func
, 5); /* ... */
136 gen
->immed_reg
= ppc_reserve_register(func
, 6);
137 gen
->const_reg
= ppc_reserve_register(func
, 7);
138 gen
->builtins_reg
= ppc_reserve_register(func
, 8);
141 gen
->offset_reg
= -1;
142 gen
->offset_value
= -9999999;
143 for (i
= 0; i
< MAX_PPC_TEMPS
; i
++) {
144 gen
->temps_map
[i
][0] = ppc_allocate_vec_register(gen
->f
);
145 gen
->temps_map
[i
][1] = ppc_allocate_vec_register(gen
->f
);
146 gen
->temps_map
[i
][2] = ppc_allocate_vec_register(gen
->f
);
147 gen
->temps_map
[i
][3] = ppc_allocate_vec_register(gen
->f
);
153 * Is the given TGSI register stored as a real PPC vector register?
156 is_ppc_vec_temporary(const struct tgsi_full_src_register
*reg
)
158 return (reg
->SrcRegister
.File
== TGSI_FILE_TEMPORARY
&&
159 reg
->SrcRegister
.Index
< MAX_PPC_TEMPS
);
164 * Is the given TGSI register stored as a real PPC vector register?
167 is_ppc_vec_temporary_dst(const struct tgsi_full_dst_register
*reg
)
169 return (reg
->DstRegister
.File
== TGSI_FILE_TEMPORARY
&&
170 reg
->DstRegister
.Index
< MAX_PPC_TEMPS
);
176 * All PPC vector load/store instructions form an effective address
177 * by adding the contents of two registers. For example:
178 * lvx v2,r8,r9 # v2 = memory[r8 + r9]
179 * stvx v2,r8,r9 # memory[r8 + r9] = v2;
180 * So our lvx/stvx instructions are typically preceded by an 'li' instruction
181 * to load r9 (above) with an immediate (an offset).
182 * This code emits that 'li' instruction, but only if the offset value is
183 * different than the previous 'li'.
184 * This optimization seems to save about 10% in the instruction count.
185 * Note that we need to unconditionally emit an 'li' inside basic blocks
186 * (such as inside loops).
189 emit_li_offset(struct gen_context
*gen
, int offset
)
191 if (gen
->offset_reg
<= 0) {
192 /* allocate a GP register for storing load/store offset */
193 gen
->offset_reg
= ppc_allocate_register(gen
->f
);
196 /* emit new 'li' if offset is changing */
197 if (gen
->offset_value
< 0 || gen
->offset_value
!= offset
) {
198 gen
->offset_value
= offset
;
199 ppc_li(gen
->f
, gen
->offset_reg
, offset
);
202 return gen
->offset_reg
;
207 * Forces subsequent emit_li_offset() calls to emit an 'li'.
208 * To be called at the top of basic blocks.
211 reset_li_offset(struct gen_context
*gen
)
213 gen
->offset_value
= -9999999;
219 * Load the given vector register with {value, value, value, value}.
220 * The value must be in the ppu_builtin_constants[] array.
221 * We wouldn't need this if there was a simple way to load PPC vector
222 * registers with immediate values!
225 load_constant_vec(struct gen_context
*gen
, int dst_vec
, float value
)
228 for (pos
= 0; pos
< Elements(ppc_builtin_constants
); pos
++) {
229 if (ppc_builtin_constants
[pos
] == value
) {
230 int offset
= pos
* 4;
231 int offset_reg
= emit_li_offset(gen
, offset
);
233 /* Load 4-byte word into vector register.
234 * The vector slot depends on the effective address we load from.
235 * We know that our builtins start at a 16-byte boundary so we
236 * know that 'swizzle' tells us which vector slot will have the
237 * loaded word. The other vector slots will be undefined.
239 ppc_lvewx(gen
->f
, dst_vec
, gen
->builtins_reg
, offset_reg
);
240 /* splat word[pos % 4] across the vector reg */
241 ppc_vspltw(gen
->f
, dst_vec
, dst_vec
, pos
% 4);
245 assert(0 && "Need to add new constant to ppc_builtin_constants array");
250 * Return index of vector register containing {1.0, 1.0, 1.0, 1.0}.
253 gen_one_vec(struct gen_context
*gen
)
255 if (gen
->one_vec
< 0) {
256 gen
->one_vec
= ppc_allocate_vec_register(gen
->f
);
257 load_constant_vec(gen
, gen
->one_vec
, 1.0f
);
263 * Return index of vector register containing {1<<31, 1<<31, 1<<31, 1<<31}.
266 gen_get_bit31_vec(struct gen_context
*gen
)
268 if (gen
->bit31_vec
< 0) {
269 gen
->bit31_vec
= ppc_allocate_vec_register(gen
->f
);
270 ppc_vspltisw(gen
->f
, gen
->bit31_vec
, -1);
271 ppc_vslw(gen
->f
, gen
->bit31_vec
, gen
->bit31_vec
, gen
->bit31_vec
);
273 return gen
->bit31_vec
;
278 * Register fetch. Return PPC vector register with result.
281 emit_fetch(struct gen_context
*gen
,
282 const struct tgsi_full_src_register
*reg
,
283 const unsigned chan_index
)
285 uint swizzle
= tgsi_util_get_full_src_register_extswizzle(reg
, chan_index
);
289 case TGSI_EXTSWIZZLE_X
:
290 case TGSI_EXTSWIZZLE_Y
:
291 case TGSI_EXTSWIZZLE_Z
:
292 case TGSI_EXTSWIZZLE_W
:
293 switch (reg
->SrcRegister
.File
) {
294 case TGSI_FILE_INPUT
:
296 int offset
= (reg
->SrcRegister
.Index
* 4 + swizzle
) * 16;
297 int offset_reg
= emit_li_offset(gen
, offset
);
298 dst_vec
= ppc_allocate_vec_register(gen
->f
);
299 ppc_lvx(gen
->f
, dst_vec
, gen
->inputs_reg
, offset_reg
);
302 case TGSI_FILE_TEMPORARY
:
303 if (is_ppc_vec_temporary(reg
)) {
304 /* use PPC vec register */
305 dst_vec
= gen
->temps_map
[reg
->SrcRegister
.Index
][swizzle
];
308 /* use memory-based temp register "file" */
309 int offset
= (reg
->SrcRegister
.Index
* 4 + swizzle
) * 16;
310 int offset_reg
= emit_li_offset(gen
, offset
);
311 dst_vec
= ppc_allocate_vec_register(gen
->f
);
312 ppc_lvx(gen
->f
, dst_vec
, gen
->temps_reg
, offset_reg
);
315 case TGSI_FILE_IMMEDIATE
:
317 int offset
= (reg
->SrcRegister
.Index
* 4 + swizzle
) * 4;
318 int offset_reg
= emit_li_offset(gen
, offset
);
319 dst_vec
= ppc_allocate_vec_register(gen
->f
);
320 /* Load 4-byte word into vector register.
321 * The vector slot depends on the effective address we load from.
322 * We know that our immediates start at a 16-byte boundary so we
323 * know that 'swizzle' tells us which vector slot will have the
324 * loaded word. The other vector slots will be undefined.
326 ppc_lvewx(gen
->f
, dst_vec
, gen
->immed_reg
, offset_reg
);
327 /* splat word[swizzle] across the vector reg */
328 ppc_vspltw(gen
->f
, dst_vec
, dst_vec
, swizzle
);
331 case TGSI_FILE_CONSTANT
:
333 int offset
= (reg
->SrcRegister
.Index
* 4 + swizzle
) * 4;
334 int offset_reg
= emit_li_offset(gen
, offset
);
335 dst_vec
= ppc_allocate_vec_register(gen
->f
);
336 /* Load 4-byte word into vector register.
337 * The vector slot depends on the effective address we load from.
338 * We know that our constants start at a 16-byte boundary so we
339 * know that 'swizzle' tells us which vector slot will have the
340 * loaded word. The other vector slots will be undefined.
342 ppc_lvewx(gen
->f
, dst_vec
, gen
->const_reg
, offset_reg
);
343 /* splat word[swizzle] across the vector reg */
344 ppc_vspltw(gen
->f
, dst_vec
, dst_vec
, swizzle
);
351 case TGSI_EXTSWIZZLE_ZERO
:
352 ppc_vzero(gen
->f
, dst_vec
);
354 case TGSI_EXTSWIZZLE_ONE
:
356 int one_vec
= gen_one_vec(gen
);
357 dst_vec
= ppc_allocate_vec_register(gen
->f
);
358 ppc_vmove(gen
->f
, dst_vec
, one_vec
);
365 assert(dst_vec
>= 0);
368 uint sign_op
= tgsi_util_get_full_src_register_sign_mode(reg
, chan_index
);
369 if (sign_op
!= TGSI_UTIL_SIGN_KEEP
) {
370 int bit31_vec
= gen_get_bit31_vec(gen
);
373 if (is_ppc_vec_temporary(reg
)) {
374 /* need to use a new temp */
375 dst_vec2
= ppc_allocate_vec_register(gen
->f
);
382 case TGSI_UTIL_SIGN_CLEAR
:
383 /* vec = vec & ~bit31 */
384 ppc_vandc(gen
->f
, dst_vec2
, dst_vec
, bit31_vec
);
386 case TGSI_UTIL_SIGN_SET
:
387 /* vec = vec | bit31 */
388 ppc_vor(gen
->f
, dst_vec2
, dst_vec
, bit31_vec
);
390 case TGSI_UTIL_SIGN_TOGGLE
:
391 /* vec = vec ^ bit31 */
392 ppc_vxor(gen
->f
, dst_vec2
, dst_vec
, bit31_vec
);
407 * Test if two TGSI src registers refer to the same memory location.
408 * We use this to avoid redundant register loads.
411 equal_src_locs(const struct tgsi_full_src_register
*a
, uint chan_a
,
412 const struct tgsi_full_src_register
*b
, uint chan_b
)
416 if (a
->SrcRegister
.File
!= b
->SrcRegister
.File
)
418 if (a
->SrcRegister
.Index
!= b
->SrcRegister
.Index
)
420 swz_a
= tgsi_util_get_full_src_register_extswizzle(a
, chan_a
);
421 swz_b
= tgsi_util_get_full_src_register_extswizzle(b
, chan_b
);
424 sign_a
= tgsi_util_get_full_src_register_sign_mode(a
, chan_a
);
425 sign_b
= tgsi_util_get_full_src_register_sign_mode(b
, chan_b
);
426 if (sign_a
!= sign_b
)
433 * Given a TGSI src register and channel index, return the PPC vector
434 * register containing the value. We use a cache to prevent re-loading
435 * the same register multiple times.
436 * \return index of PPC vector register with the desired src operand
439 get_src_vec(struct gen_context
*gen
,
440 struct tgsi_full_instruction
*inst
, int src_reg
, uint chan
)
442 const const struct tgsi_full_src_register
*src
=
443 &inst
->FullSrcRegisters
[src_reg
];
447 /* check the cache */
448 for (i
= 0; i
< gen
->num_regs
; i
++) {
449 if (equal_src_locs(&gen
->regs
[i
].src
, gen
->regs
[i
].chan
, src
, chan
)) {
451 assert(gen
->regs
[i
].vec
>= 0);
452 return gen
->regs
[i
].vec
;
456 /* cache miss: allocate new vec reg and emit fetch/load code */
457 vec
= emit_fetch(gen
, src
, chan
);
458 gen
->regs
[gen
->num_regs
].src
= *src
;
459 gen
->regs
[gen
->num_regs
].chan
= chan
;
460 gen
->regs
[gen
->num_regs
].vec
= vec
;
463 assert(gen
->num_regs
<= Elements(gen
->regs
));
472 * Clear the src operand cache. To be called at the end of each emit function.
475 release_src_vecs(struct gen_context
*gen
)
478 for (i
= 0; i
< gen
->num_regs
; i
++) {
479 const const struct tgsi_full_src_register src
= gen
->regs
[i
].src
;
480 if (!is_ppc_vec_temporary(&src
)) {
481 ppc_release_vec_register(gen
->f
, gen
->regs
[i
].vec
);
490 get_dst_vec(struct gen_context
*gen
,
491 const struct tgsi_full_instruction
*inst
,
494 const struct tgsi_full_dst_register
*reg
= &inst
->FullDstRegisters
[0];
496 if (is_ppc_vec_temporary_dst(reg
)) {
497 int vec
= gen
->temps_map
[reg
->DstRegister
.Index
][chan_index
];
501 return ppc_allocate_vec_register(gen
->f
);
507 * Register store. Store 'src_vec' at location indicated by 'reg'.
508 * \param free_vec Should the src_vec be released when done?
511 emit_store(struct gen_context
*gen
,
513 const struct tgsi_full_instruction
*inst
,
517 const struct tgsi_full_dst_register
*reg
= &inst
->FullDstRegisters
[0];
519 switch (reg
->DstRegister
.File
) {
520 case TGSI_FILE_OUTPUT
:
522 int offset
= (reg
->DstRegister
.Index
* 4 + chan_index
) * 16;
523 int offset_reg
= emit_li_offset(gen
, offset
);
524 ppc_stvx(gen
->f
, src_vec
, gen
->outputs_reg
, offset_reg
);
527 case TGSI_FILE_TEMPORARY
:
528 if (is_ppc_vec_temporary_dst(reg
)) {
530 int dst_vec
= gen
->temps_map
[reg
->DstRegister
.Index
][chan_index
];
531 if (dst_vec
!= src_vec
)
532 ppc_vmove(gen
->f
, dst_vec
, src_vec
);
537 int offset
= (reg
->DstRegister
.Index
* 4 + chan_index
) * 16;
538 int offset_reg
= emit_li_offset(gen
, offset
);
539 ppc_stvx(gen
->f
, src_vec
, gen
->temps_reg
, offset_reg
);
543 case TGSI_FILE_ADDRESS
:
547 reg
->DstRegister
.Index
,
556 switch( inst
->Instruction
.Saturate
) {
560 case TGSI_SAT_ZERO_ONE
:
564 case TGSI_SAT_MINUS_PLUS_ONE
:
571 ppc_release_vec_register(gen
->f
, src_vec
);
576 emit_scalar_unaryop(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
581 v0
= get_src_vec(gen
, inst
, 0, CHAN_X
);
582 v1
= ppc_allocate_vec_register(gen
->f
);
584 switch (inst
->Instruction
.Opcode
) {
585 case TGSI_OPCODE_RSQ
:
586 /* v1 = 1.0 / sqrt(v0) */
587 ppc_vrsqrtefp(gen
->f
, v1
, v0
);
589 case TGSI_OPCODE_RCP
:
591 ppc_vrefp(gen
->f
, v1
, v0
);
597 FOR_EACH_DST0_ENABLED_CHANNEL( *inst
, chan_index
) {
598 emit_store(gen
, v1
, inst
, chan_index
, FALSE
);
601 release_src_vecs(gen
);
602 ppc_release_vec_register(gen
->f
, v1
);
607 emit_unaryop(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
611 FOR_EACH_DST0_ENABLED_CHANNEL(*inst
, chan_index
) {
612 int v0
= get_src_vec(gen
, inst
, 0, chan_index
); /* v0 = srcreg[0] */
613 int v1
= get_dst_vec(gen
, inst
, chan_index
);
614 switch (inst
->Instruction
.Opcode
) {
615 case TGSI_OPCODE_ABS
:
616 /* turn off the most significant bit of each vector float word */
618 int bit31_vec
= gen_get_bit31_vec(gen
);
619 ppc_vandc(gen
->f
, v1
, v0
, bit31_vec
); /* v1 = v0 & ~bit31 */
622 case TGSI_OPCODE_FLR
:
623 ppc_vrfim(gen
->f
, v1
, v0
); /* v1 = floor(v0) */
625 case TGSI_OPCODE_FRC
:
626 ppc_vrfim(gen
->f
, v1
, v0
); /* tmp = floor(v0) */
627 ppc_vsubfp(gen
->f
, v1
, v0
, v1
); /* v1 = v0 - v1 */
629 case TGSI_OPCODE_EX2
:
630 ppc_vexptefp(gen
->f
, v1
, v0
); /* v1 = 2^v0 */
632 case TGSI_OPCODE_LG2
:
633 /* XXX this may be broken! */
634 ppc_vlogefp(gen
->f
, v1
, v0
); /* v1 = log2(v0) */
636 case TGSI_OPCODE_MOV
:
637 case TGSI_OPCODE_SWZ
:
639 ppc_vmove(gen
->f
, v1
, v0
);
644 emit_store(gen
, v1
, inst
, chan_index
, TRUE
); /* store v0 */
647 release_src_vecs(gen
);
652 emit_binop(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
657 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_MUL
) {
658 zero_vec
= ppc_allocate_vec_register(gen
->f
);
659 ppc_vzero(gen
->f
, zero_vec
);
662 FOR_EACH_DST0_ENABLED_CHANNEL(*inst
, chan
) {
663 /* fetch src operands */
664 int v0
= get_src_vec(gen
, inst
, 0, chan
);
665 int v1
= get_src_vec(gen
, inst
, 1, chan
);
666 int v2
= get_dst_vec(gen
, inst
, chan
);
669 switch (inst
->Instruction
.Opcode
) {
670 case TGSI_OPCODE_ADD
:
671 ppc_vaddfp(gen
->f
, v2
, v0
, v1
);
673 case TGSI_OPCODE_SUB
:
674 ppc_vsubfp(gen
->f
, v2
, v0
, v1
);
676 case TGSI_OPCODE_MUL
:
677 ppc_vmaddfp(gen
->f
, v2
, v0
, v1
, zero_vec
);
679 case TGSI_OPCODE_MIN
:
680 ppc_vminfp(gen
->f
, v2
, v0
, v1
);
682 case TGSI_OPCODE_MAX
:
683 ppc_vmaxfp(gen
->f
, v2
, v0
, v1
);
690 emit_store(gen
, v2
, inst
, chan
, TRUE
);
693 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_MUL
)
694 ppc_release_vec_register(gen
->f
, zero_vec
);
696 release_src_vecs(gen
);
701 emit_triop(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
705 FOR_EACH_DST0_ENABLED_CHANNEL(*inst
, chan
) {
706 /* fetch src operands */
707 int v0
= get_src_vec(gen
, inst
, 0, chan
);
708 int v1
= get_src_vec(gen
, inst
, 1, chan
);
709 int v2
= get_src_vec(gen
, inst
, 2, chan
);
710 int v3
= get_dst_vec(gen
, inst
, chan
);
713 switch (inst
->Instruction
.Opcode
) {
714 case TGSI_OPCODE_MAD
:
715 ppc_vmaddfp(gen
->f
, v3
, v0
, v1
, v2
); /* v3 = v0 * v1 + v2 */
717 case TGSI_OPCODE_LRP
:
718 ppc_vsubfp(gen
->f
, v3
, v1
, v2
); /* v3 = v1 - v2 */
719 ppc_vmaddfp(gen
->f
, v3
, v0
, v3
, v2
); /* v3 = v0 * v3 + v2 */
726 emit_store(gen
, v3
, inst
, chan
, TRUE
);
729 release_src_vecs(gen
);
734 * Vector comparisons, resulting in 1.0 or 0.0 values.
737 emit_inequality(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
740 int one_vec
= gen_one_vec(gen
);
742 FOR_EACH_DST0_ENABLED_CHANNEL(*inst
, chan
) {
743 /* fetch src operands */
744 int v0
= get_src_vec(gen
, inst
, 0, chan
);
745 int v1
= get_src_vec(gen
, inst
, 1, chan
);
746 int v2
= get_dst_vec(gen
, inst
, chan
);
747 boolean complement
= FALSE
;
749 switch (inst
->Instruction
.Opcode
) {
750 case TGSI_OPCODE_SNE
:
753 case TGSI_OPCODE_SEQ
:
754 ppc_vcmpeqfpx(gen
->f
, v2
, v0
, v1
); /* v2 = v0 == v1 ? ~0 : 0 */
757 case TGSI_OPCODE_SGE
:
760 case TGSI_OPCODE_SLT
:
761 ppc_vcmpgtfpx(gen
->f
, v2
, v1
, v0
); /* v2 = v1 > v0 ? ~0 : 0 */
764 case TGSI_OPCODE_SLE
:
767 case TGSI_OPCODE_SGT
:
768 ppc_vcmpgtfpx(gen
->f
, v2
, v0
, v1
); /* v2 = v0 > v1 ? ~0 : 0 */
774 /* v2 is now {0,0,0,0} or {~0,~0,~0,~0} */
777 ppc_vandc(gen
->f
, v2
, one_vec
, v2
); /* v2 = one_vec & ~v2 */
779 ppc_vand(gen
->f
, v2
, one_vec
, v2
); /* v2 = one_vec & v2 */
782 emit_store(gen
, v2
, inst
, chan
, TRUE
);
785 release_src_vecs(gen
);
790 emit_dotprod(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
795 v2
= ppc_allocate_vec_register(gen
->f
);
797 ppc_vzero(gen
->f
, v2
); /* v2 = {0, 0, 0, 0} */
799 v0
= get_src_vec(gen
, inst
, 0, CHAN_X
); /* v0 = src0.XXXX */
800 v1
= get_src_vec(gen
, inst
, 1, CHAN_X
); /* v1 = src1.XXXX */
801 ppc_vmaddfp(gen
->f
, v2
, v0
, v1
, v2
); /* v2 = v0 * v1 + v2 */
803 v0
= get_src_vec(gen
, inst
, 0, CHAN_Y
); /* v0 = src0.YYYY */
804 v1
= get_src_vec(gen
, inst
, 1, CHAN_Y
); /* v1 = src1.YYYY */
805 ppc_vmaddfp(gen
->f
, v2
, v0
, v1
, v2
); /* v2 = v0 * v1 + v2 */
807 v0
= get_src_vec(gen
, inst
, 0, CHAN_Z
); /* v0 = src0.ZZZZ */
808 v1
= get_src_vec(gen
, inst
, 1, CHAN_Z
); /* v1 = src1.ZZZZ */
809 ppc_vmaddfp(gen
->f
, v2
, v0
, v1
, v2
); /* v2 = v0 * v1 + v2 */
811 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DP4
) {
812 v0
= get_src_vec(gen
, inst
, 0, CHAN_W
); /* v0 = src0.WWWW */
813 v1
= get_src_vec(gen
, inst
, 1, CHAN_W
); /* v1 = src1.WWWW */
814 ppc_vmaddfp(gen
->f
, v2
, v0
, v1
, v2
); /* v2 = v0 * v1 + v2 */
816 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DPH
) {
817 v1
= get_src_vec(gen
, inst
, 1, CHAN_W
); /* v1 = src1.WWWW */
818 ppc_vaddfp(gen
->f
, v2
, v2
, v1
); /* v2 = v2 + v1 */
821 FOR_EACH_DST0_ENABLED_CHANNEL(*inst
, chan_index
) {
822 emit_store(gen
, v2
, inst
, chan_index
, FALSE
); /* store v2, free v2 later */
825 release_src_vecs(gen
);
827 ppc_release_vec_register(gen
->f
, v2
);
831 /** Approximation for vr = pow(va, vb) */
833 ppc_vec_pow(struct ppc_function
*f
, int vr
, int va
, int vb
)
835 /* pow(a,b) ~= exp2(log2(a) * b) */
836 int t_vec
= ppc_allocate_vec_register(f
);
837 int zero_vec
= ppc_allocate_vec_register(f
);
839 ppc_vzero(f
, zero_vec
);
841 ppc_vlogefp(f
, t_vec
, va
); /* t = log2(va) */
842 ppc_vmaddfp(f
, t_vec
, t_vec
, vb
, zero_vec
); /* t = t * vb + zero */
843 ppc_vexptefp(f
, vr
, t_vec
); /* vr = 2^t */
845 ppc_release_vec_register(f
, t_vec
);
846 ppc_release_vec_register(f
, zero_vec
);
851 emit_lit(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
853 int one_vec
= gen_one_vec(gen
);
856 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_X
)) {
857 emit_store(gen
, one_vec
, inst
, CHAN_X
, FALSE
);
861 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Y
) ||
862 IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Z
)) {
864 int zero_vec
= ppc_allocate_vec_register(gen
->f
);
866 x_vec
= get_src_vec(gen
, inst
, 0, CHAN_X
); /* x_vec = src[0].x */
868 ppc_vzero(gen
->f
, zero_vec
); /* zero = {0,0,0,0} */
869 ppc_vmaxfp(gen
->f
, x_vec
, x_vec
, zero_vec
); /* x_vec = max(x_vec, 0) */
871 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Y
)) {
872 emit_store(gen
, x_vec
, inst
, CHAN_Y
, FALSE
);
875 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Z
)) {
877 int z_vec
= ppc_allocate_vec_register(gen
->f
);
878 int pow_vec
= ppc_allocate_vec_register(gen
->f
);
879 int pos_vec
= ppc_allocate_vec_register(gen
->f
);
880 int p128_vec
= ppc_allocate_vec_register(gen
->f
);
881 int n128_vec
= ppc_allocate_vec_register(gen
->f
);
883 y_vec
= get_src_vec(gen
, inst
, 0, CHAN_Y
); /* y_vec = src[0].y */
884 ppc_vmaxfp(gen
->f
, y_vec
, y_vec
, zero_vec
); /* y_vec = max(y_vec, 0) */
886 w_vec
= get_src_vec(gen
, inst
, 0, CHAN_W
); /* w_vec = src[0].w */
888 /* clamp W to [-128, 128] */
889 load_constant_vec(gen
, p128_vec
, 128.0f
);
890 load_constant_vec(gen
, n128_vec
, -128.0f
);
891 ppc_vmaxfp(gen
->f
, w_vec
, w_vec
, n128_vec
); /* w = max(w, -128) */
892 ppc_vminfp(gen
->f
, w_vec
, w_vec
, p128_vec
); /* w = min(w, 128) */
895 * z = pow(tmp.y, tmp.w)
899 ppc_vec_pow(gen
->f
, pow_vec
, y_vec
, w_vec
); /* pow = pow(y, w) */
900 ppc_vcmpgtfpx(gen
->f
, pos_vec
, x_vec
, zero_vec
); /* pos = x > 0 */
901 ppc_vand(gen
->f
, z_vec
, pow_vec
, pos_vec
); /* z = pow & pos */
903 emit_store(gen
, z_vec
, inst
, CHAN_Z
, FALSE
);
905 ppc_release_vec_register(gen
->f
, z_vec
);
906 ppc_release_vec_register(gen
->f
, pow_vec
);
907 ppc_release_vec_register(gen
->f
, pos_vec
);
908 ppc_release_vec_register(gen
->f
, p128_vec
);
909 ppc_release_vec_register(gen
->f
, n128_vec
);
912 ppc_release_vec_register(gen
->f
, zero_vec
);
916 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_W
)) {
917 emit_store(gen
, one_vec
, inst
, CHAN_W
, FALSE
);
920 release_src_vecs(gen
);
925 emit_exp(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
927 const int one_vec
= gen_one_vec(gen
);
931 src_vec
= get_src_vec(gen
, inst
, 0, CHAN_X
);
933 /* Compute X = 2^floor(src) */
934 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_X
)) {
935 int dst_vec
= get_dst_vec(gen
, inst
, CHAN_X
);
936 int tmp_vec
= ppc_allocate_vec_register(gen
->f
);
937 ppc_vrfim(gen
->f
, tmp_vec
, src_vec
); /* tmp = floor(src); */
938 ppc_vexptefp(gen
->f
, dst_vec
, tmp_vec
); /* dst = 2 ^ tmp */
939 emit_store(gen
, dst_vec
, inst
, CHAN_X
, TRUE
);
940 ppc_release_vec_register(gen
->f
, tmp_vec
);
943 /* Compute Y = src - floor(src) */
944 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Y
)) {
945 int dst_vec
= get_dst_vec(gen
, inst
, CHAN_Y
);
946 int tmp_vec
= ppc_allocate_vec_register(gen
->f
);
947 ppc_vrfim(gen
->f
, tmp_vec
, src_vec
); /* tmp = floor(src); */
948 ppc_vsubfp(gen
->f
, dst_vec
, src_vec
, tmp_vec
); /* dst = src - tmp */
949 emit_store(gen
, dst_vec
, inst
, CHAN_Y
, TRUE
);
950 ppc_release_vec_register(gen
->f
, tmp_vec
);
953 /* Compute Z = RoughApprox2ToX(src) */
954 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Z
)) {
955 int dst_vec
= get_dst_vec(gen
, inst
, CHAN_Z
);
956 ppc_vexptefp(gen
->f
, dst_vec
, src_vec
); /* dst = 2 ^ src */
957 emit_store(gen
, dst_vec
, inst
, CHAN_Z
, TRUE
);
960 /* Compute W = 1.0 */
961 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_W
)) {
962 emit_store(gen
, one_vec
, inst
, CHAN_W
, FALSE
);
965 release_src_vecs(gen
);
970 emit_log(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
972 const int bit31_vec
= gen_get_bit31_vec(gen
);
973 const int one_vec
= gen_one_vec(gen
);
974 int src_vec
, abs_vec
;
977 src_vec
= get_src_vec(gen
, inst
, 0, CHAN_X
);
979 /* compute abs(src) */
980 abs_vec
= ppc_allocate_vec_register(gen
->f
);
981 ppc_vandc(gen
->f
, abs_vec
, src_vec
, bit31_vec
); /* abs = src & ~bit31 */
983 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_X
) &&
984 IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Y
)) {
986 /* compute tmp = floor(log2(abs)) */
987 int tmp_vec
= ppc_allocate_vec_register(gen
->f
);
988 ppc_vlogefp(gen
->f
, tmp_vec
, abs_vec
); /* tmp = log2(abs) */
989 ppc_vrfim(gen
->f
, tmp_vec
, tmp_vec
); /* tmp = floor(tmp); */
991 /* Compute X = tmp */
992 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_X
)) {
993 emit_store(gen
, tmp_vec
, inst
, CHAN_X
, FALSE
);
996 /* Compute Y = abs / 2^tmp */
997 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Y
)) {
998 const int zero_vec
= ppc_allocate_vec_register(gen
->f
);
999 ppc_vzero(gen
->f
, zero_vec
);
1000 ppc_vexptefp(gen
->f
, tmp_vec
, tmp_vec
); /* tmp = 2 ^ tmp */
1001 ppc_vrefp(gen
->f
, tmp_vec
, tmp_vec
); /* tmp = 1 / tmp */
1002 /* tmp = abs * tmp + zero */
1003 ppc_vmaddfp(gen
->f
, tmp_vec
, abs_vec
, tmp_vec
, zero_vec
);
1004 emit_store(gen
, tmp_vec
, inst
, CHAN_Y
, FALSE
);
1005 ppc_release_vec_register(gen
->f
, zero_vec
);
1008 ppc_release_vec_register(gen
->f
, tmp_vec
);
1011 /* Compute Z = RoughApproxLog2(abs) */
1012 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Z
)) {
1013 int dst_vec
= get_dst_vec(gen
, inst
, CHAN_Z
);
1014 ppc_vlogefp(gen
->f
, dst_vec
, abs_vec
); /* dst = log2(abs) */
1015 emit_store(gen
, dst_vec
, inst
, CHAN_Z
, TRUE
);
1018 /* Compute W = 1.0 */
1019 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_W
)) {
1020 emit_store(gen
, one_vec
, inst
, CHAN_W
, FALSE
);
1023 ppc_release_vec_register(gen
->f
, abs_vec
);
1024 release_src_vecs(gen
);
1029 emit_pow(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
1031 int s0_vec
= get_src_vec(gen
, inst
, 0, CHAN_X
);
1032 int s1_vec
= get_src_vec(gen
, inst
, 1, CHAN_X
);
1033 int pow_vec
= ppc_allocate_vec_register(gen
->f
);
1036 ppc_vec_pow(gen
->f
, pow_vec
, s0_vec
, s1_vec
);
1038 FOR_EACH_DST0_ENABLED_CHANNEL(*inst
, chan
) {
1039 emit_store(gen
, pow_vec
, inst
, chan
, FALSE
);
1042 ppc_release_vec_register(gen
->f
, pow_vec
);
1044 release_src_vecs(gen
);
1049 emit_xpd(struct gen_context
*gen
, struct tgsi_full_instruction
*inst
)
1051 int x0_vec
, y0_vec
, z0_vec
;
1052 int x1_vec
, y1_vec
, z1_vec
;
1053 int zero_vec
, tmp_vec
;
1056 zero_vec
= ppc_allocate_vec_register(gen
->f
);
1057 ppc_vzero(gen
->f
, zero_vec
);
1059 tmp_vec
= ppc_allocate_vec_register(gen
->f
);
1060 tmp2_vec
= ppc_allocate_vec_register(gen
->f
);
1062 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Y
) ||
1063 IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Z
)) {
1064 x0_vec
= get_src_vec(gen
, inst
, 0, CHAN_X
);
1065 x1_vec
= get_src_vec(gen
, inst
, 1, CHAN_X
);
1067 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_X
) ||
1068 IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Z
)) {
1069 y0_vec
= get_src_vec(gen
, inst
, 0, CHAN_Y
);
1070 y1_vec
= get_src_vec(gen
, inst
, 1, CHAN_Y
);
1072 if (IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_X
) ||
1073 IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Y
)) {
1074 z0_vec
= get_src_vec(gen
, inst
, 0, CHAN_Z
);
1075 z1_vec
= get_src_vec(gen
, inst
, 1, CHAN_Z
);
1078 IF_IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_X
) {
1080 ppc_vmaddfp(gen
->f
, tmp_vec
, y0_vec
, z1_vec
, zero_vec
);
1081 /* tmp = tmp - z0 * y1*/
1082 ppc_vnmsubfp(gen
->f
, tmp_vec
, tmp_vec
, z0_vec
, y1_vec
);
1083 emit_store(gen
, tmp_vec
, inst
, CHAN_X
, FALSE
);
1085 IF_IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Y
) {
1087 ppc_vmaddfp(gen
->f
, tmp_vec
, z0_vec
, x1_vec
, zero_vec
);
1088 /* tmp = tmp - x0 * z1 */
1089 ppc_vnmsubfp(gen
->f
, tmp_vec
, tmp_vec
, x0_vec
, z1_vec
);
1090 emit_store(gen
, tmp_vec
, inst
, CHAN_Y
, FALSE
);
1092 IF_IS_DST0_CHANNEL_ENABLED(*inst
, CHAN_Z
) {
1094 ppc_vmaddfp(gen
->f
, tmp_vec
, x0_vec
, y1_vec
, zero_vec
);
1095 /* tmp = tmp - y0 * x1 */
1096 ppc_vnmsubfp(gen
->f
, tmp_vec
, tmp_vec
, y0_vec
, x1_vec
);
1097 emit_store(gen
, tmp_vec
, inst
, CHAN_Z
, FALSE
);
1099 /* W is undefined */
1101 ppc_release_vec_register(gen
->f
, tmp_vec
);
1102 ppc_release_vec_register(gen
->f
, zero_vec
);
1103 release_src_vecs(gen
);
1107 emit_instruction(struct gen_context
*gen
,
1108 struct tgsi_full_instruction
*inst
)
1110 switch (inst
->Instruction
.Opcode
) {
1111 case TGSI_OPCODE_MOV
:
1112 case TGSI_OPCODE_SWZ
:
1113 case TGSI_OPCODE_ABS
:
1114 case TGSI_OPCODE_FLR
:
1115 case TGSI_OPCODE_FRC
:
1116 case TGSI_OPCODE_EX2
:
1117 case TGSI_OPCODE_LG2
:
1118 emit_unaryop(gen
, inst
);
1120 case TGSI_OPCODE_RSQ
:
1121 case TGSI_OPCODE_RCP
:
1122 emit_scalar_unaryop(gen
, inst
);
1124 case TGSI_OPCODE_ADD
:
1125 case TGSI_OPCODE_SUB
:
1126 case TGSI_OPCODE_MUL
:
1127 case TGSI_OPCODE_MIN
:
1128 case TGSI_OPCODE_MAX
:
1129 emit_binop(gen
, inst
);
1131 case TGSI_OPCODE_SEQ
:
1132 case TGSI_OPCODE_SNE
:
1133 case TGSI_OPCODE_SLT
:
1134 case TGSI_OPCODE_SGT
:
1135 case TGSI_OPCODE_SLE
:
1136 case TGSI_OPCODE_SGE
:
1137 emit_inequality(gen
, inst
);
1139 case TGSI_OPCODE_MAD
:
1140 case TGSI_OPCODE_LRP
:
1141 emit_triop(gen
, inst
);
1143 case TGSI_OPCODE_DP3
:
1144 case TGSI_OPCODE_DP4
:
1145 case TGSI_OPCODE_DPH
:
1146 emit_dotprod(gen
, inst
);
1148 case TGSI_OPCODE_LIT
:
1149 emit_lit(gen
, inst
);
1151 case TGSI_OPCODE_LOG
:
1152 emit_log(gen
, inst
);
1154 case TGSI_OPCODE_EXP
:
1155 emit_exp(gen
, inst
);
1157 case TGSI_OPCODE_POW
:
1158 emit_pow(gen
, inst
);
1160 case TGSI_OPCODE_XPD
:
1161 emit_xpd(gen
, inst
);
1163 case TGSI_OPCODE_END
:
1175 struct ppc_function
*func
,
1176 struct tgsi_full_declaration
*decl
)
1178 if( decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
1180 unsigned first
, last
, mask
;
1183 first
= decl
->DeclarationRange
.First
;
1184 last
= decl
->DeclarationRange
.Last
;
1185 mask
= decl
->Declaration
.UsageMask
;
1187 for( i
= first
; i
<= last
; i
++ ) {
1188 for( j
= 0; j
< NUM_CHANNELS
; j
++ ) {
1189 if( mask
& (1 << j
) ) {
1190 switch( decl
->Declaration
.Interpolate
) {
1191 case TGSI_INTERPOLATE_CONSTANT
:
1192 emit_coef_a0( func
, 0, i
, j
);
1193 emit_inputs( func
, 0, i
, j
);
1196 case TGSI_INTERPOLATE_LINEAR
:
1197 emit_tempf( func
, 0, 0, TGSI_SWIZZLE_X
);
1198 emit_coef_dadx( func
, 1, i
, j
);
1199 emit_tempf( func
, 2, 0, TGSI_SWIZZLE_Y
);
1200 emit_coef_dady( func
, 3, i
, j
);
1201 emit_mul( func
, 0, 1 ); /* x * dadx */
1202 emit_coef_a0( func
, 4, i
, j
);
1203 emit_mul( func
, 2, 3 ); /* y * dady */
1204 emit_add( func
, 0, 4 ); /* x * dadx + a0 */
1205 emit_add( func
, 0, 2 ); /* x * dadx + y * dady + a0 */
1206 emit_inputs( func
, 0, i
, j
);
1209 case TGSI_INTERPOLATE_PERSPECTIVE
:
1210 emit_tempf( func
, 0, 0, TGSI_SWIZZLE_X
);
1211 emit_coef_dadx( func
, 1, i
, j
);
1212 emit_tempf( func
, 2, 0, TGSI_SWIZZLE_Y
);
1213 emit_coef_dady( func
, 3, i
, j
);
1214 emit_mul( func
, 0, 1 ); /* x * dadx */
1215 emit_tempf( func
, 4, 0, TGSI_SWIZZLE_W
);
1216 emit_coef_a0( func
, 5, i
, j
);
1217 emit_rcp( func
, 4, 4 ); /* 1.0 / w */
1218 emit_mul( func
, 2, 3 ); /* y * dady */
1219 emit_add( func
, 0, 5 ); /* x * dadx + a0 */
1220 emit_add( func
, 0, 2 ); /* x * dadx + y * dady + a0 */
1221 emit_mul( func
, 0, 4 ); /* (x * dadx + y * dady + a0) / w */
1222 emit_inputs( func
, 0, i
, j
);
1239 emit_prologue(struct ppc_function
*func
)
1241 /* XXX set up stack frame */
1246 emit_epilogue(struct ppc_function
*func
)
1248 ppc_comment(func
, -4, "Epilogue:");
1250 /* XXX restore prev stack frame */
1252 debug_printf("PPC: Emitted %u instructions\n", func
->num_inst
);
1259 * Translate a TGSI vertex/fragment shader to PPC code.
1261 * \param tokens the TGSI input shader
1262 * \param func the output PPC code/function
1263 * \param immediates buffer to place immediates, later passed to PPC func
1264 * \return TRUE for success, FALSE if translation failed
1267 tgsi_emit_ppc(const struct tgsi_token
*tokens
,
1268 struct ppc_function
*func
,
1269 float (*immediates
)[4],
1270 boolean do_swizzles
)
1272 static int use_ppc_asm
= -1;
1273 struct tgsi_parse_context parse
;
1274 /*boolean instruction_phase = FALSE;*/
1276 uint num_immediates
= 0;
1277 struct gen_context gen
;
1280 if (use_ppc_asm
< 0) {
1281 /* If GALLIUM_NOPPC is set, don't use PPC codegen */
1282 use_ppc_asm
= !debug_get_bool_option("GALLIUM_NOPPC", FALSE
);
1288 debug_printf("\n********* TGSI->PPC ********\n");
1289 tgsi_dump(tokens
, 0);
1294 init_gen_context(&gen
, func
);
1296 emit_prologue(func
);
1298 tgsi_parse_init( &parse
, tokens
);
1300 while (!tgsi_parse_end_of_tokens(&parse
) && ok
) {
1301 tgsi_parse_token(&parse
);
1303 switch (parse
.FullToken
.Token
.Type
) {
1304 case TGSI_TOKEN_TYPE_DECLARATION
:
1305 if (parse
.FullHeader
.Processor
.Processor
== TGSI_PROCESSOR_FRAGMENT
) {
1306 emit_declaration(func
, &parse
.FullToken
.FullDeclaration
);
1310 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1312 _debug_printf("# ");
1314 tgsi_dump_instruction(&parse
.FullToken
.FullInstruction
, ic
);
1317 ok
= emit_instruction(&gen
, &parse
.FullToken
.FullInstruction
);
1320 debug_printf("failed to translate tgsi opcode %d to PPC (%s)\n",
1321 parse
.FullToken
.FullInstruction
.Instruction
.Opcode
,
1322 parse
.FullHeader
.Processor
.Processor
== TGSI_PROCESSOR_VERTEX
?
1323 "vertex shader" : "fragment shader");
1327 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1328 /* splat each immediate component into a float[4] vector for SoA */
1330 const uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1333 assert(num_immediates
< TGSI_EXEC_NUM_IMMEDIATES
);
1334 for (i
= 0; i
< size
; i
++) {
1335 immediates
[num_immediates
][i
] =
1336 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1348 emit_epilogue(func
);
1350 tgsi_parse_free( &parse
);
1352 if (ppc_num_instructions(func
) == 0) {
1353 /* ran out of memory for instructions */
1358 debug_printf("TGSI->PPC translation failed\n");
1363 #endif /* PIPE_ARCH_PPC */