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[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_scan.c
1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2008 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI program scan utility.
31 * Used to determine which registers and instructions are used by a shader.
32 *
33 * Authors: Brian Paul
34 */
35
36
37 #include "util/u_debug.h"
38 #include "util/u_math.h"
39 #include "util/u_memory.h"
40 #include "util/u_prim.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_scan.h"
45
46
47 static bool
48 is_memory_file(unsigned file)
49 {
50 return file == TGSI_FILE_SAMPLER ||
51 file == TGSI_FILE_SAMPLER_VIEW ||
52 file == TGSI_FILE_IMAGE ||
53 file == TGSI_FILE_BUFFER ||
54 file == TGSI_FILE_HW_ATOMIC;
55 }
56
57
58 static bool
59 is_mem_query_inst(enum tgsi_opcode opcode)
60 {
61 return opcode == TGSI_OPCODE_RESQ ||
62 opcode == TGSI_OPCODE_TXQ ||
63 opcode == TGSI_OPCODE_TXQS ||
64 opcode == TGSI_OPCODE_LODQ;
65 }
66
67 /**
68 * Is the opcode a "true" texture instruction which samples from a
69 * texture map?
70 */
71 static bool
72 is_texture_inst(enum tgsi_opcode opcode)
73 {
74 return (!is_mem_query_inst(opcode) &&
75 tgsi_get_opcode_info(opcode)->is_tex);
76 }
77
78
79 /**
80 * Is the opcode an instruction which computes a derivative explicitly or
81 * implicitly?
82 */
83 static bool
84 computes_derivative(enum tgsi_opcode opcode)
85 {
86 if (tgsi_get_opcode_info(opcode)->is_tex) {
87 return opcode != TGSI_OPCODE_TG4 &&
88 opcode != TGSI_OPCODE_TXD &&
89 opcode != TGSI_OPCODE_TXF &&
90 opcode != TGSI_OPCODE_TXF_LZ &&
91 opcode != TGSI_OPCODE_TEX_LZ &&
92 opcode != TGSI_OPCODE_TXL &&
93 opcode != TGSI_OPCODE_TXL2 &&
94 opcode != TGSI_OPCODE_TXQ &&
95 opcode != TGSI_OPCODE_TXQS;
96 }
97
98 return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
99 opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
100 opcode == TGSI_OPCODE_SAMPLE ||
101 opcode == TGSI_OPCODE_SAMPLE_B ||
102 opcode == TGSI_OPCODE_SAMPLE_C;
103 }
104
105
106 static void
107 scan_src_operand(struct tgsi_shader_info *info,
108 const struct tgsi_full_instruction *fullinst,
109 const struct tgsi_full_src_register *src,
110 unsigned src_index,
111 unsigned usage_mask_after_swizzle,
112 bool is_interp_instruction,
113 bool *is_mem_inst)
114 {
115 int ind = src->Register.Index;
116
117 if (info->processor == PIPE_SHADER_COMPUTE &&
118 src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
119 unsigned name, mask;
120
121 name = info->system_value_semantic_name[src->Register.Index];
122
123 switch (name) {
124 case TGSI_SEMANTIC_THREAD_ID:
125 case TGSI_SEMANTIC_BLOCK_ID:
126 mask = usage_mask_after_swizzle & TGSI_WRITEMASK_XYZ;
127 while (mask) {
128 unsigned i = u_bit_scan(&mask);
129
130 if (name == TGSI_SEMANTIC_THREAD_ID)
131 info->uses_thread_id[i] = true;
132 else
133 info->uses_block_id[i] = true;
134 }
135 break;
136 case TGSI_SEMANTIC_BLOCK_SIZE:
137 /* The block size is translated to IMM with a fixed block size. */
138 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
139 info->uses_block_size = true;
140 break;
141 case TGSI_SEMANTIC_GRID_SIZE:
142 info->uses_grid_size = true;
143 break;
144 }
145 }
146
147 /* Mark which inputs are effectively used */
148 if (src->Register.File == TGSI_FILE_INPUT) {
149 if (src->Register.Indirect) {
150 for (ind = 0; ind < info->num_inputs; ++ind) {
151 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
152 }
153 } else {
154 assert(ind >= 0);
155 assert(ind < PIPE_MAX_SHADER_INPUTS);
156 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
157 }
158
159 if (info->processor == PIPE_SHADER_FRAGMENT) {
160 unsigned name, index, input;
161
162 if (src->Register.Indirect && src->Indirect.ArrayID)
163 input = info->input_array_first[src->Indirect.ArrayID];
164 else
165 input = src->Register.Index;
166
167 name = info->input_semantic_name[input];
168 index = info->input_semantic_index[input];
169
170 if (name == TGSI_SEMANTIC_POSITION &&
171 usage_mask_after_swizzle & TGSI_WRITEMASK_Z)
172 info->reads_z = true;
173
174 if (name == TGSI_SEMANTIC_COLOR)
175 info->colors_read |= usage_mask_after_swizzle << (index * 4);
176
177 /* Process only interpolated varyings. Don't include POSITION.
178 * Don't include integer varyings, because they are not
179 * interpolated. Don't process inputs interpolated by INTERP
180 * opcodes. Those are tracked separately.
181 */
182 if ((!is_interp_instruction || src_index != 0) &&
183 (name == TGSI_SEMANTIC_GENERIC ||
184 name == TGSI_SEMANTIC_TEXCOORD ||
185 name == TGSI_SEMANTIC_COLOR ||
186 name == TGSI_SEMANTIC_BCOLOR ||
187 name == TGSI_SEMANTIC_FOG ||
188 name == TGSI_SEMANTIC_CLIPDIST)) {
189 switch (info->input_interpolate[input]) {
190 case TGSI_INTERPOLATE_COLOR:
191 case TGSI_INTERPOLATE_PERSPECTIVE:
192 switch (info->input_interpolate_loc[input]) {
193 case TGSI_INTERPOLATE_LOC_CENTER:
194 info->uses_persp_center = TRUE;
195 break;
196 case TGSI_INTERPOLATE_LOC_CENTROID:
197 info->uses_persp_centroid = TRUE;
198 break;
199 case TGSI_INTERPOLATE_LOC_SAMPLE:
200 info->uses_persp_sample = TRUE;
201 break;
202 }
203 break;
204 case TGSI_INTERPOLATE_LINEAR:
205 switch (info->input_interpolate_loc[input]) {
206 case TGSI_INTERPOLATE_LOC_CENTER:
207 info->uses_linear_center = TRUE;
208 break;
209 case TGSI_INTERPOLATE_LOC_CENTROID:
210 info->uses_linear_centroid = TRUE;
211 break;
212 case TGSI_INTERPOLATE_LOC_SAMPLE:
213 info->uses_linear_sample = TRUE;
214 break;
215 }
216 break;
217 /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
218 }
219 }
220 }
221 }
222
223 if (info->processor == PIPE_SHADER_TESS_CTRL &&
224 src->Register.File == TGSI_FILE_OUTPUT) {
225 unsigned input;
226
227 if (src->Register.Indirect && src->Indirect.ArrayID)
228 input = info->output_array_first[src->Indirect.ArrayID];
229 else
230 input = src->Register.Index;
231
232 switch (info->output_semantic_name[input]) {
233 case TGSI_SEMANTIC_PATCH:
234 info->reads_perpatch_outputs = true;
235 break;
236 case TGSI_SEMANTIC_TESSINNER:
237 case TGSI_SEMANTIC_TESSOUTER:
238 info->reads_tessfactor_outputs = true;
239 break;
240 default:
241 info->reads_pervertex_outputs = true;
242 }
243 }
244
245 /* check for indirect register reads */
246 if (src->Register.Indirect) {
247 info->indirect_files |= (1 << src->Register.File);
248 info->indirect_files_read |= (1 << src->Register.File);
249
250 /* record indirect constant buffer indexing */
251 if (src->Register.File == TGSI_FILE_CONSTANT) {
252 if (src->Register.Dimension) {
253 if (src->Dimension.Indirect)
254 info->const_buffers_indirect = info->const_buffers_declared;
255 else
256 info->const_buffers_indirect |= 1u << src->Dimension.Index;
257 } else {
258 info->const_buffers_indirect |= 1;
259 }
260 }
261 }
262
263 if (src->Register.Dimension && src->Dimension.Indirect)
264 info->dim_indirect_files |= 1u << src->Register.File;
265
266 /* Texture samplers */
267 if (src->Register.File == TGSI_FILE_SAMPLER) {
268 const unsigned index = src->Register.Index;
269
270 assert(fullinst->Instruction.Texture);
271 assert(index < PIPE_MAX_SAMPLERS);
272
273 if (is_texture_inst(fullinst->Instruction.Opcode)) {
274 const unsigned target = fullinst->Texture.Texture;
275 assert(target < TGSI_TEXTURE_UNKNOWN);
276 /* for texture instructions, check that the texture instruction
277 * target matches the previous sampler view declaration (if there
278 * was one.)
279 */
280 if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
281 /* probably no sampler view declaration */
282 info->sampler_targets[index] = target;
283 } else {
284 /* Make sure the texture instruction's sampler/target info
285 * agrees with the sampler view declaration.
286 */
287 assert(info->sampler_targets[index] == target);
288 }
289 }
290 }
291
292 if (is_memory_file(src->Register.File) &&
293 !is_mem_query_inst(fullinst->Instruction.Opcode)) {
294 *is_mem_inst = true;
295
296 if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
297 info->writes_memory = TRUE;
298
299 if (src->Register.File == TGSI_FILE_IMAGE) {
300 if (src->Register.Indirect)
301 info->images_atomic = info->images_declared;
302 else
303 info->images_atomic |= 1 << src->Register.Index;
304 } else if (src->Register.File == TGSI_FILE_BUFFER) {
305 if (src->Register.Indirect)
306 info->shader_buffers_atomic = info->shader_buffers_declared;
307 else
308 info->shader_buffers_atomic |= 1 << src->Register.Index;
309 }
310 } else {
311 if (src->Register.File == TGSI_FILE_IMAGE) {
312 if (src->Register.Indirect)
313 info->images_load = info->images_declared;
314 else
315 info->images_load |= 1 << src->Register.Index;
316 } else if (src->Register.File == TGSI_FILE_BUFFER) {
317 if (src->Register.Indirect)
318 info->shader_buffers_load = info->shader_buffers_declared;
319 else
320 info->shader_buffers_load |= 1 << src->Register.Index;
321 }
322 }
323 }
324 }
325
326
327 static void
328 scan_instruction(struct tgsi_shader_info *info,
329 const struct tgsi_full_instruction *fullinst,
330 unsigned *current_depth)
331 {
332 unsigned i;
333 bool is_mem_inst = false;
334 bool is_interp_instruction = false;
335 unsigned sampler_src;
336
337 assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
338 info->opcode_count[fullinst->Instruction.Opcode]++;
339
340 switch (fullinst->Instruction.Opcode) {
341 case TGSI_OPCODE_IF:
342 case TGSI_OPCODE_UIF:
343 case TGSI_OPCODE_BGNLOOP:
344 (*current_depth)++;
345 info->max_depth = MAX2(info->max_depth, *current_depth);
346 break;
347 case TGSI_OPCODE_ENDIF:
348 case TGSI_OPCODE_ENDLOOP:
349 (*current_depth)--;
350 break;
351 case TGSI_OPCODE_TEX:
352 case TGSI_OPCODE_TEX_LZ:
353 case TGSI_OPCODE_TXB:
354 case TGSI_OPCODE_TXD:
355 case TGSI_OPCODE_TXL:
356 case TGSI_OPCODE_TXP:
357 case TGSI_OPCODE_TXQ:
358 case TGSI_OPCODE_TXQS:
359 case TGSI_OPCODE_TXF:
360 case TGSI_OPCODE_TXF_LZ:
361 case TGSI_OPCODE_TEX2:
362 case TGSI_OPCODE_TXB2:
363 case TGSI_OPCODE_TXL2:
364 case TGSI_OPCODE_TG4:
365 case TGSI_OPCODE_LODQ:
366 sampler_src = fullinst->Instruction.NumSrcRegs - 1;
367 if (fullinst->Src[sampler_src].Register.File != TGSI_FILE_SAMPLER)
368 info->uses_bindless_samplers = true;
369 break;
370 case TGSI_OPCODE_RESQ:
371 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File))
372 info->uses_bindless_images = true;
373 break;
374 case TGSI_OPCODE_LOAD:
375 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
376 info->uses_bindless_images = true;
377
378 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
379 info->uses_bindless_buffer_load = true;
380 else
381 info->uses_bindless_image_load = true;
382 }
383 break;
384 case TGSI_OPCODE_ATOMUADD:
385 case TGSI_OPCODE_ATOMXCHG:
386 case TGSI_OPCODE_ATOMCAS:
387 case TGSI_OPCODE_ATOMAND:
388 case TGSI_OPCODE_ATOMOR:
389 case TGSI_OPCODE_ATOMXOR:
390 case TGSI_OPCODE_ATOMUMIN:
391 case TGSI_OPCODE_ATOMUMAX:
392 case TGSI_OPCODE_ATOMIMIN:
393 case TGSI_OPCODE_ATOMIMAX:
394 case TGSI_OPCODE_ATOMFADD:
395 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
396 info->uses_bindless_images = true;
397
398 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
399 info->uses_bindless_buffer_atomic = true;
400 else
401 info->uses_bindless_image_atomic = true;
402 }
403 break;
404 case TGSI_OPCODE_STORE:
405 if (tgsi_is_bindless_image_file(fullinst->Dst[0].Register.File)) {
406 info->uses_bindless_images = true;
407
408 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
409 info->uses_bindless_buffer_store = true;
410 else
411 info->uses_bindless_image_store = true;
412 }
413 break;
414 case TGSI_OPCODE_FBFETCH:
415 info->uses_fbfetch = true;
416 break;
417 default:
418 break;
419 }
420
421 if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
422 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
423 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
424 const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
425 unsigned input;
426
427 is_interp_instruction = true;
428
429 if (src0->Register.Indirect && src0->Indirect.ArrayID)
430 input = info->input_array_first[src0->Indirect.ArrayID];
431 else
432 input = src0->Register.Index;
433
434 /* For the INTERP opcodes, the interpolation is always
435 * PERSPECTIVE unless LINEAR is specified.
436 */
437 switch (info->input_interpolate[input]) {
438 case TGSI_INTERPOLATE_COLOR:
439 case TGSI_INTERPOLATE_CONSTANT:
440 case TGSI_INTERPOLATE_PERSPECTIVE:
441 switch (fullinst->Instruction.Opcode) {
442 case TGSI_OPCODE_INTERP_CENTROID:
443 info->uses_persp_opcode_interp_centroid = TRUE;
444 break;
445 case TGSI_OPCODE_INTERP_OFFSET:
446 info->uses_persp_opcode_interp_offset = TRUE;
447 break;
448 case TGSI_OPCODE_INTERP_SAMPLE:
449 info->uses_persp_opcode_interp_sample = TRUE;
450 break;
451 }
452 break;
453
454 case TGSI_INTERPOLATE_LINEAR:
455 switch (fullinst->Instruction.Opcode) {
456 case TGSI_OPCODE_INTERP_CENTROID:
457 info->uses_linear_opcode_interp_centroid = TRUE;
458 break;
459 case TGSI_OPCODE_INTERP_OFFSET:
460 info->uses_linear_opcode_interp_offset = TRUE;
461 break;
462 case TGSI_OPCODE_INTERP_SAMPLE:
463 info->uses_linear_opcode_interp_sample = TRUE;
464 break;
465 }
466 break;
467 }
468 }
469
470 if ((fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
471 fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG) ||
472 fullinst->Instruction.Opcode == TGSI_OPCODE_DFMA ||
473 fullinst->Instruction.Opcode == TGSI_OPCODE_DDIV ||
474 fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
475 fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
476 fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
477 fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
478 info->uses_doubles = TRUE;
479
480 for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
481 scan_src_operand(info, fullinst, &fullinst->Src[i], i,
482 tgsi_util_get_inst_usage_mask(fullinst, i),
483 is_interp_instruction, &is_mem_inst);
484
485 if (fullinst->Src[i].Register.Indirect) {
486 struct tgsi_full_src_register src = {{0}};
487
488 src.Register.File = fullinst->Src[i].Indirect.File;
489 src.Register.Index = fullinst->Src[i].Indirect.Index;
490
491 scan_src_operand(info, fullinst, &src, -1,
492 1 << fullinst->Src[i].Indirect.Swizzle,
493 false, NULL);
494 }
495
496 if (fullinst->Src[i].Register.Dimension &&
497 fullinst->Src[i].Dimension.Indirect) {
498 struct tgsi_full_src_register src = {{0}};
499
500 src.Register.File = fullinst->Src[i].DimIndirect.File;
501 src.Register.Index = fullinst->Src[i].DimIndirect.Index;
502
503 scan_src_operand(info, fullinst, &src, -1,
504 1 << fullinst->Src[i].DimIndirect.Swizzle,
505 false, NULL);
506 }
507 }
508
509 if (fullinst->Instruction.Texture) {
510 for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
511 struct tgsi_full_src_register src = {{0}};
512
513 src.Register.File = fullinst->TexOffsets[i].File;
514 src.Register.Index = fullinst->TexOffsets[i].Index;
515
516 /* The usage mask is suboptimal but should be safe. */
517 scan_src_operand(info, fullinst, &src, -1,
518 (1 << fullinst->TexOffsets[i].SwizzleX) |
519 (1 << fullinst->TexOffsets[i].SwizzleY) |
520 (1 << fullinst->TexOffsets[i].SwizzleZ),
521 false, &is_mem_inst);
522 }
523 }
524
525 /* check for indirect register writes */
526 for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
527 const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
528
529 if (dst->Register.Indirect) {
530 struct tgsi_full_src_register src = {{0}};
531
532 src.Register.File = dst->Indirect.File;
533 src.Register.Index = dst->Indirect.Index;
534
535 scan_src_operand(info, fullinst, &src, -1,
536 1 << dst->Indirect.Swizzle, false, NULL);
537
538 info->indirect_files |= (1 << dst->Register.File);
539 info->indirect_files_written |= (1 << dst->Register.File);
540 }
541
542 if (dst->Register.Dimension && dst->Dimension.Indirect) {
543 struct tgsi_full_src_register src = {{0}};
544
545 src.Register.File = dst->DimIndirect.File;
546 src.Register.Index = dst->DimIndirect.Index;
547
548 scan_src_operand(info, fullinst, &src, -1,
549 1 << dst->DimIndirect.Swizzle, false, NULL);
550
551 info->dim_indirect_files |= 1u << dst->Register.File;
552 }
553
554 if (is_memory_file(dst->Register.File)) {
555 assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
556
557 is_mem_inst = true;
558 info->writes_memory = TRUE;
559
560 if (dst->Register.File == TGSI_FILE_IMAGE) {
561 if (dst->Register.Indirect)
562 info->images_store = info->images_declared;
563 else
564 info->images_store |= 1 << dst->Register.Index;
565 } else if (dst->Register.File == TGSI_FILE_BUFFER) {
566 if (dst->Register.Indirect)
567 info->shader_buffers_store = info->shader_buffers_declared;
568 else
569 info->shader_buffers_store |= 1 << dst->Register.Index;
570 }
571 }
572 }
573
574 if (is_mem_inst)
575 info->num_memory_instructions++;
576
577 if (computes_derivative(fullinst->Instruction.Opcode))
578 info->uses_derivatives = true;
579
580 info->num_instructions++;
581 }
582
583
584 static void
585 scan_declaration(struct tgsi_shader_info *info,
586 const struct tgsi_full_declaration *fulldecl)
587 {
588 const uint file = fulldecl->Declaration.File;
589 const unsigned procType = info->processor;
590 uint reg;
591
592 if (fulldecl->Declaration.Array) {
593 unsigned array_id = fulldecl->Array.ArrayID;
594
595 switch (file) {
596 case TGSI_FILE_INPUT:
597 assert(array_id < ARRAY_SIZE(info->input_array_first));
598 info->input_array_first[array_id] = fulldecl->Range.First;
599 info->input_array_last[array_id] = fulldecl->Range.Last;
600 break;
601 case TGSI_FILE_OUTPUT:
602 assert(array_id < ARRAY_SIZE(info->output_array_first));
603 info->output_array_first[array_id] = fulldecl->Range.First;
604 info->output_array_last[array_id] = fulldecl->Range.Last;
605 break;
606 }
607 info->array_max[file] = MAX2(info->array_max[file], array_id);
608 }
609
610 for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
611 unsigned semName = fulldecl->Semantic.Name;
612 unsigned semIndex = fulldecl->Semantic.Index +
613 (reg - fulldecl->Range.First);
614 int buffer;
615 unsigned index, target, type;
616
617 /*
618 * only first 32 regs will appear in this bitfield, if larger
619 * bits will wrap around.
620 */
621 info->file_mask[file] |= (1u << (reg & 31));
622 info->file_count[file]++;
623 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
624
625 switch (file) {
626 case TGSI_FILE_CONSTANT:
627 buffer = 0;
628
629 if (fulldecl->Declaration.Dimension)
630 buffer = fulldecl->Dim.Index2D;
631
632 info->const_file_max[buffer] =
633 MAX2(info->const_file_max[buffer], (int)reg);
634 info->const_buffers_declared |= 1u << buffer;
635 break;
636
637 case TGSI_FILE_IMAGE:
638 info->images_declared |= 1u << reg;
639 if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
640 info->images_buffers |= 1 << reg;
641 break;
642
643 case TGSI_FILE_BUFFER:
644 info->shader_buffers_declared |= 1u << reg;
645 break;
646
647 case TGSI_FILE_INPUT:
648 info->input_semantic_name[reg] = (ubyte) semName;
649 info->input_semantic_index[reg] = (ubyte) semIndex;
650 info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
651 info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
652 info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
653
654 /* Vertex shaders can have inputs with holes between them. */
655 info->num_inputs = MAX2(info->num_inputs, reg + 1);
656
657 switch (semName) {
658 case TGSI_SEMANTIC_PRIMID:
659 info->uses_primid = true;
660 break;
661 case TGSI_SEMANTIC_POSITION:
662 info->reads_position = true;
663 break;
664 case TGSI_SEMANTIC_FACE:
665 info->uses_frontface = true;
666 break;
667 }
668 break;
669
670 case TGSI_FILE_SYSTEM_VALUE:
671 index = fulldecl->Range.First;
672
673 info->system_value_semantic_name[index] = semName;
674 info->num_system_values = MAX2(info->num_system_values, index + 1);
675
676 switch (semName) {
677 case TGSI_SEMANTIC_INSTANCEID:
678 info->uses_instanceid = TRUE;
679 break;
680 case TGSI_SEMANTIC_VERTEXID:
681 info->uses_vertexid = TRUE;
682 break;
683 case TGSI_SEMANTIC_VERTEXID_NOBASE:
684 info->uses_vertexid_nobase = TRUE;
685 break;
686 case TGSI_SEMANTIC_BASEVERTEX:
687 info->uses_basevertex = TRUE;
688 break;
689 case TGSI_SEMANTIC_DRAWID:
690 info->uses_drawid = TRUE;
691 break;
692 case TGSI_SEMANTIC_PRIMID:
693 info->uses_primid = TRUE;
694 break;
695 case TGSI_SEMANTIC_INVOCATIONID:
696 info->uses_invocationid = TRUE;
697 break;
698 case TGSI_SEMANTIC_POSITION:
699 info->reads_position = TRUE;
700 break;
701 case TGSI_SEMANTIC_FACE:
702 info->uses_frontface = TRUE;
703 break;
704 case TGSI_SEMANTIC_SAMPLEMASK:
705 info->reads_samplemask = TRUE;
706 break;
707 case TGSI_SEMANTIC_TESSINNER:
708 case TGSI_SEMANTIC_TESSOUTER:
709 info->reads_tess_factors = true;
710 break;
711 }
712 break;
713
714 case TGSI_FILE_OUTPUT:
715 info->output_semantic_name[reg] = (ubyte) semName;
716 info->output_semantic_index[reg] = (ubyte) semIndex;
717 info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
718 info->num_outputs = MAX2(info->num_outputs, reg + 1);
719
720 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
721 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
722 info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
723 }
724 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
725 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
726 info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
727 }
728 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
729 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
730 info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
731 }
732 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
733 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
734 info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
735 }
736
737 switch (semName) {
738 case TGSI_SEMANTIC_PRIMID:
739 info->writes_primid = true;
740 break;
741 case TGSI_SEMANTIC_VIEWPORT_INDEX:
742 info->writes_viewport_index = true;
743 break;
744 case TGSI_SEMANTIC_LAYER:
745 info->writes_layer = true;
746 break;
747 case TGSI_SEMANTIC_PSIZE:
748 info->writes_psize = true;
749 break;
750 case TGSI_SEMANTIC_CLIPVERTEX:
751 info->writes_clipvertex = true;
752 break;
753 case TGSI_SEMANTIC_COLOR:
754 info->colors_written |= 1 << semIndex;
755 break;
756 case TGSI_SEMANTIC_STENCIL:
757 info->writes_stencil = true;
758 break;
759 case TGSI_SEMANTIC_SAMPLEMASK:
760 info->writes_samplemask = true;
761 break;
762 case TGSI_SEMANTIC_EDGEFLAG:
763 info->writes_edgeflag = true;
764 break;
765 case TGSI_SEMANTIC_POSITION:
766 if (procType == PIPE_SHADER_FRAGMENT)
767 info->writes_z = true;
768 else
769 info->writes_position = true;
770 break;
771 }
772 break;
773
774 case TGSI_FILE_SAMPLER:
775 STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
776 info->samplers_declared |= 1u << reg;
777 break;
778
779 case TGSI_FILE_SAMPLER_VIEW:
780 target = fulldecl->SamplerView.Resource;
781 type = fulldecl->SamplerView.ReturnTypeX;
782
783 assert(target < TGSI_TEXTURE_UNKNOWN);
784 if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
785 /* Save sampler target for this sampler index */
786 info->sampler_targets[reg] = target;
787 info->sampler_type[reg] = type;
788 } else {
789 /* if previously declared, make sure targets agree */
790 assert(info->sampler_targets[reg] == target);
791 assert(info->sampler_type[reg] == type);
792 }
793 break;
794 }
795 }
796 }
797
798
799 static void
800 scan_immediate(struct tgsi_shader_info *info)
801 {
802 uint reg = info->immediate_count++;
803 uint file = TGSI_FILE_IMMEDIATE;
804
805 info->file_mask[file] |= (1 << reg);
806 info->file_count[file]++;
807 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
808 }
809
810
811 static void
812 scan_property(struct tgsi_shader_info *info,
813 const struct tgsi_full_property *fullprop)
814 {
815 unsigned name = fullprop->Property.PropertyName;
816 unsigned value = fullprop->u[0].Data;
817
818 assert(name < ARRAY_SIZE(info->properties));
819 info->properties[name] = value;
820
821 switch (name) {
822 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
823 info->num_written_clipdistance = value;
824 info->clipdist_writemask |= (1 << value) - 1;
825 break;
826 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
827 info->num_written_culldistance = value;
828 info->culldist_writemask |= (1 << value) - 1;
829 break;
830 }
831 }
832
833
834 /**
835 * Scan the given TGSI shader to collect information such as number of
836 * registers used, special instructions used, etc.
837 * \return info the result of the scan
838 */
839 void
840 tgsi_scan_shader(const struct tgsi_token *tokens,
841 struct tgsi_shader_info *info)
842 {
843 uint procType, i;
844 struct tgsi_parse_context parse;
845 unsigned current_depth = 0;
846
847 memset(info, 0, sizeof(*info));
848 for (i = 0; i < TGSI_FILE_COUNT; i++)
849 info->file_max[i] = -1;
850 for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
851 info->const_file_max[i] = -1;
852 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
853 for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
854 info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
855
856 /**
857 ** Setup to begin parsing input shader
858 **/
859 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
860 debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
861 return;
862 }
863 procType = parse.FullHeader.Processor.Processor;
864 assert(procType == PIPE_SHADER_FRAGMENT ||
865 procType == PIPE_SHADER_VERTEX ||
866 procType == PIPE_SHADER_GEOMETRY ||
867 procType == PIPE_SHADER_TESS_CTRL ||
868 procType == PIPE_SHADER_TESS_EVAL ||
869 procType == PIPE_SHADER_COMPUTE);
870 info->processor = procType;
871 info->num_tokens = tgsi_num_tokens(parse.Tokens);
872
873 /**
874 ** Loop over incoming program tokens/instructions
875 */
876 while (!tgsi_parse_end_of_tokens(&parse)) {
877 tgsi_parse_token( &parse );
878
879 switch( parse.FullToken.Token.Type ) {
880 case TGSI_TOKEN_TYPE_INSTRUCTION:
881 scan_instruction(info, &parse.FullToken.FullInstruction,
882 &current_depth);
883 break;
884 case TGSI_TOKEN_TYPE_DECLARATION:
885 scan_declaration(info, &parse.FullToken.FullDeclaration);
886 break;
887 case TGSI_TOKEN_TYPE_IMMEDIATE:
888 scan_immediate(info);
889 break;
890 case TGSI_TOKEN_TYPE_PROPERTY:
891 scan_property(info, &parse.FullToken.FullProperty);
892 break;
893 default:
894 assert(!"Unexpected TGSI token type");
895 }
896 }
897
898 info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
899 info->opcode_count[TGSI_OPCODE_KILL]);
900
901 /* The dimensions of the IN decleration in geometry shader have
902 * to be deduced from the type of the input primitive.
903 */
904 if (procType == PIPE_SHADER_GEOMETRY) {
905 unsigned input_primitive =
906 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
907 int num_verts = u_vertices_per_prim(input_primitive);
908 int j;
909 info->file_count[TGSI_FILE_INPUT] = num_verts;
910 info->file_max[TGSI_FILE_INPUT] =
911 MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
912 for (j = 0; j < num_verts; ++j) {
913 info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
914 }
915 }
916
917 tgsi_parse_free(&parse);
918 }
919
920 /**
921 * Collect information about the arrays of a given register file.
922 *
923 * @param tokens TGSI shader
924 * @param file the register file to scan through
925 * @param max_array_id number of entries in @p arrays; should be equal to the
926 * highest array id, i.e. tgsi_shader_info::array_max[file].
927 * @param arrays info for array of each ID will be written to arrays[ID - 1].
928 */
929 void
930 tgsi_scan_arrays(const struct tgsi_token *tokens,
931 unsigned file,
932 unsigned max_array_id,
933 struct tgsi_array_info *arrays)
934 {
935 struct tgsi_parse_context parse;
936
937 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
938 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
939 return;
940 }
941
942 memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
943
944 while (!tgsi_parse_end_of_tokens(&parse)) {
945 struct tgsi_full_instruction *inst;
946
947 tgsi_parse_token(&parse);
948
949 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
950 struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
951
952 if (decl->Declaration.Array && decl->Declaration.File == file &&
953 decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
954 struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
955 assert(!array->declared);
956 array->declared = true;
957 array->range = decl->Range;
958 }
959 }
960
961 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
962 continue;
963
964 inst = &parse.FullToken.FullInstruction;
965 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
966 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
967 if (dst->Register.File != file)
968 continue;
969
970 if (dst->Register.Indirect) {
971 if (dst->Indirect.ArrayID > 0 &&
972 dst->Indirect.ArrayID <= max_array_id) {
973 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
974 } else {
975 /* Indirect writes without an ArrayID can write anywhere. */
976 for (unsigned j = 0; j < max_array_id; ++j)
977 arrays[j].writemask |= dst->Register.WriteMask;
978 }
979 } else {
980 /* Check whether the write falls into any of the arrays anyway. */
981 for (unsigned j = 0; j < max_array_id; ++j) {
982 struct tgsi_array_info *array = &arrays[j];
983 if (array->declared &&
984 dst->Register.Index >= array->range.First &&
985 dst->Register.Index <= array->range.Last)
986 array->writemask |= dst->Register.WriteMask;
987 }
988 }
989 }
990 }
991
992 tgsi_parse_free(&parse);
993
994 return;
995 }
996
997 static void
998 check_no_subroutines(const struct tgsi_full_instruction *inst)
999 {
1000 switch (inst->Instruction.Opcode) {
1001 case TGSI_OPCODE_BGNSUB:
1002 case TGSI_OPCODE_ENDSUB:
1003 case TGSI_OPCODE_CAL:
1004 unreachable("subroutines unhandled");
1005 }
1006 }
1007
1008 static unsigned
1009 get_inst_tessfactor_writemask(const struct tgsi_shader_info *info,
1010 const struct tgsi_full_instruction *inst)
1011 {
1012 unsigned writemask = 0;
1013
1014 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
1015 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
1016
1017 if (dst->Register.File == TGSI_FILE_OUTPUT &&
1018 !dst->Register.Indirect) {
1019 unsigned name = info->output_semantic_name[dst->Register.Index];
1020
1021 if (name == TGSI_SEMANTIC_TESSINNER)
1022 writemask |= dst->Register.WriteMask;
1023 else if (name == TGSI_SEMANTIC_TESSOUTER)
1024 writemask |= dst->Register.WriteMask << 4;
1025 }
1026 }
1027 return writemask;
1028 }
1029
1030 static unsigned
1031 get_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1032 struct tgsi_parse_context *parse,
1033 unsigned end_opcode)
1034 {
1035 struct tgsi_full_instruction *inst;
1036 unsigned writemask = 0;
1037
1038 tgsi_parse_token(parse);
1039 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1040 inst = &parse->FullToken.FullInstruction;
1041 check_no_subroutines(inst);
1042
1043 while (inst->Instruction.Opcode != end_opcode) {
1044
1045 /* Recursively process nested blocks. */
1046 switch (inst->Instruction.Opcode) {
1047 case TGSI_OPCODE_IF:
1048 case TGSI_OPCODE_UIF:
1049 writemask |=
1050 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDIF);
1051 break;
1052
1053 case TGSI_OPCODE_BGNLOOP:
1054 writemask |=
1055 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1056 break;
1057
1058 case TGSI_OPCODE_BARRIER:
1059 unreachable("nested BARRIER is illegal");
1060 break;
1061
1062 default:
1063 writemask |= get_inst_tessfactor_writemask(info, inst);
1064 }
1065
1066 tgsi_parse_token(parse);
1067 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1068 inst = &parse->FullToken.FullInstruction;
1069 check_no_subroutines(inst);
1070 }
1071
1072 return writemask;
1073 }
1074
1075 static void
1076 get_if_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1077 struct tgsi_parse_context *parse,
1078 unsigned *upper_block_tf_writemask,
1079 unsigned *cond_block_tf_writemask)
1080 {
1081 struct tgsi_full_instruction *inst;
1082 unsigned then_tessfactor_writemask = 0;
1083 unsigned else_tessfactor_writemask = 0;
1084 unsigned writemask;
1085 bool is_then = true;
1086
1087 tgsi_parse_token(parse);
1088 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1089 inst = &parse->FullToken.FullInstruction;
1090 check_no_subroutines(inst);
1091
1092 while (inst->Instruction.Opcode != TGSI_OPCODE_ENDIF) {
1093
1094 switch (inst->Instruction.Opcode) {
1095 case TGSI_OPCODE_ELSE:
1096 is_then = false;
1097 break;
1098
1099 /* Recursively process nested blocks. */
1100 case TGSI_OPCODE_IF:
1101 case TGSI_OPCODE_UIF:
1102 get_if_block_tessfactor_writemask(info, parse,
1103 is_then ? &then_tessfactor_writemask :
1104 &else_tessfactor_writemask,
1105 cond_block_tf_writemask);
1106 break;
1107
1108 case TGSI_OPCODE_BGNLOOP:
1109 *cond_block_tf_writemask |=
1110 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1111 break;
1112
1113 case TGSI_OPCODE_BARRIER:
1114 unreachable("nested BARRIER is illegal");
1115 break;
1116 default:
1117 /* Process an instruction in the current block. */
1118 writemask = get_inst_tessfactor_writemask(info, inst);
1119
1120 if (writemask) {
1121 if (is_then)
1122 then_tessfactor_writemask |= writemask;
1123 else
1124 else_tessfactor_writemask |= writemask;
1125 }
1126 }
1127
1128 tgsi_parse_token(parse);
1129 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1130 inst = &parse->FullToken.FullInstruction;
1131 check_no_subroutines(inst);
1132 }
1133
1134 if (then_tessfactor_writemask || else_tessfactor_writemask) {
1135 /* If both statements write the same tess factor channels,
1136 * we can say that the upper block writes them too. */
1137 *upper_block_tf_writemask |= then_tessfactor_writemask &
1138 else_tessfactor_writemask;
1139 *cond_block_tf_writemask |= then_tessfactor_writemask |
1140 else_tessfactor_writemask;
1141 }
1142 }
1143
1144 void
1145 tgsi_scan_tess_ctrl(const struct tgsi_token *tokens,
1146 const struct tgsi_shader_info *info,
1147 struct tgsi_tessctrl_info *out)
1148 {
1149 memset(out, 0, sizeof(*out));
1150
1151 if (info->processor != PIPE_SHADER_TESS_CTRL)
1152 return;
1153
1154 struct tgsi_parse_context parse;
1155 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
1156 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
1157 return;
1158 }
1159
1160 /* The pass works as follows:
1161 * If all codepaths write tess factors, we can say that all invocations
1162 * define tess factors.
1163 *
1164 * Each tess factor channel is tracked separately.
1165 */
1166 unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
1167 unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
1168
1169 /* Initial value = true. Here the pass will accumulate results from multiple
1170 * segments surrounded by barriers. If tess factors aren't written at all,
1171 * it's a shader bug and we don't care if this will be true.
1172 */
1173 out->tessfactors_are_def_in_all_invocs = true;
1174
1175 while (!tgsi_parse_end_of_tokens(&parse)) {
1176 tgsi_parse_token(&parse);
1177
1178 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
1179 continue;
1180
1181 struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1182 check_no_subroutines(inst);
1183
1184 /* Process nested blocks. */
1185 switch (inst->Instruction.Opcode) {
1186 case TGSI_OPCODE_IF:
1187 case TGSI_OPCODE_UIF:
1188 get_if_block_tessfactor_writemask(info, &parse,
1189 &main_block_tf_writemask,
1190 &cond_block_tf_writemask);
1191 continue;
1192
1193 case TGSI_OPCODE_BGNLOOP:
1194 cond_block_tf_writemask |=
1195 get_block_tessfactor_writemask(info, &parse, TGSI_OPCODE_ENDLOOP);
1196 continue;
1197
1198 case TGSI_OPCODE_BARRIER:
1199 /* The following case must be prevented:
1200 * gl_TessLevelInner = ...;
1201 * barrier();
1202 * if (gl_InvocationID == 1)
1203 * gl_TessLevelInner = ...;
1204 *
1205 * If you consider disjoint code segments separated by barriers, each
1206 * such segment that writes tess factor channels should write the same
1207 * channels in all codepaths within that segment.
1208 */
1209 if (main_block_tf_writemask || cond_block_tf_writemask) {
1210 /* Accumulate the result: */
1211 out->tessfactors_are_def_in_all_invocs &=
1212 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1213
1214 /* Analyze the next code segment from scratch. */
1215 main_block_tf_writemask = 0;
1216 cond_block_tf_writemask = 0;
1217 }
1218 continue;
1219 }
1220
1221 main_block_tf_writemask |= get_inst_tessfactor_writemask(info, inst);
1222 }
1223
1224 /* Accumulate the result for the last code segment separated by a barrier. */
1225 if (main_block_tf_writemask || cond_block_tf_writemask) {
1226 out->tessfactors_are_def_in_all_invocs &=
1227 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1228 }
1229
1230 tgsi_parse_free(&parse);
1231 }