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[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_scan.c
1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2008 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI program scan utility.
31 * Used to determine which registers and instructions are used by a shader.
32 *
33 * Authors: Brian Paul
34 */
35
36
37 #include "util/u_debug.h"
38 #include "util/u_math.h"
39 #include "util/u_memory.h"
40 #include "util/u_prim.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_scan.h"
45
46
47 static bool
48 is_memory_file(unsigned file)
49 {
50 return file == TGSI_FILE_SAMPLER ||
51 file == TGSI_FILE_SAMPLER_VIEW ||
52 file == TGSI_FILE_IMAGE ||
53 file == TGSI_FILE_BUFFER ||
54 file == TGSI_FILE_HW_ATOMIC;
55 }
56
57
58 static bool
59 is_mem_query_inst(enum tgsi_opcode opcode)
60 {
61 return opcode == TGSI_OPCODE_RESQ ||
62 opcode == TGSI_OPCODE_TXQ ||
63 opcode == TGSI_OPCODE_TXQS ||
64 opcode == TGSI_OPCODE_LODQ;
65 }
66
67 /**
68 * Is the opcode a "true" texture instruction which samples from a
69 * texture map?
70 */
71 static bool
72 is_texture_inst(enum tgsi_opcode opcode)
73 {
74 return (!is_mem_query_inst(opcode) &&
75 tgsi_get_opcode_info(opcode)->is_tex);
76 }
77
78
79 /**
80 * Is the opcode an instruction which computes a derivative explicitly or
81 * implicitly?
82 */
83 static bool
84 computes_derivative(enum tgsi_opcode opcode)
85 {
86 if (tgsi_get_opcode_info(opcode)->is_tex) {
87 return opcode != TGSI_OPCODE_TG4 &&
88 opcode != TGSI_OPCODE_TXD &&
89 opcode != TGSI_OPCODE_TXF &&
90 opcode != TGSI_OPCODE_TXF_LZ &&
91 opcode != TGSI_OPCODE_TEX_LZ &&
92 opcode != TGSI_OPCODE_TXL &&
93 opcode != TGSI_OPCODE_TXL2 &&
94 opcode != TGSI_OPCODE_TXQ &&
95 opcode != TGSI_OPCODE_TXQS;
96 }
97
98 return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
99 opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
100 opcode == TGSI_OPCODE_SAMPLE ||
101 opcode == TGSI_OPCODE_SAMPLE_B ||
102 opcode == TGSI_OPCODE_SAMPLE_C;
103 }
104
105
106 static void
107 scan_src_operand(struct tgsi_shader_info *info,
108 const struct tgsi_full_instruction *fullinst,
109 const struct tgsi_full_src_register *src,
110 unsigned src_index,
111 unsigned usage_mask_after_swizzle,
112 bool is_interp_instruction,
113 bool *is_mem_inst)
114 {
115 int ind = src->Register.Index;
116
117 if (info->processor == PIPE_SHADER_COMPUTE &&
118 src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
119 unsigned name, mask;
120
121 name = info->system_value_semantic_name[src->Register.Index];
122
123 switch (name) {
124 case TGSI_SEMANTIC_THREAD_ID:
125 case TGSI_SEMANTIC_BLOCK_ID:
126 mask = usage_mask_after_swizzle & TGSI_WRITEMASK_XYZ;
127 while (mask) {
128 unsigned i = u_bit_scan(&mask);
129
130 if (name == TGSI_SEMANTIC_THREAD_ID)
131 info->uses_thread_id[i] = true;
132 else
133 info->uses_block_id[i] = true;
134 }
135 break;
136 case TGSI_SEMANTIC_BLOCK_SIZE:
137 /* The block size is translated to IMM with a fixed block size. */
138 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
139 info->uses_block_size = true;
140 break;
141 case TGSI_SEMANTIC_GRID_SIZE:
142 info->uses_grid_size = true;
143 break;
144 }
145 }
146
147 /* Mark which inputs are effectively used */
148 if (src->Register.File == TGSI_FILE_INPUT) {
149 if (src->Register.Indirect) {
150 for (ind = 0; ind < info->num_inputs; ++ind) {
151 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
152 }
153 } else {
154 assert(ind >= 0);
155 assert(ind < PIPE_MAX_SHADER_INPUTS);
156 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
157 }
158
159 if (info->processor == PIPE_SHADER_FRAGMENT) {
160 unsigned name, index, input;
161
162 if (src->Register.Indirect && src->Indirect.ArrayID)
163 input = info->input_array_first[src->Indirect.ArrayID];
164 else
165 input = src->Register.Index;
166
167 name = info->input_semantic_name[input];
168 index = info->input_semantic_index[input];
169
170 if (name == TGSI_SEMANTIC_POSITION &&
171 usage_mask_after_swizzle & TGSI_WRITEMASK_Z)
172 info->reads_z = true;
173
174 if (name == TGSI_SEMANTIC_COLOR)
175 info->colors_read |= usage_mask_after_swizzle << (index * 4);
176
177 /* Process only interpolated varyings. Don't include POSITION.
178 * Don't include integer varyings, because they are not
179 * interpolated. Don't process inputs interpolated by INTERP
180 * opcodes. Those are tracked separately.
181 */
182 if ((!is_interp_instruction || src_index != 0) &&
183 (name == TGSI_SEMANTIC_GENERIC ||
184 name == TGSI_SEMANTIC_TEXCOORD ||
185 name == TGSI_SEMANTIC_COLOR ||
186 name == TGSI_SEMANTIC_BCOLOR ||
187 name == TGSI_SEMANTIC_FOG ||
188 name == TGSI_SEMANTIC_CLIPDIST)) {
189 switch (info->input_interpolate[input]) {
190 case TGSI_INTERPOLATE_COLOR:
191 case TGSI_INTERPOLATE_PERSPECTIVE:
192 switch (info->input_interpolate_loc[input]) {
193 case TGSI_INTERPOLATE_LOC_CENTER:
194 info->uses_persp_center = TRUE;
195 break;
196 case TGSI_INTERPOLATE_LOC_CENTROID:
197 info->uses_persp_centroid = TRUE;
198 break;
199 case TGSI_INTERPOLATE_LOC_SAMPLE:
200 info->uses_persp_sample = TRUE;
201 break;
202 }
203 break;
204 case TGSI_INTERPOLATE_LINEAR:
205 switch (info->input_interpolate_loc[input]) {
206 case TGSI_INTERPOLATE_LOC_CENTER:
207 info->uses_linear_center = TRUE;
208 break;
209 case TGSI_INTERPOLATE_LOC_CENTROID:
210 info->uses_linear_centroid = TRUE;
211 break;
212 case TGSI_INTERPOLATE_LOC_SAMPLE:
213 info->uses_linear_sample = TRUE;
214 break;
215 }
216 break;
217 /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
218 }
219 }
220 }
221 }
222
223 if (info->processor == PIPE_SHADER_TESS_CTRL &&
224 src->Register.File == TGSI_FILE_OUTPUT) {
225 unsigned input;
226
227 if (src->Register.Indirect && src->Indirect.ArrayID)
228 input = info->output_array_first[src->Indirect.ArrayID];
229 else
230 input = src->Register.Index;
231
232 switch (info->output_semantic_name[input]) {
233 case TGSI_SEMANTIC_PATCH:
234 info->reads_perpatch_outputs = true;
235 break;
236 case TGSI_SEMANTIC_TESSINNER:
237 case TGSI_SEMANTIC_TESSOUTER:
238 info->reads_tessfactor_outputs = true;
239 break;
240 default:
241 info->reads_pervertex_outputs = true;
242 }
243 }
244
245 /* check for indirect register reads */
246 if (src->Register.Indirect) {
247 info->indirect_files |= (1 << src->Register.File);
248 info->indirect_files_read |= (1 << src->Register.File);
249
250 /* record indirect constant buffer indexing */
251 if (src->Register.File == TGSI_FILE_CONSTANT) {
252 if (src->Register.Dimension) {
253 if (src->Dimension.Indirect)
254 info->const_buffers_indirect = info->const_buffers_declared;
255 else
256 info->const_buffers_indirect |= 1u << src->Dimension.Index;
257 } else {
258 info->const_buffers_indirect |= 1;
259 }
260 }
261 }
262
263 if (src->Register.Dimension && src->Dimension.Indirect)
264 info->dim_indirect_files |= 1u << src->Register.File;
265
266 /* Texture samplers */
267 if (src->Register.File == TGSI_FILE_SAMPLER) {
268 const unsigned index = src->Register.Index;
269
270 assert(fullinst->Instruction.Texture);
271 assert(index < PIPE_MAX_SAMPLERS);
272
273 if (is_texture_inst(fullinst->Instruction.Opcode)) {
274 const unsigned target = fullinst->Texture.Texture;
275 assert(target < TGSI_TEXTURE_UNKNOWN);
276 /* for texture instructions, check that the texture instruction
277 * target matches the previous sampler view declaration (if there
278 * was one.)
279 */
280 if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
281 /* probably no sampler view declaration */
282 info->sampler_targets[index] = target;
283 } else {
284 /* Make sure the texture instruction's sampler/target info
285 * agrees with the sampler view declaration.
286 */
287 assert(info->sampler_targets[index] == target);
288 }
289 }
290 }
291
292 if (is_memory_file(src->Register.File) &&
293 !is_mem_query_inst(fullinst->Instruction.Opcode)) {
294 *is_mem_inst = true;
295
296 if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
297 info->writes_memory = TRUE;
298
299 if (src->Register.File == TGSI_FILE_IMAGE) {
300 if (src->Register.Indirect)
301 info->images_atomic = info->images_declared;
302 else
303 info->images_atomic |= 1 << src->Register.Index;
304 } else if (src->Register.File == TGSI_FILE_BUFFER) {
305 if (src->Register.Indirect)
306 info->shader_buffers_atomic = info->shader_buffers_declared;
307 else
308 info->shader_buffers_atomic |= 1 << src->Register.Index;
309 }
310 } else {
311 if (src->Register.File == TGSI_FILE_IMAGE) {
312 if (src->Register.Indirect)
313 info->images_load = info->images_declared;
314 else
315 info->images_load |= 1 << src->Register.Index;
316 } else if (src->Register.File == TGSI_FILE_BUFFER) {
317 if (src->Register.Indirect)
318 info->shader_buffers_load = info->shader_buffers_declared;
319 else
320 info->shader_buffers_load |= 1 << src->Register.Index;
321 }
322 }
323 }
324 }
325
326
327 static void
328 scan_instruction(struct tgsi_shader_info *info,
329 const struct tgsi_full_instruction *fullinst,
330 unsigned *current_depth)
331 {
332 unsigned i;
333 bool is_mem_inst = false;
334 bool is_interp_instruction = false;
335 unsigned sampler_src;
336
337 assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
338 info->opcode_count[fullinst->Instruction.Opcode]++;
339
340 switch (fullinst->Instruction.Opcode) {
341 case TGSI_OPCODE_IF:
342 case TGSI_OPCODE_UIF:
343 case TGSI_OPCODE_BGNLOOP:
344 (*current_depth)++;
345 info->max_depth = MAX2(info->max_depth, *current_depth);
346 break;
347 case TGSI_OPCODE_ENDIF:
348 case TGSI_OPCODE_ENDLOOP:
349 (*current_depth)--;
350 break;
351 case TGSI_OPCODE_TEX:
352 case TGSI_OPCODE_TEX_LZ:
353 case TGSI_OPCODE_TXB:
354 case TGSI_OPCODE_TXD:
355 case TGSI_OPCODE_TXL:
356 case TGSI_OPCODE_TXP:
357 case TGSI_OPCODE_TXQ:
358 case TGSI_OPCODE_TXQS:
359 case TGSI_OPCODE_TXF:
360 case TGSI_OPCODE_TXF_LZ:
361 case TGSI_OPCODE_TEX2:
362 case TGSI_OPCODE_TXB2:
363 case TGSI_OPCODE_TXL2:
364 case TGSI_OPCODE_TG4:
365 case TGSI_OPCODE_LODQ:
366 sampler_src = fullinst->Instruction.NumSrcRegs - 1;
367 if (fullinst->Src[sampler_src].Register.File != TGSI_FILE_SAMPLER)
368 info->uses_bindless_samplers = true;
369 break;
370 case TGSI_OPCODE_RESQ:
371 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File))
372 info->uses_bindless_images = true;
373 break;
374 case TGSI_OPCODE_LOAD:
375 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
376 info->uses_bindless_images = true;
377
378 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
379 info->uses_bindless_buffer_load = true;
380 else
381 info->uses_bindless_image_load = true;
382 }
383 break;
384 case TGSI_OPCODE_ATOMUADD:
385 case TGSI_OPCODE_ATOMXCHG:
386 case TGSI_OPCODE_ATOMCAS:
387 case TGSI_OPCODE_ATOMAND:
388 case TGSI_OPCODE_ATOMOR:
389 case TGSI_OPCODE_ATOMXOR:
390 case TGSI_OPCODE_ATOMUMIN:
391 case TGSI_OPCODE_ATOMUMAX:
392 case TGSI_OPCODE_ATOMIMIN:
393 case TGSI_OPCODE_ATOMIMAX:
394 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
395 info->uses_bindless_images = true;
396
397 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
398 info->uses_bindless_buffer_atomic = true;
399 else
400 info->uses_bindless_image_atomic = true;
401 }
402 break;
403 case TGSI_OPCODE_STORE:
404 if (tgsi_is_bindless_image_file(fullinst->Dst[0].Register.File)) {
405 info->uses_bindless_images = true;
406
407 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
408 info->uses_bindless_buffer_store = true;
409 else
410 info->uses_bindless_image_store = true;
411 }
412 break;
413 default:
414 break;
415 }
416
417 if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
418 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
419 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
420 const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
421 unsigned input;
422
423 is_interp_instruction = true;
424
425 if (src0->Register.Indirect && src0->Indirect.ArrayID)
426 input = info->input_array_first[src0->Indirect.ArrayID];
427 else
428 input = src0->Register.Index;
429
430 /* For the INTERP opcodes, the interpolation is always
431 * PERSPECTIVE unless LINEAR is specified.
432 */
433 switch (info->input_interpolate[input]) {
434 case TGSI_INTERPOLATE_COLOR:
435 case TGSI_INTERPOLATE_CONSTANT:
436 case TGSI_INTERPOLATE_PERSPECTIVE:
437 switch (fullinst->Instruction.Opcode) {
438 case TGSI_OPCODE_INTERP_CENTROID:
439 info->uses_persp_opcode_interp_centroid = TRUE;
440 break;
441 case TGSI_OPCODE_INTERP_OFFSET:
442 info->uses_persp_opcode_interp_offset = TRUE;
443 break;
444 case TGSI_OPCODE_INTERP_SAMPLE:
445 info->uses_persp_opcode_interp_sample = TRUE;
446 break;
447 }
448 break;
449
450 case TGSI_INTERPOLATE_LINEAR:
451 switch (fullinst->Instruction.Opcode) {
452 case TGSI_OPCODE_INTERP_CENTROID:
453 info->uses_linear_opcode_interp_centroid = TRUE;
454 break;
455 case TGSI_OPCODE_INTERP_OFFSET:
456 info->uses_linear_opcode_interp_offset = TRUE;
457 break;
458 case TGSI_OPCODE_INTERP_SAMPLE:
459 info->uses_linear_opcode_interp_sample = TRUE;
460 break;
461 }
462 break;
463 }
464 }
465
466 if ((fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
467 fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG) ||
468 fullinst->Instruction.Opcode == TGSI_OPCODE_DFMA ||
469 fullinst->Instruction.Opcode == TGSI_OPCODE_DDIV ||
470 fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
471 fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
472 fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
473 fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
474 info->uses_doubles = TRUE;
475
476 for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
477 scan_src_operand(info, fullinst, &fullinst->Src[i], i,
478 tgsi_util_get_inst_usage_mask(fullinst, i),
479 is_interp_instruction, &is_mem_inst);
480
481 if (fullinst->Src[i].Register.Indirect) {
482 struct tgsi_full_src_register src = {{0}};
483
484 src.Register.File = fullinst->Src[i].Indirect.File;
485 src.Register.Index = fullinst->Src[i].Indirect.Index;
486
487 scan_src_operand(info, fullinst, &src, -1,
488 1 << fullinst->Src[i].Indirect.Swizzle,
489 false, NULL);
490 }
491
492 if (fullinst->Src[i].Register.Dimension &&
493 fullinst->Src[i].Dimension.Indirect) {
494 struct tgsi_full_src_register src = {{0}};
495
496 src.Register.File = fullinst->Src[i].DimIndirect.File;
497 src.Register.Index = fullinst->Src[i].DimIndirect.Index;
498
499 scan_src_operand(info, fullinst, &src, -1,
500 1 << fullinst->Src[i].DimIndirect.Swizzle,
501 false, NULL);
502 }
503 }
504
505 if (fullinst->Instruction.Texture) {
506 for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
507 struct tgsi_full_src_register src = {{0}};
508
509 src.Register.File = fullinst->TexOffsets[i].File;
510 src.Register.Index = fullinst->TexOffsets[i].Index;
511
512 /* The usage mask is suboptimal but should be safe. */
513 scan_src_operand(info, fullinst, &src, -1,
514 (1 << fullinst->TexOffsets[i].SwizzleX) |
515 (1 << fullinst->TexOffsets[i].SwizzleY) |
516 (1 << fullinst->TexOffsets[i].SwizzleZ),
517 false, &is_mem_inst);
518 }
519 }
520
521 /* check for indirect register writes */
522 for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
523 const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
524
525 if (dst->Register.Indirect) {
526 struct tgsi_full_src_register src = {{0}};
527
528 src.Register.File = dst->Indirect.File;
529 src.Register.Index = dst->Indirect.Index;
530
531 scan_src_operand(info, fullinst, &src, -1,
532 1 << dst->Indirect.Swizzle, false, NULL);
533
534 info->indirect_files |= (1 << dst->Register.File);
535 info->indirect_files_written |= (1 << dst->Register.File);
536 }
537
538 if (dst->Register.Dimension && dst->Dimension.Indirect) {
539 struct tgsi_full_src_register src = {{0}};
540
541 src.Register.File = dst->DimIndirect.File;
542 src.Register.Index = dst->DimIndirect.Index;
543
544 scan_src_operand(info, fullinst, &src, -1,
545 1 << dst->DimIndirect.Swizzle, false, NULL);
546
547 info->dim_indirect_files |= 1u << dst->Register.File;
548 }
549
550 if (is_memory_file(dst->Register.File)) {
551 assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
552
553 is_mem_inst = true;
554 info->writes_memory = TRUE;
555
556 if (dst->Register.File == TGSI_FILE_IMAGE) {
557 if (dst->Register.Indirect)
558 info->images_store = info->images_declared;
559 else
560 info->images_store |= 1 << dst->Register.Index;
561 } else if (dst->Register.File == TGSI_FILE_BUFFER) {
562 if (dst->Register.Indirect)
563 info->shader_buffers_store = info->shader_buffers_declared;
564 else
565 info->shader_buffers_store |= 1 << dst->Register.Index;
566 }
567 }
568 }
569
570 if (is_mem_inst)
571 info->num_memory_instructions++;
572
573 if (computes_derivative(fullinst->Instruction.Opcode))
574 info->uses_derivatives = true;
575
576 info->num_instructions++;
577 }
578
579
580 static void
581 scan_declaration(struct tgsi_shader_info *info,
582 const struct tgsi_full_declaration *fulldecl)
583 {
584 const uint file = fulldecl->Declaration.File;
585 const unsigned procType = info->processor;
586 uint reg;
587
588 if (fulldecl->Declaration.Array) {
589 unsigned array_id = fulldecl->Array.ArrayID;
590
591 switch (file) {
592 case TGSI_FILE_INPUT:
593 assert(array_id < ARRAY_SIZE(info->input_array_first));
594 info->input_array_first[array_id] = fulldecl->Range.First;
595 info->input_array_last[array_id] = fulldecl->Range.Last;
596 break;
597 case TGSI_FILE_OUTPUT:
598 assert(array_id < ARRAY_SIZE(info->output_array_first));
599 info->output_array_first[array_id] = fulldecl->Range.First;
600 info->output_array_last[array_id] = fulldecl->Range.Last;
601 break;
602 }
603 info->array_max[file] = MAX2(info->array_max[file], array_id);
604 }
605
606 for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
607 unsigned semName = fulldecl->Semantic.Name;
608 unsigned semIndex = fulldecl->Semantic.Index +
609 (reg - fulldecl->Range.First);
610 int buffer;
611 unsigned index, target, type;
612
613 /*
614 * only first 32 regs will appear in this bitfield, if larger
615 * bits will wrap around.
616 */
617 info->file_mask[file] |= (1u << (reg & 31));
618 info->file_count[file]++;
619 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
620
621 switch (file) {
622 case TGSI_FILE_CONSTANT:
623 buffer = 0;
624
625 if (fulldecl->Declaration.Dimension)
626 buffer = fulldecl->Dim.Index2D;
627
628 info->const_file_max[buffer] =
629 MAX2(info->const_file_max[buffer], (int)reg);
630 info->const_buffers_declared |= 1u << buffer;
631 break;
632
633 case TGSI_FILE_IMAGE:
634 info->images_declared |= 1u << reg;
635 if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
636 info->images_buffers |= 1 << reg;
637 break;
638
639 case TGSI_FILE_BUFFER:
640 info->shader_buffers_declared |= 1u << reg;
641 break;
642
643 case TGSI_FILE_INPUT:
644 info->input_semantic_name[reg] = (ubyte) semName;
645 info->input_semantic_index[reg] = (ubyte) semIndex;
646 info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
647 info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
648 info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
649
650 /* Vertex shaders can have inputs with holes between them. */
651 info->num_inputs = MAX2(info->num_inputs, reg + 1);
652
653 switch (semName) {
654 case TGSI_SEMANTIC_PRIMID:
655 info->uses_primid = true;
656 break;
657 case TGSI_SEMANTIC_POSITION:
658 info->reads_position = true;
659 break;
660 case TGSI_SEMANTIC_FACE:
661 info->uses_frontface = true;
662 break;
663 }
664 break;
665
666 case TGSI_FILE_SYSTEM_VALUE:
667 index = fulldecl->Range.First;
668
669 info->system_value_semantic_name[index] = semName;
670 info->num_system_values = MAX2(info->num_system_values, index + 1);
671
672 switch (semName) {
673 case TGSI_SEMANTIC_INSTANCEID:
674 info->uses_instanceid = TRUE;
675 break;
676 case TGSI_SEMANTIC_VERTEXID:
677 info->uses_vertexid = TRUE;
678 break;
679 case TGSI_SEMANTIC_VERTEXID_NOBASE:
680 info->uses_vertexid_nobase = TRUE;
681 break;
682 case TGSI_SEMANTIC_BASEVERTEX:
683 info->uses_basevertex = TRUE;
684 break;
685 case TGSI_SEMANTIC_PRIMID:
686 info->uses_primid = TRUE;
687 break;
688 case TGSI_SEMANTIC_INVOCATIONID:
689 info->uses_invocationid = TRUE;
690 break;
691 case TGSI_SEMANTIC_POSITION:
692 info->reads_position = TRUE;
693 break;
694 case TGSI_SEMANTIC_FACE:
695 info->uses_frontface = TRUE;
696 break;
697 case TGSI_SEMANTIC_SAMPLEMASK:
698 info->reads_samplemask = TRUE;
699 break;
700 case TGSI_SEMANTIC_TESSINNER:
701 case TGSI_SEMANTIC_TESSOUTER:
702 info->reads_tess_factors = true;
703 break;
704 }
705 break;
706
707 case TGSI_FILE_OUTPUT:
708 info->output_semantic_name[reg] = (ubyte) semName;
709 info->output_semantic_index[reg] = (ubyte) semIndex;
710 info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
711 info->num_outputs = MAX2(info->num_outputs, reg + 1);
712
713 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
714 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
715 info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
716 }
717 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
718 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
719 info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
720 }
721 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
722 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
723 info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
724 }
725 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
726 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
727 info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
728 }
729
730 switch (semName) {
731 case TGSI_SEMANTIC_PRIMID:
732 info->writes_primid = true;
733 break;
734 case TGSI_SEMANTIC_VIEWPORT_INDEX:
735 info->writes_viewport_index = true;
736 break;
737 case TGSI_SEMANTIC_LAYER:
738 info->writes_layer = true;
739 break;
740 case TGSI_SEMANTIC_PSIZE:
741 info->writes_psize = true;
742 break;
743 case TGSI_SEMANTIC_CLIPVERTEX:
744 info->writes_clipvertex = true;
745 break;
746 case TGSI_SEMANTIC_COLOR:
747 info->colors_written |= 1 << semIndex;
748 break;
749 case TGSI_SEMANTIC_STENCIL:
750 info->writes_stencil = true;
751 break;
752 case TGSI_SEMANTIC_SAMPLEMASK:
753 info->writes_samplemask = true;
754 break;
755 case TGSI_SEMANTIC_EDGEFLAG:
756 info->writes_edgeflag = true;
757 break;
758 case TGSI_SEMANTIC_POSITION:
759 if (procType == PIPE_SHADER_FRAGMENT)
760 info->writes_z = true;
761 else
762 info->writes_position = true;
763 break;
764 }
765 break;
766
767 case TGSI_FILE_SAMPLER:
768 STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
769 info->samplers_declared |= 1u << reg;
770 break;
771
772 case TGSI_FILE_SAMPLER_VIEW:
773 target = fulldecl->SamplerView.Resource;
774 type = fulldecl->SamplerView.ReturnTypeX;
775
776 assert(target < TGSI_TEXTURE_UNKNOWN);
777 if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
778 /* Save sampler target for this sampler index */
779 info->sampler_targets[reg] = target;
780 info->sampler_type[reg] = type;
781 } else {
782 /* if previously declared, make sure targets agree */
783 assert(info->sampler_targets[reg] == target);
784 assert(info->sampler_type[reg] == type);
785 }
786 break;
787 }
788 }
789 }
790
791
792 static void
793 scan_immediate(struct tgsi_shader_info *info)
794 {
795 uint reg = info->immediate_count++;
796 uint file = TGSI_FILE_IMMEDIATE;
797
798 info->file_mask[file] |= (1 << reg);
799 info->file_count[file]++;
800 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
801 }
802
803
804 static void
805 scan_property(struct tgsi_shader_info *info,
806 const struct tgsi_full_property *fullprop)
807 {
808 unsigned name = fullprop->Property.PropertyName;
809 unsigned value = fullprop->u[0].Data;
810
811 assert(name < ARRAY_SIZE(info->properties));
812 info->properties[name] = value;
813
814 switch (name) {
815 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
816 info->num_written_clipdistance = value;
817 info->clipdist_writemask |= (1 << value) - 1;
818 break;
819 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
820 info->num_written_culldistance = value;
821 info->culldist_writemask |= (1 << value) - 1;
822 break;
823 }
824 }
825
826
827 /**
828 * Scan the given TGSI shader to collect information such as number of
829 * registers used, special instructions used, etc.
830 * \return info the result of the scan
831 */
832 void
833 tgsi_scan_shader(const struct tgsi_token *tokens,
834 struct tgsi_shader_info *info)
835 {
836 uint procType, i;
837 struct tgsi_parse_context parse;
838 unsigned current_depth = 0;
839
840 memset(info, 0, sizeof(*info));
841 for (i = 0; i < TGSI_FILE_COUNT; i++)
842 info->file_max[i] = -1;
843 for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
844 info->const_file_max[i] = -1;
845 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
846 for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
847 info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
848
849 /**
850 ** Setup to begin parsing input shader
851 **/
852 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
853 debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
854 return;
855 }
856 procType = parse.FullHeader.Processor.Processor;
857 assert(procType == PIPE_SHADER_FRAGMENT ||
858 procType == PIPE_SHADER_VERTEX ||
859 procType == PIPE_SHADER_GEOMETRY ||
860 procType == PIPE_SHADER_TESS_CTRL ||
861 procType == PIPE_SHADER_TESS_EVAL ||
862 procType == PIPE_SHADER_COMPUTE);
863 info->processor = procType;
864 info->num_tokens = tgsi_num_tokens(parse.Tokens);
865
866 /**
867 ** Loop over incoming program tokens/instructions
868 */
869 while (!tgsi_parse_end_of_tokens(&parse)) {
870 tgsi_parse_token( &parse );
871
872 switch( parse.FullToken.Token.Type ) {
873 case TGSI_TOKEN_TYPE_INSTRUCTION:
874 scan_instruction(info, &parse.FullToken.FullInstruction,
875 &current_depth);
876 break;
877 case TGSI_TOKEN_TYPE_DECLARATION:
878 scan_declaration(info, &parse.FullToken.FullDeclaration);
879 break;
880 case TGSI_TOKEN_TYPE_IMMEDIATE:
881 scan_immediate(info);
882 break;
883 case TGSI_TOKEN_TYPE_PROPERTY:
884 scan_property(info, &parse.FullToken.FullProperty);
885 break;
886 default:
887 assert(!"Unexpected TGSI token type");
888 }
889 }
890
891 info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
892 info->opcode_count[TGSI_OPCODE_KILL]);
893
894 /* The dimensions of the IN decleration in geometry shader have
895 * to be deduced from the type of the input primitive.
896 */
897 if (procType == PIPE_SHADER_GEOMETRY) {
898 unsigned input_primitive =
899 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
900 int num_verts = u_vertices_per_prim(input_primitive);
901 int j;
902 info->file_count[TGSI_FILE_INPUT] = num_verts;
903 info->file_max[TGSI_FILE_INPUT] =
904 MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
905 for (j = 0; j < num_verts; ++j) {
906 info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
907 }
908 }
909
910 tgsi_parse_free(&parse);
911 }
912
913 /**
914 * Collect information about the arrays of a given register file.
915 *
916 * @param tokens TGSI shader
917 * @param file the register file to scan through
918 * @param max_array_id number of entries in @p arrays; should be equal to the
919 * highest array id, i.e. tgsi_shader_info::array_max[file].
920 * @param arrays info for array of each ID will be written to arrays[ID - 1].
921 */
922 void
923 tgsi_scan_arrays(const struct tgsi_token *tokens,
924 unsigned file,
925 unsigned max_array_id,
926 struct tgsi_array_info *arrays)
927 {
928 struct tgsi_parse_context parse;
929
930 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
931 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
932 return;
933 }
934
935 memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
936
937 while (!tgsi_parse_end_of_tokens(&parse)) {
938 struct tgsi_full_instruction *inst;
939
940 tgsi_parse_token(&parse);
941
942 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
943 struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
944
945 if (decl->Declaration.Array && decl->Declaration.File == file &&
946 decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
947 struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
948 assert(!array->declared);
949 array->declared = true;
950 array->range = decl->Range;
951 }
952 }
953
954 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
955 continue;
956
957 inst = &parse.FullToken.FullInstruction;
958 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
959 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
960 if (dst->Register.File != file)
961 continue;
962
963 if (dst->Register.Indirect) {
964 if (dst->Indirect.ArrayID > 0 &&
965 dst->Indirect.ArrayID <= max_array_id) {
966 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
967 } else {
968 /* Indirect writes without an ArrayID can write anywhere. */
969 for (unsigned j = 0; j < max_array_id; ++j)
970 arrays[j].writemask |= dst->Register.WriteMask;
971 }
972 } else {
973 /* Check whether the write falls into any of the arrays anyway. */
974 for (unsigned j = 0; j < max_array_id; ++j) {
975 struct tgsi_array_info *array = &arrays[j];
976 if (array->declared &&
977 dst->Register.Index >= array->range.First &&
978 dst->Register.Index <= array->range.Last)
979 array->writemask |= dst->Register.WriteMask;
980 }
981 }
982 }
983 }
984
985 tgsi_parse_free(&parse);
986
987 return;
988 }
989
990 static void
991 check_no_subroutines(const struct tgsi_full_instruction *inst)
992 {
993 switch (inst->Instruction.Opcode) {
994 case TGSI_OPCODE_BGNSUB:
995 case TGSI_OPCODE_ENDSUB:
996 case TGSI_OPCODE_CAL:
997 unreachable("subroutines unhandled");
998 }
999 }
1000
1001 static unsigned
1002 get_inst_tessfactor_writemask(const struct tgsi_shader_info *info,
1003 const struct tgsi_full_instruction *inst)
1004 {
1005 unsigned writemask = 0;
1006
1007 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
1008 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
1009
1010 if (dst->Register.File == TGSI_FILE_OUTPUT &&
1011 !dst->Register.Indirect) {
1012 unsigned name = info->output_semantic_name[dst->Register.Index];
1013
1014 if (name == TGSI_SEMANTIC_TESSINNER)
1015 writemask |= dst->Register.WriteMask;
1016 else if (name == TGSI_SEMANTIC_TESSOUTER)
1017 writemask |= dst->Register.WriteMask << 4;
1018 }
1019 }
1020 return writemask;
1021 }
1022
1023 static unsigned
1024 get_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1025 struct tgsi_parse_context *parse,
1026 unsigned end_opcode)
1027 {
1028 struct tgsi_full_instruction *inst;
1029 unsigned writemask = 0;
1030
1031 do {
1032 tgsi_parse_token(parse);
1033 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1034 inst = &parse->FullToken.FullInstruction;
1035 check_no_subroutines(inst);
1036
1037 /* Recursively process nested blocks. */
1038 switch (inst->Instruction.Opcode) {
1039 case TGSI_OPCODE_IF:
1040 case TGSI_OPCODE_UIF:
1041 writemask |=
1042 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDIF);
1043 continue;
1044
1045 case TGSI_OPCODE_BGNLOOP:
1046 writemask |=
1047 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1048 continue;
1049
1050 case TGSI_OPCODE_BARRIER:
1051 unreachable("nested BARRIER is illegal");
1052 continue;
1053 }
1054
1055 writemask |= get_inst_tessfactor_writemask(info, inst);
1056 } while (inst->Instruction.Opcode != end_opcode);
1057
1058 return writemask;
1059 }
1060
1061 static void
1062 get_if_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1063 struct tgsi_parse_context *parse,
1064 unsigned *upper_block_tf_writemask,
1065 unsigned *cond_block_tf_writemask)
1066 {
1067 struct tgsi_full_instruction *inst;
1068 unsigned then_tessfactor_writemask = 0;
1069 unsigned else_tessfactor_writemask = 0;
1070 bool is_then = true;
1071
1072 do {
1073 tgsi_parse_token(parse);
1074 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1075 inst = &parse->FullToken.FullInstruction;
1076 check_no_subroutines(inst);
1077
1078 switch (inst->Instruction.Opcode) {
1079 case TGSI_OPCODE_ELSE:
1080 is_then = false;
1081 continue;
1082
1083 /* Recursively process nested blocks. */
1084 case TGSI_OPCODE_IF:
1085 case TGSI_OPCODE_UIF:
1086 get_if_block_tessfactor_writemask(info, parse,
1087 is_then ? &then_tessfactor_writemask :
1088 &else_tessfactor_writemask,
1089 cond_block_tf_writemask);
1090 continue;
1091
1092 case TGSI_OPCODE_BGNLOOP:
1093 *cond_block_tf_writemask |=
1094 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1095 continue;
1096
1097 case TGSI_OPCODE_BARRIER:
1098 unreachable("nested BARRIER is illegal");
1099 continue;
1100 }
1101
1102 /* Process an instruction in the current block. */
1103 unsigned writemask = get_inst_tessfactor_writemask(info, inst);
1104
1105 if (writemask) {
1106 if (is_then)
1107 then_tessfactor_writemask |= writemask;
1108 else
1109 else_tessfactor_writemask |= writemask;
1110 }
1111 } while (inst->Instruction.Opcode != TGSI_OPCODE_ENDIF);
1112
1113 if (then_tessfactor_writemask || else_tessfactor_writemask) {
1114 /* If both statements write the same tess factor channels,
1115 * we can say that the upper block writes them too. */
1116 *upper_block_tf_writemask |= then_tessfactor_writemask &
1117 else_tessfactor_writemask;
1118 *cond_block_tf_writemask |= then_tessfactor_writemask |
1119 else_tessfactor_writemask;
1120 }
1121 }
1122
1123 void
1124 tgsi_scan_tess_ctrl(const struct tgsi_token *tokens,
1125 const struct tgsi_shader_info *info,
1126 struct tgsi_tessctrl_info *out)
1127 {
1128 memset(out, 0, sizeof(*out));
1129
1130 if (info->processor != PIPE_SHADER_TESS_CTRL)
1131 return;
1132
1133 struct tgsi_parse_context parse;
1134 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
1135 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
1136 return;
1137 }
1138
1139 /* The pass works as follows:
1140 * If all codepaths write tess factors, we can say that all invocations
1141 * define tess factors.
1142 *
1143 * Each tess factor channel is tracked separately.
1144 */
1145 unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
1146 unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
1147
1148 /* Initial value = true. Here the pass will accumulate results from multiple
1149 * segments surrounded by barriers. If tess factors aren't written at all,
1150 * it's a shader bug and we don't care if this will be true.
1151 */
1152 out->tessfactors_are_def_in_all_invocs = true;
1153
1154 while (!tgsi_parse_end_of_tokens(&parse)) {
1155 tgsi_parse_token(&parse);
1156
1157 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
1158 continue;
1159
1160 struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1161 check_no_subroutines(inst);
1162
1163 /* Process nested blocks. */
1164 switch (inst->Instruction.Opcode) {
1165 case TGSI_OPCODE_IF:
1166 case TGSI_OPCODE_UIF:
1167 get_if_block_tessfactor_writemask(info, &parse,
1168 &main_block_tf_writemask,
1169 &cond_block_tf_writemask);
1170 continue;
1171
1172 case TGSI_OPCODE_BGNLOOP:
1173 cond_block_tf_writemask |=
1174 get_block_tessfactor_writemask(info, &parse, TGSI_OPCODE_ENDIF);
1175 continue;
1176
1177 case TGSI_OPCODE_BARRIER:
1178 /* The following case must be prevented:
1179 * gl_TessLevelInner = ...;
1180 * barrier();
1181 * if (gl_InvocationID == 1)
1182 * gl_TessLevelInner = ...;
1183 *
1184 * If you consider disjoint code segments separated by barriers, each
1185 * such segment that writes tess factor channels should write the same
1186 * channels in all codepaths within that segment.
1187 */
1188 if (main_block_tf_writemask || cond_block_tf_writemask) {
1189 /* Accumulate the result: */
1190 out->tessfactors_are_def_in_all_invocs &=
1191 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1192
1193 /* Analyze the next code segment from scratch. */
1194 main_block_tf_writemask = 0;
1195 cond_block_tf_writemask = 0;
1196 }
1197 continue;
1198 }
1199
1200 main_block_tf_writemask |= get_inst_tessfactor_writemask(info, inst);
1201 }
1202
1203 /* Accumulate the result for the last code segment separated by a barrier. */
1204 if (main_block_tf_writemask || cond_block_tf_writemask) {
1205 out->tessfactors_are_def_in_all_invocs &=
1206 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1207 }
1208
1209 tgsi_parse_free(&parse);
1210 }