src/gallium/auxiliary/tgsi/tgsi_scan.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 VMware, Inc.
   4  * All Rights Reserved.
   5  * Copyright 2008 VMware, Inc.  All rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  **************************************************************************/
  28
  29 /**
  30  * TGSI program scan utility.
  31  * Used to determine which registers and instructions are used by a shader.
  32  *
  33  * Authors:  Brian Paul
  34  */
  35
  36
  37 #include "util/u_debug.h"
  38 #include "util/u_math.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_prim.h"
  41 #include "tgsi/tgsi_info.h"
  42 #include "tgsi/tgsi_parse.h"
  43 #include "tgsi/tgsi_util.h"
  44 #include "tgsi/tgsi_scan.h"
  45
  46
  47 static bool
  48 is_memory_file(unsigned file)
  49 {
  50    return file == TGSI_FILE_SAMPLER ||
  51           file == TGSI_FILE_SAMPLER_VIEW ||
  52           file == TGSI_FILE_IMAGE ||
  53           file == TGSI_FILE_BUFFER;
  54 }
  55
  56
  57 static bool
  58 is_mem_query_inst(enum tgsi_opcode opcode)
  59 {
  60    return opcode == TGSI_OPCODE_RESQ ||
  61           opcode == TGSI_OPCODE_TXQ ||
  62           opcode == TGSI_OPCODE_TXQS ||
  63           opcode == TGSI_OPCODE_LODQ;
  64 }
  65
  66 /**
  67  * Is the opcode a "true" texture instruction which samples from a
  68  * texture map?
  69  */
  70 static bool
  71 is_texture_inst(enum tgsi_opcode opcode)
  72 {
  73    return (!is_mem_query_inst(opcode) &&
  74            tgsi_get_opcode_info(opcode)->is_tex);
  75 }
  76
  77
  78 /**
  79  * Is the opcode an instruction which computes a derivative explicitly or
  80  * implicitly?
  81  */
  82 static bool
  83 computes_derivative(enum tgsi_opcode opcode)
  84 {
  85    if (tgsi_get_opcode_info(opcode)->is_tex) {
  86       return opcode != TGSI_OPCODE_TG4 &&
  87              opcode != TGSI_OPCODE_TXD &&
  88              opcode != TGSI_OPCODE_TXF &&
  89              opcode != TGSI_OPCODE_TXF_LZ &&
  90              opcode != TGSI_OPCODE_TEX_LZ &&
  91              opcode != TGSI_OPCODE_TXL &&
  92              opcode != TGSI_OPCODE_TXL2 &&
  93              opcode != TGSI_OPCODE_TXQ &&
  94              opcode != TGSI_OPCODE_TXQS;
  95    }
  96
  97    return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
  98           opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
  99           opcode == TGSI_OPCODE_SAMPLE ||
 100           opcode == TGSI_OPCODE_SAMPLE_B ||
 101           opcode == TGSI_OPCODE_SAMPLE_C;
 102 }
 103
 104
 105 static void
 106 scan_src_operand(struct tgsi_shader_info *info,
 107                  const struct tgsi_full_instruction *fullinst,
 108                  const struct tgsi_full_src_register *src,
 109                  unsigned src_index,
 110                  unsigned usage_mask_after_swizzle,
 111                  bool is_interp_instruction,
 112                  bool *is_mem_inst)
 113 {
 114    int ind = src->Register.Index;
 115
 116    if (info->processor == PIPE_SHADER_COMPUTE &&
 117        src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
 118       unsigned name, mask;
 119
 120       name = info->system_value_semantic_name[src->Register.Index];
 121
 122       switch (name) {
 123       case TGSI_SEMANTIC_THREAD_ID:
 124       case TGSI_SEMANTIC_BLOCK_ID:
 125          mask = usage_mask_after_swizzle & TGSI_WRITEMASK_XYZ;
 126          while (mask) {
 127             unsigned i = u_bit_scan(&mask);
 128
 129             if (name == TGSI_SEMANTIC_THREAD_ID)
 130                info->uses_thread_id[i] = true;
 131             else
 132                info->uses_block_id[i] = true;
 133          }
 134          break;
 135       case TGSI_SEMANTIC_BLOCK_SIZE:
 136          /* The block size is translated to IMM with a fixed block size. */
 137          if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
 138             info->uses_block_size = true;
 139          break;
 140       case TGSI_SEMANTIC_GRID_SIZE:
 141          info->uses_grid_size = true;
 142          break;
 143       }
 144    }
 145
 146    /* Mark which inputs are effectively used */
 147    if (src->Register.File == TGSI_FILE_INPUT) {
 148       if (src->Register.Indirect) {
 149          for (ind = 0; ind < info->num_inputs; ++ind) {
 150             info->input_usage_mask[ind] |= usage_mask_after_swizzle;
 151          }
 152       } else {
 153          assert(ind >= 0);
 154          assert(ind < PIPE_MAX_SHADER_INPUTS);
 155          info->input_usage_mask[ind] |= usage_mask_after_swizzle;
 156       }
 157
 158       if (info->processor == PIPE_SHADER_FRAGMENT) {
 159          unsigned name, index, input;
 160
 161          if (src->Register.Indirect && src->Indirect.ArrayID)
 162             input = info->input_array_first[src->Indirect.ArrayID];
 163          else
 164             input = src->Register.Index;
 165
 166          name = info->input_semantic_name[input];
 167          index = info->input_semantic_index[input];
 168
 169          if (name == TGSI_SEMANTIC_POSITION &&
 170              usage_mask_after_swizzle & TGSI_WRITEMASK_Z)
 171             info->reads_z = true;
 172
 173          if (name == TGSI_SEMANTIC_COLOR)
 174             info->colors_read |= usage_mask_after_swizzle << (index * 4);
 175
 176          /* Process only interpolated varyings. Don't include POSITION.
 177           * Don't include integer varyings, because they are not
 178           * interpolated. Don't process inputs interpolated by INTERP
 179           * opcodes. Those are tracked separately.
 180           */
 181          if ((!is_interp_instruction || src_index != 0) &&
 182              (name == TGSI_SEMANTIC_GENERIC ||
 183               name == TGSI_SEMANTIC_TEXCOORD ||
 184               name == TGSI_SEMANTIC_COLOR ||
 185               name == TGSI_SEMANTIC_BCOLOR ||
 186               name == TGSI_SEMANTIC_FOG ||
 187               name == TGSI_SEMANTIC_CLIPDIST)) {
 188             switch (info->input_interpolate[input]) {
 189             case TGSI_INTERPOLATE_COLOR:
 190             case TGSI_INTERPOLATE_PERSPECTIVE:
 191                switch (info->input_interpolate_loc[input]) {
 192                case TGSI_INTERPOLATE_LOC_CENTER:
 193                   info->uses_persp_center = TRUE;
 194                   break;
 195                case TGSI_INTERPOLATE_LOC_CENTROID:
 196                   info->uses_persp_centroid = TRUE;
 197                   break;
 198                case TGSI_INTERPOLATE_LOC_SAMPLE:
 199                   info->uses_persp_sample = TRUE;
 200                   break;
 201                }
 202                break;
 203             case TGSI_INTERPOLATE_LINEAR:
 204                switch (info->input_interpolate_loc[input]) {
 205                case TGSI_INTERPOLATE_LOC_CENTER:
 206                   info->uses_linear_center = TRUE;
 207                   break;
 208                case TGSI_INTERPOLATE_LOC_CENTROID:
 209                   info->uses_linear_centroid = TRUE;
 210                   break;
 211                case TGSI_INTERPOLATE_LOC_SAMPLE:
 212                   info->uses_linear_sample = TRUE;
 213                   break;
 214                }
 215                break;
 216                /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
 217             }
 218          }
 219       }
 220    }
 221
 222    if (info->processor == PIPE_SHADER_TESS_CTRL &&
 223        src->Register.File == TGSI_FILE_OUTPUT) {
 224       unsigned input;
 225
 226       if (src->Register.Indirect && src->Indirect.ArrayID)
 227          input = info->output_array_first[src->Indirect.ArrayID];
 228       else
 229          input = src->Register.Index;
 230
 231       switch (info->output_semantic_name[input]) {
 232       case TGSI_SEMANTIC_PATCH:
 233          info->reads_perpatch_outputs = true;
 234          break;
 235       case TGSI_SEMANTIC_TESSINNER:
 236       case TGSI_SEMANTIC_TESSOUTER:
 237          info->reads_tessfactor_outputs = true;
 238          break;
 239       default:
 240          info->reads_pervertex_outputs = true;
 241       }
 242    }
 243
 244    /* check for indirect register reads */
 245    if (src->Register.Indirect) {
 246       info->indirect_files |= (1 << src->Register.File);
 247       info->indirect_files_read |= (1 << src->Register.File);
 248
 249       /* record indirect constant buffer indexing */
 250       if (src->Register.File == TGSI_FILE_CONSTANT) {
 251          if (src->Register.Dimension) {
 252             if (src->Dimension.Indirect)
 253                info->const_buffers_indirect = info->const_buffers_declared;
 254             else
 255                info->const_buffers_indirect |= 1u << src->Dimension.Index;
 256          } else {
 257             info->const_buffers_indirect |= 1;
 258          }
 259       }
 260    }
 261
 262    if (src->Register.Dimension && src->Dimension.Indirect)
 263       info->dim_indirect_files |= 1u << src->Register.File;
 264
 265    /* Texture samplers */
 266    if (src->Register.File == TGSI_FILE_SAMPLER) {
 267       const unsigned index = src->Register.Index;
 268
 269       assert(fullinst->Instruction.Texture);
 270       assert(index < PIPE_MAX_SAMPLERS);
 271
 272       if (is_texture_inst(fullinst->Instruction.Opcode)) {
 273          const unsigned target = fullinst->Texture.Texture;
 274          assert(target < TGSI_TEXTURE_UNKNOWN);
 275          /* for texture instructions, check that the texture instruction
 276           * target matches the previous sampler view declaration (if there
 277           * was one.)
 278           */
 279          if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
 280             /* probably no sampler view declaration */
 281             info->sampler_targets[index] = target;
 282          } else {
 283             /* Make sure the texture instruction's sampler/target info
 284              * agrees with the sampler view declaration.
 285              */
 286             assert(info->sampler_targets[index] == target);
 287          }
 288       }
 289    }
 290
 291    if (is_memory_file(src->Register.File) &&
 292        !is_mem_query_inst(fullinst->Instruction.Opcode)) {
 293       *is_mem_inst = true;
 294
 295       if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
 296          info->writes_memory = TRUE;
 297
 298          if (src->Register.File == TGSI_FILE_IMAGE) {
 299             if (src->Register.Indirect)
 300                info->images_atomic = info->images_declared;
 301             else
 302                info->images_atomic |= 1 << src->Register.Index;
 303          } else if (src->Register.File == TGSI_FILE_BUFFER) {
 304             if (src->Register.Indirect)
 305                info->shader_buffers_atomic = info->shader_buffers_declared;
 306             else
 307                info->shader_buffers_atomic |= 1 << src->Register.Index;
 308          }
 309       } else {
 310          if (src->Register.File == TGSI_FILE_IMAGE) {
 311             if (src->Register.Indirect)
 312                info->images_load = info->images_declared;
 313             else
 314                info->images_load |= 1 << src->Register.Index;
 315          } else if (src->Register.File == TGSI_FILE_BUFFER) {
 316             if (src->Register.Indirect)
 317                info->shader_buffers_load = info->shader_buffers_declared;
 318             else
 319                info->shader_buffers_load |= 1 << src->Register.Index;
 320          }
 321       }
 322    }
 323 }
 324
 325
 326 static void
 327 scan_instruction(struct tgsi_shader_info *info,
 328                  const struct tgsi_full_instruction *fullinst,
 329                  unsigned *current_depth)
 330 {
 331    unsigned i;
 332    bool is_mem_inst = false;
 333    bool is_interp_instruction = false;
 334    unsigned sampler_src;
 335
 336    assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
 337    info->opcode_count[fullinst->Instruction.Opcode]++;
 338
 339    switch (fullinst->Instruction.Opcode) {
 340    case TGSI_OPCODE_IF:
 341    case TGSI_OPCODE_UIF:
 342    case TGSI_OPCODE_BGNLOOP:
 343       (*current_depth)++;
 344       info->max_depth = MAX2(info->max_depth, *current_depth);
 345       break;
 346    case TGSI_OPCODE_ENDIF:
 347    case TGSI_OPCODE_ENDLOOP:
 348       (*current_depth)--;
 349       break;
 350    case TGSI_OPCODE_TEX:
 351    case TGSI_OPCODE_TEX_LZ:
 352    case TGSI_OPCODE_TXB:
 353    case TGSI_OPCODE_TXD:
 354    case TGSI_OPCODE_TXL:
 355    case TGSI_OPCODE_TXP:
 356    case TGSI_OPCODE_TXQ:
 357    case TGSI_OPCODE_TXQS:
 358    case TGSI_OPCODE_TXF:
 359    case TGSI_OPCODE_TXF_LZ:
 360    case TGSI_OPCODE_TEX2:
 361    case TGSI_OPCODE_TXB2:
 362    case TGSI_OPCODE_TXL2:
 363    case TGSI_OPCODE_TG4:
 364    case TGSI_OPCODE_LODQ:
 365       sampler_src = fullinst->Instruction.NumSrcRegs - 1;
 366       if (fullinst->Src[sampler_src].Register.File != TGSI_FILE_SAMPLER)
 367          info->uses_bindless_samplers = true;
 368       break;
 369    case TGSI_OPCODE_RESQ:
 370    case TGSI_OPCODE_LOAD:
 371    case TGSI_OPCODE_ATOMUADD:
 372    case TGSI_OPCODE_ATOMXCHG:
 373    case TGSI_OPCODE_ATOMCAS:
 374    case TGSI_OPCODE_ATOMAND:
 375    case TGSI_OPCODE_ATOMOR:
 376    case TGSI_OPCODE_ATOMXOR:
 377    case TGSI_OPCODE_ATOMUMIN:
 378    case TGSI_OPCODE_ATOMUMAX:
 379    case TGSI_OPCODE_ATOMIMIN:
 380    case TGSI_OPCODE_ATOMIMAX:
 381       if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File))
 382          info->uses_bindless_images = true;
 383       break;
 384    case TGSI_OPCODE_STORE:
 385       if (tgsi_is_bindless_image_file(fullinst->Dst[0].Register.File))
 386          info->uses_bindless_images = true;
 387       break;
 388    default:
 389       break;
 390    }
 391
 392    if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
 393        fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
 394        fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
 395       const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
 396       unsigned input;
 397
 398       is_interp_instruction = true;
 399
 400       if (src0->Register.Indirect && src0->Indirect.ArrayID)
 401          input = info->input_array_first[src0->Indirect.ArrayID];
 402       else
 403          input = src0->Register.Index;
 404
 405       /* For the INTERP opcodes, the interpolation is always
 406        * PERSPECTIVE unless LINEAR is specified.
 407        */
 408       switch (info->input_interpolate[input]) {
 409       case TGSI_INTERPOLATE_COLOR:
 410       case TGSI_INTERPOLATE_CONSTANT:
 411       case TGSI_INTERPOLATE_PERSPECTIVE:
 412          switch (fullinst->Instruction.Opcode) {
 413          case TGSI_OPCODE_INTERP_CENTROID:
 414             info->uses_persp_opcode_interp_centroid = TRUE;
 415             break;
 416          case TGSI_OPCODE_INTERP_OFFSET:
 417             info->uses_persp_opcode_interp_offset = TRUE;
 418             break;
 419          case TGSI_OPCODE_INTERP_SAMPLE:
 420             info->uses_persp_opcode_interp_sample = TRUE;
 421             break;
 422          }
 423          break;
 424
 425       case TGSI_INTERPOLATE_LINEAR:
 426          switch (fullinst->Instruction.Opcode) {
 427          case TGSI_OPCODE_INTERP_CENTROID:
 428             info->uses_linear_opcode_interp_centroid = TRUE;
 429             break;
 430          case TGSI_OPCODE_INTERP_OFFSET:
 431             info->uses_linear_opcode_interp_offset = TRUE;
 432             break;
 433          case TGSI_OPCODE_INTERP_SAMPLE:
 434             info->uses_linear_opcode_interp_sample = TRUE;
 435             break;
 436          }
 437          break;
 438       }
 439    }
 440
 441    if ((fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
 442         fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG) ||
 443        fullinst->Instruction.Opcode == TGSI_OPCODE_DFMA ||
 444        fullinst->Instruction.Opcode == TGSI_OPCODE_DDIV ||
 445        fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
 446        fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
 447        fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
 448        fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
 449       info->uses_doubles = TRUE;
 450
 451    for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
 452       scan_src_operand(info, fullinst, &fullinst->Src[i], i,
 453                        tgsi_util_get_inst_usage_mask(fullinst, i),
 454                        is_interp_instruction, &is_mem_inst);
 455
 456       if (fullinst->Src[i].Register.Indirect) {
 457          struct tgsi_full_src_register src = {{0}};
 458
 459          src.Register.File = fullinst->Src[i].Indirect.File;
 460          src.Register.Index = fullinst->Src[i].Indirect.Index;
 461
 462          scan_src_operand(info, fullinst, &src, -1,
 463                           1 << fullinst->Src[i].Indirect.Swizzle,
 464                           false, NULL);
 465       }
 466
 467       if (fullinst->Src[i].Register.Dimension &&
 468           fullinst->Src[i].Dimension.Indirect) {
 469          struct tgsi_full_src_register src = {{0}};
 470
 471          src.Register.File = fullinst->Src[i].DimIndirect.File;
 472          src.Register.Index = fullinst->Src[i].DimIndirect.Index;
 473
 474          scan_src_operand(info, fullinst, &src, -1,
 475                           1 << fullinst->Src[i].DimIndirect.Swizzle,
 476                           false, NULL);
 477       }
 478    }
 479
 480    if (fullinst->Instruction.Texture) {
 481       for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
 482          struct tgsi_full_src_register src = {{0}};
 483
 484          src.Register.File = fullinst->TexOffsets[i].File;
 485          src.Register.Index = fullinst->TexOffsets[i].Index;
 486
 487          /* The usage mask is suboptimal but should be safe. */
 488          scan_src_operand(info, fullinst, &src, -1,
 489                           (1 << fullinst->TexOffsets[i].SwizzleX) |
 490                           (1 << fullinst->TexOffsets[i].SwizzleY) |
 491                           (1 << fullinst->TexOffsets[i].SwizzleZ),
 492                           false, &is_mem_inst);
 493       }
 494    }
 495
 496    /* check for indirect register writes */
 497    for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
 498       const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
 499
 500       if (dst->Register.Indirect) {
 501          struct tgsi_full_src_register src = {{0}};
 502
 503          src.Register.File = dst->Indirect.File;
 504          src.Register.Index = dst->Indirect.Index;
 505
 506          scan_src_operand(info, fullinst, &src, -1,
 507                           1 << dst->Indirect.Swizzle, false, NULL);
 508
 509          info->indirect_files |= (1 << dst->Register.File);
 510          info->indirect_files_written |= (1 << dst->Register.File);
 511       }
 512
 513       if (dst->Register.Dimension && dst->Dimension.Indirect) {
 514          struct tgsi_full_src_register src = {{0}};
 515
 516          src.Register.File = dst->DimIndirect.File;
 517          src.Register.Index = dst->DimIndirect.Index;
 518
 519          scan_src_operand(info, fullinst, &src, -1,
 520                           1 << dst->DimIndirect.Swizzle, false, NULL);
 521
 522          info->dim_indirect_files |= 1u << dst->Register.File;
 523       }
 524
 525       if (is_memory_file(dst->Register.File)) {
 526          assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
 527
 528          is_mem_inst = true;
 529          info->writes_memory = TRUE;
 530
 531          if (dst->Register.File == TGSI_FILE_IMAGE) {
 532             if (dst->Register.Indirect)
 533                info->images_store = info->images_declared;
 534             else
 535                info->images_store |= 1 << dst->Register.Index;
 536          } else if (dst->Register.File == TGSI_FILE_BUFFER) {
 537             if (dst->Register.Indirect)
 538                info->shader_buffers_store = info->shader_buffers_declared;
 539             else
 540                info->shader_buffers_store |= 1 << dst->Register.Index;
 541          }
 542       }
 543    }
 544
 545    if (is_mem_inst)
 546       info->num_memory_instructions++;
 547
 548    if (computes_derivative(fullinst->Instruction.Opcode))
 549       info->uses_derivatives = true;
 550
 551    info->num_instructions++;
 552 }
 553
 554
 555 static void
 556 scan_declaration(struct tgsi_shader_info *info,
 557                  const struct tgsi_full_declaration *fulldecl)
 558 {
 559    const uint file = fulldecl->Declaration.File;
 560    const unsigned procType = info->processor;
 561    uint reg;
 562
 563    if (fulldecl->Declaration.Array) {
 564       unsigned array_id = fulldecl->Array.ArrayID;
 565
 566       switch (file) {
 567       case TGSI_FILE_INPUT:
 568          assert(array_id < ARRAY_SIZE(info->input_array_first));
 569          info->input_array_first[array_id] = fulldecl->Range.First;
 570          info->input_array_last[array_id] = fulldecl->Range.Last;
 571          break;
 572       case TGSI_FILE_OUTPUT:
 573          assert(array_id < ARRAY_SIZE(info->output_array_first));
 574          info->output_array_first[array_id] = fulldecl->Range.First;
 575          info->output_array_last[array_id] = fulldecl->Range.Last;
 576          break;
 577       }
 578       info->array_max[file] = MAX2(info->array_max[file], array_id);
 579    }
 580
 581    for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
 582       unsigned semName = fulldecl->Semantic.Name;
 583       unsigned semIndex = fulldecl->Semantic.Index +
 584          (reg - fulldecl->Range.First);
 585       int buffer;
 586       unsigned index, target, type;
 587
 588       /*
 589        * only first 32 regs will appear in this bitfield, if larger
 590        * bits will wrap around.
 591        */
 592       info->file_mask[file] |= (1u << (reg & 31));
 593       info->file_count[file]++;
 594       info->file_max[file] = MAX2(info->file_max[file], (int)reg);
 595
 596       switch (file) {
 597       case TGSI_FILE_CONSTANT:
 598          buffer = 0;
 599
 600          if (fulldecl->Declaration.Dimension)
 601             buffer = fulldecl->Dim.Index2D;
 602
 603          info->const_file_max[buffer] =
 604             MAX2(info->const_file_max[buffer], (int)reg);
 605          info->const_buffers_declared |= 1u << buffer;
 606          break;
 607
 608       case TGSI_FILE_IMAGE:
 609          info->images_declared |= 1u << reg;
 610          if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
 611             info->images_buffers |= 1 << reg;
 612          break;
 613
 614       case TGSI_FILE_BUFFER:
 615          info->shader_buffers_declared |= 1u << reg;
 616          break;
 617
 618       case TGSI_FILE_INPUT:
 619          info->input_semantic_name[reg] = (ubyte) semName;
 620          info->input_semantic_index[reg] = (ubyte) semIndex;
 621          info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
 622          info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
 623          info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
 624
 625          /* Vertex shaders can have inputs with holes between them. */
 626          info->num_inputs = MAX2(info->num_inputs, reg + 1);
 627
 628          switch (semName) {
 629          case TGSI_SEMANTIC_PRIMID:
 630             info->uses_primid = true;
 631             break;
 632          case TGSI_SEMANTIC_POSITION:
 633             info->reads_position = true;
 634             break;
 635          case TGSI_SEMANTIC_FACE:
 636             info->uses_frontface = true;
 637             break;
 638          }
 639          break;
 640
 641       case TGSI_FILE_SYSTEM_VALUE:
 642          index = fulldecl->Range.First;
 643
 644          info->system_value_semantic_name[index] = semName;
 645          info->num_system_values = MAX2(info->num_system_values, index + 1);
 646
 647          switch (semName) {
 648          case TGSI_SEMANTIC_INSTANCEID:
 649             info->uses_instanceid = TRUE;
 650             break;
 651          case TGSI_SEMANTIC_VERTEXID:
 652             info->uses_vertexid = TRUE;
 653             break;
 654          case TGSI_SEMANTIC_VERTEXID_NOBASE:
 655             info->uses_vertexid_nobase = TRUE;
 656             break;
 657          case TGSI_SEMANTIC_BASEVERTEX:
 658             info->uses_basevertex = TRUE;
 659             break;
 660          case TGSI_SEMANTIC_PRIMID:
 661             info->uses_primid = TRUE;
 662             break;
 663          case TGSI_SEMANTIC_INVOCATIONID:
 664             info->uses_invocationid = TRUE;
 665             break;
 666          case TGSI_SEMANTIC_POSITION:
 667             info->reads_position = TRUE;
 668             break;
 669          case TGSI_SEMANTIC_FACE:
 670             info->uses_frontface = TRUE;
 671             break;
 672          case TGSI_SEMANTIC_SAMPLEMASK:
 673             info->reads_samplemask = TRUE;
 674             break;
 675          case TGSI_SEMANTIC_TESSINNER:
 676          case TGSI_SEMANTIC_TESSOUTER:
 677             info->reads_tess_factors = true;
 678             break;
 679          }
 680          break;
 681
 682       case TGSI_FILE_OUTPUT:
 683          info->output_semantic_name[reg] = (ubyte) semName;
 684          info->output_semantic_index[reg] = (ubyte) semIndex;
 685          info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
 686          info->num_outputs = MAX2(info->num_outputs, reg + 1);
 687
 688          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
 689             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
 690             info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
 691          }
 692          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
 693             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
 694             info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
 695          }
 696          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
 697             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
 698             info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
 699          }
 700          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
 701             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
 702             info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
 703          }
 704
 705          switch (semName) {
 706          case TGSI_SEMANTIC_PRIMID:
 707             info->writes_primid = true;
 708             break;
 709          case TGSI_SEMANTIC_VIEWPORT_INDEX:
 710             info->writes_viewport_index = true;
 711             break;
 712          case TGSI_SEMANTIC_LAYER:
 713             info->writes_layer = true;
 714             break;
 715          case TGSI_SEMANTIC_PSIZE:
 716             info->writes_psize = true;
 717             break;
 718          case TGSI_SEMANTIC_CLIPVERTEX:
 719             info->writes_clipvertex = true;
 720             break;
 721          case TGSI_SEMANTIC_COLOR:
 722             info->colors_written |= 1 << semIndex;
 723             break;
 724          case TGSI_SEMANTIC_STENCIL:
 725             info->writes_stencil = true;
 726             break;
 727          case TGSI_SEMANTIC_SAMPLEMASK:
 728             info->writes_samplemask = true;
 729             break;
 730          case TGSI_SEMANTIC_EDGEFLAG:
 731             info->writes_edgeflag = true;
 732             break;
 733          case TGSI_SEMANTIC_POSITION:
 734             if (procType == PIPE_SHADER_FRAGMENT)
 735                info->writes_z = true;
 736             else
 737                info->writes_position = true;
 738             break;
 739          }
 740          break;
 741
 742       case TGSI_FILE_SAMPLER:
 743          STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
 744          info->samplers_declared |= 1u << reg;
 745          break;
 746
 747       case TGSI_FILE_SAMPLER_VIEW:
 748          target = fulldecl->SamplerView.Resource;
 749          type = fulldecl->SamplerView.ReturnTypeX;
 750
 751          assert(target < TGSI_TEXTURE_UNKNOWN);
 752          if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
 753             /* Save sampler target for this sampler index */
 754             info->sampler_targets[reg] = target;
 755             info->sampler_type[reg] = type;
 756          } else {
 757             /* if previously declared, make sure targets agree */
 758             assert(info->sampler_targets[reg] == target);
 759             assert(info->sampler_type[reg] == type);
 760          }
 761          break;
 762       }
 763    }
 764 }
 765
 766
 767 static void
 768 scan_immediate(struct tgsi_shader_info *info)
 769 {
 770    uint reg = info->immediate_count++;
 771    uint file = TGSI_FILE_IMMEDIATE;
 772
 773    info->file_mask[file] |= (1 << reg);
 774    info->file_count[file]++;
 775    info->file_max[file] = MAX2(info->file_max[file], (int)reg);
 776 }
 777
 778
 779 static void
 780 scan_property(struct tgsi_shader_info *info,
 781               const struct tgsi_full_property *fullprop)
 782 {
 783    unsigned name = fullprop->Property.PropertyName;
 784    unsigned value = fullprop->u[0].Data;
 785
 786    assert(name < ARRAY_SIZE(info->properties));
 787    info->properties[name] = value;
 788
 789    switch (name) {
 790    case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
 791       info->num_written_clipdistance = value;
 792       info->clipdist_writemask |= (1 << value) - 1;
 793       break;
 794    case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
 795       info->num_written_culldistance = value;
 796       info->culldist_writemask |= (1 << value) - 1;
 797       break;
 798    }
 799 }
 800
 801
 802 /**
 803  * Scan the given TGSI shader to collect information such as number of
 804  * registers used, special instructions used, etc.
 805  * \return info  the result of the scan
 806  */
 807 void
 808 tgsi_scan_shader(const struct tgsi_token *tokens,
 809                  struct tgsi_shader_info *info)
 810 {
 811    uint procType, i;
 812    struct tgsi_parse_context parse;
 813    unsigned current_depth = 0;
 814
 815    memset(info, 0, sizeof(*info));
 816    for (i = 0; i < TGSI_FILE_COUNT; i++)
 817       info->file_max[i] = -1;
 818    for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
 819       info->const_file_max[i] = -1;
 820    info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
 821    for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
 822       info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
 823
 824    /**
 825     ** Setup to begin parsing input shader
 826     **/
 827    if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 828       debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
 829       return;
 830    }
 831    procType = parse.FullHeader.Processor.Processor;
 832    assert(procType == PIPE_SHADER_FRAGMENT ||
 833           procType == PIPE_SHADER_VERTEX ||
 834           procType == PIPE_SHADER_GEOMETRY ||
 835           procType == PIPE_SHADER_TESS_CTRL ||
 836           procType == PIPE_SHADER_TESS_EVAL ||
 837           procType == PIPE_SHADER_COMPUTE);
 838    info->processor = procType;
 839    info->num_tokens = tgsi_num_tokens(parse.Tokens);
 840
 841    /**
 842     ** Loop over incoming program tokens/instructions
 843     */
 844    while (!tgsi_parse_end_of_tokens(&parse)) {
 845       tgsi_parse_token( &parse );
 846
 847       switch( parse.FullToken.Token.Type ) {
 848       case TGSI_TOKEN_TYPE_INSTRUCTION:
 849          scan_instruction(info, &parse.FullToken.FullInstruction,
 850                           &current_depth);
 851          break;
 852       case TGSI_TOKEN_TYPE_DECLARATION:
 853          scan_declaration(info, &parse.FullToken.FullDeclaration);
 854          break;
 855       case TGSI_TOKEN_TYPE_IMMEDIATE:
 856          scan_immediate(info);
 857          break;
 858       case TGSI_TOKEN_TYPE_PROPERTY:
 859          scan_property(info, &parse.FullToken.FullProperty);
 860          break;
 861       default:
 862          assert(!"Unexpected TGSI token type");
 863       }
 864    }
 865
 866    info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
 867                       info->opcode_count[TGSI_OPCODE_KILL]);
 868
 869    /* The dimensions of the IN decleration in geometry shader have
 870     * to be deduced from the type of the input primitive.
 871     */
 872    if (procType == PIPE_SHADER_GEOMETRY) {
 873       unsigned input_primitive =
 874             info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
 875       int num_verts = u_vertices_per_prim(input_primitive);
 876       int j;
 877       info->file_count[TGSI_FILE_INPUT] = num_verts;
 878       info->file_max[TGSI_FILE_INPUT] =
 879             MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
 880       for (j = 0; j < num_verts; ++j) {
 881          info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
 882       }
 883    }
 884
 885    tgsi_parse_free(&parse);
 886 }
 887
 888 /**
 889  * Collect information about the arrays of a given register file.
 890  *
 891  * @param tokens TGSI shader
 892  * @param file the register file to scan through
 893  * @param max_array_id number of entries in @p arrays; should be equal to the
 894  *                     highest array id, i.e. tgsi_shader_info::array_max[file].
 895  * @param arrays info for array of each ID will be written to arrays[ID - 1].
 896  */
 897 void
 898 tgsi_scan_arrays(const struct tgsi_token *tokens,
 899                  unsigned file,
 900                  unsigned max_array_id,
 901                  struct tgsi_array_info *arrays)
 902 {
 903    struct tgsi_parse_context parse;
 904
 905    if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
 906       debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
 907       return;
 908    }
 909
 910    memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
 911
 912    while (!tgsi_parse_end_of_tokens(&parse)) {
 913       struct tgsi_full_instruction *inst;
 914
 915       tgsi_parse_token(&parse);
 916
 917       if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
 918          struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
 919
 920          if (decl->Declaration.Array && decl->Declaration.File == file &&
 921              decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
 922             struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
 923             assert(!array->declared);
 924             array->declared = true;
 925             array->range = decl->Range;
 926          }
 927       }
 928
 929       if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
 930          continue;
 931
 932       inst = &parse.FullToken.FullInstruction;
 933       for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
 934          const struct tgsi_full_dst_register *dst = &inst->Dst[i];
 935          if (dst->Register.File != file)
 936             continue;
 937
 938          if (dst->Register.Indirect) {
 939             if (dst->Indirect.ArrayID > 0 &&
 940                 dst->Indirect.ArrayID <= max_array_id) {
 941                arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
 942             } else {
 943                /* Indirect writes without an ArrayID can write anywhere. */
 944                for (unsigned j = 0; j < max_array_id; ++j)
 945                   arrays[j].writemask |= dst->Register.WriteMask;
 946             }
 947          } else {
 948             /* Check whether the write falls into any of the arrays anyway. */
 949             for (unsigned j = 0; j < max_array_id; ++j) {
 950                struct tgsi_array_info *array = &arrays[j];
 951                if (array->declared &&
 952                    dst->Register.Index >= array->range.First &&
 953                    dst->Register.Index <= array->range.Last)
 954                   array->writemask |= dst->Register.WriteMask;
 955             }
 956          }
 957       }
 958    }
 959
 960    tgsi_parse_free(&parse);
 961
 962    return;
 963 }
 964
 965 static void
 966 check_no_subroutines(const struct tgsi_full_instruction *inst)
 967 {
 968    switch (inst->Instruction.Opcode) {
 969    case TGSI_OPCODE_BGNSUB:
 970    case TGSI_OPCODE_ENDSUB:
 971    case TGSI_OPCODE_CAL:
 972       unreachable("subroutines unhandled");
 973    }
 974 }
 975
 976 static unsigned
 977 get_inst_tessfactor_writemask(const struct tgsi_shader_info *info,
 978                               const struct tgsi_full_instruction *inst)
 979 {
 980    unsigned writemask = 0;
 981
 982    for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
 983       const struct tgsi_full_dst_register *dst = &inst->Dst[i];
 984
 985       if (dst->Register.File == TGSI_FILE_OUTPUT &&
 986           !dst->Register.Indirect) {
 987          unsigned name = info->output_semantic_name[dst->Register.Index];
 988
 989          if (name == TGSI_SEMANTIC_TESSINNER)
 990             writemask |= dst->Register.WriteMask;
 991          else if (name == TGSI_SEMANTIC_TESSOUTER)
 992             writemask |= dst->Register.WriteMask << 4;
 993       }
 994    }
 995    return writemask;
 996 }
 997
 998 static unsigned
 999 get_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1000                                struct tgsi_parse_context *parse,
1001                                unsigned end_opcode)
1002 {
1003    struct tgsi_full_instruction *inst;
1004    unsigned writemask = 0;
1005
1006    do {
1007       tgsi_parse_token(parse);
1008       assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1009       inst = &parse->FullToken.FullInstruction;
1010       check_no_subroutines(inst);
1011
1012       /* Recursively process nested blocks. */
1013       switch (inst->Instruction.Opcode) {
1014       case TGSI_OPCODE_IF:
1015       case TGSI_OPCODE_UIF:
1016          writemask |=
1017             get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDIF);
1018          continue;
1019
1020       case TGSI_OPCODE_BGNLOOP:
1021          writemask |=
1022             get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1023          continue;
1024
1025       case TGSI_OPCODE_BARRIER:
1026          unreachable("nested BARRIER is illegal");
1027          continue;
1028       }
1029
1030       writemask |= get_inst_tessfactor_writemask(info, inst);
1031    } while (inst->Instruction.Opcode != end_opcode);
1032
1033    return writemask;
1034 }
1035
1036 static void
1037 get_if_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1038                                   struct tgsi_parse_context *parse,
1039                                   unsigned *upper_block_tf_writemask,
1040                                   unsigned *cond_block_tf_writemask)
1041 {
1042    struct tgsi_full_instruction *inst;
1043    unsigned then_tessfactor_writemask = 0;
1044    unsigned else_tessfactor_writemask = 0;
1045    bool is_then = true;
1046
1047    do {
1048       tgsi_parse_token(parse);
1049       assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1050       inst = &parse->FullToken.FullInstruction;
1051       check_no_subroutines(inst);
1052
1053       switch (inst->Instruction.Opcode) {
1054       case TGSI_OPCODE_ELSE:
1055          is_then = false;
1056          continue;
1057
1058       /* Recursively process nested blocks. */
1059       case TGSI_OPCODE_IF:
1060       case TGSI_OPCODE_UIF:
1061          get_if_block_tessfactor_writemask(info, parse,
1062                                            is_then ? &then_tessfactor_writemask :
1063                                                      &else_tessfactor_writemask,
1064                                            cond_block_tf_writemask);
1065          continue;
1066
1067       case TGSI_OPCODE_BGNLOOP:
1068          *cond_block_tf_writemask |=
1069             get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1070          continue;
1071
1072       case TGSI_OPCODE_BARRIER:
1073          unreachable("nested BARRIER is illegal");
1074          continue;
1075       }
1076
1077       /* Process an instruction in the current block. */
1078       unsigned writemask = get_inst_tessfactor_writemask(info, inst);
1079
1080       if (writemask) {
1081          if (is_then)
1082             then_tessfactor_writemask |= writemask;
1083          else
1084             else_tessfactor_writemask |= writemask;
1085       }
1086    } while (inst->Instruction.Opcode != TGSI_OPCODE_ENDIF);
1087
1088    if (then_tessfactor_writemask || else_tessfactor_writemask) {
1089       /* If both statements write the same tess factor channels,
1090        * we can say that the upper block writes them too. */
1091       *upper_block_tf_writemask |= then_tessfactor_writemask &
1092                                    else_tessfactor_writemask;
1093       *cond_block_tf_writemask |= then_tessfactor_writemask |
1094                                   else_tessfactor_writemask;
1095    }
1096 }
1097
1098 void
1099 tgsi_scan_tess_ctrl(const struct tgsi_token *tokens,
1100                     const struct tgsi_shader_info *info,
1101                     struct tgsi_tessctrl_info *out)
1102 {
1103    memset(out, 0, sizeof(*out));
1104
1105    if (info->processor != PIPE_SHADER_TESS_CTRL)
1106       return;
1107
1108    struct tgsi_parse_context parse;
1109    if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
1110       debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
1111       return;
1112    }
1113
1114    /* The pass works as follows:
1115     * If all codepaths write tess factors, we can say that all invocations
1116     * define tess factors.
1117     *
1118     * Each tess factor channel is tracked separately.
1119     */
1120    unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
1121    unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
1122
1123    /* Initial value = true. Here the pass will accumulate results from multiple
1124     * segments surrounded by barriers. If tess factors aren't written at all,
1125     * it's a shader bug and we don't care if this will be true.
1126     */
1127    out->tessfactors_are_def_in_all_invocs = true;
1128
1129    while (!tgsi_parse_end_of_tokens(&parse)) {
1130       tgsi_parse_token(&parse);
1131
1132       if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
1133          continue;
1134
1135       struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1136       check_no_subroutines(inst);
1137
1138       /* Process nested blocks. */
1139       switch (inst->Instruction.Opcode) {
1140       case TGSI_OPCODE_IF:
1141       case TGSI_OPCODE_UIF:
1142          get_if_block_tessfactor_writemask(info, &parse,
1143                                            &main_block_tf_writemask,
1144                                            &cond_block_tf_writemask);
1145          continue;
1146
1147       case TGSI_OPCODE_BGNLOOP:
1148          cond_block_tf_writemask |=
1149             get_block_tessfactor_writemask(info, &parse, TGSI_OPCODE_ENDIF);
1150          continue;
1151
1152       case TGSI_OPCODE_BARRIER:
1153          /* The following case must be prevented:
1154           *    gl_TessLevelInner = ...;
1155           *    barrier();
1156           *    if (gl_InvocationID == 1)
1157           *       gl_TessLevelInner = ...;
1158           *
1159           * If you consider disjoint code segments separated by barriers, each
1160           * such segment that writes tess factor channels should write the same
1161           * channels in all codepaths within that segment.
1162           */
1163          if (main_block_tf_writemask || cond_block_tf_writemask) {
1164             /* Accumulate the result: */
1165             out->tessfactors_are_def_in_all_invocs &=
1166                !(cond_block_tf_writemask & ~main_block_tf_writemask);
1167
1168             /* Analyze the next code segment from scratch. */
1169             main_block_tf_writemask = 0;
1170             cond_block_tf_writemask = 0;
1171          }
1172          continue;
1173       }
1174
1175       main_block_tf_writemask |= get_inst_tessfactor_writemask(info, inst);
1176    }
1177
1178    /* Accumulate the result for the last code segment separated by a barrier. */
1179    if (main_block_tf_writemask || cond_block_tf_writemask) {
1180       out->tessfactors_are_def_in_all_invocs &=
1181          !(cond_block_tf_writemask & ~main_block_tf_writemask);
1182    }
1183
1184    tgsi_parse_free(&parse);
1185 }