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[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_scan.c
1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2008 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI program scan utility.
31 * Used to determine which registers and instructions are used by a shader.
32 *
33 * Authors: Brian Paul
34 */
35
36
37 #include "util/u_debug.h"
38 #include "util/u_math.h"
39 #include "util/u_memory.h"
40 #include "util/u_prim.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_scan.h"
45
46
47 static bool
48 is_memory_file(unsigned file)
49 {
50 return file == TGSI_FILE_SAMPLER ||
51 file == TGSI_FILE_SAMPLER_VIEW ||
52 file == TGSI_FILE_IMAGE ||
53 file == TGSI_FILE_BUFFER;
54 }
55
56
57 static bool
58 is_mem_query_inst(unsigned opcode)
59 {
60 return opcode == TGSI_OPCODE_RESQ ||
61 opcode == TGSI_OPCODE_TXQ ||
62 opcode == TGSI_OPCODE_TXQS ||
63 opcode == TGSI_OPCODE_TXQ_LZ ||
64 opcode == TGSI_OPCODE_LODQ;
65 }
66
67 /**
68 * Is the opcode a "true" texture instruction which samples from a
69 * texture map?
70 */
71 static bool
72 is_texture_inst(unsigned opcode)
73 {
74 return (!is_mem_query_inst(opcode) &&
75 tgsi_get_opcode_info(opcode)->is_tex);
76 }
77
78
79 /**
80 * Is the opcode an instruction which computes a derivative explicitly or
81 * implicitly?
82 */
83 static bool
84 computes_derivative(unsigned opcode)
85 {
86 if (tgsi_get_opcode_info(opcode)->is_tex) {
87 return opcode != TGSI_OPCODE_TG4 &&
88 opcode != TGSI_OPCODE_TXD &&
89 opcode != TGSI_OPCODE_TXF &&
90 opcode != TGSI_OPCODE_TXF_LZ &&
91 opcode != TGSI_OPCODE_TEX_LZ &&
92 opcode != TGSI_OPCODE_TXL &&
93 opcode != TGSI_OPCODE_TXL2 &&
94 opcode != TGSI_OPCODE_TXQ &&
95 opcode != TGSI_OPCODE_TXQ_LZ &&
96 opcode != TGSI_OPCODE_TXQS;
97 }
98
99 return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
100 opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
101 opcode == TGSI_OPCODE_SAMPLE ||
102 opcode == TGSI_OPCODE_SAMPLE_B ||
103 opcode == TGSI_OPCODE_SAMPLE_C;
104 }
105
106
107 static void
108 scan_src_operand(struct tgsi_shader_info *info,
109 const struct tgsi_full_instruction *fullinst,
110 const struct tgsi_full_src_register *src,
111 unsigned src_index,
112 unsigned usage_mask,
113 bool is_interp_instruction,
114 bool *is_mem_inst)
115 {
116 int ind = src->Register.Index;
117
118 /* Mark which inputs are effectively used */
119 if (src->Register.File == TGSI_FILE_INPUT) {
120 if (src->Register.Indirect) {
121 for (ind = 0; ind < info->num_inputs; ++ind) {
122 info->input_usage_mask[ind] |= usage_mask;
123 }
124 } else {
125 assert(ind >= 0);
126 assert(ind < PIPE_MAX_SHADER_INPUTS);
127 info->input_usage_mask[ind] |= usage_mask;
128 }
129
130 if (info->processor == PIPE_SHADER_FRAGMENT) {
131 unsigned name, index, input;
132
133 if (src->Register.Indirect && src->Indirect.ArrayID)
134 input = info->input_array_first[src->Indirect.ArrayID];
135 else
136 input = src->Register.Index;
137
138 name = info->input_semantic_name[input];
139 index = info->input_semantic_index[input];
140
141 if (name == TGSI_SEMANTIC_POSITION &&
142 (src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
143 src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
144 src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
145 src->Register.SwizzleW == TGSI_SWIZZLE_Z))
146 info->reads_z = TRUE;
147
148 if (name == TGSI_SEMANTIC_COLOR) {
149 unsigned mask =
150 (1 << src->Register.SwizzleX) |
151 (1 << src->Register.SwizzleY) |
152 (1 << src->Register.SwizzleZ) |
153 (1 << src->Register.SwizzleW);
154
155 info->colors_read |= mask << (index * 4);
156 }
157
158 /* Process only interpolated varyings. Don't include POSITION.
159 * Don't include integer varyings, because they are not
160 * interpolated. Don't process inputs interpolated by INTERP
161 * opcodes. Those are tracked separately.
162 */
163 if ((!is_interp_instruction || src_index != 0) &&
164 (name == TGSI_SEMANTIC_GENERIC ||
165 name == TGSI_SEMANTIC_TEXCOORD ||
166 name == TGSI_SEMANTIC_COLOR ||
167 name == TGSI_SEMANTIC_BCOLOR ||
168 name == TGSI_SEMANTIC_FOG ||
169 name == TGSI_SEMANTIC_CLIPDIST)) {
170 switch (info->input_interpolate[input]) {
171 case TGSI_INTERPOLATE_COLOR:
172 case TGSI_INTERPOLATE_PERSPECTIVE:
173 switch (info->input_interpolate_loc[input]) {
174 case TGSI_INTERPOLATE_LOC_CENTER:
175 info->uses_persp_center = TRUE;
176 break;
177 case TGSI_INTERPOLATE_LOC_CENTROID:
178 info->uses_persp_centroid = TRUE;
179 break;
180 case TGSI_INTERPOLATE_LOC_SAMPLE:
181 info->uses_persp_sample = TRUE;
182 break;
183 }
184 break;
185 case TGSI_INTERPOLATE_LINEAR:
186 switch (info->input_interpolate_loc[input]) {
187 case TGSI_INTERPOLATE_LOC_CENTER:
188 info->uses_linear_center = TRUE;
189 break;
190 case TGSI_INTERPOLATE_LOC_CENTROID:
191 info->uses_linear_centroid = TRUE;
192 break;
193 case TGSI_INTERPOLATE_LOC_SAMPLE:
194 info->uses_linear_sample = TRUE;
195 break;
196 }
197 break;
198 /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
199 }
200 }
201 }
202 }
203
204 if (info->processor == PIPE_SHADER_TESS_CTRL &&
205 src->Register.File == TGSI_FILE_OUTPUT) {
206 unsigned input;
207
208 if (src->Register.Indirect && src->Indirect.ArrayID)
209 input = info->output_array_first[src->Indirect.ArrayID];
210 else
211 input = src->Register.Index;
212
213 switch (info->output_semantic_name[input]) {
214 case TGSI_SEMANTIC_PATCH:
215 info->reads_perpatch_outputs = true;
216 break;
217 case TGSI_SEMANTIC_TESSINNER:
218 case TGSI_SEMANTIC_TESSOUTER:
219 info->reads_tessfactor_outputs = true;
220 break;
221 default:
222 info->reads_pervertex_outputs = true;
223 }
224 }
225
226 /* check for indirect register reads */
227 if (src->Register.Indirect) {
228 info->indirect_files |= (1 << src->Register.File);
229 info->indirect_files_read |= (1 << src->Register.File);
230
231 /* record indirect constant buffer indexing */
232 if (src->Register.File == TGSI_FILE_CONSTANT) {
233 if (src->Register.Dimension) {
234 if (src->Dimension.Indirect)
235 info->const_buffers_indirect = info->const_buffers_declared;
236 else
237 info->const_buffers_indirect |= 1u << src->Dimension.Index;
238 } else {
239 info->const_buffers_indirect |= 1;
240 }
241 }
242 }
243
244 if (src->Register.Dimension && src->Dimension.Indirect)
245 info->dim_indirect_files |= 1u << src->Register.File;
246
247 /* Texture samplers */
248 if (src->Register.File == TGSI_FILE_SAMPLER) {
249 const unsigned index = src->Register.Index;
250
251 assert(fullinst->Instruction.Texture);
252 assert(index < ARRAY_SIZE(info->is_msaa_sampler));
253 assert(index < PIPE_MAX_SAMPLERS);
254
255 if (is_texture_inst(fullinst->Instruction.Opcode)) {
256 const unsigned target = fullinst->Texture.Texture;
257 assert(target < TGSI_TEXTURE_UNKNOWN);
258 /* for texture instructions, check that the texture instruction
259 * target matches the previous sampler view declaration (if there
260 * was one.)
261 */
262 if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
263 /* probably no sampler view declaration */
264 info->sampler_targets[index] = target;
265 } else {
266 /* Make sure the texture instruction's sampler/target info
267 * agrees with the sampler view declaration.
268 */
269 assert(info->sampler_targets[index] == target);
270 }
271 /* MSAA samplers */
272 if (target == TGSI_TEXTURE_2D_MSAA ||
273 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
274 info->is_msaa_sampler[src->Register.Index] = TRUE;
275 }
276 }
277 }
278
279 if (is_memory_file(src->Register.File) &&
280 !is_mem_query_inst(fullinst->Instruction.Opcode)) {
281 *is_mem_inst = true;
282
283 if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
284 info->writes_memory = TRUE;
285
286 if (src->Register.File == TGSI_FILE_IMAGE) {
287 if (src->Register.Indirect)
288 info->images_atomic = info->images_declared;
289 else
290 info->images_atomic |= 1 << src->Register.Index;
291 } else if (src->Register.File == TGSI_FILE_BUFFER) {
292 if (src->Register.Indirect)
293 info->shader_buffers_atomic = info->shader_buffers_declared;
294 else
295 info->shader_buffers_atomic |= 1 << src->Register.Index;
296 }
297 } else {
298 if (src->Register.File == TGSI_FILE_IMAGE) {
299 if (src->Register.Indirect)
300 info->images_load = info->images_declared;
301 else
302 info->images_load |= 1 << src->Register.Index;
303 } else if (src->Register.File == TGSI_FILE_BUFFER) {
304 if (src->Register.Indirect)
305 info->shader_buffers_load = info->shader_buffers_declared;
306 else
307 info->shader_buffers_load |= 1 << src->Register.Index;
308 }
309 }
310 }
311 }
312
313
314 static void
315 scan_instruction(struct tgsi_shader_info *info,
316 const struct tgsi_full_instruction *fullinst,
317 unsigned *current_depth)
318 {
319 unsigned i;
320 bool is_mem_inst = false;
321 bool is_interp_instruction = false;
322
323 assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
324 info->opcode_count[fullinst->Instruction.Opcode]++;
325
326 switch (fullinst->Instruction.Opcode) {
327 case TGSI_OPCODE_IF:
328 case TGSI_OPCODE_UIF:
329 case TGSI_OPCODE_BGNLOOP:
330 (*current_depth)++;
331 info->max_depth = MAX2(info->max_depth, *current_depth);
332 break;
333 case TGSI_OPCODE_ENDIF:
334 case TGSI_OPCODE_ENDLOOP:
335 (*current_depth)--;
336 break;
337 default:
338 break;
339 }
340
341 if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
342 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
343 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
344 const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
345 unsigned input;
346
347 is_interp_instruction = true;
348
349 if (src0->Register.Indirect && src0->Indirect.ArrayID)
350 input = info->input_array_first[src0->Indirect.ArrayID];
351 else
352 input = src0->Register.Index;
353
354 /* For the INTERP opcodes, the interpolation is always
355 * PERSPECTIVE unless LINEAR is specified.
356 */
357 switch (info->input_interpolate[input]) {
358 case TGSI_INTERPOLATE_COLOR:
359 case TGSI_INTERPOLATE_CONSTANT:
360 case TGSI_INTERPOLATE_PERSPECTIVE:
361 switch (fullinst->Instruction.Opcode) {
362 case TGSI_OPCODE_INTERP_CENTROID:
363 info->uses_persp_opcode_interp_centroid = TRUE;
364 break;
365 case TGSI_OPCODE_INTERP_OFFSET:
366 info->uses_persp_opcode_interp_offset = TRUE;
367 break;
368 case TGSI_OPCODE_INTERP_SAMPLE:
369 info->uses_persp_opcode_interp_sample = TRUE;
370 break;
371 }
372 break;
373
374 case TGSI_INTERPOLATE_LINEAR:
375 switch (fullinst->Instruction.Opcode) {
376 case TGSI_OPCODE_INTERP_CENTROID:
377 info->uses_linear_opcode_interp_centroid = TRUE;
378 break;
379 case TGSI_OPCODE_INTERP_OFFSET:
380 info->uses_linear_opcode_interp_offset = TRUE;
381 break;
382 case TGSI_OPCODE_INTERP_SAMPLE:
383 info->uses_linear_opcode_interp_sample = TRUE;
384 break;
385 }
386 break;
387 }
388 }
389
390 if (fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
391 fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG)
392 info->uses_doubles = TRUE;
393
394 for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
395 scan_src_operand(info, fullinst, &fullinst->Src[i], i,
396 tgsi_util_get_inst_usage_mask(fullinst, i),
397 is_interp_instruction, &is_mem_inst);
398 }
399
400 if (fullinst->Instruction.Texture) {
401 for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
402 struct tgsi_full_src_register src = {{0}};
403
404 src.Register.File = fullinst->TexOffsets[i].File;
405 src.Register.Index = fullinst->TexOffsets[i].Index;
406 src.Register.SwizzleX = fullinst->TexOffsets[i].SwizzleX;
407 src.Register.SwizzleY = fullinst->TexOffsets[i].SwizzleY;
408 src.Register.SwizzleZ = fullinst->TexOffsets[i].SwizzleZ;
409
410 /* The usage mask is suboptimal but should be safe. */
411 scan_src_operand(info, fullinst, &src, 0, TGSI_WRITEMASK_XYZ,
412 false, &is_mem_inst);
413 }
414 }
415
416 /* check for indirect register writes */
417 for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
418 const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
419 if (dst->Register.Indirect) {
420 info->indirect_files |= (1 << dst->Register.File);
421 info->indirect_files_written |= (1 << dst->Register.File);
422 }
423
424 if (dst->Register.Dimension && dst->Dimension.Indirect)
425 info->dim_indirect_files |= 1u << dst->Register.File;
426
427 if (is_memory_file(dst->Register.File)) {
428 assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
429
430 is_mem_inst = true;
431 info->writes_memory = TRUE;
432
433 if (dst->Register.File == TGSI_FILE_IMAGE) {
434 if (dst->Register.Indirect)
435 info->images_store = info->images_declared;
436 else
437 info->images_store |= 1 << dst->Register.Index;
438 } else if (dst->Register.File == TGSI_FILE_BUFFER) {
439 if (dst->Register.Indirect)
440 info->shader_buffers_store = info->shader_buffers_declared;
441 else
442 info->shader_buffers_store |= 1 << dst->Register.Index;
443 }
444 }
445 }
446
447 if (is_mem_inst)
448 info->num_memory_instructions++;
449
450 if (computes_derivative(fullinst->Instruction.Opcode))
451 info->uses_derivatives = true;
452
453 info->num_instructions++;
454 }
455
456
457 static void
458 scan_declaration(struct tgsi_shader_info *info,
459 const struct tgsi_full_declaration *fulldecl)
460 {
461 const uint file = fulldecl->Declaration.File;
462 const unsigned procType = info->processor;
463 uint reg;
464
465 if (fulldecl->Declaration.Array) {
466 unsigned array_id = fulldecl->Array.ArrayID;
467
468 switch (file) {
469 case TGSI_FILE_INPUT:
470 assert(array_id < ARRAY_SIZE(info->input_array_first));
471 info->input_array_first[array_id] = fulldecl->Range.First;
472 info->input_array_last[array_id] = fulldecl->Range.Last;
473 break;
474 case TGSI_FILE_OUTPUT:
475 assert(array_id < ARRAY_SIZE(info->output_array_first));
476 info->output_array_first[array_id] = fulldecl->Range.First;
477 info->output_array_last[array_id] = fulldecl->Range.Last;
478 break;
479 }
480 info->array_max[file] = MAX2(info->array_max[file], array_id);
481 }
482
483 for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
484 unsigned semName = fulldecl->Semantic.Name;
485 unsigned semIndex = fulldecl->Semantic.Index +
486 (reg - fulldecl->Range.First);
487 int buffer;
488 unsigned index, target, type;
489
490 /* only first 32 regs will appear in this bitfield */
491 info->file_mask[file] |= (1 << reg);
492 info->file_count[file]++;
493 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
494
495 switch (file) {
496 case TGSI_FILE_CONSTANT:
497 buffer = 0;
498
499 if (fulldecl->Declaration.Dimension)
500 buffer = fulldecl->Dim.Index2D;
501
502 info->const_file_max[buffer] =
503 MAX2(info->const_file_max[buffer], (int)reg);
504 info->const_buffers_declared |= 1u << buffer;
505 break;
506
507 case TGSI_FILE_IMAGE:
508 info->images_declared |= 1u << reg;
509 if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
510 info->images_buffers |= 1 << reg;
511 break;
512
513 case TGSI_FILE_BUFFER:
514 info->shader_buffers_declared |= 1u << reg;
515 break;
516
517 case TGSI_FILE_INPUT:
518 info->input_semantic_name[reg] = (ubyte) semName;
519 info->input_semantic_index[reg] = (ubyte) semIndex;
520 info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
521 info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
522 info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
523
524 /* Vertex shaders can have inputs with holes between them. */
525 info->num_inputs = MAX2(info->num_inputs, reg + 1);
526
527 if (semName == TGSI_SEMANTIC_PRIMID)
528 info->uses_primid = TRUE;
529 else if (procType == PIPE_SHADER_FRAGMENT) {
530 if (semName == TGSI_SEMANTIC_POSITION)
531 info->reads_position = TRUE;
532 else if (semName == TGSI_SEMANTIC_FACE)
533 info->uses_frontface = TRUE;
534 }
535 break;
536
537 case TGSI_FILE_SYSTEM_VALUE:
538 index = fulldecl->Range.First;
539
540 info->system_value_semantic_name[index] = semName;
541 info->num_system_values = MAX2(info->num_system_values, index + 1);
542
543 switch (semName) {
544 case TGSI_SEMANTIC_INSTANCEID:
545 info->uses_instanceid = TRUE;
546 break;
547 case TGSI_SEMANTIC_VERTEXID:
548 info->uses_vertexid = TRUE;
549 break;
550 case TGSI_SEMANTIC_VERTEXID_NOBASE:
551 info->uses_vertexid_nobase = TRUE;
552 break;
553 case TGSI_SEMANTIC_BASEVERTEX:
554 info->uses_basevertex = TRUE;
555 break;
556 case TGSI_SEMANTIC_PRIMID:
557 info->uses_primid = TRUE;
558 break;
559 case TGSI_SEMANTIC_INVOCATIONID:
560 info->uses_invocationid = TRUE;
561 break;
562 case TGSI_SEMANTIC_POSITION:
563 info->reads_position = TRUE;
564 break;
565 case TGSI_SEMANTIC_FACE:
566 info->uses_frontface = TRUE;
567 break;
568 case TGSI_SEMANTIC_SAMPLEMASK:
569 info->reads_samplemask = TRUE;
570 break;
571 case TGSI_SEMANTIC_TESSINNER:
572 case TGSI_SEMANTIC_TESSOUTER:
573 info->reads_tess_factors = true;
574 break;
575 }
576 break;
577
578 case TGSI_FILE_OUTPUT:
579 info->output_semantic_name[reg] = (ubyte) semName;
580 info->output_semantic_index[reg] = (ubyte) semIndex;
581 info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
582 info->num_outputs = MAX2(info->num_outputs, reg + 1);
583
584 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
585 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
586 info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
587 }
588 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
589 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
590 info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
591 }
592 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
593 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
594 info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
595 }
596 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
597 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
598 info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
599 }
600
601 switch (semName) {
602 case TGSI_SEMANTIC_PRIMID:
603 info->writes_primid = true;
604 break;
605 case TGSI_SEMANTIC_VIEWPORT_INDEX:
606 info->writes_viewport_index = true;
607 break;
608 case TGSI_SEMANTIC_LAYER:
609 info->writes_layer = true;
610 break;
611 case TGSI_SEMANTIC_PSIZE:
612 info->writes_psize = true;
613 break;
614 case TGSI_SEMANTIC_CLIPVERTEX:
615 info->writes_clipvertex = true;
616 break;
617 case TGSI_SEMANTIC_COLOR:
618 info->colors_written |= 1 << semIndex;
619 break;
620 case TGSI_SEMANTIC_STENCIL:
621 info->writes_stencil = true;
622 break;
623 case TGSI_SEMANTIC_SAMPLEMASK:
624 info->writes_samplemask = true;
625 break;
626 case TGSI_SEMANTIC_EDGEFLAG:
627 info->writes_edgeflag = true;
628 break;
629 case TGSI_SEMANTIC_POSITION:
630 if (procType == PIPE_SHADER_FRAGMENT)
631 info->writes_z = true;
632 else
633 info->writes_position = true;
634 break;
635 }
636 break;
637
638 case TGSI_FILE_SAMPLER:
639 STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
640 info->samplers_declared |= 1u << reg;
641 break;
642
643 case TGSI_FILE_SAMPLER_VIEW:
644 target = fulldecl->SamplerView.Resource;
645 type = fulldecl->SamplerView.ReturnTypeX;
646
647 assert(target < TGSI_TEXTURE_UNKNOWN);
648 if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
649 /* Save sampler target for this sampler index */
650 info->sampler_targets[reg] = target;
651 info->sampler_type[reg] = type;
652 } else {
653 /* if previously declared, make sure targets agree */
654 assert(info->sampler_targets[reg] == target);
655 assert(info->sampler_type[reg] == type);
656 }
657 break;
658 }
659 }
660 }
661
662
663 static void
664 scan_immediate(struct tgsi_shader_info *info)
665 {
666 uint reg = info->immediate_count++;
667 uint file = TGSI_FILE_IMMEDIATE;
668
669 info->file_mask[file] |= (1 << reg);
670 info->file_count[file]++;
671 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
672 }
673
674
675 static void
676 scan_property(struct tgsi_shader_info *info,
677 const struct tgsi_full_property *fullprop)
678 {
679 unsigned name = fullprop->Property.PropertyName;
680 unsigned value = fullprop->u[0].Data;
681
682 assert(name < ARRAY_SIZE(info->properties));
683 info->properties[name] = value;
684
685 switch (name) {
686 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
687 info->num_written_clipdistance = value;
688 info->clipdist_writemask |= (1 << value) - 1;
689 break;
690 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
691 info->num_written_culldistance = value;
692 info->culldist_writemask |= (1 << value) - 1;
693 break;
694 }
695 }
696
697
698 /**
699 * Scan the given TGSI shader to collect information such as number of
700 * registers used, special instructions used, etc.
701 * \return info the result of the scan
702 */
703 void
704 tgsi_scan_shader(const struct tgsi_token *tokens,
705 struct tgsi_shader_info *info)
706 {
707 uint procType, i;
708 struct tgsi_parse_context parse;
709 unsigned current_depth = 0;
710
711 memset(info, 0, sizeof(*info));
712 for (i = 0; i < TGSI_FILE_COUNT; i++)
713 info->file_max[i] = -1;
714 for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
715 info->const_file_max[i] = -1;
716 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
717 for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
718 info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
719
720 /**
721 ** Setup to begin parsing input shader
722 **/
723 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
724 debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
725 return;
726 }
727 procType = parse.FullHeader.Processor.Processor;
728 assert(procType == PIPE_SHADER_FRAGMENT ||
729 procType == PIPE_SHADER_VERTEX ||
730 procType == PIPE_SHADER_GEOMETRY ||
731 procType == PIPE_SHADER_TESS_CTRL ||
732 procType == PIPE_SHADER_TESS_EVAL ||
733 procType == PIPE_SHADER_COMPUTE);
734 info->processor = procType;
735
736 /**
737 ** Loop over incoming program tokens/instructions
738 */
739 while (!tgsi_parse_end_of_tokens(&parse)) {
740 info->num_tokens++;
741
742 tgsi_parse_token( &parse );
743
744 switch( parse.FullToken.Token.Type ) {
745 case TGSI_TOKEN_TYPE_INSTRUCTION:
746 scan_instruction(info, &parse.FullToken.FullInstruction,
747 &current_depth);
748 break;
749 case TGSI_TOKEN_TYPE_DECLARATION:
750 scan_declaration(info, &parse.FullToken.FullDeclaration);
751 break;
752 case TGSI_TOKEN_TYPE_IMMEDIATE:
753 scan_immediate(info);
754 break;
755 case TGSI_TOKEN_TYPE_PROPERTY:
756 scan_property(info, &parse.FullToken.FullProperty);
757 break;
758 default:
759 assert(!"Unexpected TGSI token type");
760 }
761 }
762
763 info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
764 info->opcode_count[TGSI_OPCODE_KILL]);
765
766 /* The dimensions of the IN decleration in geometry shader have
767 * to be deduced from the type of the input primitive.
768 */
769 if (procType == PIPE_SHADER_GEOMETRY) {
770 unsigned input_primitive =
771 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
772 int num_verts = u_vertices_per_prim(input_primitive);
773 int j;
774 info->file_count[TGSI_FILE_INPUT] = num_verts;
775 info->file_max[TGSI_FILE_INPUT] =
776 MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
777 for (j = 0; j < num_verts; ++j) {
778 info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
779 }
780 }
781
782 tgsi_parse_free(&parse);
783 }
784
785 /**
786 * Collect information about the arrays of a given register file.
787 *
788 * @param tokens TGSI shader
789 * @param file the register file to scan through
790 * @param max_array_id number of entries in @p arrays; should be equal to the
791 * highest array id, i.e. tgsi_shader_info::array_max[file].
792 * @param arrays info for array of each ID will be written to arrays[ID - 1].
793 */
794 void
795 tgsi_scan_arrays(const struct tgsi_token *tokens,
796 unsigned file,
797 unsigned max_array_id,
798 struct tgsi_array_info *arrays)
799 {
800 struct tgsi_parse_context parse;
801
802 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
803 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
804 return;
805 }
806
807 memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
808
809 while (!tgsi_parse_end_of_tokens(&parse)) {
810 struct tgsi_full_instruction *inst;
811
812 tgsi_parse_token(&parse);
813
814 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
815 struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
816
817 if (decl->Declaration.Array && decl->Declaration.File == file &&
818 decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
819 struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
820 assert(!array->declared);
821 array->declared = true;
822 array->range = decl->Range;
823 }
824 }
825
826 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
827 continue;
828
829 inst = &parse.FullToken.FullInstruction;
830 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
831 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
832 if (dst->Register.File != file)
833 continue;
834
835 if (dst->Register.Indirect) {
836 if (dst->Indirect.ArrayID > 0 &&
837 dst->Indirect.ArrayID <= max_array_id) {
838 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
839 } else {
840 /* Indirect writes without an ArrayID can write anywhere. */
841 for (unsigned j = 0; j < max_array_id; ++j)
842 arrays[j].writemask |= dst->Register.WriteMask;
843 }
844 } else {
845 /* Check whether the write falls into any of the arrays anyway. */
846 for (unsigned j = 0; j < max_array_id; ++j) {
847 struct tgsi_array_info *array = &arrays[j];
848 if (array->declared &&
849 dst->Register.Index >= array->range.First &&
850 dst->Register.Index <= array->range.Last)
851 array->writemask |= dst->Register.WriteMask;
852 }
853 }
854 }
855 }
856
857 tgsi_parse_free(&parse);
858
859 return;
860 }
861
862
863 /**
864 * Check if the given shader is a "passthrough" shader consisting of only
865 * MOV instructions of the form: MOV OUT[n], IN[n]
866 *
867 */
868 boolean
869 tgsi_is_passthrough_shader(const struct tgsi_token *tokens)
870 {
871 struct tgsi_parse_context parse;
872
873 /**
874 ** Setup to begin parsing input shader
875 **/
876 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
877 debug_printf("tgsi_parse_init() failed in tgsi_is_passthrough_shader()!\n");
878 return FALSE;
879 }
880
881 /**
882 ** Loop over incoming program tokens/instructions
883 */
884 while (!tgsi_parse_end_of_tokens(&parse)) {
885
886 tgsi_parse_token(&parse);
887
888 switch (parse.FullToken.Token.Type) {
889 case TGSI_TOKEN_TYPE_INSTRUCTION:
890 {
891 struct tgsi_full_instruction *fullinst =
892 &parse.FullToken.FullInstruction;
893 const struct tgsi_full_src_register *src =
894 &fullinst->Src[0];
895 const struct tgsi_full_dst_register *dst =
896 &fullinst->Dst[0];
897
898 /* Do a whole bunch of checks for a simple move */
899 if (fullinst->Instruction.Opcode != TGSI_OPCODE_MOV ||
900 (src->Register.File != TGSI_FILE_INPUT &&
901 src->Register.File != TGSI_FILE_SYSTEM_VALUE) ||
902 dst->Register.File != TGSI_FILE_OUTPUT ||
903 src->Register.Index != dst->Register.Index ||
904
905 src->Register.Negate ||
906 src->Register.Absolute ||
907
908 src->Register.SwizzleX != TGSI_SWIZZLE_X ||
909 src->Register.SwizzleY != TGSI_SWIZZLE_Y ||
910 src->Register.SwizzleZ != TGSI_SWIZZLE_Z ||
911 src->Register.SwizzleW != TGSI_SWIZZLE_W ||
912
913 dst->Register.WriteMask != TGSI_WRITEMASK_XYZW)
914 {
915 tgsi_parse_free(&parse);
916 return FALSE;
917 }
918 }
919 break;
920
921 case TGSI_TOKEN_TYPE_DECLARATION:
922 /* fall-through */
923 case TGSI_TOKEN_TYPE_IMMEDIATE:
924 /* fall-through */
925 case TGSI_TOKEN_TYPE_PROPERTY:
926 /* fall-through */
927 default:
928 ; /* no-op */
929 }
930 }
931
932 tgsi_parse_free(&parse);
933
934 /* if we get here, it's a pass-through shader */
935 return TRUE;
936 }