src/gallium/auxiliary/tgsi/tgsi_scan.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 VMware, Inc.
   4  * All Rights Reserved.
   5  * Copyright 2008 VMware, Inc.  All rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  **************************************************************************/
  28
  29 /**
  30  * TGSI program scan utility.
  31  * Used to determine which registers and instructions are used by a shader.
  32  *
  33  * Authors:  Brian Paul
  34  */
  35
  36
  37 #include "util/u_debug.h"
  38 #include "util/u_math.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_prim.h"
  41 #include "tgsi/tgsi_info.h"
  42 #include "tgsi/tgsi_parse.h"
  43 #include "tgsi/tgsi_util.h"
  44 #include "tgsi/tgsi_scan.h"
  45
  46
  47 static bool
  48 is_memory_file(unsigned file)
  49 {
  50    return file == TGSI_FILE_SAMPLER ||
  51           file == TGSI_FILE_SAMPLER_VIEW ||
  52           file == TGSI_FILE_IMAGE ||
  53           file == TGSI_FILE_BUFFER;
  54 }
  55
  56
  57 static bool
  58 is_mem_query_inst(unsigned opcode)
  59 {
  60    return opcode == TGSI_OPCODE_RESQ ||
  61           opcode == TGSI_OPCODE_TXQ ||
  62           opcode == TGSI_OPCODE_TXQS ||
  63           opcode == TGSI_OPCODE_TXQ_LZ ||
  64           opcode == TGSI_OPCODE_LODQ;
  65 }
  66
  67 /**
  68  * Is the opcode a "true" texture instruction which samples from a
  69  * texture map?
  70  */
  71 static bool
  72 is_texture_inst(unsigned opcode)
  73 {
  74    return (!is_mem_query_inst(opcode) &&
  75            tgsi_get_opcode_info(opcode)->is_tex);
  76 }
  77
  78
  79 /**
  80  * Is the opcode an instruction which computes a derivative explicitly or
  81  * implicitly?
  82  */
  83 static bool
  84 computes_derivative(unsigned opcode)
  85 {
  86    if (tgsi_get_opcode_info(opcode)->is_tex) {
  87       return opcode != TGSI_OPCODE_TG4 &&
  88              opcode != TGSI_OPCODE_TXD &&
  89              opcode != TGSI_OPCODE_TXF &&
  90              opcode != TGSI_OPCODE_TXF_LZ &&
  91              opcode != TGSI_OPCODE_TEX_LZ &&
  92              opcode != TGSI_OPCODE_TXL &&
  93              opcode != TGSI_OPCODE_TXL2 &&
  94              opcode != TGSI_OPCODE_TXQ &&
  95              opcode != TGSI_OPCODE_TXQ_LZ &&
  96              opcode != TGSI_OPCODE_TXQS;
  97    }
  98
  99    return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
 100           opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
 101           opcode == TGSI_OPCODE_SAMPLE ||
 102           opcode == TGSI_OPCODE_SAMPLE_B ||
 103           opcode == TGSI_OPCODE_SAMPLE_C;
 104 }
 105
 106
 107 static void
 108 scan_src_operand(struct tgsi_shader_info *info,
 109                  const struct tgsi_full_instruction *fullinst,
 110                  const struct tgsi_full_src_register *src,
 111                  unsigned src_index,
 112                  unsigned usage_mask,
 113                  bool is_interp_instruction,
 114                  bool *is_mem_inst)
 115 {
 116    int ind = src->Register.Index;
 117
 118    if (info->processor == PIPE_SHADER_COMPUTE &&
 119        src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
 120       unsigned swizzle[4], i, name;
 121
 122       name = info->system_value_semantic_name[src->Register.Index];
 123       swizzle[0] = src->Register.SwizzleX;
 124       swizzle[1] = src->Register.SwizzleY;
 125       swizzle[2] = src->Register.SwizzleZ;
 126       swizzle[3] = src->Register.SwizzleW;
 127
 128       switch (name) {
 129       case TGSI_SEMANTIC_THREAD_ID:
 130       case TGSI_SEMANTIC_BLOCK_ID:
 131          for (i = 0; i < 4; i++) {
 132             if (swizzle[i] <= TGSI_SWIZZLE_Z) {
 133                if (name == TGSI_SEMANTIC_THREAD_ID)
 134                   info->uses_thread_id[swizzle[i]] = true;
 135                else
 136                   info->uses_block_id[swizzle[i]] = true;
 137             }
 138          }
 139          break;
 140       case TGSI_SEMANTIC_BLOCK_SIZE:
 141          /* The block size is translated to IMM with a fixed block size. */
 142          if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
 143             info->uses_block_size = true;
 144          break;
 145       case TGSI_SEMANTIC_GRID_SIZE:
 146          info->uses_grid_size = true;
 147          break;
 148       }
 149    }
 150
 151    /* Mark which inputs are effectively used */
 152    if (src->Register.File == TGSI_FILE_INPUT) {
 153       if (src->Register.Indirect) {
 154          for (ind = 0; ind < info->num_inputs; ++ind) {
 155             info->input_usage_mask[ind] |= usage_mask;
 156          }
 157       } else {
 158          assert(ind >= 0);
 159          assert(ind < PIPE_MAX_SHADER_INPUTS);
 160          info->input_usage_mask[ind] |= usage_mask;
 161       }
 162
 163       if (info->processor == PIPE_SHADER_FRAGMENT) {
 164          unsigned name, index, input;
 165
 166          if (src->Register.Indirect && src->Indirect.ArrayID)
 167             input = info->input_array_first[src->Indirect.ArrayID];
 168          else
 169             input = src->Register.Index;
 170
 171          name = info->input_semantic_name[input];
 172          index = info->input_semantic_index[input];
 173
 174          if (name == TGSI_SEMANTIC_POSITION &&
 175              (src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
 176               src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
 177               src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
 178               src->Register.SwizzleW == TGSI_SWIZZLE_Z))
 179             info->reads_z = TRUE;
 180
 181          if (name == TGSI_SEMANTIC_COLOR) {
 182             unsigned mask =
 183                (1 << src->Register.SwizzleX) |
 184                (1 << src->Register.SwizzleY) |
 185                (1 << src->Register.SwizzleZ) |
 186                (1 << src->Register.SwizzleW);
 187
 188             info->colors_read |= mask << (index * 4);
 189          }
 190
 191          /* Process only interpolated varyings. Don't include POSITION.
 192           * Don't include integer varyings, because they are not
 193           * interpolated. Don't process inputs interpolated by INTERP
 194           * opcodes. Those are tracked separately.
 195           */
 196          if ((!is_interp_instruction || src_index != 0) &&
 197              (name == TGSI_SEMANTIC_GENERIC ||
 198               name == TGSI_SEMANTIC_TEXCOORD ||
 199               name == TGSI_SEMANTIC_COLOR ||
 200               name == TGSI_SEMANTIC_BCOLOR ||
 201               name == TGSI_SEMANTIC_FOG ||
 202               name == TGSI_SEMANTIC_CLIPDIST)) {
 203             switch (info->input_interpolate[input]) {
 204             case TGSI_INTERPOLATE_COLOR:
 205             case TGSI_INTERPOLATE_PERSPECTIVE:
 206                switch (info->input_interpolate_loc[input]) {
 207                case TGSI_INTERPOLATE_LOC_CENTER:
 208                   info->uses_persp_center = TRUE;
 209                   break;
 210                case TGSI_INTERPOLATE_LOC_CENTROID:
 211                   info->uses_persp_centroid = TRUE;
 212                   break;
 213                case TGSI_INTERPOLATE_LOC_SAMPLE:
 214                   info->uses_persp_sample = TRUE;
 215                   break;
 216                }
 217                break;
 218             case TGSI_INTERPOLATE_LINEAR:
 219                switch (info->input_interpolate_loc[input]) {
 220                case TGSI_INTERPOLATE_LOC_CENTER:
 221                   info->uses_linear_center = TRUE;
 222                   break;
 223                case TGSI_INTERPOLATE_LOC_CENTROID:
 224                   info->uses_linear_centroid = TRUE;
 225                   break;
 226                case TGSI_INTERPOLATE_LOC_SAMPLE:
 227                   info->uses_linear_sample = TRUE;
 228                   break;
 229                }
 230                break;
 231                /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
 232             }
 233          }
 234       }
 235    }
 236
 237    if (info->processor == PIPE_SHADER_TESS_CTRL &&
 238        src->Register.File == TGSI_FILE_OUTPUT) {
 239       unsigned input;
 240
 241       if (src->Register.Indirect && src->Indirect.ArrayID)
 242          input = info->output_array_first[src->Indirect.ArrayID];
 243       else
 244          input = src->Register.Index;
 245
 246       switch (info->output_semantic_name[input]) {
 247       case TGSI_SEMANTIC_PATCH:
 248          info->reads_perpatch_outputs = true;
 249          break;
 250       case TGSI_SEMANTIC_TESSINNER:
 251       case TGSI_SEMANTIC_TESSOUTER:
 252          info->reads_tessfactor_outputs = true;
 253          break;
 254       default:
 255          info->reads_pervertex_outputs = true;
 256       }
 257    }
 258
 259    /* check for indirect register reads */
 260    if (src->Register.Indirect) {
 261       info->indirect_files |= (1 << src->Register.File);
 262       info->indirect_files_read |= (1 << src->Register.File);
 263
 264       /* record indirect constant buffer indexing */
 265       if (src->Register.File == TGSI_FILE_CONSTANT) {
 266          if (src->Register.Dimension) {
 267             if (src->Dimension.Indirect)
 268                info->const_buffers_indirect = info->const_buffers_declared;
 269             else
 270                info->const_buffers_indirect |= 1u << src->Dimension.Index;
 271          } else {
 272             info->const_buffers_indirect |= 1;
 273          }
 274       }
 275    }
 276
 277    if (src->Register.Dimension && src->Dimension.Indirect)
 278       info->dim_indirect_files |= 1u << src->Register.File;
 279
 280    /* Texture samplers */
 281    if (src->Register.File == TGSI_FILE_SAMPLER) {
 282       const unsigned index = src->Register.Index;
 283
 284       assert(fullinst->Instruction.Texture);
 285       assert(index < ARRAY_SIZE(info->is_msaa_sampler));
 286       assert(index < PIPE_MAX_SAMPLERS);
 287
 288       if (is_texture_inst(fullinst->Instruction.Opcode)) {
 289          const unsigned target = fullinst->Texture.Texture;
 290          assert(target < TGSI_TEXTURE_UNKNOWN);
 291          /* for texture instructions, check that the texture instruction
 292           * target matches the previous sampler view declaration (if there
 293           * was one.)
 294           */
 295          if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
 296             /* probably no sampler view declaration */
 297             info->sampler_targets[index] = target;
 298          } else {
 299             /* Make sure the texture instruction's sampler/target info
 300              * agrees with the sampler view declaration.
 301              */
 302             assert(info->sampler_targets[index] == target);
 303          }
 304          /* MSAA samplers */
 305          if (target == TGSI_TEXTURE_2D_MSAA ||
 306              target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
 307             info->is_msaa_sampler[src->Register.Index] = TRUE;
 308          }
 309       }
 310    }
 311
 312    if (is_memory_file(src->Register.File) &&
 313        !is_mem_query_inst(fullinst->Instruction.Opcode)) {
 314       *is_mem_inst = true;
 315
 316       if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
 317          info->writes_memory = TRUE;
 318
 319          if (src->Register.File == TGSI_FILE_IMAGE) {
 320             if (src->Register.Indirect)
 321                info->images_atomic = info->images_declared;
 322             else
 323                info->images_atomic |= 1 << src->Register.Index;
 324          } else if (src->Register.File == TGSI_FILE_BUFFER) {
 325             if (src->Register.Indirect)
 326                info->shader_buffers_atomic = info->shader_buffers_declared;
 327             else
 328                info->shader_buffers_atomic |= 1 << src->Register.Index;
 329          }
 330       } else {
 331          if (src->Register.File == TGSI_FILE_IMAGE) {
 332             if (src->Register.Indirect)
 333                info->images_load = info->images_declared;
 334             else
 335                info->images_load |= 1 << src->Register.Index;
 336          } else if (src->Register.File == TGSI_FILE_BUFFER) {
 337             if (src->Register.Indirect)
 338                info->shader_buffers_load = info->shader_buffers_declared;
 339             else
 340                info->shader_buffers_load |= 1 << src->Register.Index;
 341          }
 342       }
 343    }
 344 }
 345
 346
 347 static void
 348 scan_instruction(struct tgsi_shader_info *info,
 349                  const struct tgsi_full_instruction *fullinst,
 350                  unsigned *current_depth)
 351 {
 352    unsigned i;
 353    bool is_mem_inst = false;
 354    bool is_interp_instruction = false;
 355
 356    assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
 357    info->opcode_count[fullinst->Instruction.Opcode]++;
 358
 359    switch (fullinst->Instruction.Opcode) {
 360    case TGSI_OPCODE_IF:
 361    case TGSI_OPCODE_UIF:
 362    case TGSI_OPCODE_BGNLOOP:
 363       (*current_depth)++;
 364       info->max_depth = MAX2(info->max_depth, *current_depth);
 365       break;
 366    case TGSI_OPCODE_ENDIF:
 367    case TGSI_OPCODE_ENDLOOP:
 368       (*current_depth)--;
 369       break;
 370    default:
 371       break;
 372    }
 373
 374    if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
 375        fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
 376        fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
 377       const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
 378       unsigned input;
 379
 380       is_interp_instruction = true;
 381
 382       if (src0->Register.Indirect && src0->Indirect.ArrayID)
 383          input = info->input_array_first[src0->Indirect.ArrayID];
 384       else
 385          input = src0->Register.Index;
 386
 387       /* For the INTERP opcodes, the interpolation is always
 388        * PERSPECTIVE unless LINEAR is specified.
 389        */
 390       switch (info->input_interpolate[input]) {
 391       case TGSI_INTERPOLATE_COLOR:
 392       case TGSI_INTERPOLATE_CONSTANT:
 393       case TGSI_INTERPOLATE_PERSPECTIVE:
 394          switch (fullinst->Instruction.Opcode) {
 395          case TGSI_OPCODE_INTERP_CENTROID:
 396             info->uses_persp_opcode_interp_centroid = TRUE;
 397             break;
 398          case TGSI_OPCODE_INTERP_OFFSET:
 399             info->uses_persp_opcode_interp_offset = TRUE;
 400             break;
 401          case TGSI_OPCODE_INTERP_SAMPLE:
 402             info->uses_persp_opcode_interp_sample = TRUE;
 403             break;
 404          }
 405          break;
 406
 407       case TGSI_INTERPOLATE_LINEAR:
 408          switch (fullinst->Instruction.Opcode) {
 409          case TGSI_OPCODE_INTERP_CENTROID:
 410             info->uses_linear_opcode_interp_centroid = TRUE;
 411             break;
 412          case TGSI_OPCODE_INTERP_OFFSET:
 413             info->uses_linear_opcode_interp_offset = TRUE;
 414             break;
 415          case TGSI_OPCODE_INTERP_SAMPLE:
 416             info->uses_linear_opcode_interp_sample = TRUE;
 417             break;
 418          }
 419          break;
 420       }
 421    }
 422
 423    if (fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
 424        fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG)
 425       info->uses_doubles = TRUE;
 426
 427    for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
 428       scan_src_operand(info, fullinst, &fullinst->Src[i], i,
 429                        tgsi_util_get_inst_usage_mask(fullinst, i),
 430                        is_interp_instruction, &is_mem_inst);
 431    }
 432
 433    if (fullinst->Instruction.Texture) {
 434       for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
 435          struct tgsi_full_src_register src = {{0}};
 436
 437          src.Register.File = fullinst->TexOffsets[i].File;
 438          src.Register.Index = fullinst->TexOffsets[i].Index;
 439          src.Register.SwizzleX = fullinst->TexOffsets[i].SwizzleX;
 440          src.Register.SwizzleY = fullinst->TexOffsets[i].SwizzleY;
 441          src.Register.SwizzleZ = fullinst->TexOffsets[i].SwizzleZ;
 442
 443          /* The usage mask is suboptimal but should be safe. */
 444          scan_src_operand(info, fullinst, &src, 0, TGSI_WRITEMASK_XYZ,
 445                           false, &is_mem_inst);
 446       }
 447    }
 448
 449    /* check for indirect register writes */
 450    for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
 451       const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
 452       if (dst->Register.Indirect) {
 453          info->indirect_files |= (1 << dst->Register.File);
 454          info->indirect_files_written |= (1 << dst->Register.File);
 455       }
 456
 457       if (dst->Register.Dimension && dst->Dimension.Indirect)
 458          info->dim_indirect_files |= 1u << dst->Register.File;
 459
 460       if (is_memory_file(dst->Register.File)) {
 461          assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
 462
 463          is_mem_inst = true;
 464          info->writes_memory = TRUE;
 465
 466          if (dst->Register.File == TGSI_FILE_IMAGE) {
 467             if (dst->Register.Indirect)
 468                info->images_store = info->images_declared;
 469             else
 470                info->images_store |= 1 << dst->Register.Index;
 471          } else if (dst->Register.File == TGSI_FILE_BUFFER) {
 472             if (dst->Register.Indirect)
 473                info->shader_buffers_store = info->shader_buffers_declared;
 474             else
 475                info->shader_buffers_store |= 1 << dst->Register.Index;
 476          }
 477       }
 478    }
 479
 480    if (is_mem_inst)
 481       info->num_memory_instructions++;
 482
 483    if (computes_derivative(fullinst->Instruction.Opcode))
 484       info->uses_derivatives = true;
 485
 486    info->num_instructions++;
 487 }
 488
 489
 490 static void
 491 scan_declaration(struct tgsi_shader_info *info,
 492                  const struct tgsi_full_declaration *fulldecl)
 493 {
 494    const uint file = fulldecl->Declaration.File;
 495    const unsigned procType = info->processor;
 496    uint reg;
 497
 498    if (fulldecl->Declaration.Array) {
 499       unsigned array_id = fulldecl->Array.ArrayID;
 500
 501       switch (file) {
 502       case TGSI_FILE_INPUT:
 503          assert(array_id < ARRAY_SIZE(info->input_array_first));
 504          info->input_array_first[array_id] = fulldecl->Range.First;
 505          info->input_array_last[array_id] = fulldecl->Range.Last;
 506          break;
 507       case TGSI_FILE_OUTPUT:
 508          assert(array_id < ARRAY_SIZE(info->output_array_first));
 509          info->output_array_first[array_id] = fulldecl->Range.First;
 510          info->output_array_last[array_id] = fulldecl->Range.Last;
 511          break;
 512       }
 513       info->array_max[file] = MAX2(info->array_max[file], array_id);
 514    }
 515
 516    for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
 517       unsigned semName = fulldecl->Semantic.Name;
 518       unsigned semIndex = fulldecl->Semantic.Index +
 519          (reg - fulldecl->Range.First);
 520       int buffer;
 521       unsigned index, target, type;
 522
 523       /* only first 32 regs will appear in this bitfield */
 524       info->file_mask[file] |= (1 << reg);
 525       info->file_count[file]++;
 526       info->file_max[file] = MAX2(info->file_max[file], (int)reg);
 527
 528       switch (file) {
 529       case TGSI_FILE_CONSTANT:
 530          buffer = 0;
 531
 532          if (fulldecl->Declaration.Dimension)
 533             buffer = fulldecl->Dim.Index2D;
 534
 535          info->const_file_max[buffer] =
 536             MAX2(info->const_file_max[buffer], (int)reg);
 537          info->const_buffers_declared |= 1u << buffer;
 538          break;
 539
 540       case TGSI_FILE_IMAGE:
 541          info->images_declared |= 1u << reg;
 542          if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
 543             info->images_buffers |= 1 << reg;
 544          break;
 545
 546       case TGSI_FILE_BUFFER:
 547          info->shader_buffers_declared |= 1u << reg;
 548          break;
 549
 550       case TGSI_FILE_INPUT:
 551          info->input_semantic_name[reg] = (ubyte) semName;
 552          info->input_semantic_index[reg] = (ubyte) semIndex;
 553          info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
 554          info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
 555          info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
 556
 557          /* Vertex shaders can have inputs with holes between them. */
 558          info->num_inputs = MAX2(info->num_inputs, reg + 1);
 559
 560          switch (semName) {
 561          case TGSI_SEMANTIC_PRIMID:
 562             info->uses_primid = true;
 563             break;
 564          case TGSI_SEMANTIC_POSITION:
 565             info->reads_position = true;
 566             break;
 567          case TGSI_SEMANTIC_FACE:
 568             info->uses_frontface = true;
 569             break;
 570          }
 571          break;
 572
 573       case TGSI_FILE_SYSTEM_VALUE:
 574          index = fulldecl->Range.First;
 575
 576          info->system_value_semantic_name[index] = semName;
 577          info->num_system_values = MAX2(info->num_system_values, index + 1);
 578
 579          switch (semName) {
 580          case TGSI_SEMANTIC_INSTANCEID:
 581             info->uses_instanceid = TRUE;
 582             break;
 583          case TGSI_SEMANTIC_VERTEXID:
 584             info->uses_vertexid = TRUE;
 585             break;
 586          case TGSI_SEMANTIC_VERTEXID_NOBASE:
 587             info->uses_vertexid_nobase = TRUE;
 588             break;
 589          case TGSI_SEMANTIC_BASEVERTEX:
 590             info->uses_basevertex = TRUE;
 591             break;
 592          case TGSI_SEMANTIC_PRIMID:
 593             info->uses_primid = TRUE;
 594             break;
 595          case TGSI_SEMANTIC_INVOCATIONID:
 596             info->uses_invocationid = TRUE;
 597             break;
 598          case TGSI_SEMANTIC_POSITION:
 599             info->reads_position = TRUE;
 600             break;
 601          case TGSI_SEMANTIC_FACE:
 602             info->uses_frontface = TRUE;
 603             break;
 604          case TGSI_SEMANTIC_SAMPLEMASK:
 605             info->reads_samplemask = TRUE;
 606             break;
 607          case TGSI_SEMANTIC_TESSINNER:
 608          case TGSI_SEMANTIC_TESSOUTER:
 609             info->reads_tess_factors = true;
 610             break;
 611          }
 612          break;
 613
 614       case TGSI_FILE_OUTPUT:
 615          info->output_semantic_name[reg] = (ubyte) semName;
 616          info->output_semantic_index[reg] = (ubyte) semIndex;
 617          info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
 618          info->num_outputs = MAX2(info->num_outputs, reg + 1);
 619
 620          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
 621             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
 622             info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
 623          }
 624          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
 625             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
 626             info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
 627          }
 628          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
 629             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
 630             info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
 631          }
 632          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
 633             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
 634             info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
 635          }
 636
 637          switch (semName) {
 638          case TGSI_SEMANTIC_PRIMID:
 639             info->writes_primid = true;
 640             break;
 641          case TGSI_SEMANTIC_VIEWPORT_INDEX:
 642             info->writes_viewport_index = true;
 643             break;
 644          case TGSI_SEMANTIC_LAYER:
 645             info->writes_layer = true;
 646             break;
 647          case TGSI_SEMANTIC_PSIZE:
 648             info->writes_psize = true;
 649             break;
 650          case TGSI_SEMANTIC_CLIPVERTEX:
 651             info->writes_clipvertex = true;
 652             break;
 653          case TGSI_SEMANTIC_COLOR:
 654             info->colors_written |= 1 << semIndex;
 655             break;
 656          case TGSI_SEMANTIC_STENCIL:
 657             info->writes_stencil = true;
 658             break;
 659          case TGSI_SEMANTIC_SAMPLEMASK:
 660             info->writes_samplemask = true;
 661             break;
 662          case TGSI_SEMANTIC_EDGEFLAG:
 663             info->writes_edgeflag = true;
 664             break;
 665          case TGSI_SEMANTIC_POSITION:
 666             if (procType == PIPE_SHADER_FRAGMENT)
 667                info->writes_z = true;
 668             else
 669                info->writes_position = true;
 670             break;
 671          }
 672          break;
 673
 674       case TGSI_FILE_SAMPLER:
 675          STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
 676          info->samplers_declared |= 1u << reg;
 677          break;
 678
 679       case TGSI_FILE_SAMPLER_VIEW:
 680          target = fulldecl->SamplerView.Resource;
 681          type = fulldecl->SamplerView.ReturnTypeX;
 682
 683          assert(target < TGSI_TEXTURE_UNKNOWN);
 684          if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
 685             /* Save sampler target for this sampler index */
 686             info->sampler_targets[reg] = target;
 687             info->sampler_type[reg] = type;
 688          } else {
 689             /* if previously declared, make sure targets agree */
 690             assert(info->sampler_targets[reg] == target);
 691             assert(info->sampler_type[reg] == type);
 692          }
 693          break;
 694       }
 695    }
 696 }
 697
 698
 699 static void
 700 scan_immediate(struct tgsi_shader_info *info)
 701 {
 702    uint reg = info->immediate_count++;
 703    uint file = TGSI_FILE_IMMEDIATE;
 704
 705    info->file_mask[file] |= (1 << reg);
 706    info->file_count[file]++;
 707    info->file_max[file] = MAX2(info->file_max[file], (int)reg);
 708 }
 709
 710
 711 static void
 712 scan_property(struct tgsi_shader_info *info,
 713               const struct tgsi_full_property *fullprop)
 714 {
 715    unsigned name = fullprop->Property.PropertyName;
 716    unsigned value = fullprop->u[0].Data;
 717
 718    assert(name < ARRAY_SIZE(info->properties));
 719    info->properties[name] = value;
 720
 721    switch (name) {
 722    case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
 723       info->num_written_clipdistance = value;
 724       info->clipdist_writemask |= (1 << value) - 1;
 725       break;
 726    case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
 727       info->num_written_culldistance = value;
 728       info->culldist_writemask |= (1 << value) - 1;
 729       break;
 730    }
 731 }
 732
 733
 734 /**
 735  * Scan the given TGSI shader to collect information such as number of
 736  * registers used, special instructions used, etc.
 737  * \return info  the result of the scan
 738  */
 739 void
 740 tgsi_scan_shader(const struct tgsi_token *tokens,
 741                  struct tgsi_shader_info *info)
 742 {
 743    uint procType, i;
 744    struct tgsi_parse_context parse;
 745    unsigned current_depth = 0;
 746
 747    memset(info, 0, sizeof(*info));
 748    for (i = 0; i < TGSI_FILE_COUNT; i++)
 749       info->file_max[i] = -1;
 750    for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
 751       info->const_file_max[i] = -1;
 752    info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
 753    for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
 754       info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
 755
 756    /**
 757     ** Setup to begin parsing input shader
 758     **/
 759    if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 760       debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
 761       return;
 762    }
 763    procType = parse.FullHeader.Processor.Processor;
 764    assert(procType == PIPE_SHADER_FRAGMENT ||
 765           procType == PIPE_SHADER_VERTEX ||
 766           procType == PIPE_SHADER_GEOMETRY ||
 767           procType == PIPE_SHADER_TESS_CTRL ||
 768           procType == PIPE_SHADER_TESS_EVAL ||
 769           procType == PIPE_SHADER_COMPUTE);
 770    info->processor = procType;
 771
 772    /**
 773     ** Loop over incoming program tokens/instructions
 774     */
 775    while (!tgsi_parse_end_of_tokens(&parse)) {
 776       info->num_tokens++;
 777
 778       tgsi_parse_token( &parse );
 779
 780       switch( parse.FullToken.Token.Type ) {
 781       case TGSI_TOKEN_TYPE_INSTRUCTION:
 782          scan_instruction(info, &parse.FullToken.FullInstruction,
 783                           &current_depth);
 784          break;
 785       case TGSI_TOKEN_TYPE_DECLARATION:
 786          scan_declaration(info, &parse.FullToken.FullDeclaration);
 787          break;
 788       case TGSI_TOKEN_TYPE_IMMEDIATE:
 789          scan_immediate(info);
 790          break;
 791       case TGSI_TOKEN_TYPE_PROPERTY:
 792          scan_property(info, &parse.FullToken.FullProperty);
 793          break;
 794       default:
 795          assert(!"Unexpected TGSI token type");
 796       }
 797    }
 798
 799    info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
 800                       info->opcode_count[TGSI_OPCODE_KILL]);
 801
 802    /* The dimensions of the IN decleration in geometry shader have
 803     * to be deduced from the type of the input primitive.
 804     */
 805    if (procType == PIPE_SHADER_GEOMETRY) {
 806       unsigned input_primitive =
 807             info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
 808       int num_verts = u_vertices_per_prim(input_primitive);
 809       int j;
 810       info->file_count[TGSI_FILE_INPUT] = num_verts;
 811       info->file_max[TGSI_FILE_INPUT] =
 812             MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
 813       for (j = 0; j < num_verts; ++j) {
 814          info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
 815       }
 816    }
 817
 818    tgsi_parse_free(&parse);
 819 }
 820
 821 /**
 822  * Collect information about the arrays of a given register file.
 823  *
 824  * @param tokens TGSI shader
 825  * @param file the register file to scan through
 826  * @param max_array_id number of entries in @p arrays; should be equal to the
 827  *                     highest array id, i.e. tgsi_shader_info::array_max[file].
 828  * @param arrays info for array of each ID will be written to arrays[ID - 1].
 829  */
 830 void
 831 tgsi_scan_arrays(const struct tgsi_token *tokens,
 832                  unsigned file,
 833                  unsigned max_array_id,
 834                  struct tgsi_array_info *arrays)
 835 {
 836    struct tgsi_parse_context parse;
 837
 838    if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
 839       debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
 840       return;
 841    }
 842
 843    memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
 844
 845    while (!tgsi_parse_end_of_tokens(&parse)) {
 846       struct tgsi_full_instruction *inst;
 847
 848       tgsi_parse_token(&parse);
 849
 850       if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
 851          struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
 852
 853          if (decl->Declaration.Array && decl->Declaration.File == file &&
 854              decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
 855             struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
 856             assert(!array->declared);
 857             array->declared = true;
 858             array->range = decl->Range;
 859          }
 860       }
 861
 862       if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
 863          continue;
 864
 865       inst = &parse.FullToken.FullInstruction;
 866       for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
 867          const struct tgsi_full_dst_register *dst = &inst->Dst[i];
 868          if (dst->Register.File != file)
 869             continue;
 870
 871          if (dst->Register.Indirect) {
 872             if (dst->Indirect.ArrayID > 0 &&
 873                 dst->Indirect.ArrayID <= max_array_id) {
 874                arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
 875             } else {
 876                /* Indirect writes without an ArrayID can write anywhere. */
 877                for (unsigned j = 0; j < max_array_id; ++j)
 878                   arrays[j].writemask |= dst->Register.WriteMask;
 879             }
 880          } else {
 881             /* Check whether the write falls into any of the arrays anyway. */
 882             for (unsigned j = 0; j < max_array_id; ++j) {
 883                struct tgsi_array_info *array = &arrays[j];
 884                if (array->declared &&
 885                    dst->Register.Index >= array->range.First &&
 886                    dst->Register.Index <= array->range.Last)
 887                   array->writemask |= dst->Register.WriteMask;
 888             }
 889          }
 890       }
 891    }
 892
 893    tgsi_parse_free(&parse);
 894
 895    return;
 896 }