src/gallium/auxiliary/tgsi/tgsi_scan.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 VMware, Inc.
   4  * All Rights Reserved.
   5  * Copyright 2008 VMware, Inc.  All rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  **************************************************************************/
  28
  29 /**
  30  * TGSI program scan utility.
  31  * Used to determine which registers and instructions are used by a shader.
  32  *
  33  * Authors:  Brian Paul
  34  */
  35
  36
  37 #include "util/u_debug.h"
  38 #include "util/u_math.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_prim.h"
  41 #include "tgsi/tgsi_info.h"
  42 #include "tgsi/tgsi_parse.h"
  43 #include "tgsi/tgsi_util.h"
  44 #include "tgsi/tgsi_scan.h"
  45
  46
  47 static bool
  48 is_memory_file(unsigned file)
  49 {
  50    return file == TGSI_FILE_SAMPLER ||
  51           file == TGSI_FILE_SAMPLER_VIEW ||
  52           file == TGSI_FILE_IMAGE ||
  53           file == TGSI_FILE_BUFFER;
  54 }
  55
  56
  57 static bool
  58 is_mem_query_inst(unsigned opcode)
  59 {
  60    return opcode == TGSI_OPCODE_RESQ ||
  61           opcode == TGSI_OPCODE_TXQ ||
  62           opcode == TGSI_OPCODE_TXQS ||
  63           opcode == TGSI_OPCODE_LODQ;
  64 }
  65
  66 /**
  67  * Is the opcode a "true" texture instruction which samples from a
  68  * texture map?
  69  */
  70 static bool
  71 is_texture_inst(unsigned opcode)
  72 {
  73    return (!is_mem_query_inst(opcode) &&
  74            tgsi_get_opcode_info(opcode)->is_tex);
  75 }
  76
  77
  78 /**
  79  * Is the opcode an instruction which computes a derivative explicitly or
  80  * implicitly?
  81  */
  82 static bool
  83 computes_derivative(unsigned opcode)
  84 {
  85    if (tgsi_get_opcode_info(opcode)->is_tex) {
  86       return opcode != TGSI_OPCODE_TG4 &&
  87              opcode != TGSI_OPCODE_TXD &&
  88              opcode != TGSI_OPCODE_TXF &&
  89              opcode != TGSI_OPCODE_TXF_LZ &&
  90              opcode != TGSI_OPCODE_TEX_LZ &&
  91              opcode != TGSI_OPCODE_TXL &&
  92              opcode != TGSI_OPCODE_TXL2 &&
  93              opcode != TGSI_OPCODE_TXQ &&
  94              opcode != TGSI_OPCODE_TXQS;
  95    }
  96
  97    return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
  98           opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
  99           opcode == TGSI_OPCODE_SAMPLE ||
 100           opcode == TGSI_OPCODE_SAMPLE_B ||
 101           opcode == TGSI_OPCODE_SAMPLE_C;
 102 }
 103
 104
 105 static void
 106 scan_src_operand(struct tgsi_shader_info *info,
 107                  const struct tgsi_full_instruction *fullinst,
 108                  const struct tgsi_full_src_register *src,
 109                  unsigned src_index,
 110                  unsigned usage_mask,
 111                  bool is_interp_instruction,
 112                  bool *is_mem_inst)
 113 {
 114    int ind = src->Register.Index;
 115
 116    if (info->processor == PIPE_SHADER_COMPUTE &&
 117        src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
 118       unsigned swizzle[4], i, name;
 119
 120       name = info->system_value_semantic_name[src->Register.Index];
 121       swizzle[0] = src->Register.SwizzleX;
 122       swizzle[1] = src->Register.SwizzleY;
 123       swizzle[2] = src->Register.SwizzleZ;
 124       swizzle[3] = src->Register.SwizzleW;
 125
 126       switch (name) {
 127       case TGSI_SEMANTIC_THREAD_ID:
 128       case TGSI_SEMANTIC_BLOCK_ID:
 129          for (i = 0; i < 4; i++) {
 130             if (swizzle[i] <= TGSI_SWIZZLE_Z) {
 131                if (name == TGSI_SEMANTIC_THREAD_ID)
 132                   info->uses_thread_id[swizzle[i]] = true;
 133                else
 134                   info->uses_block_id[swizzle[i]] = true;
 135             }
 136          }
 137          break;
 138       case TGSI_SEMANTIC_BLOCK_SIZE:
 139          /* The block size is translated to IMM with a fixed block size. */
 140          if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
 141             info->uses_block_size = true;
 142          break;
 143       case TGSI_SEMANTIC_GRID_SIZE:
 144          info->uses_grid_size = true;
 145          break;
 146       }
 147    }
 148
 149    /* Mark which inputs are effectively used */
 150    if (src->Register.File == TGSI_FILE_INPUT) {
 151       if (src->Register.Indirect) {
 152          for (ind = 0; ind < info->num_inputs; ++ind) {
 153             info->input_usage_mask[ind] |= usage_mask;
 154          }
 155       } else {
 156          assert(ind >= 0);
 157          assert(ind < PIPE_MAX_SHADER_INPUTS);
 158          info->input_usage_mask[ind] |= usage_mask;
 159       }
 160
 161       if (info->processor == PIPE_SHADER_FRAGMENT) {
 162          unsigned name, index, input;
 163
 164          if (src->Register.Indirect && src->Indirect.ArrayID)
 165             input = info->input_array_first[src->Indirect.ArrayID];
 166          else
 167             input = src->Register.Index;
 168
 169          name = info->input_semantic_name[input];
 170          index = info->input_semantic_index[input];
 171
 172          if (name == TGSI_SEMANTIC_POSITION &&
 173              (src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
 174               src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
 175               src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
 176               src->Register.SwizzleW == TGSI_SWIZZLE_Z))
 177             info->reads_z = TRUE;
 178
 179          if (name == TGSI_SEMANTIC_COLOR) {
 180             unsigned mask =
 181                (1 << src->Register.SwizzleX) |
 182                (1 << src->Register.SwizzleY) |
 183                (1 << src->Register.SwizzleZ) |
 184                (1 << src->Register.SwizzleW);
 185
 186             info->colors_read |= mask << (index * 4);
 187          }
 188
 189          /* Process only interpolated varyings. Don't include POSITION.
 190           * Don't include integer varyings, because they are not
 191           * interpolated. Don't process inputs interpolated by INTERP
 192           * opcodes. Those are tracked separately.
 193           */
 194          if ((!is_interp_instruction || src_index != 0) &&
 195              (name == TGSI_SEMANTIC_GENERIC ||
 196               name == TGSI_SEMANTIC_TEXCOORD ||
 197               name == TGSI_SEMANTIC_COLOR ||
 198               name == TGSI_SEMANTIC_BCOLOR ||
 199               name == TGSI_SEMANTIC_FOG ||
 200               name == TGSI_SEMANTIC_CLIPDIST)) {
 201             switch (info->input_interpolate[input]) {
 202             case TGSI_INTERPOLATE_COLOR:
 203             case TGSI_INTERPOLATE_PERSPECTIVE:
 204                switch (info->input_interpolate_loc[input]) {
 205                case TGSI_INTERPOLATE_LOC_CENTER:
 206                   info->uses_persp_center = TRUE;
 207                   break;
 208                case TGSI_INTERPOLATE_LOC_CENTROID:
 209                   info->uses_persp_centroid = TRUE;
 210                   break;
 211                case TGSI_INTERPOLATE_LOC_SAMPLE:
 212                   info->uses_persp_sample = TRUE;
 213                   break;
 214                }
 215                break;
 216             case TGSI_INTERPOLATE_LINEAR:
 217                switch (info->input_interpolate_loc[input]) {
 218                case TGSI_INTERPOLATE_LOC_CENTER:
 219                   info->uses_linear_center = TRUE;
 220                   break;
 221                case TGSI_INTERPOLATE_LOC_CENTROID:
 222                   info->uses_linear_centroid = TRUE;
 223                   break;
 224                case TGSI_INTERPOLATE_LOC_SAMPLE:
 225                   info->uses_linear_sample = TRUE;
 226                   break;
 227                }
 228                break;
 229                /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
 230             }
 231          }
 232       }
 233    }
 234
 235    if (info->processor == PIPE_SHADER_TESS_CTRL &&
 236        src->Register.File == TGSI_FILE_OUTPUT) {
 237       unsigned input;
 238
 239       if (src->Register.Indirect && src->Indirect.ArrayID)
 240          input = info->output_array_first[src->Indirect.ArrayID];
 241       else
 242          input = src->Register.Index;
 243
 244       switch (info->output_semantic_name[input]) {
 245       case TGSI_SEMANTIC_PATCH:
 246          info->reads_perpatch_outputs = true;
 247          break;
 248       case TGSI_SEMANTIC_TESSINNER:
 249       case TGSI_SEMANTIC_TESSOUTER:
 250          info->reads_tessfactor_outputs = true;
 251          break;
 252       default:
 253          info->reads_pervertex_outputs = true;
 254       }
 255    }
 256
 257    /* check for indirect register reads */
 258    if (src->Register.Indirect) {
 259       info->indirect_files |= (1 << src->Register.File);
 260       info->indirect_files_read |= (1 << src->Register.File);
 261
 262       /* record indirect constant buffer indexing */
 263       if (src->Register.File == TGSI_FILE_CONSTANT) {
 264          if (src->Register.Dimension) {
 265             if (src->Dimension.Indirect)
 266                info->const_buffers_indirect = info->const_buffers_declared;
 267             else
 268                info->const_buffers_indirect |= 1u << src->Dimension.Index;
 269          } else {
 270             info->const_buffers_indirect |= 1;
 271          }
 272       }
 273    }
 274
 275    if (src->Register.Dimension && src->Dimension.Indirect)
 276       info->dim_indirect_files |= 1u << src->Register.File;
 277
 278    /* Texture samplers */
 279    if (src->Register.File == TGSI_FILE_SAMPLER) {
 280       const unsigned index = src->Register.Index;
 281
 282       assert(fullinst->Instruction.Texture);
 283       assert(index < ARRAY_SIZE(info->is_msaa_sampler));
 284       assert(index < PIPE_MAX_SAMPLERS);
 285
 286       if (is_texture_inst(fullinst->Instruction.Opcode)) {
 287          const unsigned target = fullinst->Texture.Texture;
 288          assert(target < TGSI_TEXTURE_UNKNOWN);
 289          /* for texture instructions, check that the texture instruction
 290           * target matches the previous sampler view declaration (if there
 291           * was one.)
 292           */
 293          if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
 294             /* probably no sampler view declaration */
 295             info->sampler_targets[index] = target;
 296          } else {
 297             /* Make sure the texture instruction's sampler/target info
 298              * agrees with the sampler view declaration.
 299              */
 300             assert(info->sampler_targets[index] == target);
 301          }
 302          /* MSAA samplers */
 303          if (target == TGSI_TEXTURE_2D_MSAA ||
 304              target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
 305             info->is_msaa_sampler[src->Register.Index] = TRUE;
 306          }
 307       }
 308    }
 309
 310    if (is_memory_file(src->Register.File) &&
 311        !is_mem_query_inst(fullinst->Instruction.Opcode)) {
 312       *is_mem_inst = true;
 313
 314       if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
 315          info->writes_memory = TRUE;
 316
 317          if (src->Register.File == TGSI_FILE_IMAGE) {
 318             if (src->Register.Indirect)
 319                info->images_atomic = info->images_declared;
 320             else
 321                info->images_atomic |= 1 << src->Register.Index;
 322          } else if (src->Register.File == TGSI_FILE_BUFFER) {
 323             if (src->Register.Indirect)
 324                info->shader_buffers_atomic = info->shader_buffers_declared;
 325             else
 326                info->shader_buffers_atomic |= 1 << src->Register.Index;
 327          }
 328       } else {
 329          if (src->Register.File == TGSI_FILE_IMAGE) {
 330             if (src->Register.Indirect)
 331                info->images_load = info->images_declared;
 332             else
 333                info->images_load |= 1 << src->Register.Index;
 334          } else if (src->Register.File == TGSI_FILE_BUFFER) {
 335             if (src->Register.Indirect)
 336                info->shader_buffers_load = info->shader_buffers_declared;
 337             else
 338                info->shader_buffers_load |= 1 << src->Register.Index;
 339          }
 340       }
 341    }
 342 }
 343
 344
 345 static void
 346 scan_instruction(struct tgsi_shader_info *info,
 347                  const struct tgsi_full_instruction *fullinst,
 348                  unsigned *current_depth)
 349 {
 350    unsigned i;
 351    bool is_mem_inst = false;
 352    bool is_interp_instruction = false;
 353    unsigned sampler_src;
 354
 355    assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
 356    info->opcode_count[fullinst->Instruction.Opcode]++;
 357
 358    switch (fullinst->Instruction.Opcode) {
 359    case TGSI_OPCODE_IF:
 360    case TGSI_OPCODE_UIF:
 361    case TGSI_OPCODE_BGNLOOP:
 362       (*current_depth)++;
 363       info->max_depth = MAX2(info->max_depth, *current_depth);
 364       break;
 365    case TGSI_OPCODE_ENDIF:
 366    case TGSI_OPCODE_ENDLOOP:
 367       (*current_depth)--;
 368       break;
 369    case TGSI_OPCODE_TEX:
 370    case TGSI_OPCODE_TEX_LZ:
 371    case TGSI_OPCODE_TXB:
 372    case TGSI_OPCODE_TXD:
 373    case TGSI_OPCODE_TXL:
 374    case TGSI_OPCODE_TXP:
 375    case TGSI_OPCODE_TXQ:
 376    case TGSI_OPCODE_TXQS:
 377    case TGSI_OPCODE_TXF:
 378    case TGSI_OPCODE_TXF_LZ:
 379    case TGSI_OPCODE_TEX2:
 380    case TGSI_OPCODE_TXB2:
 381    case TGSI_OPCODE_TXL2:
 382    case TGSI_OPCODE_TG4:
 383    case TGSI_OPCODE_LODQ:
 384       sampler_src = fullinst->Instruction.NumSrcRegs - 1;
 385       if (fullinst->Src[sampler_src].Register.File != TGSI_FILE_SAMPLER)
 386          info->uses_bindless_samplers = true;
 387       break;
 388    case TGSI_OPCODE_RESQ:
 389    case TGSI_OPCODE_LOAD:
 390    case TGSI_OPCODE_ATOMUADD:
 391    case TGSI_OPCODE_ATOMXCHG:
 392    case TGSI_OPCODE_ATOMCAS:
 393    case TGSI_OPCODE_ATOMAND:
 394    case TGSI_OPCODE_ATOMOR:
 395    case TGSI_OPCODE_ATOMXOR:
 396    case TGSI_OPCODE_ATOMUMIN:
 397    case TGSI_OPCODE_ATOMUMAX:
 398    case TGSI_OPCODE_ATOMIMIN:
 399    case TGSI_OPCODE_ATOMIMAX:
 400       if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File))
 401          info->uses_bindless_images = true;
 402       break;
 403    case TGSI_OPCODE_STORE:
 404       if (tgsi_is_bindless_image_file(fullinst->Dst[0].Register.File))
 405          info->uses_bindless_images = true;
 406       break;
 407    default:
 408       break;
 409    }
 410
 411    if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
 412        fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
 413        fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
 414       const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
 415       unsigned input;
 416
 417       is_interp_instruction = true;
 418
 419       if (src0->Register.Indirect && src0->Indirect.ArrayID)
 420          input = info->input_array_first[src0->Indirect.ArrayID];
 421       else
 422          input = src0->Register.Index;
 423
 424       /* For the INTERP opcodes, the interpolation is always
 425        * PERSPECTIVE unless LINEAR is specified.
 426        */
 427       switch (info->input_interpolate[input]) {
 428       case TGSI_INTERPOLATE_COLOR:
 429       case TGSI_INTERPOLATE_CONSTANT:
 430       case TGSI_INTERPOLATE_PERSPECTIVE:
 431          switch (fullinst->Instruction.Opcode) {
 432          case TGSI_OPCODE_INTERP_CENTROID:
 433             info->uses_persp_opcode_interp_centroid = TRUE;
 434             break;
 435          case TGSI_OPCODE_INTERP_OFFSET:
 436             info->uses_persp_opcode_interp_offset = TRUE;
 437             break;
 438          case TGSI_OPCODE_INTERP_SAMPLE:
 439             info->uses_persp_opcode_interp_sample = TRUE;
 440             break;
 441          }
 442          break;
 443
 444       case TGSI_INTERPOLATE_LINEAR:
 445          switch (fullinst->Instruction.Opcode) {
 446          case TGSI_OPCODE_INTERP_CENTROID:
 447             info->uses_linear_opcode_interp_centroid = TRUE;
 448             break;
 449          case TGSI_OPCODE_INTERP_OFFSET:
 450             info->uses_linear_opcode_interp_offset = TRUE;
 451             break;
 452          case TGSI_OPCODE_INTERP_SAMPLE:
 453             info->uses_linear_opcode_interp_sample = TRUE;
 454             break;
 455          }
 456          break;
 457       }
 458    }
 459
 460    if ((fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
 461         fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG) ||
 462        fullinst->Instruction.Opcode == TGSI_OPCODE_DFMA ||
 463        fullinst->Instruction.Opcode == TGSI_OPCODE_DDIV ||
 464        fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
 465        fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
 466        fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
 467        fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
 468       info->uses_doubles = TRUE;
 469
 470    for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
 471       scan_src_operand(info, fullinst, &fullinst->Src[i], i,
 472                        tgsi_util_get_inst_usage_mask(fullinst, i),
 473                        is_interp_instruction, &is_mem_inst);
 474    }
 475
 476    if (fullinst->Instruction.Texture) {
 477       for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
 478          struct tgsi_full_src_register src = {{0}};
 479
 480          src.Register.File = fullinst->TexOffsets[i].File;
 481          src.Register.Index = fullinst->TexOffsets[i].Index;
 482          src.Register.SwizzleX = fullinst->TexOffsets[i].SwizzleX;
 483          src.Register.SwizzleY = fullinst->TexOffsets[i].SwizzleY;
 484          src.Register.SwizzleZ = fullinst->TexOffsets[i].SwizzleZ;
 485
 486          /* The usage mask is suboptimal but should be safe. */
 487          scan_src_operand(info, fullinst, &src, 0, TGSI_WRITEMASK_XYZ,
 488                           false, &is_mem_inst);
 489       }
 490    }
 491
 492    /* check for indirect register writes */
 493    for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
 494       const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
 495       if (dst->Register.Indirect) {
 496          info->indirect_files |= (1 << dst->Register.File);
 497          info->indirect_files_written |= (1 << dst->Register.File);
 498       }
 499
 500       if (dst->Register.Dimension && dst->Dimension.Indirect)
 501          info->dim_indirect_files |= 1u << dst->Register.File;
 502
 503       if (is_memory_file(dst->Register.File)) {
 504          assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
 505
 506          is_mem_inst = true;
 507          info->writes_memory = TRUE;
 508
 509          if (dst->Register.File == TGSI_FILE_IMAGE) {
 510             if (dst->Register.Indirect)
 511                info->images_store = info->images_declared;
 512             else
 513                info->images_store |= 1 << dst->Register.Index;
 514          } else if (dst->Register.File == TGSI_FILE_BUFFER) {
 515             if (dst->Register.Indirect)
 516                info->shader_buffers_store = info->shader_buffers_declared;
 517             else
 518                info->shader_buffers_store |= 1 << dst->Register.Index;
 519          }
 520       }
 521    }
 522
 523    if (is_mem_inst)
 524       info->num_memory_instructions++;
 525
 526    if (computes_derivative(fullinst->Instruction.Opcode))
 527       info->uses_derivatives = true;
 528
 529    info->num_instructions++;
 530 }
 531
 532
 533 static void
 534 scan_declaration(struct tgsi_shader_info *info,
 535                  const struct tgsi_full_declaration *fulldecl)
 536 {
 537    const uint file = fulldecl->Declaration.File;
 538    const unsigned procType = info->processor;
 539    uint reg;
 540
 541    if (fulldecl->Declaration.Array) {
 542       unsigned array_id = fulldecl->Array.ArrayID;
 543
 544       switch (file) {
 545       case TGSI_FILE_INPUT:
 546          assert(array_id < ARRAY_SIZE(info->input_array_first));
 547          info->input_array_first[array_id] = fulldecl->Range.First;
 548          info->input_array_last[array_id] = fulldecl->Range.Last;
 549          break;
 550       case TGSI_FILE_OUTPUT:
 551          assert(array_id < ARRAY_SIZE(info->output_array_first));
 552          info->output_array_first[array_id] = fulldecl->Range.First;
 553          info->output_array_last[array_id] = fulldecl->Range.Last;
 554          break;
 555       }
 556       info->array_max[file] = MAX2(info->array_max[file], array_id);
 557    }
 558
 559    for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
 560       unsigned semName = fulldecl->Semantic.Name;
 561       unsigned semIndex = fulldecl->Semantic.Index +
 562          (reg - fulldecl->Range.First);
 563       int buffer;
 564       unsigned index, target, type;
 565
 566       /* only first 32 regs will appear in this bitfield */
 567       info->file_mask[file] |= (1 << reg);
 568       info->file_count[file]++;
 569       info->file_max[file] = MAX2(info->file_max[file], (int)reg);
 570
 571       switch (file) {
 572       case TGSI_FILE_CONSTANT:
 573          buffer = 0;
 574
 575          if (fulldecl->Declaration.Dimension)
 576             buffer = fulldecl->Dim.Index2D;
 577
 578          info->const_file_max[buffer] =
 579             MAX2(info->const_file_max[buffer], (int)reg);
 580          info->const_buffers_declared |= 1u << buffer;
 581          break;
 582
 583       case TGSI_FILE_IMAGE:
 584          info->images_declared |= 1u << reg;
 585          if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
 586             info->images_buffers |= 1 << reg;
 587          break;
 588
 589       case TGSI_FILE_BUFFER:
 590          info->shader_buffers_declared |= 1u << reg;
 591          break;
 592
 593       case TGSI_FILE_INPUT:
 594          info->input_semantic_name[reg] = (ubyte) semName;
 595          info->input_semantic_index[reg] = (ubyte) semIndex;
 596          info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
 597          info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
 598          info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
 599
 600          /* Vertex shaders can have inputs with holes between them. */
 601          info->num_inputs = MAX2(info->num_inputs, reg + 1);
 602
 603          switch (semName) {
 604          case TGSI_SEMANTIC_PRIMID:
 605             info->uses_primid = true;
 606             break;
 607          case TGSI_SEMANTIC_POSITION:
 608             info->reads_position = true;
 609             break;
 610          case TGSI_SEMANTIC_FACE:
 611             info->uses_frontface = true;
 612             break;
 613          }
 614          break;
 615
 616       case TGSI_FILE_SYSTEM_VALUE:
 617          index = fulldecl->Range.First;
 618
 619          info->system_value_semantic_name[index] = semName;
 620          info->num_system_values = MAX2(info->num_system_values, index + 1);
 621
 622          switch (semName) {
 623          case TGSI_SEMANTIC_INSTANCEID:
 624             info->uses_instanceid = TRUE;
 625             break;
 626          case TGSI_SEMANTIC_VERTEXID:
 627             info->uses_vertexid = TRUE;
 628             break;
 629          case TGSI_SEMANTIC_VERTEXID_NOBASE:
 630             info->uses_vertexid_nobase = TRUE;
 631             break;
 632          case TGSI_SEMANTIC_BASEVERTEX:
 633             info->uses_basevertex = TRUE;
 634             break;
 635          case TGSI_SEMANTIC_PRIMID:
 636             info->uses_primid = TRUE;
 637             break;
 638          case TGSI_SEMANTIC_INVOCATIONID:
 639             info->uses_invocationid = TRUE;
 640             break;
 641          case TGSI_SEMANTIC_POSITION:
 642             info->reads_position = TRUE;
 643             break;
 644          case TGSI_SEMANTIC_FACE:
 645             info->uses_frontface = TRUE;
 646             break;
 647          case TGSI_SEMANTIC_SAMPLEMASK:
 648             info->reads_samplemask = TRUE;
 649             break;
 650          case TGSI_SEMANTIC_TESSINNER:
 651          case TGSI_SEMANTIC_TESSOUTER:
 652             info->reads_tess_factors = true;
 653             break;
 654          }
 655          break;
 656
 657       case TGSI_FILE_OUTPUT:
 658          info->output_semantic_name[reg] = (ubyte) semName;
 659          info->output_semantic_index[reg] = (ubyte) semIndex;
 660          info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
 661          info->num_outputs = MAX2(info->num_outputs, reg + 1);
 662
 663          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
 664             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
 665             info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
 666          }
 667          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
 668             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
 669             info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
 670          }
 671          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
 672             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
 673             info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
 674          }
 675          if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
 676             info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
 677             info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
 678          }
 679
 680          switch (semName) {
 681          case TGSI_SEMANTIC_PRIMID:
 682             info->writes_primid = true;
 683             break;
 684          case TGSI_SEMANTIC_VIEWPORT_INDEX:
 685             info->writes_viewport_index = true;
 686             break;
 687          case TGSI_SEMANTIC_LAYER:
 688             info->writes_layer = true;
 689             break;
 690          case TGSI_SEMANTIC_PSIZE:
 691             info->writes_psize = true;
 692             break;
 693          case TGSI_SEMANTIC_CLIPVERTEX:
 694             info->writes_clipvertex = true;
 695             break;
 696          case TGSI_SEMANTIC_COLOR:
 697             info->colors_written |= 1 << semIndex;
 698             break;
 699          case TGSI_SEMANTIC_STENCIL:
 700             info->writes_stencil = true;
 701             break;
 702          case TGSI_SEMANTIC_SAMPLEMASK:
 703             info->writes_samplemask = true;
 704             break;
 705          case TGSI_SEMANTIC_EDGEFLAG:
 706             info->writes_edgeflag = true;
 707             break;
 708          case TGSI_SEMANTIC_POSITION:
 709             if (procType == PIPE_SHADER_FRAGMENT)
 710                info->writes_z = true;
 711             else
 712                info->writes_position = true;
 713             break;
 714          }
 715          break;
 716
 717       case TGSI_FILE_SAMPLER:
 718          STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
 719          info->samplers_declared |= 1u << reg;
 720          break;
 721
 722       case TGSI_FILE_SAMPLER_VIEW:
 723          target = fulldecl->SamplerView.Resource;
 724          type = fulldecl->SamplerView.ReturnTypeX;
 725
 726          assert(target < TGSI_TEXTURE_UNKNOWN);
 727          if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
 728             /* Save sampler target for this sampler index */
 729             info->sampler_targets[reg] = target;
 730             info->sampler_type[reg] = type;
 731          } else {
 732             /* if previously declared, make sure targets agree */
 733             assert(info->sampler_targets[reg] == target);
 734             assert(info->sampler_type[reg] == type);
 735          }
 736          break;
 737       }
 738    }
 739 }
 740
 741
 742 static void
 743 scan_immediate(struct tgsi_shader_info *info)
 744 {
 745    uint reg = info->immediate_count++;
 746    uint file = TGSI_FILE_IMMEDIATE;
 747
 748    info->file_mask[file] |= (1 << reg);
 749    info->file_count[file]++;
 750    info->file_max[file] = MAX2(info->file_max[file], (int)reg);
 751 }
 752
 753
 754 static void
 755 scan_property(struct tgsi_shader_info *info,
 756               const struct tgsi_full_property *fullprop)
 757 {
 758    unsigned name = fullprop->Property.PropertyName;
 759    unsigned value = fullprop->u[0].Data;
 760
 761    assert(name < ARRAY_SIZE(info->properties));
 762    info->properties[name] = value;
 763
 764    switch (name) {
 765    case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
 766       info->num_written_clipdistance = value;
 767       info->clipdist_writemask |= (1 << value) - 1;
 768       break;
 769    case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
 770       info->num_written_culldistance = value;
 771       info->culldist_writemask |= (1 << value) - 1;
 772       break;
 773    }
 774 }
 775
 776
 777 /**
 778  * Scan the given TGSI shader to collect information such as number of
 779  * registers used, special instructions used, etc.
 780  * \return info  the result of the scan
 781  */
 782 void
 783 tgsi_scan_shader(const struct tgsi_token *tokens,
 784                  struct tgsi_shader_info *info)
 785 {
 786    uint procType, i;
 787    struct tgsi_parse_context parse;
 788    unsigned current_depth = 0;
 789
 790    memset(info, 0, sizeof(*info));
 791    for (i = 0; i < TGSI_FILE_COUNT; i++)
 792       info->file_max[i] = -1;
 793    for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
 794       info->const_file_max[i] = -1;
 795    info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
 796    for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
 797       info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
 798
 799    /**
 800     ** Setup to begin parsing input shader
 801     **/
 802    if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 803       debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
 804       return;
 805    }
 806    procType = parse.FullHeader.Processor.Processor;
 807    assert(procType == PIPE_SHADER_FRAGMENT ||
 808           procType == PIPE_SHADER_VERTEX ||
 809           procType == PIPE_SHADER_GEOMETRY ||
 810           procType == PIPE_SHADER_TESS_CTRL ||
 811           procType == PIPE_SHADER_TESS_EVAL ||
 812           procType == PIPE_SHADER_COMPUTE);
 813    info->processor = procType;
 814
 815    /**
 816     ** Loop over incoming program tokens/instructions
 817     */
 818    while (!tgsi_parse_end_of_tokens(&parse)) {
 819       info->num_tokens++;
 820
 821       tgsi_parse_token( &parse );
 822
 823       switch( parse.FullToken.Token.Type ) {
 824       case TGSI_TOKEN_TYPE_INSTRUCTION:
 825          scan_instruction(info, &parse.FullToken.FullInstruction,
 826                           &current_depth);
 827          break;
 828       case TGSI_TOKEN_TYPE_DECLARATION:
 829          scan_declaration(info, &parse.FullToken.FullDeclaration);
 830          break;
 831       case TGSI_TOKEN_TYPE_IMMEDIATE:
 832          scan_immediate(info);
 833          break;
 834       case TGSI_TOKEN_TYPE_PROPERTY:
 835          scan_property(info, &parse.FullToken.FullProperty);
 836          break;
 837       default:
 838          assert(!"Unexpected TGSI token type");
 839       }
 840    }
 841
 842    info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
 843                       info->opcode_count[TGSI_OPCODE_KILL]);
 844
 845    /* The dimensions of the IN decleration in geometry shader have
 846     * to be deduced from the type of the input primitive.
 847     */
 848    if (procType == PIPE_SHADER_GEOMETRY) {
 849       unsigned input_primitive =
 850             info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
 851       int num_verts = u_vertices_per_prim(input_primitive);
 852       int j;
 853       info->file_count[TGSI_FILE_INPUT] = num_verts;
 854       info->file_max[TGSI_FILE_INPUT] =
 855             MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
 856       for (j = 0; j < num_verts; ++j) {
 857          info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
 858       }
 859    }
 860
 861    tgsi_parse_free(&parse);
 862 }
 863
 864 /**
 865  * Collect information about the arrays of a given register file.
 866  *
 867  * @param tokens TGSI shader
 868  * @param file the register file to scan through
 869  * @param max_array_id number of entries in @p arrays; should be equal to the
 870  *                     highest array id, i.e. tgsi_shader_info::array_max[file].
 871  * @param arrays info for array of each ID will be written to arrays[ID - 1].
 872  */
 873 void
 874 tgsi_scan_arrays(const struct tgsi_token *tokens,
 875                  unsigned file,
 876                  unsigned max_array_id,
 877                  struct tgsi_array_info *arrays)
 878 {
 879    struct tgsi_parse_context parse;
 880
 881    if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
 882       debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
 883       return;
 884    }
 885
 886    memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
 887
 888    while (!tgsi_parse_end_of_tokens(&parse)) {
 889       struct tgsi_full_instruction *inst;
 890
 891       tgsi_parse_token(&parse);
 892
 893       if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
 894          struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
 895
 896          if (decl->Declaration.Array && decl->Declaration.File == file &&
 897              decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
 898             struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
 899             assert(!array->declared);
 900             array->declared = true;
 901             array->range = decl->Range;
 902          }
 903       }
 904
 905       if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
 906          continue;
 907
 908       inst = &parse.FullToken.FullInstruction;
 909       for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
 910          const struct tgsi_full_dst_register *dst = &inst->Dst[i];
 911          if (dst->Register.File != file)
 912             continue;
 913
 914          if (dst->Register.Indirect) {
 915             if (dst->Indirect.ArrayID > 0 &&
 916                 dst->Indirect.ArrayID <= max_array_id) {
 917                arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
 918             } else {
 919                /* Indirect writes without an ArrayID can write anywhere. */
 920                for (unsigned j = 0; j < max_array_id; ++j)
 921                   arrays[j].writemask |= dst->Register.WriteMask;
 922             }
 923          } else {
 924             /* Check whether the write falls into any of the arrays anyway. */
 925             for (unsigned j = 0; j < max_array_id; ++j) {
 926                struct tgsi_array_info *array = &arrays[j];
 927                if (array->declared &&
 928                    dst->Register.Index >= array->range.First &&
 929                    dst->Register.Index <= array->range.Last)
 930                   array->writemask |= dst->Register.WriteMask;
 931             }
 932          }
 933       }
 934    }
 935
 936    tgsi_parse_free(&parse);
 937
 938    return;
 939 }