src/gallium/auxiliary/util/u_cpu_detect.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Dennis Smit
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  20  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  **************************************************************************/
  26
  27 /**
  28  * @file
  29  * CPU feature detection.
  30  *
  31  * @author Dennis Smit
  32  * @author Based on the work of Eric Anholt <anholt@FreeBSD.org>
  33  */
  34
  35 #include "pipe/p_config.h"
  36
  37 #include "u_debug.h"
  38 #include "u_cpu_detect.h"
  39
  40 #if defined(PIPE_ARCH_PPC)
  41 #if defined(PIPE_OS_APPLE)
  42 #include <sys/sysctl.h>
  43 #else
  44 #include <signal.h>
  45 #include <setjmp.h>
  46 #endif
  47 #endif
  48
  49 #if defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
  50 #include <sys/param.h>
  51 #include <sys/sysctl.h>
  52 #include <machine/cpu.h>
  53 #endif
  54
  55 #if defined(PIPE_OS_FREEBSD) || defined(PIPE_OS_DRAGONFLY)
  56 #include <sys/types.h>
  57 #include <sys/sysctl.h>
  58 #endif
  59
  60 #if defined(PIPE_OS_LINUX)
  61 #include <signal.h>
  62 #include <fcntl.h>
  63 #include <elf.h>
  64 #endif
  65
  66 #ifdef PIPE_OS_UNIX
  67 #include <unistd.h>
  68 #endif
  69
  70 #if defined(HAS_ANDROID_CPUFEATURES)
  71 #include <cpu-features.h>
  72 #endif
  73
  74 #if defined(PIPE_OS_WINDOWS)
  75 #include <windows.h>
  76 #if defined(PIPE_CC_MSVC)
  77 #include <intrin.h>
  78 #endif
  79 #endif
  80
  81
  82 #ifdef DEBUG
  83 DEBUG_GET_ONCE_BOOL_OPTION(dump_cpu, "GALLIUM_DUMP_CPU", FALSE)
  84 #endif
  85
  86
  87 struct util_cpu_caps util_cpu_caps;
  88
  89 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
  90 static int has_cpuid(void);
  91 #endif
  92
  93
  94 #if defined(PIPE_ARCH_PPC) && !defined(PIPE_OS_APPLE)
  95 static jmp_buf  __lv_powerpc_jmpbuf;
  96 static volatile sig_atomic_t __lv_powerpc_canjump = 0;
  97
  98 static void
  99 sigill_handler(int sig)
 100 {
 101    if (!__lv_powerpc_canjump) {
 102       signal (sig, SIG_DFL);
 103       raise (sig);
 104    }
 105
 106    __lv_powerpc_canjump = 0;
 107    longjmp(__lv_powerpc_jmpbuf, 1);
 108 }
 109 #endif
 110
 111 #if defined(PIPE_ARCH_PPC)
 112 static void
 113 check_os_altivec_support(void)
 114 {
 115 #if defined(PIPE_OS_APPLE)
 116    int sels[2] = {CTL_HW, HW_VECTORUNIT};
 117    int has_vu = 0;
 118    int len = sizeof (has_vu);
 119    int err;
 120
 121    err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 122
 123    if (err == 0) {
 124       if (has_vu != 0) {
 125          util_cpu_caps.has_altivec = 1;
 126       }
 127    }
 128 #else /* !PIPE_OS_APPLE */
 129    /* not on Apple/Darwin, do it the brute-force way */
 130    /* this is borrowed from the libmpeg2 library */
 131    signal(SIGILL, sigill_handler);
 132    if (setjmp(__lv_powerpc_jmpbuf)) {
 133       signal(SIGILL, SIG_DFL);
 134    } else {
 135       boolean enable_altivec = TRUE;    /* Default: enable  if available, and if not overridden */
 136       boolean enable_vsx = TRUE;
 137 #ifdef DEBUG
 138       /* Disabling Altivec code generation is not the same as disabling VSX code generation,
 139        * which can be done simply by passing -mattr=-vsx to the LLVM compiler; cf.
 140        * lp_build_create_jit_compiler_for_module().
 141        * If you want to disable Altivec code generation, the best place to do it is here.
 142        */
 143       char *env_control = getenv("GALLIVM_ALTIVEC");    /* 1=enable (default); 0=disable */
 144       if (env_control && env_control[0] == '0') {
 145          enable_altivec = FALSE;
 146       }
 147 #endif
 148       /* VSX instructions can be explicitly enabled/disabled via GALLIVM_VSX=1 or 0 */
 149       char *env_vsx = getenv("GALLIVM_VSX");
 150       if (env_vsx && env_vsx[0] == '0') {
 151          enable_vsx = FALSE;
 152       }
 153       if (enable_altivec) {
 154          __lv_powerpc_canjump = 1;
 155
 156          __asm __volatile
 157             ("mtspr 256, %0\n\t"
 158              "vand %%v0, %%v0, %%v0"
 159              :
 160              : "r" (-1));
 161
 162          util_cpu_caps.has_altivec = 1;
 163
 164          if (enable_vsx) {
 165             __asm __volatile("xxland %vs0, %vs0, %vs0");
 166             util_cpu_caps.has_vsx = 1;
 167          }
 168          signal(SIGILL, SIG_DFL);
 169       } else {
 170          util_cpu_caps.has_altivec = 0;
 171       }
 172    }
 173 #endif /* !PIPE_OS_APPLE */
 174 }
 175 #endif /* PIPE_ARCH_PPC */
 176
 177
 178 #if defined(PIPE_ARCH_X86) || defined (PIPE_ARCH_X86_64)
 179 static int has_cpuid(void)
 180 {
 181 #if defined(PIPE_ARCH_X86)
 182 #if defined(PIPE_OS_GCC)
 183    int a, c;
 184
 185    __asm __volatile
 186       ("pushf\n"
 187        "popl %0\n"
 188        "movl %0, %1\n"
 189        "xorl $0x200000, %0\n"
 190        "push %0\n"
 191        "popf\n"
 192        "pushf\n"
 193        "popl %0\n"
 194        : "=a" (a), "=c" (c)
 195        :
 196        : "cc");
 197
 198    return a != c;
 199 #else
 200    /* FIXME */
 201    return 1;
 202 #endif
 203 #elif defined(PIPE_ARCH_X86_64)
 204    return 1;
 205 #else
 206    return 0;
 207 #endif
 208 }
 209
 210
 211 /**
 212  * @sa cpuid.h included in gcc-4.3 onwards.
 213  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh.aspx
 214  */
 215 static inline void
 216 cpuid(uint32_t ax, uint32_t *p)
 217 {
 218 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 219    __asm __volatile (
 220      "xchgl %%ebx, %1\n\t"
 221      "cpuid\n\t"
 222      "xchgl %%ebx, %1"
 223      : "=a" (p[0]),
 224        "=S" (p[1]),
 225        "=c" (p[2]),
 226        "=d" (p[3])
 227      : "0" (ax)
 228    );
 229 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 230    __asm __volatile (
 231      "cpuid\n\t"
 232      : "=a" (p[0]),
 233        "=b" (p[1]),
 234        "=c" (p[2]),
 235        "=d" (p[3])
 236      : "0" (ax)
 237    );
 238 #elif defined(PIPE_CC_MSVC)
 239    __cpuid(p, ax);
 240 #else
 241    p[0] = 0;
 242    p[1] = 0;
 243    p[2] = 0;
 244    p[3] = 0;
 245 #endif
 246 }
 247
 248 /**
 249  * @sa cpuid.h included in gcc-4.4 onwards.
 250  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh%28v=vs.90%29.aspx
 251  */
 252 static inline void
 253 cpuid_count(uint32_t ax, uint32_t cx, uint32_t *p)
 254 {
 255 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 256    __asm __volatile (
 257      "xchgl %%ebx, %1\n\t"
 258      "cpuid\n\t"
 259      "xchgl %%ebx, %1"
 260      : "=a" (p[0]),
 261        "=S" (p[1]),
 262        "=c" (p[2]),
 263        "=d" (p[3])
 264      : "0" (ax), "2" (cx)
 265    );
 266 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 267    __asm __volatile (
 268      "cpuid\n\t"
 269      : "=a" (p[0]),
 270        "=b" (p[1]),
 271        "=c" (p[2]),
 272        "=d" (p[3])
 273      : "0" (ax), "2" (cx)
 274    );
 275 #elif defined(PIPE_CC_MSVC)
 276    __cpuidex(p, ax, cx);
 277 #else
 278    p[0] = 0;
 279    p[1] = 0;
 280    p[2] = 0;
 281    p[3] = 0;
 282 #endif
 283 }
 284
 285
 286 static inline uint64_t xgetbv(void)
 287 {
 288 #if defined(PIPE_CC_GCC)
 289    uint32_t eax, edx;
 290
 291    __asm __volatile (
 292      ".byte 0x0f, 0x01, 0xd0" // xgetbv isn't supported on gcc < 4.4
 293      : "=a"(eax),
 294        "=d"(edx)
 295      : "c"(0)
 296    );
 297
 298    return ((uint64_t)edx << 32) | eax;
 299 #elif defined(PIPE_CC_MSVC) && defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
 300    return _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
 301 #else
 302    return 0;
 303 #endif
 304 }
 305
 306
 307 #if defined(PIPE_ARCH_X86)
 308 PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
 309 {
 310    struct {
 311       uint32_t pad1[7];
 312       uint32_t mxcsr_mask;
 313       uint32_t pad2[128-8];
 314    } PIPE_ALIGN_VAR(16) fxarea;
 315
 316    fxarea.mxcsr_mask = 0;
 317 #if defined(PIPE_CC_GCC)
 318    __asm __volatile ("fxsave %0" : "+m" (fxarea));
 319 #elif defined(PIPE_CC_MSVC) || defined(PIPE_CC_ICL)
 320    _fxsave(&fxarea);
 321 #else
 322    fxarea.mxcsr_mask = 0;
 323 #endif
 324    return !!(fxarea.mxcsr_mask & (1 << 6));
 325 }
 326 #endif
 327
 328 #endif /* X86 or X86_64 */
 329
 330 #if defined(PIPE_ARCH_ARM)
 331 static void
 332 check_os_arm_support(void)
 333 {
 334    /*
 335     * On Android, the cpufeatures library is preferred way of checking
 336     * CPU capabilities. However, it is not available for standalone Mesa
 337     * builds, i.e. when Android build system (Android.mk-based) is not
 338     * used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
 339     * have a separate macro that only gets enabled from respective Android.mk.
 340     */
 341 #if defined(HAS_ANDROID_CPUFEATURES)
 342    AndroidCpuFamily cpu_family = android_getCpuFamily();
 343    uint64_t cpu_features = android_getCpuFeatures();
 344
 345    if (cpu_family == ANDROID_CPU_FAMILY_ARM) {
 346       if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON)
 347          util_cpu_caps.has_neon = 1;
 348    }
 349 #elif defined(PIPE_OS_LINUX)
 350     Elf32_auxv_t aux;
 351     int fd;
 352
 353     fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
 354     if (fd >= 0) {
 355        while (read(fd, &aux, sizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {
 356           if (aux.a_type == AT_HWCAP) {
 357              uint32_t hwcap = aux.a_un.a_val;
 358
 359              util_cpu_caps.has_neon = (hwcap >> 12) & 1;
 360              break;
 361           }
 362        }
 363        close (fd);
 364     }
 365 #endif /* PIPE_OS_LINUX */
 366 }
 367 #endif /* PIPE_ARCH_ARM */
 368
 369 void
 370 util_cpu_detect(void)
 371 {
 372    static boolean util_cpu_detect_initialized = FALSE;
 373
 374    if(util_cpu_detect_initialized)
 375       return;
 376
 377    memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
 378
 379    /* Count the number of CPUs in system */
 380 #if defined(PIPE_OS_WINDOWS)
 381    {
 382       SYSTEM_INFO system_info;
 383       GetSystemInfo(&system_info);
 384       util_cpu_caps.nr_cpus = system_info.dwNumberOfProcessors;
 385    }
 386 #elif defined(PIPE_OS_UNIX) && defined(_SC_NPROCESSORS_ONLN)
 387    util_cpu_caps.nr_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 388    if (util_cpu_caps.nr_cpus == ~0)
 389       util_cpu_caps.nr_cpus = 1;
 390 #elif defined(PIPE_OS_BSD)
 391    {
 392       int mib[2], ncpu;
 393       int len;
 394
 395       mib[0] = CTL_HW;
 396       mib[1] = HW_NCPU;
 397
 398       len = sizeof (ncpu);
 399       sysctl(mib, 2, &ncpu, &len, NULL, 0);
 400       util_cpu_caps.nr_cpus = ncpu;
 401    }
 402 #else
 403    util_cpu_caps.nr_cpus = 1;
 404 #endif
 405
 406    /* Make the fallback cacheline size nonzero so that it can be
 407     * safely passed to align().
 408     */
 409    util_cpu_caps.cacheline = sizeof(void *);
 410
 411 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 412    if (has_cpuid()) {
 413       uint32_t regs[4];
 414       uint32_t regs2[4];
 415
 416       util_cpu_caps.cacheline = 32;
 417
 418       /* Get max cpuid level */
 419       cpuid(0x00000000, regs);
 420
 421       if (regs[0] >= 0x00000001) {
 422          unsigned int cacheline;
 423
 424          cpuid (0x00000001, regs2);
 425
 426          util_cpu_caps.x86_cpu_type = (regs2[0] >> 8) & 0xf;
 427          if (util_cpu_caps.x86_cpu_type == 0xf)
 428              util_cpu_caps.x86_cpu_type = 8 + ((regs2[0] >> 20) & 255); /* use extended family (P4, IA64) */
 429
 430          /* general feature flags */
 431          util_cpu_caps.has_tsc    = (regs2[3] >>  4) & 1; /* 0x0000010 */
 432          util_cpu_caps.has_mmx    = (regs2[3] >> 23) & 1; /* 0x0800000 */
 433          util_cpu_caps.has_sse    = (regs2[3] >> 25) & 1; /* 0x2000000 */
 434          util_cpu_caps.has_sse2   = (regs2[3] >> 26) & 1; /* 0x4000000 */
 435          util_cpu_caps.has_sse3   = (regs2[2] >>  0) & 1; /* 0x0000001 */
 436          util_cpu_caps.has_ssse3  = (regs2[2] >>  9) & 1; /* 0x0000020 */
 437          util_cpu_caps.has_sse4_1 = (regs2[2] >> 19) & 1;
 438          util_cpu_caps.has_sse4_2 = (regs2[2] >> 20) & 1;
 439          util_cpu_caps.has_popcnt = (regs2[2] >> 23) & 1;
 440          util_cpu_caps.has_avx    = ((regs2[2] >> 28) & 1) && // AVX
 441                                     ((regs2[2] >> 27) & 1) && // OSXSAVE
 442                                     ((xgetbv() & 6) == 6);    // XMM & YMM
 443          util_cpu_caps.has_f16c   = ((regs2[2] >> 29) & 1) && util_cpu_caps.has_avx;
 444          util_cpu_caps.has_fma    = ((regs2[2] >> 12) & 1) && util_cpu_caps.has_avx;
 445          util_cpu_caps.has_mmx2   = util_cpu_caps.has_sse; /* SSE cpus supports mmxext too */
 446 #if defined(PIPE_ARCH_X86_64)
 447          util_cpu_caps.has_daz = 1;
 448 #else
 449          util_cpu_caps.has_daz = util_cpu_caps.has_sse3 ||
 450             (util_cpu_caps.has_sse2 && sse2_has_daz());
 451 #endif
 452
 453          cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
 454          if (cacheline > 0)
 455             util_cpu_caps.cacheline = cacheline;
 456       }
 457       if (util_cpu_caps.has_avx && regs[0] >= 0x00000007) {
 458          uint32_t regs7[4];
 459          cpuid_count(0x00000007, 0x00000000, regs7);
 460          util_cpu_caps.has_avx2 = (regs7[1] >> 5) & 1;
 461       }
 462
 463       // check for avx512
 464       if (((regs2[2] >> 27) & 1) && // OSXSAVE
 465           (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS
 466           ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS
 467          uint32_t regs3[4];
 468          cpuid_count(0x00000007, 0x00000000, regs3);
 469          util_cpu_caps.has_avx512f    = (regs3[1] >> 16) & 1;
 470          util_cpu_caps.has_avx512dq   = (regs3[1] >> 17) & 1;
 471          util_cpu_caps.has_avx512ifma = (regs3[1] >> 21) & 1;
 472          util_cpu_caps.has_avx512pf   = (regs3[1] >> 26) & 1;
 473          util_cpu_caps.has_avx512er   = (regs3[1] >> 27) & 1;
 474          util_cpu_caps.has_avx512cd   = (regs3[1] >> 28) & 1;
 475          util_cpu_caps.has_avx512bw   = (regs3[1] >> 30) & 1;
 476          util_cpu_caps.has_avx512vl   = (regs3[1] >> 31) & 1;
 477          util_cpu_caps.has_avx512vbmi = (regs3[2] >>  1) & 1;
 478       }
 479
 480       if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69) {
 481          /* GenuineIntel */
 482          util_cpu_caps.has_intel = 1;
 483       }
 484
 485       cpuid(0x80000000, regs);
 486
 487       if (regs[0] >= 0x80000001) {
 488
 489          cpuid(0x80000001, regs2);
 490
 491          util_cpu_caps.has_mmx  |= (regs2[3] >> 23) & 1;
 492          util_cpu_caps.has_mmx2 |= (regs2[3] >> 22) & 1;
 493          util_cpu_caps.has_3dnow = (regs2[3] >> 31) & 1;
 494          util_cpu_caps.has_3dnow_ext = (regs2[3] >> 30) & 1;
 495
 496          util_cpu_caps.has_xop = util_cpu_caps.has_avx &&
 497                                  ((regs2[2] >> 11) & 1);
 498       }
 499
 500       if (regs[0] >= 0x80000006) {
 501          /* should we really do this if the clflush size above worked? */
 502          unsigned int cacheline;
 503          cpuid(0x80000006, regs2);
 504          cacheline = regs2[2] & 0xFF;
 505          if (cacheline > 0)
 506             util_cpu_caps.cacheline = cacheline;
 507       }
 508
 509       if (!util_cpu_caps.has_sse) {
 510          util_cpu_caps.has_sse2 = 0;
 511          util_cpu_caps.has_sse3 = 0;
 512          util_cpu_caps.has_ssse3 = 0;
 513          util_cpu_caps.has_sse4_1 = 0;
 514       }
 515    }
 516 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
 517
 518 #if defined(PIPE_ARCH_ARM)
 519    check_os_arm_support();
 520 #endif
 521
 522 #if defined(PIPE_ARCH_PPC)
 523    check_os_altivec_support();
 524 #endif /* PIPE_ARCH_PPC */
 525
 526 #ifdef DEBUG
 527    if (debug_get_option_dump_cpu()) {
 528       debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
 529
 530       debug_printf("util_cpu_caps.x86_cpu_type = %u\n", util_cpu_caps.x86_cpu_type);
 531       debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
 532
 533       debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps.has_tsc);
 534       debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps.has_mmx);
 535       debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps.has_mmx2);
 536       debug_printf("util_cpu_caps.has_sse = %u\n", util_cpu_caps.has_sse);
 537       debug_printf("util_cpu_caps.has_sse2 = %u\n", util_cpu_caps.has_sse2);
 538       debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps.has_sse3);
 539       debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps.has_ssse3);
 540       debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps.has_sse4_1);
 541       debug_printf("util_cpu_caps.has_sse4_2 = %u\n", util_cpu_caps.has_sse4_2);
 542       debug_printf("util_cpu_caps.has_avx = %u\n", util_cpu_caps.has_avx);
 543       debug_printf("util_cpu_caps.has_avx2 = %u\n", util_cpu_caps.has_avx2);
 544       debug_printf("util_cpu_caps.has_f16c = %u\n", util_cpu_caps.has_f16c);
 545       debug_printf("util_cpu_caps.has_popcnt = %u\n", util_cpu_caps.has_popcnt);
 546       debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps.has_3dnow);
 547       debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps.has_3dnow_ext);
 548       debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
 549       debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps.has_altivec);
 550       debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx);
 551       debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
 552       debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
 553       debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f);
 554       debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq);
 555       debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma);
 556       debug_printf("util_cpu_caps.has_avx512pf = %u\n", util_cpu_caps.has_avx512pf);
 557       debug_printf("util_cpu_caps.has_avx512er = %u\n", util_cpu_caps.has_avx512er);
 558       debug_printf("util_cpu_caps.has_avx512cd = %u\n", util_cpu_caps.has_avx512cd);
 559       debug_printf("util_cpu_caps.has_avx512bw = %u\n", util_cpu_caps.has_avx512bw);
 560       debug_printf("util_cpu_caps.has_avx512vl = %u\n", util_cpu_caps.has_avx512vl);
 561       debug_printf("util_cpu_caps.has_avx512vbmi = %u\n", util_cpu_caps.has_avx512vbmi);
 562    }
 563 #endif
 564
 565    util_cpu_detect_initialized = TRUE;
 566 }