src/gallium/auxiliary/util/u_cpu_detect.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Dennis Smit
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  20  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  **************************************************************************/
  26
  27 /**
  28  * @file
  29  * CPU feature detection.
  30  *
  31  * @author Dennis Smit
  32  * @author Based on the work of Eric Anholt <anholt@FreeBSD.org>
  33  */
  34
  35 #include "pipe/p_config.h"
  36
  37 #include "u_debug.h"
  38 #include "u_cpu_detect.h"
  39
  40 #if defined(PIPE_ARCH_PPC)
  41 #if defined(PIPE_OS_APPLE)
  42 #include <sys/sysctl.h>
  43 #else
  44 #include <signal.h>
  45 #include <setjmp.h>
  46 #endif
  47 #endif
  48
  49 #if defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
  50 #include <sys/param.h>
  51 #include <sys/sysctl.h>
  52 #include <machine/cpu.h>
  53 #endif
  54
  55 #if defined(PIPE_OS_FREEBSD) || defined(PIPE_OS_DRAGONFLY)
  56 #include <sys/types.h>
  57 #include <sys/sysctl.h>
  58 #endif
  59
  60 #if defined(PIPE_OS_LINUX)
  61 #include <signal.h>
  62 #include <fcntl.h>
  63 #include <elf.h>
  64 #endif
  65
  66 #ifdef PIPE_OS_UNIX
  67 #include <unistd.h>
  68 #endif
  69
  70 #if defined(HAS_ANDROID_CPUFEATURES)
  71 #include <cpu-features.h>
  72 #endif
  73
  74 #if defined(PIPE_OS_WINDOWS)
  75 #include <windows.h>
  76 #if defined(PIPE_CC_MSVC)
  77 #include <intrin.h>
  78 #endif
  79 #endif
  80
  81
  82 #ifdef DEBUG
  83 DEBUG_GET_ONCE_BOOL_OPTION(dump_cpu, "GALLIUM_DUMP_CPU", FALSE)
  84 #endif
  85
  86
  87 struct util_cpu_caps util_cpu_caps;
  88
  89 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
  90 static int has_cpuid(void);
  91 #endif
  92
  93
  94 #if defined(PIPE_ARCH_PPC) && !defined(PIPE_OS_APPLE)
  95 static jmp_buf  __lv_powerpc_jmpbuf;
  96 static volatile sig_atomic_t __lv_powerpc_canjump = 0;
  97
  98 static void
  99 sigill_handler(int sig)
 100 {
 101    if (!__lv_powerpc_canjump) {
 102       signal (sig, SIG_DFL);
 103       raise (sig);
 104    }
 105
 106    __lv_powerpc_canjump = 0;
 107    longjmp(__lv_powerpc_jmpbuf, 1);
 108 }
 109 #endif
 110
 111 #if defined(PIPE_ARCH_PPC)
 112 static void
 113 check_os_altivec_support(void)
 114 {
 115 #if defined(PIPE_OS_APPLE)
 116    int sels[2] = {CTL_HW, HW_VECTORUNIT};
 117    int has_vu = 0;
 118    int len = sizeof (has_vu);
 119    int err;
 120
 121    err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 122
 123    if (err == 0) {
 124       if (has_vu != 0) {
 125          util_cpu_caps.has_altivec = 1;
 126       }
 127    }
 128 #else /* !PIPE_OS_APPLE */
 129    /* not on Apple/Darwin, do it the brute-force way */
 130    /* this is borrowed from the libmpeg2 library */
 131    signal(SIGILL, sigill_handler);
 132    if (setjmp(__lv_powerpc_jmpbuf)) {
 133       signal(SIGILL, SIG_DFL);
 134    } else {
 135       boolean enable_altivec = TRUE;    /* Default: enable  if available, and if not overridden */
 136 #ifdef DEBUG
 137       /* Disabling Altivec code generation is not the same as disabling VSX code generation,
 138        * which can be done simply by passing -mattr=-vsx to the LLVM compiler; cf.
 139        * lp_build_create_jit_compiler_for_module().
 140        * If you want to disable Altivec code generation, the best place to do it is here.
 141        */
 142       char *env_control = getenv("GALLIVM_ALTIVEC");    /* 1=enable (default); 0=disable */
 143       if (env_control && env_control[0] == '0') {
 144          enable_altivec = FALSE;
 145       }
 146 #endif
 147       if (enable_altivec) {
 148          __lv_powerpc_canjump = 1;
 149
 150          __asm __volatile
 151             ("mtspr 256, %0\n\t"
 152              "vand %%v0, %%v0, %%v0"
 153              :
 154              : "r" (-1));
 155
 156          signal(SIGILL, SIG_DFL);
 157          util_cpu_caps.has_altivec = 1;
 158       } else {
 159          util_cpu_caps.has_altivec = 0;
 160       }
 161    }
 162 #endif /* !PIPE_OS_APPLE */
 163 }
 164 #endif /* PIPE_ARCH_PPC */
 165
 166
 167 #if defined(PIPE_ARCH_X86) || defined (PIPE_ARCH_X86_64)
 168 static int has_cpuid(void)
 169 {
 170 #if defined(PIPE_ARCH_X86)
 171 #if defined(PIPE_OS_GCC)
 172    int a, c;
 173
 174    __asm __volatile
 175       ("pushf\n"
 176        "popl %0\n"
 177        "movl %0, %1\n"
 178        "xorl $0x200000, %0\n"
 179        "push %0\n"
 180        "popf\n"
 181        "pushf\n"
 182        "popl %0\n"
 183        : "=a" (a), "=c" (c)
 184        :
 185        : "cc");
 186
 187    return a != c;
 188 #else
 189    /* FIXME */
 190    return 1;
 191 #endif
 192 #elif defined(PIPE_ARCH_X86_64)
 193    return 1;
 194 #else
 195    return 0;
 196 #endif
 197 }
 198
 199
 200 /**
 201  * @sa cpuid.h included in gcc-4.3 onwards.
 202  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh.aspx
 203  */
 204 static inline void
 205 cpuid(uint32_t ax, uint32_t *p)
 206 {
 207 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 208    __asm __volatile (
 209      "xchgl %%ebx, %1\n\t"
 210      "cpuid\n\t"
 211      "xchgl %%ebx, %1"
 212      : "=a" (p[0]),
 213        "=S" (p[1]),
 214        "=c" (p[2]),
 215        "=d" (p[3])
 216      : "0" (ax)
 217    );
 218 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 219    __asm __volatile (
 220      "cpuid\n\t"
 221      : "=a" (p[0]),
 222        "=b" (p[1]),
 223        "=c" (p[2]),
 224        "=d" (p[3])
 225      : "0" (ax)
 226    );
 227 #elif defined(PIPE_CC_MSVC)
 228    __cpuid(p, ax);
 229 #else
 230    p[0] = 0;
 231    p[1] = 0;
 232    p[2] = 0;
 233    p[3] = 0;
 234 #endif
 235 }
 236
 237 /**
 238  * @sa cpuid.h included in gcc-4.4 onwards.
 239  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh%28v=vs.90%29.aspx
 240  */
 241 static inline void
 242 cpuid_count(uint32_t ax, uint32_t cx, uint32_t *p)
 243 {
 244 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 245    __asm __volatile (
 246      "xchgl %%ebx, %1\n\t"
 247      "cpuid\n\t"
 248      "xchgl %%ebx, %1"
 249      : "=a" (p[0]),
 250        "=S" (p[1]),
 251        "=c" (p[2]),
 252        "=d" (p[3])
 253      : "0" (ax), "2" (cx)
 254    );
 255 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 256    __asm __volatile (
 257      "cpuid\n\t"
 258      : "=a" (p[0]),
 259        "=b" (p[1]),
 260        "=c" (p[2]),
 261        "=d" (p[3])
 262      : "0" (ax), "2" (cx)
 263    );
 264 #elif defined(PIPE_CC_MSVC)
 265    __cpuidex(p, ax, cx);
 266 #else
 267    p[0] = 0;
 268    p[1] = 0;
 269    p[2] = 0;
 270    p[3] = 0;
 271 #endif
 272 }
 273
 274
 275 static inline uint64_t xgetbv(void)
 276 {
 277 #if defined(PIPE_CC_GCC)
 278    uint32_t eax, edx;
 279
 280    __asm __volatile (
 281      ".byte 0x0f, 0x01, 0xd0" // xgetbv isn't supported on gcc < 4.4
 282      : "=a"(eax),
 283        "=d"(edx)
 284      : "c"(0)
 285    );
 286
 287    return ((uint64_t)edx << 32) | eax;
 288 #elif defined(PIPE_CC_MSVC) && defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
 289    return _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
 290 #else
 291    return 0;
 292 #endif
 293 }
 294
 295
 296 #if defined(PIPE_ARCH_X86)
 297 PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
 298 {
 299    struct {
 300       uint32_t pad1[7];
 301       uint32_t mxcsr_mask;
 302       uint32_t pad2[128-8];
 303    } PIPE_ALIGN_VAR(16) fxarea;
 304
 305    fxarea.mxcsr_mask = 0;
 306 #if defined(PIPE_CC_GCC)
 307    __asm __volatile ("fxsave %0" : "+m" (fxarea));
 308 #elif defined(PIPE_CC_MSVC) || defined(PIPE_CC_ICL)
 309    _fxsave(&fxarea);
 310 #else
 311    fxarea.mxcsr_mask = 0;
 312 #endif
 313    return !!(fxarea.mxcsr_mask & (1 << 6));
 314 }
 315 #endif
 316
 317 #endif /* X86 or X86_64 */
 318
 319 #if defined(PIPE_ARCH_ARM)
 320 static void
 321 check_os_arm_support(void)
 322 {
 323    /*
 324     * On Android, the cpufeatures library is preferred way of checking
 325     * CPU capabilities. However, it is not available for standalone Mesa
 326     * builds, i.e. when Android build system (Android.mk-based) is not
 327     * used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
 328     * have a separate macro that only gets enabled from respective Android.mk.
 329     */
 330 #if defined(HAS_ANDROID_CPUFEATURES)
 331    AndroidCpuFamily cpu_family = android_getCpuFamily();
 332    uint64_t cpu_features = android_getCpuFeatures();
 333
 334    if (cpu_family == ANDROID_CPU_FAMILY_ARM) {
 335       if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON)
 336          util_cpu_caps.has_neon = 1;
 337    }
 338 #elif defined(PIPE_OS_LINUX)
 339     Elf32_auxv_t aux;
 340     int fd;
 341
 342     fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
 343     if (fd >= 0) {
 344        while (read(fd, &aux, sizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {
 345           if (aux.a_type == AT_HWCAP) {
 346              uint32_t hwcap = aux.a_un.a_val;
 347
 348              util_cpu_caps.has_neon = (hwcap >> 12) & 1;
 349              break;
 350           }
 351        }
 352        close (fd);
 353     }
 354 #endif /* PIPE_OS_LINUX */
 355 }
 356 #endif /* PIPE_ARCH_ARM */
 357
 358 void
 359 util_cpu_detect(void)
 360 {
 361    static boolean util_cpu_detect_initialized = FALSE;
 362
 363    if(util_cpu_detect_initialized)
 364       return;
 365
 366    memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
 367
 368    /* Count the number of CPUs in system */
 369 #if defined(PIPE_OS_WINDOWS)
 370    {
 371       SYSTEM_INFO system_info;
 372       GetSystemInfo(&system_info);
 373       util_cpu_caps.nr_cpus = system_info.dwNumberOfProcessors;
 374    }
 375 #elif defined(PIPE_OS_UNIX) && defined(_SC_NPROCESSORS_ONLN)
 376    util_cpu_caps.nr_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 377    if (util_cpu_caps.nr_cpus == ~0u)
 378       util_cpu_caps.nr_cpus = 1;
 379 #elif defined(PIPE_OS_BSD)
 380    {
 381       int mib[2], ncpu;
 382       int len;
 383
 384       mib[0] = CTL_HW;
 385       mib[1] = HW_NCPU;
 386
 387       len = sizeof (ncpu);
 388       sysctl(mib, 2, &ncpu, &len, NULL, 0);
 389       util_cpu_caps.nr_cpus = ncpu;
 390    }
 391 #else
 392    util_cpu_caps.nr_cpus = 1;
 393 #endif
 394
 395    /* Make the fallback cacheline size nonzero so that it can be
 396     * safely passed to align().
 397     */
 398    util_cpu_caps.cacheline = sizeof(void *);
 399
 400 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 401    if (has_cpuid()) {
 402       uint32_t regs[4];
 403       uint32_t regs2[4];
 404
 405       util_cpu_caps.cacheline = 32;
 406
 407       /* Get max cpuid level */
 408       cpuid(0x00000000, regs);
 409
 410       if (regs[0] >= 0x00000001) {
 411          unsigned int cacheline;
 412
 413          cpuid (0x00000001, regs2);
 414
 415          util_cpu_caps.x86_cpu_type = (regs2[0] >> 8) & 0xf;
 416          if (util_cpu_caps.x86_cpu_type == 0xf)
 417              util_cpu_caps.x86_cpu_type = 8 + ((regs2[0] >> 20) & 255); /* use extended family (P4, IA64) */
 418
 419          /* general feature flags */
 420          util_cpu_caps.has_tsc    = (regs2[3] >>  4) & 1; /* 0x0000010 */
 421          util_cpu_caps.has_mmx    = (regs2[3] >> 23) & 1; /* 0x0800000 */
 422          util_cpu_caps.has_sse    = (regs2[3] >> 25) & 1; /* 0x2000000 */
 423          util_cpu_caps.has_sse2   = (regs2[3] >> 26) & 1; /* 0x4000000 */
 424          util_cpu_caps.has_sse3   = (regs2[2] >>  0) & 1; /* 0x0000001 */
 425          util_cpu_caps.has_ssse3  = (regs2[2] >>  9) & 1; /* 0x0000020 */
 426          util_cpu_caps.has_sse4_1 = (regs2[2] >> 19) & 1;
 427          util_cpu_caps.has_sse4_2 = (regs2[2] >> 20) & 1;
 428          util_cpu_caps.has_popcnt = (regs2[2] >> 23) & 1;
 429          util_cpu_caps.has_avx    = ((regs2[2] >> 28) & 1) && // AVX
 430                                     ((regs2[2] >> 27) & 1) && // OSXSAVE
 431                                     ((xgetbv() & 6) == 6);    // XMM & YMM
 432          util_cpu_caps.has_f16c   = ((regs2[2] >> 29) & 1) && util_cpu_caps.has_avx;
 433          util_cpu_caps.has_fma    = ((regs2[2] >> 12) & 1) && util_cpu_caps.has_avx;
 434          util_cpu_caps.has_mmx2   = util_cpu_caps.has_sse; /* SSE cpus supports mmxext too */
 435 #if defined(PIPE_ARCH_X86_64)
 436          util_cpu_caps.has_daz = 1;
 437 #else
 438          util_cpu_caps.has_daz = util_cpu_caps.has_sse3 ||
 439             (util_cpu_caps.has_sse2 && sse2_has_daz());
 440 #endif
 441
 442          cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
 443          if (cacheline > 0)
 444             util_cpu_caps.cacheline = cacheline;
 445       }
 446       if (util_cpu_caps.has_avx && regs[0] >= 0x00000007) {
 447          uint32_t regs7[4];
 448          cpuid_count(0x00000007, 0x00000000, regs7);
 449          util_cpu_caps.has_avx2 = (regs7[1] >> 5) & 1;
 450       }
 451
 452       // check for avx512
 453       if (((regs2[2] >> 27) & 1) && // OSXSAVE
 454           (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS
 455           ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS
 456          uint32_t regs3[4];
 457          cpuid_count(0x00000007, 0x00000000, regs3);
 458          util_cpu_caps.has_avx512f    = (regs3[1] >> 16) & 1;
 459          util_cpu_caps.has_avx512dq   = (regs3[1] >> 17) & 1;
 460          util_cpu_caps.has_avx512ifma = (regs3[1] >> 21) & 1;
 461          util_cpu_caps.has_avx512pf   = (regs3[1] >> 26) & 1;
 462          util_cpu_caps.has_avx512er   = (regs3[1] >> 27) & 1;
 463          util_cpu_caps.has_avx512cd   = (regs3[1] >> 28) & 1;
 464          util_cpu_caps.has_avx512bw   = (regs3[1] >> 30) & 1;
 465          util_cpu_caps.has_avx512vl   = (regs3[1] >> 31) & 1;
 466          util_cpu_caps.has_avx512vbmi = (regs3[2] >>  1) & 1;
 467       }
 468
 469       if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69) {
 470          /* GenuineIntel */
 471          util_cpu_caps.has_intel = 1;
 472       }
 473
 474       cpuid(0x80000000, regs);
 475
 476       if (regs[0] >= 0x80000001) {
 477
 478          cpuid(0x80000001, regs2);
 479
 480          util_cpu_caps.has_mmx  |= (regs2[3] >> 23) & 1;
 481          util_cpu_caps.has_mmx2 |= (regs2[3] >> 22) & 1;
 482          util_cpu_caps.has_3dnow = (regs2[3] >> 31) & 1;
 483          util_cpu_caps.has_3dnow_ext = (regs2[3] >> 30) & 1;
 484
 485          util_cpu_caps.has_xop = util_cpu_caps.has_avx &&
 486                                  ((regs2[2] >> 11) & 1);
 487       }
 488
 489       if (regs[0] >= 0x80000006) {
 490          /* should we really do this if the clflush size above worked? */
 491          unsigned int cacheline;
 492          cpuid(0x80000006, regs2);
 493          cacheline = regs2[2] & 0xFF;
 494          if (cacheline > 0)
 495             util_cpu_caps.cacheline = cacheline;
 496       }
 497
 498       if (!util_cpu_caps.has_sse) {
 499          util_cpu_caps.has_sse2 = 0;
 500          util_cpu_caps.has_sse3 = 0;
 501          util_cpu_caps.has_ssse3 = 0;
 502          util_cpu_caps.has_sse4_1 = 0;
 503       }
 504    }
 505 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
 506
 507 #if defined(PIPE_ARCH_ARM)
 508    check_os_arm_support();
 509 #endif
 510
 511 #if defined(PIPE_ARCH_PPC)
 512    check_os_altivec_support();
 513 #endif /* PIPE_ARCH_PPC */
 514
 515 #ifdef DEBUG
 516    if (debug_get_option_dump_cpu()) {
 517       debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
 518
 519       debug_printf("util_cpu_caps.x86_cpu_type = %u\n", util_cpu_caps.x86_cpu_type);
 520       debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
 521
 522       debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps.has_tsc);
 523       debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps.has_mmx);
 524       debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps.has_mmx2);
 525       debug_printf("util_cpu_caps.has_sse = %u\n", util_cpu_caps.has_sse);
 526       debug_printf("util_cpu_caps.has_sse2 = %u\n", util_cpu_caps.has_sse2);
 527       debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps.has_sse3);
 528       debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps.has_ssse3);
 529       debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps.has_sse4_1);
 530       debug_printf("util_cpu_caps.has_sse4_2 = %u\n", util_cpu_caps.has_sse4_2);
 531       debug_printf("util_cpu_caps.has_avx = %u\n", util_cpu_caps.has_avx);
 532       debug_printf("util_cpu_caps.has_avx2 = %u\n", util_cpu_caps.has_avx2);
 533       debug_printf("util_cpu_caps.has_f16c = %u\n", util_cpu_caps.has_f16c);
 534       debug_printf("util_cpu_caps.has_popcnt = %u\n", util_cpu_caps.has_popcnt);
 535       debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps.has_3dnow);
 536       debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps.has_3dnow_ext);
 537       debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
 538       debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps.has_altivec);
 539       debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
 540       debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
 541       debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f);
 542       debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq);
 543       debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma);
 544       debug_printf("util_cpu_caps.has_avx512pf = %u\n", util_cpu_caps.has_avx512pf);
 545       debug_printf("util_cpu_caps.has_avx512er = %u\n", util_cpu_caps.has_avx512er);
 546       debug_printf("util_cpu_caps.has_avx512cd = %u\n", util_cpu_caps.has_avx512cd);
 547       debug_printf("util_cpu_caps.has_avx512bw = %u\n", util_cpu_caps.has_avx512bw);
 548       debug_printf("util_cpu_caps.has_avx512vl = %u\n", util_cpu_caps.has_avx512vl);
 549       debug_printf("util_cpu_caps.has_avx512vbmi = %u\n", util_cpu_caps.has_avx512vbmi);
 550    }
 551 #endif
 552
 553    util_cpu_detect_initialized = TRUE;
 554 }