1 /**************************************************************************
3 * Copyright 2008 Dennis Smit
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 **************************************************************************/
28 * Based on the work of Eric Anholt <anholt@FreeBSD.org>
31 /* FIXME: clean this entire file up */
33 #include "u_cpu_detect.h"
42 #if defined(ARCH_POWERPC)
43 #if defined(OS_DARWIN)
44 #include <sys/sysctl.h>
51 #if defined(OS_NETBSD) || defined(OS_OPENBSD)
52 #include <sys/param.h>
53 #include <sys/sysctl.h>
54 #include <machine/cpu.h>
57 #if defined(OS_FREEBSD)
58 #include <sys/types.h>
59 #include <sys/sysctl.h>
76 static struct cpu_detect_caps __cpu_detect_caps
;
77 static int __cpu_detect_initialized
= 0;
79 static int has_cpuid(void);
80 static int cpuid(unsigned int ax
, unsigned int *p
);
82 /* The sigill handlers */
83 #if defined(ARCH_X86) /* x86 (linux katmai handler check thing) */
84 #if defined(OS_LINUX) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
85 static void sigill_handler_sse(int signal
, struct sigcontext sc
)
87 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
88 * instructions are 3 bytes long. We must increment the instruction
89 * pointer manually to avoid repeated execution of the offending
92 * If the SIGILL is caused by a divide-by-zero when unmasked
93 * exceptions aren't supported, the SIMD FPU status and control
94 * word will be restored at the end of the test, so we don't need
95 * to worry about doing it here. Besides, we may not be able to...
99 __cpu_detect_caps
.hasSSE
=0;
102 static void sigfpe_handler_sse(int signal
, struct sigcontext sc
)
104 if (sc
.fpstate
->magic
!= 0xffff) {
105 /* Our signal context has the extended FPU state, so reset the
106 * divide-by-zero exception mask and clear the divide-by-zero
109 sc
.fpstate
->mxcsr
|= 0x00000200;
110 sc
.fpstate
->mxcsr
&= 0xfffffffb;
112 /* If we ever get here, we're completely hosed.
117 #endif /* OS_LINUX && _POSIX_SOURCE && X86_FXSR_MAGIC */
119 #if defined(OS_WIN32)
120 LONG CALLBACK
win32_sig_handler_sse(EXCEPTION_POINTERS
* ep
)
122 if(ep
->ExceptionRecord
->ExceptionCode
==EXCEPTION_ILLEGAL_INSTRUCTION
){
123 ep
->ContextRecord
->Eip
+=3;
124 __cpu_detect_caps
.hasSSE
=0;
125 return EXCEPTION_CONTINUE_EXECUTION
;
127 return EXCEPTION_CONTINUE_SEARCH
;
129 #endif /* OS_WIN32 */
132 #if defined(ARCH_POWERPC) && !defined(OS_DARWIN)
133 static sigjmp_buf __lv_powerpc_jmpbuf
;
134 static volatile sig_atomic_t __lv_powerpc_canjump
= 0;
136 static void sigill_handler (int sig
);
138 static void sigill_handler (int sig
)
140 if (!__lv_powerpc_canjump
) {
141 signal (sig
, SIG_DFL
);
145 __lv_powerpc_canjump
= 0;
146 siglongjmp(__lv_powerpc_jmpbuf
, 1);
149 static void check_os_altivec_support(void)
151 #if defined(OS_DARWIN)
152 int sels
[2] = {CTL_HW
, HW_VECTORUNIT
};
154 int len
= sizeof (has_vu
);
157 err
= sysctl(sels
, 2, &has_vu
, &len
, NULL
, 0);
161 __cpu_detect_caps
.hasAltiVec
= 1;
164 #else /* !OS_DARWIN */
165 /* no Darwin, do it the brute-force way */
166 /* this is borrowed from the libmpeg2 library */
167 signal(SIGILL
, sigill_handler
);
168 if (sigsetjmp(__lv_powerpc_jmpbuf
, 1)) {
169 signal(SIGILL
, SIG_DFL
);
171 __lv_powerpc_canjump
= 1;
175 "vand %%v0, %%v0, %%v0"
179 signal(SIGILL
, SIG_DFL
);
180 __cpu_detect_caps
.hasAltiVec
= 1;
186 /* If we're running on a processor that can do SSE, let's see if we
187 * are allowed to or not. This will catch 2.4.0 or later kernels that
188 * haven't been configured for a Pentium III but are running on one,
189 * and RedHat patched 2.2 kernels that have broken exception handling
190 * support for user space apps that do SSE.
192 static void check_os_katmai_support(void)
194 #if defined(ARCH_X86)
195 #if defined(OS_FREEBSD)
197 int len
= sizeof (has_sse
);
199 ret
= sysctlbyname("hw.instruction_sse", &has_sse
, &len
, NULL
, 0);
201 __cpu_detect_caps
.hasSSE
=0;
203 #elif defined(OS_NETBSD) || defined(OS_OPENBSD)
204 int has_sse
, has_sse2
, ret
, mib
[2];
207 mib
[0] = CTL_MACHDEP
;
209 varlen
= sizeof (has_sse
);
211 ret
= sysctl(mib
, 2, &has_sse
, &varlen
, NULL
, 0);
212 if (ret
< 0 || !has_sse
) {
213 __cpu_detect_caps
.hasSSE
= 0;
215 __cpu_detect_caps
.hasSSE
= 1;
219 varlen
= sizeof (has_sse2
);
220 ret
= sysctl(mib
, 2, &has_sse2
, &varlen
, NULL
, 0);
221 if (ret
< 0 || !has_sse2
) {
222 __cpu_detect_caps
.hasSSE2
= 0;
224 __cpu_detect_caps
.hasSSE2
= 1;
226 __cpu_detect_caps
.hasSSE
= 0; /* FIXME ?!?!? */
228 #elif defined(OS_WIN32)
229 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil
;
230 if (__cpu_detect_caps
.hasSSE
) {
231 exc_fil
= SetUnhandledExceptionFilter(win32_sig_handler_sse
);
232 __asm
__volatile ("xorps %xmm0, %xmm0");
233 SetUnhandledExceptionFilter(exc_fil
);
235 #elif defined(OS_LINUX)
236 struct sigaction saved_sigill
;
237 struct sigaction saved_sigfpe
;
239 /* Save the original signal handlers.
241 sigaction(SIGILL
, NULL
, &saved_sigill
);
242 sigaction(SIGFPE
, NULL
, &saved_sigfpe
);
244 signal(SIGILL
, (void (*)(int))sigill_handler_sse
);
245 signal(SIGFPE
, (void (*)(int))sigfpe_handler_sse
);
247 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
248 * supports the extended FPU save and restore required for SSE. If
249 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
250 * doesn't support Streaming SIMD Exceptions, even if the processor
253 if (__cpu_detect_caps
.hasSSE
) {
254 __asm
__volatile ("xorps %xmm1, %xmm0");
257 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
258 * it supports unmasked SIMD FPU exceptions. If we unmask the
259 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
260 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
261 * as expected, we're okay but we need to clean up after it.
263 * Are we being too stringent in our requirement that the OS support
264 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
265 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
266 * doesn't even support them. We at least know the user-space SSE
267 * support is good in kernels that do support unmasked exceptions,
268 * and therefore to be safe I'm going to leave this test in here.
270 if (__cpu_detect_caps
.hasSSE
) {
271 // test_os_katmai_exception_support();
274 /* Restore the original signal handlers.
276 sigaction(SIGILL
, &saved_sigill
, NULL
);
277 sigaction(SIGFPE
, &saved_sigfpe
, NULL
);
280 /* We can't use POSIX signal handling to test the availability of
281 * SSE, so we disable it by default.
283 __cpu_detect_caps
.hasSSE
= 0;
284 #endif /* __linux__ */
289 static int has_cpuid(void)
291 #if defined(ARCH_X86)
298 "xorl $0x200000, %0\n"
313 static int cpuid(unsigned int ax
, unsigned int *p
)
315 #if defined(ARCH_X86)
319 ("movl %%ebx, %%esi\n\t"
322 : "=a" (p
[0]), "=S" (p
[1]),
323 "=c" (p
[2]), "=d" (p
[3])
332 void cpu_detect_initialize()
334 unsigned int regs
[4];
335 unsigned int regs2
[4];
340 memset(&__cpu_detect_caps
, 0, sizeof (struct cpu_detect_caps
));
342 /* Check for arch type */
343 #if defined(ARCH_MIPS)
344 __cpu_detect_caps
.type
= CPU_DETECT_TYPE_MIPS
;
345 #elif defined(ARCH_ALPHA)
346 __cpu_detect_caps
.type
= CPU_DETECT_TYPE_ALPHA
;
347 #elif defined(ARCH_SPARC)
348 __cpu_detect_caps
.type
= CPU_DETECT_TYPE_SPARC
;
349 #elif defined(ARCH_X86)
350 __cpu_detect_caps
.type
= CPU_DETECT_TYPE_X86
;
351 #elif defined(ARCH_POWERPC)
352 __cpu_detect_caps
.type
= CPU_DETECT_TYPE_POWERPC
;
354 __cpu_detect_caps
.type
= CPU_DETECT_TYPE_OTHER
;
357 /* Count the number of CPUs in system */
358 #if !defined(OS_WIN32) && !defined(OS_UNKNOWN) && defined(_SC_NPROCESSORS_ONLN)
359 __cpu_detect_caps
.nrcpu
= sysconf(_SC_NPROCESSORS_ONLN
);
360 if (__cpu_detect_caps
.nrcpu
== -1)
361 __cpu_detect_caps
.nrcpu
= 1;
363 #elif defined(OS_NETBSD) || defined(OS_FREEBSD) || defined(OS_OPENBSD)
369 sysctl(mib
, 2, &ncpu
, &len
, NULL
, 0);
370 __cpu_detect_caps
.nrcpu
= ncpu
;
373 __cpu_detect_caps
.nrcpu
= 1;
376 #if defined(ARCH_X86)
377 /* No cpuid, old 486 or lower */
378 if (has_cpuid() == 0)
381 __cpu_detect_caps
.cacheline
= 32;
383 /* Get max cpuid level */
384 cpuid(0x00000000, regs
);
386 if (regs
[0] >= 0x00000001) {
387 unsigned int cacheline
;
389 cpuid (0x00000001, regs2
);
391 __cpu_detect_caps
.x86cpuType
= (regs2
[0] >> 8) & 0xf;
392 if (__cpu_detect_caps
.x86cpuType
== 0xf)
393 __cpu_detect_caps
.x86cpuType
= 8 + ((regs2
[0] >> 20) & 255); /* use extended family (P4, IA64) */
395 /* general feature flags */
396 __cpu_detect_caps
.hasTSC
= (regs2
[3] & (1 << 8 )) >> 8; /* 0x0000010 */
397 __cpu_detect_caps
.hasMMX
= (regs2
[3] & (1 << 23 )) >> 23; /* 0x0800000 */
398 __cpu_detect_caps
.hasSSE
= (regs2
[3] & (1 << 25 )) >> 25; /* 0x2000000 */
399 __cpu_detect_caps
.hasSSE2
= (regs2
[3] & (1 << 26 )) >> 26; /* 0x4000000 */
400 __cpu_detect_caps
.hasSSE3
= (regs2
[2] & (1)); /* 0x0000001 */
401 __cpu_detect_caps
.hasSSSE3
= (regs2
[2] & (1 << 9 )) >> 9; /* 0x0000020 */
402 __cpu_detect_caps
.hasMMX2
= __cpu_detect_caps
.hasSSE
; /* SSE cpus supports mmxext too */
404 cacheline
= ((regs2
[1] >> 8) & 0xFF) * 8;
406 __cpu_detect_caps
.cacheline
= cacheline
;
409 cpuid(0x80000000, regs
);
411 if (regs
[0] >= 0x80000001) {
413 cpuid(0x80000001, regs2
);
415 __cpu_detect_caps
.hasMMX
|= (regs2
[3] & (1 << 23 )) >> 23; /* 0x0800000 */
416 __cpu_detect_caps
.hasMMX2
|= (regs2
[3] & (1 << 22 )) >> 22; /* 0x400000 */
417 __cpu_detect_caps
.has3DNow
= (regs2
[3] & (1 << 31 )) >> 31; /* 0x80000000 */
418 __cpu_detect_caps
.has3DNowExt
= (regs2
[3] & (1 << 30 )) >> 30;
421 if (regs
[0] >= 0x80000006) {
422 cpuid(0x80000006, regs2
);
423 __cpu_detect_caps
.cacheline
= regs2
[2] & 0xFF;
427 #if defined(OS_LINUX) || defined(OS_FREEBSD) || defined(OS_NETBSD) || defined(OS_CYGWIN) || defined(OS_OPENBSD)
428 if (__cpu_detect_caps
.hasSSE
)
429 check_os_katmai_support();
431 if (!__cpu_detect_caps
.hasSSE
) {
432 __cpu_detect_caps
.hasSSE2
= 0;
433 __cpu_detect_caps
.hasSSE3
= 0;
434 __cpu_detect_caps
.hasSSSE3
= 0;
437 __cpu_detect_caps
.hasSSE
= 0;
438 __cpu_detect_caps
.hasSSE2
= 0;
439 __cpu_detect_caps
.hasSSE3
= 0;
440 __cpu_detect_caps
.hasSSSE3
= 0;
442 #endif /* ARCH_X86 */
444 #if defined(ARCH_POWERPC)
445 check_os_altivec_support();
446 #endif /* ARCH_POWERPC */
448 __cpu_detect_initialized
= 1;
451 struct cpu_detect_caps
*cpu_detect_get_caps()
453 return &__cpu_detect_caps
;
456 /* The getters and setters for feature flags */
457 int cpu_detect_get_tsc()
459 return __cpu_detect_caps
.hasTSC
;
462 int cpu_detect_get_mmx()
464 return __cpu_detect_caps
.hasMMX
;
467 int cpu_detect_get_mmx2()
469 return __cpu_detect_caps
.hasMMX2
;
472 int cpu_detect_get_sse()
474 return __cpu_detect_caps
.hasSSE
;
477 int cpu_detect_get_sse2()
479 return __cpu_detect_caps
.hasSSE2
;
482 int cpu_detect_get_sse3()
484 return __cpu_detect_caps
.hasSSE3
;
487 int cpu_detect_get_ssse3()
489 return __cpu_detect_caps
.hasSSSE3
;
492 int cpu_detect_get_3dnow()
494 return __cpu_detect_caps
.has3DNow
;
497 int cpu_detect_get_3dnow2()
499 return __cpu_detect_caps
.has3DNowExt
;
502 int cpu_detect_get_altivec()
504 return __cpu_detect_caps
.hasAltiVec
;