src/gallium/drivers/cell/ppu/cell_gen_fp.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 /**
  31  * Generate SPU fragment program/shader code.
  32  *
  33  * Note that we generate SOA-style code here.  So each TGSI instruction
  34  * operates on four pixels (and is translated into four SPU instructions,
  35  * generally speaking).
  36  *
  37  * \author Brian Paul
  38  */
  39
  40
  41 #include "pipe/p_defines.h"
  42 #include "pipe/p_state.h"
  43 #include "pipe/p_shader_tokens.h"
  44 #include "tgsi/tgsi_parse.h"
  45 #include "tgsi/tgsi_util.h"
  46 #include "tgsi/tgsi_exec.h"
  47 #include "tgsi/tgsi_dump.h"
  48 #include "rtasm/rtasm_ppc_spe.h"
  49 #include "util/u_memory.h"
  50 #include "cell_context.h"
  51 #include "cell_gen_fp.h"
  52
  53
  54 #define MAX_TEMPS 16
  55 #define MAX_IMMED  8
  56
  57 #define CHAN_X  0
  58 #define CHAN_Y  1
  59 #define CHAN_Z  2
  60 #define CHAN_W  3
  61
  62 /**
  63  * Context needed during code generation.
  64  */
  65 struct codegen
  66 {
  67    int inputs_reg;      /**< 1st function parameter */
  68    int outputs_reg;     /**< 2nd function parameter */
  69    int constants_reg;   /**< 3rd function parameter */
  70    int temp_regs[MAX_TEMPS][4]; /**< maps TGSI temps to SPE registers */
  71    int imm_regs[MAX_IMMED][4];  /**< maps TGSI immediates to SPE registers */
  72
  73    int num_imm;  /**< number of immediates */
  74
  75    int one_reg;         /**< register containing {1.0, 1.0, 1.0, 1.0} */
  76
  77    /** Per-instruction temps / intermediate temps */
  78    int num_itemps;
  79    int itemps[4];
  80
  81    /** Current IF/ELSE/ENDIF nesting level */
  82    int if_nesting;
  83    /** Index of execution mask register */
  84    int exec_mask_reg;
  85
  86    struct spe_function *f;
  87    boolean error;
  88 };
  89
  90
  91 /**
  92  * Allocate an intermediate temporary register.
  93  */
  94 static int
  95 get_itemp(struct codegen *gen)
  96 {
  97    int t = spe_allocate_available_register(gen->f);
  98    assert(gen->num_itemps < Elements(gen->itemps));
  99    gen->itemps[gen->num_itemps++] = t;
 100    return t;
 101 }
 102
 103 /**
 104  * Free all intermediate temporary registers.  To be called after each
 105  * instruction has been emitted.
 106  */
 107 static void
 108 free_itemps(struct codegen *gen)
 109 {
 110    int i;
 111    for (i = 0; i < gen->num_itemps; i++) {
 112       spe_release_register(gen->f, gen->itemps[i]);
 113    }
 114    gen->num_itemps = 0;
 115 }
 116
 117
 118 /**
 119  * Return index of an SPE register containing {1.0, 1.0, 1.0, 1.0}.
 120  * The register is allocated and initialized upon the first call.
 121  */
 122 static int
 123 get_const_one_reg(struct codegen *gen)
 124 {
 125    if (gen->one_reg <= 0) {
 126       gen->one_reg = spe_allocate_available_register(gen->f);
 127
 128       spe_indent(gen->f, 4);
 129       spe_comment(gen->f, -4, "INIT CONSTANT 1.0:");
 130
 131       /* one = {1.0, 1.0, 1.0, 1.0} */
 132       spe_load_float(gen->f, gen->one_reg, 1.0f);
 133
 134       spe_indent(gen->f, -4);
 135    }
 136
 137    return gen->one_reg;
 138 }
 139
 140
 141 /**
 142  * Return index of the pixel execution mask.
 143  * The register is allocated an initialized upon the first call.
 144  *
 145  * The pixel execution mask controls which pixels in a quad are
 146  * modified, according to surrounding conditionals, loops, etc.
 147  */
 148 static int
 149 get_exec_mask_reg(struct codegen *gen)
 150 {
 151    if (gen->exec_mask_reg <= 0) {
 152       gen->exec_mask_reg = spe_allocate_available_register(gen->f);
 153
 154       spe_indent(gen->f, 4);
 155       spe_comment(gen->f, -4, "INIT EXEC MASK = ~0:");
 156
 157       /* exec_mask = {~0, ~0, ~0, ~0} */
 158       spe_load_int(gen->f, gen->exec_mask_reg, ~0);
 159
 160       spe_indent(gen->f, -4);
 161    }
 162
 163    return gen->exec_mask_reg;
 164 }
 165
 166
 167 /**
 168  * Return the index of the SPU temporary containing the named TGSI
 169  * source register.  If the TGSI register is a TGSI_FILE_TEMPORARY we
 170  * just return the corresponding SPE register.  If the TGIS register
 171  * is TGSI_FILE_INPUT/CONSTANT/IMMEDIATE we allocate a new SPE register
 172  * and emit an SPE load instruction.
 173  */
 174 static int
 175 get_src_reg(struct codegen *gen,
 176             int channel,
 177             const struct tgsi_full_src_register *src)
 178 {
 179    int reg = -1;
 180    int swizzle = tgsi_util_get_full_src_register_extswizzle(src, channel);
 181    boolean reg_is_itemp = FALSE;
 182    uint sign_op;
 183
 184    assert(swizzle >= 0);
 185    assert(swizzle <= 3);
 186
 187    channel = swizzle;
 188
 189    switch (src->SrcRegister.File) {
 190    case TGSI_FILE_TEMPORARY:
 191       reg = gen->temp_regs[src->SrcRegister.Index][channel];
 192       break;
 193    case TGSI_FILE_INPUT:
 194       {
 195          /* offset is measured in quadwords, not bytes */
 196          int offset = src->SrcRegister.Index * 4 + channel;
 197          reg = get_itemp(gen);
 198          reg_is_itemp = TRUE;
 199          /* Load:  reg = memory[(machine_reg) + offset] */
 200          spe_lqd(gen->f, reg, gen->inputs_reg, offset);
 201       }
 202       break;
 203    case TGSI_FILE_IMMEDIATE:
 204       reg = gen->imm_regs[src->SrcRegister.Index][channel];
 205       break;
 206    case TGSI_FILE_CONSTANT:
 207       /* xxx fall-through for now / fix */
 208    default:
 209       assert(0);
 210    }
 211
 212    /*
 213     * Handle absolute value, negate or set-negative of src register.
 214     */
 215    sign_op = tgsi_util_get_full_src_register_sign_mode(src, channel);
 216    if (sign_op != TGSI_UTIL_SIGN_KEEP) {
 217       /*
 218        * All sign ops are done by manipulating bit 31, the IEEE float sign bit.
 219        */
 220       const int bit31mask_reg = get_itemp(gen);
 221       int result_reg;
 222
 223       if (reg_is_itemp) {
 224          /* re-use 'reg' for the result */
 225          result_reg = reg;
 226       }
 227       else {
 228          /* alloc a new reg for the result */
 229          result_reg = get_itemp(gen);
 230       }
 231
 232       /* mask with bit 31 set, the rest cleared */
 233       spe_load_int(gen->f, bit31mask_reg, (1 << 31));
 234
 235       if (sign_op == TGSI_UTIL_SIGN_CLEAR) {
 236          spe_andc(gen->f, result_reg, reg, bit31mask_reg);
 237       }
 238       else if (sign_op == TGSI_UTIL_SIGN_SET) {
 239          spe_and(gen->f, result_reg, reg, bit31mask_reg);
 240       }
 241       else {
 242          assert(sign_op == TGSI_UTIL_SIGN_TOGGLE);
 243          spe_xor(gen->f, result_reg, reg, bit31mask_reg);
 244       }
 245
 246       reg = result_reg;
 247    }
 248
 249    return reg;
 250 }
 251
 252
 253 /**
 254  * Return the index of an SPE register to use for the given TGSI register.
 255  * If the TGSI register is TGSI_FILE_TEMPORARAY, the index of the
 256  * corresponding SPE register is returned.  If the TGSI register is
 257  * TGSI_FILE_OUTPUT we allocate an intermediate temporary register.
 258  * See store_dest_reg() below...
 259  */
 260 static int
 261 get_dst_reg(struct codegen *gen,
 262             int channel,
 263             const struct tgsi_full_dst_register *dest)
 264 {
 265    int reg = -1;
 266
 267    switch (dest->DstRegister.File) {
 268    case TGSI_FILE_TEMPORARY:
 269       if (gen->if_nesting > 0)
 270          reg = get_itemp(gen);
 271       else
 272          reg = gen->temp_regs[dest->DstRegister.Index][channel];
 273       break;
 274    case TGSI_FILE_OUTPUT:
 275       reg = get_itemp(gen);
 276       break;
 277    default:
 278       assert(0);
 279    }
 280
 281    return reg;
 282 }
 283
 284
 285 /**
 286  * When a TGSI instruction is writing to an output register, this
 287  * function emits the SPE store instruction to store the value_reg.
 288  * \param value_reg  the SPE register containing the value to store.
 289  *                   This would have been returned by get_dst_reg().
 290  */
 291 static void
 292 store_dest_reg(struct codegen *gen,
 293                int value_reg, int channel,
 294                const struct tgsi_full_dst_register *dest)
 295 {
 296    switch (dest->DstRegister.File) {
 297    case TGSI_FILE_TEMPORARY:
 298       if (gen->if_nesting > 0) {
 299          int d_reg = gen->temp_regs[dest->DstRegister.Index][channel];
 300          int exec_reg = get_exec_mask_reg(gen);
 301          /* Mix d with new value according to exec mask:
 302           * d[i] = mask_reg[i] ? value_reg : d_reg
 303           */
 304          spe_selb(gen->f, d_reg, d_reg, value_reg, exec_reg);
 305       }
 306       else {
 307          /* we're not inside a condition or loop: do nothing special */
 308       }
 309       break;
 310    case TGSI_FILE_OUTPUT:
 311       {
 312          /* offset is measured in quadwords, not bytes */
 313          int offset = dest->DstRegister.Index * 4 + channel;
 314          if (gen->if_nesting > 0) {
 315             int exec_reg = get_exec_mask_reg(gen);
 316             int curval_reg = get_itemp(gen);
 317             /* First read the current value from memory:
 318              * Load:  curval = memory[(machine_reg) + offset]
 319              */
 320             spe_lqd(gen->f, curval_reg, gen->outputs_reg, offset);
 321             /* Mix curval with newvalue according to exec mask:
 322              * d[i] = mask_reg[i] ? value_reg : d_reg
 323              */
 324             spe_selb(gen->f, curval_reg, curval_reg, value_reg, exec_reg);
 325             /* Store: memory[(machine_reg) + offset] = curval */
 326             spe_stqd(gen->f, curval_reg, gen->outputs_reg, offset);
 327          }
 328          else {
 329             /* Store: memory[(machine_reg) + offset] = reg */
 330             spe_stqd(gen->f, value_reg, gen->outputs_reg, offset);
 331          }
 332       }
 333       break;
 334    default:
 335       assert(0);
 336    }
 337 }
 338
 339
 340 static boolean
 341 emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
 342 {
 343    int ch;
 344    spe_comment(gen->f, -4, "MOV:");
 345    for (ch = 0; ch < 4; ch++) {
 346       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 347          int src_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 348          int dst_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 349          /* XXX we don't always need to actually emit a mov instruction here */
 350          spe_move(gen->f, dst_reg, src_reg);
 351          store_dest_reg(gen, dst_reg, ch, &inst->FullDstRegisters[0]);
 352          free_itemps(gen);
 353       }
 354    }
 355    return true;
 356 }
 357
 358
 359
 360 /**
 361  * Emit addition instructions.  Recall that a single TGSI_OPCODE_ADD
 362  * becomes (up to) four SPU "fa" instructions because we're doing SOA
 363  * processing.
 364  */
 365 static boolean
 366 emit_ADD(struct codegen *gen, const struct tgsi_full_instruction *inst)
 367 {
 368    int ch;
 369    spe_comment(gen->f, -4, "ADD:");
 370    /* Loop over Red/Green/Blue/Alpha channels */
 371    for (ch = 0; ch < 4; ch++) {
 372       /* If the dest R, G, B or A writemask is enabled... */
 373       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 374          /* get indexes of the two src, one dest SPE registers */
 375          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 376          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 377          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 378
 379          /* Emit actual SPE instruction: d = s1 + s2 */
 380          spe_fa(gen->f, d_reg, s1_reg, s2_reg);
 381
 382          /* Store the result (a no-op for TGSI_FILE_TEMPORARY dests) */
 383          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 384          /* Free any intermediate temps we allocated */
 385          free_itemps(gen);
 386       }
 387    }
 388    return true;
 389 }
 390
 391 /**
 392  * Emit subtract.  See emit_ADD for comments.
 393  */
 394 static boolean
 395 emit_SUB(struct codegen *gen, const struct tgsi_full_instruction *inst)
 396 {
 397    int ch;
 398    spe_comment(gen->f, -4, "SUB:");
 399    /* Loop over Red/Green/Blue/Alpha channels */
 400    for (ch = 0; ch < 4; ch++) {
 401       /* If the dest R, G, B or A writemask is enabled... */
 402       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 403          /* get indexes of the two src, one dest SPE registers */
 404          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 405          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 406          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 407
 408          /* Emit actual SPE instruction: d = s1 - s2 */
 409          spe_fs(gen->f, d_reg, s1_reg, s2_reg);
 410
 411          /* Store the result (a no-op for TGSI_FILE_TEMPORARY dests) */
 412          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 413          /* Free any intermediate temps we allocated */
 414          free_itemps(gen);
 415       }
 416    }
 417    return true;
 418 }
 419
 420 /**
 421  * Emit multiply add.  See emit_ADD for comments.
 422  */
 423 static boolean
 424 emit_MAD(struct codegen *gen, const struct tgsi_full_instruction *inst)
 425 {
 426    int ch;
 427    spe_comment(gen->f, -4, "MAD:");
 428    for (ch = 0; ch < 4; ch++) {
 429       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 430          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 431          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 432          int s3_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
 433          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 434          /* d = s1 * s2 + s3 */
 435          spe_fma(gen->f, d_reg, s1_reg, s2_reg, s3_reg);
 436          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 437          free_itemps(gen);
 438       }
 439    }
 440    return true;
 441 }
 442
 443
 444 /**
 445  * Emit linear interpolate.  See emit_ADD for comments.
 446  */
 447 static boolean
 448 emit_LERP(struct codegen *gen, const struct tgsi_full_instruction *inst)
 449 {
 450    int ch;
 451    spe_comment(gen->f, -4, "LERP:");
 452    for (ch = 0; ch < 4; ch++) {
 453       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 454          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 455          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 456          int s3_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
 457          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 458          /* d = s3 + s1(s2 - s3) */
 459          spe_fs(gen->f, d_reg, s2_reg, s3_reg);
 460          spe_fma(gen->f, d_reg, d_reg, s1_reg, s3_reg);
 461          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 462          free_itemps(gen);
 463       }
 464    }
 465    return true;
 466 }
 467
 468 /**
 469  * Emit multiply.  See emit_ADD for comments.
 470  */
 471 static boolean
 472 emit_MUL(struct codegen *gen, const struct tgsi_full_instruction *inst)
 473 {
 474    int ch;
 475    spe_comment(gen->f, -4, "MUL:");
 476    for (ch = 0; ch < 4; ch++) {
 477       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 478          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 479          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 480          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 481          /* d = s1 * s2 */
 482          spe_fm(gen->f, d_reg, s1_reg, s2_reg);
 483          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 484          free_itemps(gen);
 485       }
 486    }
 487    return true;
 488 }
 489
 490 /**
 491  * Emit reciprocal.  See emit_ADD for comments.
 492  */
 493 static boolean
 494 emit_RCP(struct codegen *gen, const struct tgsi_full_instruction *inst)
 495 {
 496    int ch;
 497    spe_comment(gen->f, -4, "RCP:");
 498    for (ch = 0; ch < 4; ch++) {
 499       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 500          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 501          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 502          /* d = 1/s1 */
 503          spe_frest(gen->f, d_reg, s1_reg);
 504          spe_fi(gen->f, d_reg, s1_reg, d_reg);
 505          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 506          free_itemps(gen);
 507       }
 508    }
 509    return true;
 510 }
 511
 512 /**
 513  * Emit reciprocal sqrt.  See emit_ADD for comments.
 514  */
 515 static boolean
 516 emit_RSQ(struct codegen *gen, const struct tgsi_full_instruction *inst)
 517 {
 518    int ch;
 519    spe_comment(gen->f, -4, "RSQ:");
 520    for (ch = 0; ch < 4; ch++) {
 521       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 522          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 523          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 524          /* d = 1/s1 */
 525          spe_frsqest(gen->f, d_reg, s1_reg);
 526          spe_fi(gen->f, d_reg, s1_reg, d_reg);
 527          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 528          free_itemps(gen);
 529       }
 530    }
 531    return true;
 532 }
 533
 534 /**
 535  * Emit absolute value.  See emit_ADD for comments.
 536  */
 537 static boolean
 538 emit_ABS(struct codegen *gen, const struct tgsi_full_instruction *inst)
 539 {
 540    int ch;
 541    spe_comment(gen->f, -4, "ABS:");
 542    for (ch = 0; ch < 4; ch++) {
 543       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 544          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 545          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 546          const int bit31mask_reg = get_itemp(gen);
 547
 548          /* mask with bit 31 set, the rest cleared */
 549          spe_load_int(gen->f, bit31mask_reg, (1 << 31));
 550
 551          /* d = sign bit cleared in s1 */
 552          spe_andc(gen->f, d_reg, s1_reg, bit31mask_reg);
 553
 554          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 555          free_itemps(gen);
 556       }
 557    }
 558    return true;
 559 }
 560
 561 /**
 562  * Emit 3 component dot product.  See emit_ADD for comments.
 563  */
 564 static boolean
 565 emit_DP3(struct codegen *gen, const struct tgsi_full_instruction *inst)
 566 {
 567    int ch;
 568    spe_comment(gen->f, -4, "DP3:");
 569
 570    int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
 571    int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
 572    int d_reg = get_dst_reg(gen, CHAN_X, &inst->FullDstRegisters[0]);
 573    /* d = x * x */
 574    spe_fm(gen->f, d_reg, s1_reg, s2_reg);
 575
 576    s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
 577    s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
 578    /* d = y * y + d */
 579    spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
 580
 581    s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
 582    s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
 583    /* d = z * z + d */
 584    spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
 585
 586    for (ch = 0; ch < 4; ch++) {
 587       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 588          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 589          free_itemps(gen);
 590       }
 591    }
 592    return true;
 593 }
 594
 595 /**
 596  * Emit 4 component dot product.  See emit_ADD for comments.
 597  */
 598 static boolean
 599 emit_DP4(struct codegen *gen, const struct tgsi_full_instruction *inst)
 600 {
 601    int ch;
 602    spe_comment(gen->f, -4, "DP3:");
 603
 604    int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
 605    int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
 606    int d_reg = get_dst_reg(gen, CHAN_X, &inst->FullDstRegisters[0]);
 607    /* d = x * x */
 608    spe_fm(gen->f, d_reg, s1_reg, s2_reg);
 609
 610    s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
 611    s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
 612    /* d = y * y + d */
 613    spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
 614
 615    s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
 616    s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
 617    /* d = z * z + d */
 618    spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
 619
 620    s1_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[0]);
 621    s2_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
 622    /* d = w * w + d */
 623    spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
 624
 625    for (ch = 0; ch < 4; ch++) {
 626       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 627          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 628          free_itemps(gen);
 629       }
 630    }
 631    return true;
 632 }
 633
 634 /**
 635  * Emit set-if-greater-than.
 636  * Note that the SPE fcgt instruction produces 0x0 and 0xffffffff as
 637  * the result but OpenGL/TGSI needs 0.0 and 1.0 results.
 638  * We can easily convert 0x0/0xffffffff to 0.0/1.0 with a bitwise AND.
 639  */
 640 static boolean
 641 emit_SGT(struct codegen *gen, const struct tgsi_full_instruction *inst)
 642 {
 643    int ch;
 644
 645    spe_comment(gen->f, -4, "SGT:");
 646
 647    for (ch = 0; ch < 4; ch++) {
 648       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 649          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 650          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 651          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 652
 653          /* d = (s1 > s2) */
 654          spe_fcgt(gen->f, d_reg, s1_reg, s2_reg);
 655
 656          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 657          /* d = d & one_reg */
 658          spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
 659
 660          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 661          free_itemps(gen);
 662       }
 663    }
 664
 665    return true;
 666 }
 667
 668 /**
 669  * Emit set-if_less-then.  See emit_SGT for comments.
 670  */
 671 static boolean
 672 emit_SLT(struct codegen *gen, const struct tgsi_full_instruction *inst)
 673 {
 674    int ch;
 675
 676    spe_comment(gen->f, -4, "SLT:");
 677
 678    for (ch = 0; ch < 4; ch++) {
 679       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 680          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 681          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 682          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 683
 684          /* d = (s1 < s2) */
 685          spe_fcgt(gen->f, d_reg, s2_reg, s1_reg);
 686
 687          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 688          /* d = d & one_reg */
 689          spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
 690
 691          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 692          free_itemps(gen);
 693       }
 694    }
 695
 696    return true;
 697 }
 698
 699 /**
 700  * Emit set-if_greater-then-or-equal.  See emit_SGT for comments.
 701  */
 702 static boolean
 703 emit_SGE(struct codegen *gen, const struct tgsi_full_instruction *inst)
 704 {
 705    int ch;
 706
 707    spe_comment(gen->f, -4, "SGE:");
 708
 709    for (ch = 0; ch < 4; ch++) {
 710       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 711          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 712          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 713          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 714
 715          /* d = (s1 >= s2) */
 716          spe_fcgt(gen->f, d_reg, s2_reg, s1_reg);
 717
 718          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 719          /* d = ~d & one_reg */
 720          spe_andc(gen->f, d_reg, get_const_one_reg(gen), d_reg);
 721
 722          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 723          free_itemps(gen);
 724       }
 725    }
 726
 727    return true;
 728 }
 729
 730 /**
 731  * Emit set-if_less-then-or-equal.  See emit_SGT for comments.
 732  */
 733 static boolean
 734 emit_SLE(struct codegen *gen, const struct tgsi_full_instruction *inst)
 735 {
 736    int ch;
 737
 738    spe_comment(gen->f, -4, "SLE:");
 739
 740    for (ch = 0; ch < 4; ch++) {
 741       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 742          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 743          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 744          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 745
 746          /* d = (s1 <= s2) */
 747          spe_fcgt(gen->f, d_reg, s1_reg, s2_reg);
 748
 749          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 750          /* d = ~d & one_reg */
 751          spe_andc(gen->f, d_reg, get_const_one_reg(gen), d_reg);
 752
 753          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 754          free_itemps(gen);
 755       }
 756    }
 757
 758    return true;
 759 }
 760
 761 /**
 762  * Emit set-if_equal.  See emit_SGT for comments.
 763  */
 764 static boolean
 765 emit_SEQ(struct codegen *gen, const struct tgsi_full_instruction *inst)
 766 {
 767    int ch;
 768
 769    spe_comment(gen->f, -4, "SEQ:");
 770
 771    for (ch = 0; ch < 4; ch++) {
 772       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 773          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 774          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 775          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 776
 777          /* d = (s1 == s2) */
 778          spe_fceq(gen->f, d_reg, s1_reg, s2_reg);
 779
 780          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 781          /* d = d & one_reg */
 782          spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
 783
 784          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 785          free_itemps(gen);
 786       }
 787    }
 788
 789    return true;
 790 }
 791
 792 /**
 793  * Emit set-if_not_equal.  See emit_SGT for comments.
 794  */
 795 static boolean
 796 emit_SNE(struct codegen *gen, const struct tgsi_full_instruction *inst)
 797 {
 798    int ch;
 799
 800    spe_comment(gen->f, -4, "SNE:");
 801
 802    for (ch = 0; ch < 4; ch++) {
 803       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 804          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 805          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 806          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 807
 808          /* d = (s1 != s2) */
 809          spe_fceq(gen->f, d_reg, s1_reg, s2_reg);
 810          spe_nor(gen->f, d_reg, d_reg, d_reg);
 811
 812          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 813          /* d = d & one_reg */
 814          spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
 815
 816          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 817          free_itemps(gen);
 818       }
 819    }
 820
 821    return true;
 822 }
 823
 824 /**
 825  * Emit compare.  See emit_SGT for comments.
 826  */
 827 static boolean
 828 emit_CMP(struct codegen *gen, const struct tgsi_full_instruction *inst)
 829 {
 830    int ch;
 831
 832    spe_comment(gen->f, -4, "CMP:");
 833
 834    for (ch = 0; ch < 4; ch++) {
 835       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 836          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 837          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 838          int s3_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
 839          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 840          int zero_reg = get_itemp(gen);
 841
 842          spe_xor(gen->f, zero_reg, zero_reg, zero_reg);
 843
 844          /* d = (s1 < 0) ? s2 : s3 */
 845          spe_fcgt(gen->f, d_reg, zero_reg, s1_reg);
 846          spe_selb(gen->f, d_reg, s3_reg, s2_reg, d_reg);
 847
 848          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 849          free_itemps(gen);
 850       }
 851    }
 852
 853    return true;
 854 }
 855
 856 /**
 857  * Emit max.  See emit_SGT for comments.
 858  */
 859 static boolean
 860 emit_MAX(struct codegen *gen, const struct tgsi_full_instruction *inst)
 861 {
 862    int ch;
 863
 864    spe_comment(gen->f, -4, "MAX:");
 865
 866    for (ch = 0; ch < 4; ch++) {
 867       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 868          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 869          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 870          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 871
 872          /* d = (s1 > s2) ? s1 : s2 */
 873          spe_fcgt(gen->f, d_reg, s1_reg, s2_reg);
 874          spe_selb(gen->f, d_reg, s2_reg, s1_reg, d_reg);
 875
 876          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 877          free_itemps(gen);
 878       }
 879    }
 880
 881    return true;
 882 }
 883
 884 /**
 885  * Emit max.  See emit_SGT for comments.
 886  */
 887 static boolean
 888 emit_MIN(struct codegen *gen, const struct tgsi_full_instruction *inst)
 889 {
 890    int ch;
 891
 892    spe_comment(gen->f, -4, "MIN:");
 893
 894    for (ch = 0; ch < 4; ch++) {
 895       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 896          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 897          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 898          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 899
 900          /* d = (s2 > s1) ? s1 : s2 */
 901          spe_fcgt(gen->f, d_reg, s2_reg, s1_reg);
 902          spe_selb(gen->f, d_reg, s2_reg, s1_reg, d_reg);
 903
 904          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 905          free_itemps(gen);
 906       }
 907    }
 908
 909    return true;
 910 }
 911
 912 static boolean
 913 emit_IF(struct codegen *gen, const struct tgsi_full_instruction *inst)
 914 {
 915    const int channel = 0;
 916    const int exec_reg = get_exec_mask_reg(gen);
 917
 918    spe_comment(gen->f, -4, "IF:");
 919
 920    /* update execution mask with the predicate register */
 921    int tmp_reg = get_itemp(gen);
 922    int s1_reg = get_src_reg(gen, channel, &inst->FullSrcRegisters[0]);
 923
 924    /* tmp = (s1_reg == 0) */
 925    spe_ceqi(gen->f, tmp_reg, s1_reg, 0);
 926    /* tmp = !tmp */
 927    spe_complement(gen->f, tmp_reg);
 928    /* exec_mask = exec_mask & tmp */
 929    spe_and(gen->f, exec_reg, exec_reg, tmp_reg);
 930
 931    gen->if_nesting++;
 932
 933    free_itemps(gen);
 934
 935    return true;
 936 }
 937
 938
 939 static boolean
 940 emit_ELSE(struct codegen *gen, const struct tgsi_full_instruction *inst)
 941 {
 942    const int exec_reg = get_exec_mask_reg(gen);
 943
 944    spe_comment(gen->f, -4, "ELSE:");
 945
 946    /* exec_mask = !exec_mask */
 947    spe_complement(gen->f, exec_reg);
 948
 949    return true;
 950 }
 951
 952
 953 static boolean
 954 emit_ENDIF(struct codegen *gen, const struct tgsi_full_instruction *inst)
 955 {
 956    const int exec_reg = get_exec_mask_reg(gen);
 957
 958    spe_comment(gen->f, -4, "ENDIF:");
 959
 960    /* XXX todo: pop execution mask */
 961
 962    spe_load_int(gen->f, exec_reg, ~0x0);
 963
 964    gen->if_nesting--;
 965    return true;
 966 }
 967
 968
 969 static boolean
 970 emit_DDX_DDY(struct codegen *gen, const struct tgsi_full_instruction *inst,
 971              boolean ddx)
 972 {
 973    int ch;
 974
 975    spe_comment(gen->f, -4, ddx ? "DDX:" : "DDY:");
 976
 977    for (ch = 0; ch < 4; ch++) {
 978       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 979          int s_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 980          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 981
 982          int t1_reg = get_itemp(gen);
 983          int t2_reg = get_itemp(gen);
 984
 985          spe_splat_word(gen->f, t1_reg, s_reg, 0); /* upper-left pixel */
 986          if (ddx) {
 987             spe_splat_word(gen->f, t2_reg, s_reg, 1); /* upper-right pixel */
 988          }
 989          else {
 990             spe_splat_word(gen->f, t2_reg, s_reg, 2); /* lower-left pixel */
 991          }
 992          spe_fs(gen->f, d_reg, t2_reg, t1_reg);
 993
 994          free_itemps(gen);
 995       }
 996    }
 997
 998    return true;
 999 }
1000
1001
1002
1003
1004 /**
1005  * Emit END instruction.
1006  * We just return from the shader function at this point.
1007  *
1008  * Note that there may be more code after this that would be
1009  * called by TGSI_OPCODE_CALL.
1010  */
1011 static boolean
1012 emit_END(struct codegen *gen)
1013 {
1014    spe_comment(gen->f, -4, "END:");
1015    /* return from function call */
1016    spe_bi(gen->f, SPE_REG_RA, 0, 0);
1017    return true;
1018 }
1019
1020
1021 /**
1022  * Emit code for the given instruction.  Just a big switch stmt.
1023  */
1024 static boolean
1025 emit_instruction(struct codegen *gen,
1026                  const struct tgsi_full_instruction *inst)
1027 {
1028    switch (inst->Instruction.Opcode) {
1029    case TGSI_OPCODE_MOV:
1030       return emit_MOV(gen, inst);
1031    case TGSI_OPCODE_MUL:
1032       return emit_MUL(gen, inst);
1033    case TGSI_OPCODE_ADD:
1034       return emit_ADD(gen, inst);
1035    case TGSI_OPCODE_SUB:
1036       return emit_SUB(gen, inst);
1037    case TGSI_OPCODE_MAD:
1038       return emit_MAD(gen, inst);
1039    case TGSI_OPCODE_LERP:
1040       return emit_LERP(gen, inst);
1041    case TGSI_OPCODE_DP3:
1042       return emit_DP3(gen, inst);
1043    case TGSI_OPCODE_DP4:
1044       return emit_DP4(gen, inst);
1045    case TGSI_OPCODE_RCP:
1046       return emit_RCP(gen, inst);
1047    case TGSI_OPCODE_RSQ:
1048       return emit_RSQ(gen, inst);
1049    case TGSI_OPCODE_ABS:
1050       return emit_ABS(gen, inst);
1051    case TGSI_OPCODE_SGT:
1052       return emit_SGT(gen, inst);
1053    case TGSI_OPCODE_SLT:
1054       return emit_SLT(gen, inst);
1055    case TGSI_OPCODE_SGE:
1056       return emit_SGE(gen, inst);
1057    case TGSI_OPCODE_SLE:
1058       return emit_SLE(gen, inst);
1059    case TGSI_OPCODE_SEQ:
1060       return emit_SEQ(gen, inst);
1061    case TGSI_OPCODE_SNE:
1062       return emit_SNE(gen, inst);
1063    case TGSI_OPCODE_CMP:
1064       return emit_CMP(gen, inst);
1065    case TGSI_OPCODE_MAX:
1066       return emit_MAX(gen, inst);
1067    case TGSI_OPCODE_MIN:
1068       return emit_MIN(gen, inst);
1069    case TGSI_OPCODE_END:
1070       return emit_END(gen);
1071
1072    case TGSI_OPCODE_IF:
1073       return emit_IF(gen, inst);
1074    case TGSI_OPCODE_ELSE:
1075       return emit_ELSE(gen, inst);
1076    case TGSI_OPCODE_ENDIF:
1077       return emit_ENDIF(gen, inst);
1078
1079    case TGSI_OPCODE_DDX:
1080       return emit_DDX_DDY(gen, inst, true);
1081    case TGSI_OPCODE_DDY:
1082       return emit_DDX_DDY(gen, inst, false);
1083
1084    /* XXX lots more cases to do... */
1085
1086    default:
1087       fprintf(stderr, "Cell: unimplemented TGSI instruction %d!\n",
1088               inst->Instruction.Opcode);
1089       return false;
1090    }
1091
1092    return true;
1093 }
1094
1095
1096
1097 /**
1098  * Emit code for a TGSI immediate value (vector of four floats).
1099  * This involves register allocation and initialization.
1100  * XXX the initialization should be done by a "prepare" stage, not
1101  * per quad execution!
1102  */
1103 static boolean
1104 emit_immediate(struct codegen *gen, const struct tgsi_full_immediate *immed)
1105 {
1106    int ch;
1107
1108    assert(gen->num_imm < MAX_TEMPS);
1109
1110    spe_comment(gen->f, -4, "IMMEDIATE:");
1111
1112    for (ch = 0; ch < 4; ch++) {
1113       float val = immed->u.ImmediateFloat32[ch].Float;
1114       int reg = spe_allocate_available_register(gen->f);
1115
1116       if (reg < 0)
1117          return false;
1118
1119       /* update immediate map */
1120       gen->imm_regs[gen->num_imm][ch] = reg;
1121
1122       /* emit initializer instruction */
1123       spe_load_float(gen->f, reg, val);
1124    }
1125
1126    gen->num_imm++;
1127
1128    return true;
1129 }
1130
1131
1132
1133 /**
1134  * Emit "code" for a TGSI declaration.
1135  * We only care about TGSI TEMPORARY register declarations at this time.
1136  * For each TGSI TEMPORARY we allocate four SPE registers.
1137  */
1138 static boolean
1139 emit_declaration(struct cell_context *cell,
1140                  struct codegen *gen, const struct tgsi_full_declaration *decl)
1141 {
1142    int i, ch;
1143
1144    switch (decl->Declaration.File) {
1145    case TGSI_FILE_TEMPORARY:
1146       if (cell->debug_flags & CELL_DEBUG_ASM) {
1147          printf("Declare temp reg %d .. %d\n",
1148                 decl->DeclarationRange.First,
1149                 decl->DeclarationRange.Last);
1150       }
1151
1152       for (i = decl->DeclarationRange.First;
1153            i <= decl->DeclarationRange.Last;
1154            i++) {
1155          assert(i < MAX_TEMPS);
1156          for (ch = 0; ch < 4; ch++) {
1157             gen->temp_regs[i][ch] = spe_allocate_available_register(gen->f);
1158             if (gen->temp_regs[i][ch] < 0)
1159                return false; /* out of regs */
1160          }
1161
1162          /* XXX if we run out of SPE registers, we need to spill
1163           * to SPU memory.  someday...
1164           */
1165
1166          if (cell->debug_flags & CELL_DEBUG_ASM) {
1167             printf("  SPE regs: %d %d %d %d\n",
1168                    gen->temp_regs[i][0],
1169                    gen->temp_regs[i][1],
1170                    gen->temp_regs[i][2],
1171                    gen->temp_regs[i][3]);
1172          }
1173       }
1174       break;
1175    default:
1176       ; /* ignore */
1177    }
1178
1179    return true;
1180 }
1181
1182
1183 /**
1184  * Translate TGSI shader code to SPE instructions.  This is done when
1185  * the state tracker gives us a new shader (via pipe->create_fs_state()).
1186  *
1187  * \param cell    the rendering context (in)
1188  * \param tokens  the TGSI shader (in)
1189  * \param f       the generated function (out)
1190  */
1191 boolean
1192 cell_gen_fragment_program(struct cell_context *cell,
1193                           const struct tgsi_token *tokens,
1194                           struct spe_function *f)
1195 {
1196    struct tgsi_parse_context parse;
1197    struct codegen gen;
1198
1199    memset(&gen, 0, sizeof(gen));
1200    gen.f = f;
1201
1202    /* For SPE function calls: reg $3 = first param, $4 = second param, etc. */
1203    gen.inputs_reg = 3;     /* pointer to inputs array */
1204    gen.outputs_reg = 4;    /* pointer to outputs array */
1205    gen.constants_reg = 5;  /* pointer to constants array */
1206
1207    spe_init_func(f, SPU_MAX_FRAGMENT_PROGRAM_INSTS * SPE_INST_SIZE);
1208    spe_allocate_register(f, gen.inputs_reg);
1209    spe_allocate_register(f, gen.outputs_reg);
1210    spe_allocate_register(f, gen.constants_reg);
1211
1212    if (cell->debug_flags & CELL_DEBUG_ASM) {
1213       spe_print_code(f, true);
1214       spe_indent(f, 8);
1215       printf("Begin %s\n", __FUNCTION__);
1216       tgsi_dump(tokens, 0);
1217    }
1218
1219    tgsi_parse_init(&parse, tokens);
1220
1221    while (!tgsi_parse_end_of_tokens(&parse) && !gen.error) {
1222       tgsi_parse_token(&parse);
1223
1224       switch (parse.FullToken.Token.Type) {
1225       case TGSI_TOKEN_TYPE_IMMEDIATE:
1226          if (!emit_immediate(&gen,  &parse.FullToken.FullImmediate))
1227             gen.error = true;
1228          break;
1229
1230       case TGSI_TOKEN_TYPE_DECLARATION:
1231          if (!emit_declaration(cell, &gen, &parse.FullToken.FullDeclaration))
1232             gen.error = true;
1233          break;
1234
1235       case TGSI_TOKEN_TYPE_INSTRUCTION:
1236          if (!emit_instruction(&gen, &parse.FullToken.FullInstruction))
1237             gen.error = true;
1238          break;
1239
1240       default:
1241          assert(0);
1242       }
1243    }
1244
1245
1246    if (gen.error) {
1247       /* terminate the SPE code */
1248       return emit_END(&gen);
1249    }
1250
1251    if (cell->debug_flags & CELL_DEBUG_ASM) {
1252       printf("cell_gen_fragment_program nr instructions: %d\n", f->num_inst);
1253       printf("End %s\n", __FUNCTION__);
1254    }
1255
1256    tgsi_parse_free( &parse );
1257
1258    return !gen.error;
1259 }