src/gallium/drivers/cell/ppu/cell_gen_fp.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
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  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 /**
  31  * Generate SPU fragment program/shader code.
  32  *
  33  * Note that we generate SOA-style code here.  So each TGSI instruction
  34  * operates on four pixels (and is translated into four SPU instructions,
  35  * generally speaking).
  36  *
  37  * \author Brian Paul
  38  */
  39
  40
  41 #include "pipe/p_defines.h"
  42 #include "pipe/p_state.h"
  43 #include "pipe/p_shader_tokens.h"
  44 #include "tgsi/tgsi_parse.h"
  45 #include "tgsi/tgsi_util.h"
  46 #include "tgsi/tgsi_exec.h"
  47 #include "tgsi/tgsi_dump.h"
  48 #include "rtasm/rtasm_ppc_spe.h"
  49 #include "util/u_memory.h"
  50 #include "cell_context.h"
  51 #include "cell_gen_fp.h"
  52
  53
  54 /** Set to 1 to enable debug/disassembly printfs */
  55 #define DISASSEM 1
  56
  57
  58 #define MAX_TEMPS 16
  59 #define MAX_IMMED  8
  60
  61
  62 /**
  63  * Context needed during code generation.
  64  */
  65 struct codegen
  66 {
  67    int inputs_reg;      /**< 1st function parameter */
  68    int outputs_reg;     /**< 2nd function parameter */
  69    int constants_reg;   /**< 3rd function parameter */
  70    int temp_regs[MAX_TEMPS][4]; /**< maps TGSI temps to SPE registers */
  71    int imm_regs[MAX_IMMED][4];  /**< maps TGSI immediates to SPE registers */
  72
  73    int num_imm;  /**< number of immediates */
  74
  75    int one_reg;         /**< register containing {1.0, 1.0, 1.0, 1.0} */
  76
  77    /** Per-instruction temps / intermediate temps */
  78    int num_itemps;
  79    int itemps[4];
  80
  81    /** Current IF/ELSE/ENDIF nesting level */
  82    int if_nesting;
  83    /** Index of execution mask register */
  84    int exec_mask_reg;
  85
  86    struct spe_function *f;
  87    boolean error;
  88 };
  89
  90
  91 /**
  92  * Allocate an intermediate temporary register.
  93  */
  94 static int
  95 get_itemp(struct codegen *gen)
  96 {
  97    int t = spe_allocate_available_register(gen->f);
  98    assert(gen->num_itemps < Elements(gen->itemps));
  99    gen->itemps[gen->num_itemps++] = t;
 100    return t;
 101 }
 102
 103 /**
 104  * Free all intermediate temporary registers.  To be called after each
 105  * instruction has been emitted.
 106  */
 107 static void
 108 free_itemps(struct codegen *gen)
 109 {
 110    int i;
 111    for (i = 0; i < gen->num_itemps; i++) {
 112       spe_release_register(gen->f, gen->itemps[i]);
 113    }
 114    gen->num_itemps = 0;
 115 }
 116
 117
 118 /**
 119  * Return index of an SPE register containing {1.0, 1.0, 1.0, 1.0}.
 120  * The register is allocated and initialized upon the first call.
 121  */
 122 static int
 123 get_const_one_reg(struct codegen *gen)
 124 {
 125    if (gen->one_reg <= 0) {
 126       gen->one_reg = spe_allocate_available_register(gen->f);
 127
 128       spe_indent(gen->f, 4);
 129       spe_comment(gen->f, -4, "INIT CONSTANT 1.0:");
 130
 131       /* one = {1.0, 1.0, 1.0, 1.0} */
 132       spe_load_float(gen->f, gen->one_reg, 1.0f);
 133
 134       spe_indent(gen->f, -4);
 135    }
 136
 137    return gen->one_reg;
 138 }
 139
 140
 141 /**
 142  * Return index of the pixel execution mask.
 143  * The register is allocated an initialized upon the first call.
 144  *
 145  * The pixel execution mask controls which pixels in a quad are
 146  * modified, according to surrounding conditionals, loops, etc.
 147  */
 148 static int
 149 get_exec_mask_reg(struct codegen *gen)
 150 {
 151    if (gen->exec_mask_reg <= 0) {
 152       gen->exec_mask_reg = spe_allocate_available_register(gen->f);
 153
 154       spe_indent(gen->f, 4);
 155       spe_comment(gen->f, -4, "INIT EXEC MASK = ~0:");
 156
 157       /* exec_mask = {~0, ~0, ~0, ~0} */
 158       spe_load_int(gen->f, gen->exec_mask_reg, ~0);
 159
 160       spe_indent(gen->f, -4);
 161    }
 162
 163    return gen->exec_mask_reg;
 164 }
 165
 166
 167 /**
 168  * Return the index of the SPU temporary containing the named TGSI
 169  * source register.  If the TGSI register is a TGSI_FILE_TEMPORARY we
 170  * just return the corresponding SPE register.  If the TGIS register
 171  * is TGSI_FILE_INPUT/CONSTANT/IMMEDIATE we allocate a new SPE register
 172  * and emit an SPE load instruction.
 173  */
 174 static int
 175 get_src_reg(struct codegen *gen,
 176             int channel,
 177             const struct tgsi_full_src_register *src)
 178 {
 179    int reg = -1;
 180    int swizzle = tgsi_util_get_full_src_register_extswizzle(src, channel);
 181    boolean reg_is_itemp = FALSE;
 182    uint sign_op;
 183
 184    assert(swizzle >= 0);
 185    assert(swizzle <= 3);
 186
 187    channel = swizzle;
 188
 189    switch (src->SrcRegister.File) {
 190    case TGSI_FILE_TEMPORARY:
 191       reg = gen->temp_regs[src->SrcRegister.Index][channel];
 192       break;
 193    case TGSI_FILE_INPUT:
 194       {
 195          /* offset is measured in quadwords, not bytes */
 196          int offset = src->SrcRegister.Index * 4 + channel;
 197          reg = get_itemp(gen);
 198          reg_is_itemp = TRUE;
 199          /* Load:  reg = memory[(machine_reg) + offset] */
 200          spe_lqd(gen->f, reg, gen->inputs_reg, offset);
 201       }
 202       break;
 203    case TGSI_FILE_IMMEDIATE:
 204       reg = gen->imm_regs[src->SrcRegister.Index][channel];
 205       break;
 206    case TGSI_FILE_CONSTANT:
 207       /* xxx fall-through for now / fix */
 208    default:
 209       assert(0);
 210    }
 211
 212    /*
 213     * Handle absolute value, negate or set-negative of src register.
 214     */
 215    sign_op = tgsi_util_get_full_src_register_sign_mode(src, channel);
 216    if (sign_op != TGSI_UTIL_SIGN_KEEP) {
 217       /*
 218        * All sign ops are done by manipulating bit 31, the IEEE float sign bit.
 219        */
 220       const int bit31mask_reg = get_itemp(gen);
 221       int result_reg;
 222
 223       if (reg_is_itemp) {
 224          /* re-use 'reg' for the result */
 225          result_reg = reg;
 226       }
 227       else {
 228          /* alloc a new reg for the result */
 229          result_reg = get_itemp(gen);
 230       }
 231
 232       /* mask with bit 31 set, the rest cleared */
 233       spe_load_int(gen->f, bit31mask_reg, (1 << 31));
 234
 235       if (sign_op == TGSI_UTIL_SIGN_CLEAR) {
 236          spe_andc(gen->f, result_reg, reg, bit31mask_reg);
 237       }
 238       else if (sign_op == TGSI_UTIL_SIGN_SET) {
 239          spe_and(gen->f, result_reg, reg, bit31mask_reg);
 240       }
 241       else {
 242          assert(sign_op == TGSI_UTIL_SIGN_TOGGLE);
 243          spe_xor(gen->f, result_reg, reg, bit31mask_reg);
 244       }
 245
 246       reg = result_reg;
 247    }
 248
 249    return reg;
 250 }
 251
 252
 253 /**
 254  * Return the index of an SPE register to use for the given TGSI register.
 255  * If the TGSI register is TGSI_FILE_TEMPORARAY, the index of the
 256  * corresponding SPE register is returned.  If the TGSI register is
 257  * TGSI_FILE_OUTPUT we allocate an intermediate temporary register.
 258  * See store_dest_reg() below...
 259  */
 260 static int
 261 get_dst_reg(struct codegen *gen,
 262             int channel,
 263             const struct tgsi_full_dst_register *dest)
 264 {
 265    int reg = -1;
 266
 267    switch (dest->DstRegister.File) {
 268    case TGSI_FILE_TEMPORARY:
 269       if (gen->if_nesting > 0)
 270          reg = get_itemp(gen);
 271       else
 272          reg = gen->temp_regs[dest->DstRegister.Index][channel];
 273       break;
 274    case TGSI_FILE_OUTPUT:
 275       reg = get_itemp(gen);
 276       break;
 277    default:
 278       assert(0);
 279    }
 280
 281    return reg;
 282 }
 283
 284
 285 /**
 286  * When a TGSI instruction is writing to an output register, this
 287  * function emits the SPE store instruction to store the value_reg.
 288  * \param value_reg  the SPE register containing the value to store.
 289  *                   This would have been returned by get_dst_reg().
 290  */
 291 static void
 292 store_dest_reg(struct codegen *gen,
 293                int value_reg, int channel,
 294                const struct tgsi_full_dst_register *dest)
 295 {
 296    switch (dest->DstRegister.File) {
 297    case TGSI_FILE_TEMPORARY:
 298       if (gen->if_nesting > 0) {
 299          int d_reg = gen->temp_regs[dest->DstRegister.Index][channel];
 300          int exec_reg = get_exec_mask_reg(gen);
 301          /* Mix d with new value according to exec mask:
 302           * d[i] = mask_reg[i] ? value_reg : d_reg
 303           */
 304          spe_selb(gen->f, d_reg, d_reg, value_reg, exec_reg);
 305       }
 306       else {
 307          /* we're not inside a condition or loop: do nothing special */
 308       }
 309       break;
 310    case TGSI_FILE_OUTPUT:
 311       {
 312          /* offset is measured in quadwords, not bytes */
 313          int offset = dest->DstRegister.Index * 4 + channel;
 314          if (gen->if_nesting > 0) {
 315             int exec_reg = get_exec_mask_reg(gen);
 316             int curval_reg = get_itemp(gen);
 317             /* First read the current value from memory:
 318              * Load:  curval = memory[(machine_reg) + offset]
 319              */
 320             spe_lqd(gen->f, curval_reg, gen->outputs_reg, offset);
 321             /* Mix curval with newvalue according to exec mask:
 322              * d[i] = mask_reg[i] ? value_reg : d_reg
 323              */
 324             spe_selb(gen->f, curval_reg, curval_reg, value_reg, exec_reg);
 325             /* Store: memory[(machine_reg) + offset] = curval */
 326             spe_stqd(gen->f, curval_reg, gen->outputs_reg, offset);
 327          }
 328          else {
 329             /* Store: memory[(machine_reg) + offset] = reg */
 330             spe_stqd(gen->f, value_reg, gen->outputs_reg, offset);
 331          }
 332       }
 333       break;
 334    default:
 335       assert(0);
 336    }
 337 }
 338
 339
 340 static boolean
 341 emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
 342 {
 343    int ch;
 344    spe_comment(gen->f, -4, "MOV:");
 345    for (ch = 0; ch < 4; ch++) {
 346       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 347          int src_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 348          int dst_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 349          /* XXX we don't always need to actually emit a mov instruction here */
 350          spe_move(gen->f, dst_reg, src_reg);
 351          store_dest_reg(gen, dst_reg, ch, &inst->FullDstRegisters[0]);
 352          free_itemps(gen);
 353       }
 354    }
 355    return true;
 356 }
 357
 358
 359
 360 /**
 361  * Emit addition instructions.  Recall that a single TGSI_OPCODE_ADD
 362  * becomes (up to) four SPU "fa" instructions because we're doing SOA
 363  * processing.
 364  */
 365 static boolean
 366 emit_ADD(struct codegen *gen, const struct tgsi_full_instruction *inst)
 367 {
 368    int ch;
 369    spe_comment(gen->f, -4, "ADD:");
 370    /* Loop over Red/Green/Blue/Alpha channels */
 371    for (ch = 0; ch < 4; ch++) {
 372       /* If the dest R, G, B or A writemask is enabled... */
 373       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 374          /* get indexes of the two src, one dest SPE registers */
 375          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 376          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 377          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 378
 379          /* Emit actual SPE instruction: d = s1 + s2 */
 380          spe_fa(gen->f, d_reg, s1_reg, s2_reg);
 381
 382          /* Store the result (a no-op for TGSI_FILE_TEMPORARY dests) */
 383          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 384          /* Free any intermediate temps we allocated */
 385          free_itemps(gen);
 386       }
 387    }
 388    return true;
 389 }
 390
 391 /**
 392  * Emit subtract.  See emit_ADD for comments.
 393  */
 394 static boolean
 395 emit_SUB(struct codegen *gen, const struct tgsi_full_instruction *inst)
 396 {
 397    int ch;
 398    spe_comment(gen->f, -4, "SUB:");
 399    /* Loop over Red/Green/Blue/Alpha channels */
 400    for (ch = 0; ch < 4; ch++) {
 401       /* If the dest R, G, B or A writemask is enabled... */
 402       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 403          /* get indexes of the two src, one dest SPE registers */
 404          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 405          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 406          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 407
 408          /* Emit actual SPE instruction: d = s1 - s2 */
 409          spe_fs(gen->f, d_reg, s1_reg, s2_reg);
 410
 411          /* Store the result (a no-op for TGSI_FILE_TEMPORARY dests) */
 412          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 413          /* Free any intermediate temps we allocated */
 414          free_itemps(gen);
 415       }
 416    }
 417    return true;
 418 }
 419
 420 /**
 421  * Emit multiply add.  See emit_ADD for comments.
 422  */
 423 static boolean
 424 emit_MAD(struct codegen *gen, const struct tgsi_full_instruction *inst)
 425 {
 426    int ch;
 427    spe_comment(gen->f, -4, "MAD:");
 428    for (ch = 0; ch < 4; ch++) {
 429       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 430          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 431          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 432          int s3_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
 433          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 434          /* d = s1 * s2 + s3 */
 435          spe_fma(gen->f, d_reg, s1_reg, s2_reg, s3_reg);
 436          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 437          free_itemps(gen);
 438       }
 439    }
 440    return true;
 441 }
 442
 443
 444 /**
 445  * Emit multiply.  See emit_ADD for comments.
 446  */
 447 static boolean
 448 emit_MUL(struct codegen *gen, const struct tgsi_full_instruction *inst)
 449 {
 450    int ch;
 451    spe_comment(gen->f, -4, "MUL:");
 452    for (ch = 0; ch < 4; ch++) {
 453       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 454          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 455          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 456          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 457          /* d = s1 * s2 */
 458          spe_fm(gen->f, d_reg, s1_reg, s2_reg);
 459          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 460          free_itemps(gen);
 461       }
 462    }
 463    return true;
 464 }
 465
 466 /**
 467  * Emit absolute value.  See emit_ADD for comments.
 468  */
 469 static boolean
 470 emit_ABS(struct codegen *gen, const struct tgsi_full_instruction *inst)
 471 {
 472    int ch;
 473    spe_comment(gen->f, -4, "ABS:");
 474    for (ch = 0; ch < 4; ch++) {
 475       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 476          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 477          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 478          const int bit31mask_reg = get_itemp(gen);
 479
 480          /* mask with bit 31 set, the rest cleared */
 481          spe_load_int(gen->f, bit31mask_reg, (1 << 31));
 482
 483          /* d = sign bit cleared in s1 */
 484          spe_andc(gen->f, d_reg, s1_reg, bit31mask_reg);
 485
 486          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 487          free_itemps(gen);
 488       }
 489    }
 490    return true;
 491 }
 492
 493 /**
 494  * Emit set-if-greater-than.
 495  * Note that the SPE fcgt instruction produces 0x0 and 0xffffffff as
 496  * the result but OpenGL/TGSI needs 0.0 and 1.0 results.
 497  * We can easily convert 0x0/0xffffffff to 0.0/1.0 with a bitwise AND.
 498  */
 499 static boolean
 500 emit_SGT(struct codegen *gen, const struct tgsi_full_instruction *inst)
 501 {
 502    int ch;
 503
 504    spe_comment(gen->f, -4, "SGT:");
 505
 506    for (ch = 0; ch < 4; ch++) {
 507       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 508          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 509          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 510          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 511
 512          /* d = (s1 > s2) */
 513          spe_fcgt(gen->f, d_reg, s1_reg, s2_reg);
 514
 515          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 516          /* d = d & one_reg */
 517          spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
 518
 519          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 520          free_itemps(gen);
 521       }
 522    }
 523
 524    return true;
 525 }
 526
 527 /**
 528  * Emit set-if_less-then.  See emit_SGT for comments.
 529  */
 530 static boolean
 531 emit_SLT(struct codegen *gen, const struct tgsi_full_instruction *inst)
 532 {
 533    int ch;
 534
 535    spe_comment(gen->f, -4, "SLT:");
 536
 537    for (ch = 0; ch < 4; ch++) {
 538       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 539          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 540          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 541          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 542
 543          /* d = (s1 < s2) */
 544          spe_fcgt(gen->f, d_reg, s2_reg, s1_reg);
 545
 546          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 547          /* d = d & one_reg */
 548          spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
 549
 550          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 551          free_itemps(gen);
 552       }
 553    }
 554
 555    return true;
 556 }
 557
 558 /**
 559  * Emit set-if_equal.  See emit_SGT for comments.
 560  */
 561 static boolean
 562 emit_SEQ(struct codegen *gen, const struct tgsi_full_instruction *inst)
 563 {
 564    int ch;
 565
 566    spe_comment(gen->f, -4, "SEQ:");
 567
 568    for (ch = 0; ch < 4; ch++) {
 569       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 570          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 571          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 572          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 573
 574          /* d = (s1 == s2) */
 575          spe_fceq(gen->f, d_reg, s1_reg, s2_reg);
 576
 577          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 578          /* d = d & one_reg */
 579          spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
 580
 581          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 582          free_itemps(gen);
 583       }
 584    }
 585
 586    return true;
 587 }
 588
 589 /**
 590  * Emit set-if_not_equal.  See emit_SGT for comments.
 591  */
 592 static boolean
 593 emit_SNE(struct codegen *gen, const struct tgsi_full_instruction *inst)
 594 {
 595    int ch;
 596
 597    spe_comment(gen->f, -4, "SNE:");
 598
 599    for (ch = 0; ch < 4; ch++) {
 600       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 601          int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 602          int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
 603          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 604
 605          /* d = (s1 != s2) */
 606          spe_fceq(gen->f, d_reg, s1_reg, s2_reg);
 607          spe_nor(gen->f, d_reg, d_reg, d_reg);
 608
 609          /* convert d from 0x0/0xffffffff to 0.0/1.0 */
 610          /* d = d & one_reg */
 611          spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
 612
 613          store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
 614          free_itemps(gen);
 615       }
 616    }
 617
 618    return true;
 619 }
 620
 621
 622 static boolean
 623 emit_IF(struct codegen *gen, const struct tgsi_full_instruction *inst)
 624 {
 625    const int channel = 0;
 626    const int exec_reg = get_exec_mask_reg(gen);
 627
 628    spe_comment(gen->f, -4, "IF:");
 629
 630    /* update execution mask with the predicate register */
 631    int tmp_reg = get_itemp(gen);
 632    int s1_reg = get_src_reg(gen, channel, &inst->FullSrcRegisters[0]);
 633
 634    /* tmp = (s1_reg == 0) */
 635    spe_ceqi(gen->f, tmp_reg, s1_reg, 0);
 636    /* tmp = !tmp */
 637    spe_complement(gen->f, tmp_reg);
 638    /* exec_mask = exec_mask & tmp */
 639    spe_and(gen->f, exec_reg, exec_reg, tmp_reg);
 640
 641    gen->if_nesting++;
 642
 643    free_itemps(gen);
 644
 645    return true;
 646 }
 647
 648
 649 static boolean
 650 emit_ELSE(struct codegen *gen, const struct tgsi_full_instruction *inst)
 651 {
 652    const int exec_reg = get_exec_mask_reg(gen);
 653
 654    spe_comment(gen->f, -4, "ELSE:");
 655
 656    /* exec_mask = !exec_mask */
 657    spe_complement(gen->f, exec_reg);
 658
 659    return true;
 660 }
 661
 662
 663 static boolean
 664 emit_ENDIF(struct codegen *gen, const struct tgsi_full_instruction *inst)
 665 {
 666    const int exec_reg = get_exec_mask_reg(gen);
 667
 668    spe_comment(gen->f, -4, "ENDIF:");
 669
 670    /* XXX todo: pop execution mask */
 671
 672    spe_load_int(gen->f, exec_reg, ~0x0);
 673
 674    gen->if_nesting--;
 675    return true;
 676 }
 677
 678
 679 static boolean
 680 emit_DDX_DDY(struct codegen *gen, const struct tgsi_full_instruction *inst,
 681              boolean ddx)
 682 {
 683    int ch;
 684
 685    spe_comment(gen->f, -4, ddx ? "DDX:" : "DDY:");
 686
 687    for (ch = 0; ch < 4; ch++) {
 688       if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
 689          int s_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
 690          int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
 691
 692          int t1_reg = get_itemp(gen);
 693          int t2_reg = get_itemp(gen);
 694
 695          spe_splat_word(gen->f, t1_reg, s_reg, 0); /* upper-left pixel */
 696          if (ddx) {
 697             spe_splat_word(gen->f, t2_reg, s_reg, 1); /* upper-right pixel */
 698          }
 699          else {
 700             spe_splat_word(gen->f, t2_reg, s_reg, 2); /* lower-left pixel */
 701          }
 702          spe_fs(gen->f, d_reg, t2_reg, t1_reg);
 703
 704          free_itemps(gen);
 705       }
 706    }
 707
 708    return true;
 709 }
 710
 711
 712
 713
 714 /**
 715  * Emit END instruction.
 716  * We just return from the shader function at this point.
 717  *
 718  * Note that there may be more code after this that would be
 719  * called by TGSI_OPCODE_CALL.
 720  */
 721 static boolean
 722 emit_END(struct codegen *gen)
 723 {
 724    spe_comment(gen->f, -4, "END:");
 725    /* return from function call */
 726    spe_bi(gen->f, SPE_REG_RA, 0, 0);
 727    return true;
 728 }
 729
 730
 731 /**
 732  * Emit code for the given instruction.  Just a big switch stmt.
 733  */
 734 static boolean
 735 emit_instruction(struct codegen *gen,
 736                  const struct tgsi_full_instruction *inst)
 737 {
 738    switch (inst->Instruction.Opcode) {
 739    case TGSI_OPCODE_MOV:
 740       return emit_MOV(gen, inst);
 741    case TGSI_OPCODE_MUL:
 742       return emit_MUL(gen, inst);
 743    case TGSI_OPCODE_ADD:
 744       return emit_ADD(gen, inst);
 745    case TGSI_OPCODE_SUB:
 746       return emit_SUB(gen, inst);
 747    case TGSI_OPCODE_MAD:
 748       return emit_MAD(gen, inst);
 749    case TGSI_OPCODE_ABS:
 750       return emit_ABS(gen, inst);
 751    case TGSI_OPCODE_SGT:
 752       return emit_SGT(gen, inst);
 753    case TGSI_OPCODE_SLT:
 754       return emit_SLT(gen, inst);
 755    case TGSI_OPCODE_SEQ:
 756       return emit_SEQ(gen, inst);
 757    case TGSI_OPCODE_SNE:
 758       return emit_SNE(gen, inst);
 759    case TGSI_OPCODE_END:
 760       return emit_END(gen);
 761
 762    case TGSI_OPCODE_IF:
 763       return emit_IF(gen, inst);
 764    case TGSI_OPCODE_ELSE:
 765       return emit_ELSE(gen, inst);
 766    case TGSI_OPCODE_ENDIF:
 767       return emit_ENDIF(gen, inst);
 768
 769    case TGSI_OPCODE_DDX:
 770       return emit_DDX_DDY(gen, inst, true);
 771    case TGSI_OPCODE_DDY:
 772       return emit_DDX_DDY(gen, inst, false);
 773
 774    /* XXX lots more cases to do... */
 775
 776    default:
 777       return false;
 778    }
 779
 780    return true;
 781 }
 782
 783
 784
 785 /**
 786  * Emit code for a TGSI immediate value (vector of four floats).
 787  * This involves register allocation and initialization.
 788  * XXX the initialization should be done by a "prepare" stage, not
 789  * per quad execution!
 790  */
 791 static boolean
 792 emit_immediate(struct codegen *gen, const struct tgsi_full_immediate *immed)
 793 {
 794    int ch;
 795
 796    assert(gen->num_imm < MAX_TEMPS);
 797
 798    spe_comment(gen->f, -4, "IMMEDIATE:");
 799
 800    for (ch = 0; ch < 4; ch++) {
 801       float val = immed->u.ImmediateFloat32[ch].Float;
 802       int reg = spe_allocate_available_register(gen->f);
 803
 804       if (reg < 0)
 805          return false;
 806
 807       /* update immediate map */
 808       gen->imm_regs[gen->num_imm][ch] = reg;
 809
 810       /* emit initializer instruction */
 811       spe_load_float(gen->f, reg, val);
 812    }
 813
 814    gen->num_imm++;
 815
 816    return true;
 817 }
 818
 819
 820
 821 /**
 822  * Emit "code" for a TGSI declaration.
 823  * We only care about TGSI TEMPORARY register declarations at this time.
 824  * For each TGSI TEMPORARY we allocate four SPE registers.
 825  */
 826 static boolean
 827 emit_declaration(struct codegen *gen, const struct tgsi_full_declaration *decl)
 828 {
 829    int i, ch;
 830
 831    switch (decl->Declaration.File) {
 832    case TGSI_FILE_TEMPORARY:
 833 #if DISASSEM
 834       printf("Declare temp reg %d .. %d\n",
 835              decl->DeclarationRange.First,
 836              decl->DeclarationRange.Last);
 837 #endif
 838       for (i = decl->DeclarationRange.First;
 839            i <= decl->DeclarationRange.Last;
 840            i++) {
 841          assert(i < MAX_TEMPS);
 842          for (ch = 0; ch < 4; ch++) {
 843             gen->temp_regs[i][ch] = spe_allocate_available_register(gen->f);
 844             if (gen->temp_regs[i][ch] < 0)
 845                return false; /* out of regs */
 846          }
 847
 848          /* XXX if we run out of SPE registers, we need to spill
 849           * to SPU memory.  someday...
 850           */
 851
 852 #if DISASSEM
 853          printf("  SPE regs: %d %d %d %d\n",
 854                 gen->temp_regs[i][0],
 855                 gen->temp_regs[i][1],
 856                 gen->temp_regs[i][2],
 857                 gen->temp_regs[i][3]);
 858 #endif
 859       }
 860       break;
 861    default:
 862       ; /* ignore */
 863    }
 864
 865    return true;
 866 }
 867
 868
 869 /**
 870  * Translate TGSI shader code to SPE instructions.  This is done when
 871  * the state tracker gives us a new shader (via pipe->create_fs_state()).
 872  *
 873  * \param cell    the rendering context (in)
 874  * \param tokens  the TGSI shader (in)
 875  * \param f       the generated function (out)
 876  */
 877 boolean
 878 cell_gen_fragment_program(struct cell_context *cell,
 879                           const struct tgsi_token *tokens,
 880                           struct spe_function *f)
 881 {
 882    struct tgsi_parse_context parse;
 883    struct codegen gen;
 884
 885    memset(&gen, 0, sizeof(gen));
 886    gen.f = f;
 887
 888    /* For SPE function calls: reg $3 = first param, $4 = second param, etc. */
 889    gen.inputs_reg = 3;     /* pointer to inputs array */
 890    gen.outputs_reg = 4;    /* pointer to outputs array */
 891    gen.constants_reg = 5;  /* pointer to constants array */
 892
 893    spe_init_func(f, SPU_MAX_FRAGMENT_PROGRAM_INSTS * SPE_INST_SIZE);
 894    spe_allocate_register(f, gen.inputs_reg);
 895    spe_allocate_register(f, gen.outputs_reg);
 896    spe_allocate_register(f, gen.constants_reg);
 897
 898 #if DISASSEM
 899    spe_print_code(f, true);
 900    spe_indent(f, 8);
 901    printf("Begin %s\n", __FUNCTION__);
 902    tgsi_dump(tokens, 0);
 903 #endif
 904
 905    tgsi_parse_init(&parse, tokens);
 906
 907    while (!tgsi_parse_end_of_tokens(&parse) && !gen.error) {
 908       tgsi_parse_token(&parse);
 909
 910       switch (parse.FullToken.Token.Type) {
 911       case TGSI_TOKEN_TYPE_IMMEDIATE:
 912          if (!emit_immediate(&gen,  &parse.FullToken.FullImmediate))
 913             gen.error = true;
 914          break;
 915
 916       case TGSI_TOKEN_TYPE_DECLARATION:
 917          if (!emit_declaration(&gen, &parse.FullToken.FullDeclaration))
 918             gen.error = true;
 919          break;
 920
 921       case TGSI_TOKEN_TYPE_INSTRUCTION:
 922          if (!emit_instruction(&gen, &parse.FullToken.FullInstruction))
 923             gen.error = true;
 924          break;
 925
 926       default:
 927          assert(0);
 928       }
 929    }
 930
 931
 932    if (gen.error) {
 933       /* terminate the SPE code */
 934       return emit_END(&gen);
 935    }
 936
 937 #if DISASSEM
 938    printf("cell_gen_fragment_program nr instructions: %d\n", f->num_inst);
 939    printf("End %s\n", __FUNCTION__);
 940 #endif
 941
 942    tgsi_parse_free( &parse );
 943
 944    return !gen.error;
 945 }