src/gallium/drivers/cell/spu/spu_command.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 /**
  30  * SPU command processing code
  31  */
  32
  33
  34 #include <stdio.h>
  35 #include <libmisc.h>
  36
  37 #include "pipe/p_defines.h"
  38
  39 #include "spu_command.h"
  40 #include "spu_main.h"
  41 #include "spu_render.h"
  42 #include "spu_per_fragment_op.h"
  43 #include "spu_texture.h"
  44 #include "spu_tile.h"
  45 #include "spu_vertex_shader.h"
  46 #include "spu_dcache.h"
  47 #include "cell/common.h"
  48
  49
  50 struct spu_vs_context draw;
  51
  52
  53 /**
  54  * Buffers containing dynamically generated SPU code:
  55  */
  56 static unsigned char attribute_fetch_code_buffer[136 * PIPE_MAX_ATTRIBS]
  57     ALIGN16_ATTRIB;
  58
  59
  60
  61 static INLINE int
  62 align(int value, int alignment)
  63 {
  64    return (value + alignment - 1) & ~(alignment - 1);
  65 }
  66
  67
  68
  69 /**
  70  * Tell the PPU that this SPU has finished copying a buffer to
  71  * local store and that it may be reused by the PPU.
  72  * This is done by writting a 16-byte batch-buffer-status block back into
  73  * main memory (in cell_context->buffer_status[]).
  74  */
  75 static void
  76 release_buffer(uint buffer)
  77 {
  78    /* Evidently, using less than a 16-byte status doesn't work reliably */
  79    static const vector unsigned int status = {CELL_BUFFER_STATUS_FREE,
  80                                               CELL_BUFFER_STATUS_FREE,
  81                                               CELL_BUFFER_STATUS_FREE,
  82                                               CELL_BUFFER_STATUS_FREE};
  83    const uint index = 4 * (spu.init.id * CELL_NUM_BUFFERS + buffer);
  84    uint *dst = spu.init.buffer_status + index;
  85
  86    ASSERT(buffer < CELL_NUM_BUFFERS);
  87
  88    mfc_put((void *) &status,    /* src in local memory */
  89            (unsigned int) dst,  /* dst in main memory */
  90            sizeof(status),      /* size */
  91            TAG_MISC,            /* tag is unimportant */
  92            0, /* tid */
  93            0  /* rid */);
  94 }
  95
  96
  97 /**
  98  * Write CELL_FENCE_SIGNALLED back to the fence status qword in main memory.
  99  * There's a qword of status per SPU.
 100  */
 101 static void
 102 cmd_fence(struct cell_command_fence *fence_cmd)
 103 {
 104    static const vector unsigned int status = {CELL_FENCE_SIGNALLED,
 105                                               CELL_FENCE_SIGNALLED,
 106                                               CELL_FENCE_SIGNALLED,
 107                                               CELL_FENCE_SIGNALLED};
 108    uint *dst = (uint *) fence_cmd->fence;
 109    dst += 4 * spu.init.id;  /* main store/memory address, not local store */
 110    ASSERT_ALIGN16(dst);
 111    mfc_put((void *) &status,    /* src in local memory */
 112            (unsigned int) dst,  /* dst in main memory */
 113            sizeof(status),      /* size */
 114            TAG_FENCE,           /* tag */
 115            0, /* tid */
 116            0  /* rid */);
 117 }
 118
 119
 120 static void
 121 cmd_clear_surface(const struct cell_command_clear_surface *clear)
 122 {
 123    D_PRINTF(CELL_DEBUG_CMD, "CLEAR SURF %u to 0x%08x\n", clear->surface, clear->value);
 124
 125    if (clear->surface == 0) {
 126       spu.fb.color_clear_value = clear->value;
 127       if (spu.init.debug_flags & CELL_DEBUG_CHECKER) {
 128          uint x = (spu.init.id << 4) | (spu.init.id << 12) |
 129             (spu.init.id << 20) | (spu.init.id << 28);
 130          spu.fb.color_clear_value ^= x;
 131       }
 132    }
 133    else {
 134       spu.fb.depth_clear_value = clear->value;
 135    }
 136
 137 #define CLEAR_OPT 1
 138 #if CLEAR_OPT
 139
 140    /* Simply set all tiles' status to CLEAR.
 141     * When we actually begin rendering into a tile, we'll initialize it to
 142     * the clear value.  If any tiles go untouched during the frame,
 143     * really_clear_tiles() will set them to the clear value.
 144     */
 145    if (clear->surface == 0) {
 146       memset(spu.ctile_status, TILE_STATUS_CLEAR, sizeof(spu.ctile_status));
 147    }
 148    else {
 149       memset(spu.ztile_status, TILE_STATUS_CLEAR, sizeof(spu.ztile_status));
 150    }
 151
 152 #else
 153
 154    /*
 155     * This path clears the whole framebuffer to the clear color right now.
 156     */
 157
 158    /*
 159    printf("SPU: %s num=%d w=%d h=%d\n",
 160           __FUNCTION__, num_tiles, spu.fb.width_tiles, spu.fb.height_tiles);
 161    */
 162
 163    /* init a single tile to the clear value */
 164    if (clear->surface == 0) {
 165       clear_c_tile(&spu.ctile);
 166    }
 167    else {
 168       clear_z_tile(&spu.ztile);
 169    }
 170
 171    /* walk over my tiles, writing the 'clear' tile's data */
 172    {
 173       const uint num_tiles = spu.fb.width_tiles * spu.fb.height_tiles;
 174       uint i;
 175       for (i = spu.init.id; i < num_tiles; i += spu.init.num_spus) {
 176          uint tx = i % spu.fb.width_tiles;
 177          uint ty = i / spu.fb.width_tiles;
 178          if (clear->surface == 0)
 179             put_tile(tx, ty, &spu.ctile, TAG_SURFACE_CLEAR, 0);
 180          else
 181             put_tile(tx, ty, &spu.ztile, TAG_SURFACE_CLEAR, 1);
 182       }
 183    }
 184
 185    if (spu.init.debug_flags & CELL_DEBUG_SYNC) {
 186       wait_on_mask(1 << TAG_SURFACE_CLEAR);
 187    }
 188
 189 #endif /* CLEAR_OPT */
 190
 191    D_PRINTF(CELL_DEBUG_CMD, "CLEAR SURF done\n");
 192 }
 193
 194
 195 static void
 196 cmd_release_verts(const struct cell_command_release_verts *release)
 197 {
 198    D_PRINTF(CELL_DEBUG_CMD, "RELEASE VERTS %u\n", release->vertex_buf);
 199    ASSERT(release->vertex_buf != ~0U);
 200    release_buffer(release->vertex_buf);
 201 }
 202
 203
 204 /**
 205  * Process a CELL_CMD_STATE_FRAGMENT_OPS command.
 206  * This involves installing new fragment ops SPU code.
 207  * If this function is never called, we'll use a regular C fallback function
 208  * for fragment processing.
 209  */
 210 static void
 211 cmd_state_fragment_ops(const struct cell_command_fragment_ops *fops)
 212 {
 213    static int warned = 0;
 214
 215    D_PRINTF(CELL_DEBUG_CMD, "CMD_STATE_FRAGMENT_OPS\n");
 216    /* Copy SPU code from batch buffer to spu buffer */
 217    memcpy(spu.fragment_ops_code, fops->code, SPU_MAX_FRAGMENT_OPS_INSTS * 4);
 218    /* Copy state info (for fallback case only) */
 219    memcpy(&spu.depth_stencil_alpha, &fops->dsa, sizeof(fops->dsa));
 220    memcpy(&spu.blend, &fops->blend, sizeof(fops->blend));
 221    memcpy(&spu.blend_color, &fops->blend_color, sizeof(fops->blend_color));
 222
 223    /* Parity twist!  For now, always use the fallback code by default,
 224     * only switching to codegen when specifically requested.  This
 225     * allows us to develop freely without risking taking down the
 226     * branch.
 227     *
 228     * Later, the parity of this check will be reversed, so that
 229     * codegen is *always* used, unless we specifically indicate that
 230     * we don't want it.
 231     *
 232     * Eventually, the option will be removed completely, because in
 233     * final code we'll always use codegen and won't even provide the
 234     * raw state records that the fallback code requires.
 235     */
 236    if ((spu.init.debug_flags & CELL_DEBUG_FRAGMENT_OP_FALLBACK) == 0) {
 237       spu.fragment_ops = (spu_fragment_ops_func) spu.fragment_ops_code;
 238    }
 239    else {
 240       /* otherwise, the default fallback code remains in place */
 241       if (!warned) {
 242          fprintf(stderr, "Cell Warning: using fallback per-fragment code\n");
 243          warned = 1;
 244       }
 245    }
 246
 247    spu.read_depth_stencil = (spu.depth_stencil_alpha.depth.enabled || spu.depth_stencil_alpha.stencil[0].enabled);
 248 }
 249
 250
 251 static void
 252 cmd_state_fragment_program(const struct cell_command_fragment_program *fp)
 253 {
 254    D_PRINTF(CELL_DEBUG_CMD, "CMD_STATE_FRAGMENT_PROGRAM\n");
 255    /* Copy SPU code from batch buffer to spu buffer */
 256    memcpy(spu.fragment_program_code, fp->code,
 257           SPU_MAX_FRAGMENT_PROGRAM_INSTS * 4);
 258 #if 01
 259    /* Point function pointer at new code */
 260    spu.fragment_program = (spu_fragment_program_func)spu.fragment_program_code;
 261 #endif
 262 }
 263
 264
 265 static uint
 266 cmd_state_fs_constants(const uint64_t *buffer, uint pos)
 267 {
 268    const uint num_const = buffer[pos + 1];
 269    const float *constants = (const float *) &buffer[pos + 2];
 270    uint i;
 271
 272    D_PRINTF(CELL_DEBUG_CMD, "CMD_STATE_FS_CONSTANTS (%u)\n", num_const);
 273
 274    /* Expand each float to float[4] for SOA execution */
 275    for (i = 0; i < num_const; i++) {
 276       D_PRINTF(CELL_DEBUG_CMD, "  const[%u] = %f\n", i, constants[i]);
 277       spu.constants[i] = spu_splats(constants[i]);
 278    }
 279
 280    /* return new buffer pos (in 8-byte words) */
 281    return pos + 2 + num_const / 2;
 282 }
 283
 284
 285 static void
 286 cmd_state_framebuffer(const struct cell_command_framebuffer *cmd)
 287 {
 288    D_PRINTF(CELL_DEBUG_CMD, "FRAMEBUFFER: %d x %d at %p, cformat 0x%x  zformat 0x%x\n",
 289              cmd->width,
 290              cmd->height,
 291              cmd->color_start,
 292              cmd->color_format,
 293              cmd->depth_format);
 294
 295    ASSERT_ALIGN16(cmd->color_start);
 296    ASSERT_ALIGN16(cmd->depth_start);
 297
 298    spu.fb.color_start = cmd->color_start;
 299    spu.fb.depth_start = cmd->depth_start;
 300    spu.fb.color_format = cmd->color_format;
 301    spu.fb.depth_format = cmd->depth_format;
 302    spu.fb.width = cmd->width;
 303    spu.fb.height = cmd->height;
 304    spu.fb.width_tiles = (spu.fb.width + TILE_SIZE - 1) / TILE_SIZE;
 305    spu.fb.height_tiles = (spu.fb.height + TILE_SIZE - 1) / TILE_SIZE;
 306
 307    switch (spu.fb.depth_format) {
 308    case PIPE_FORMAT_Z32_UNORM:
 309       spu.fb.zsize = 4;
 310       spu.fb.zscale = (float) 0xffffffffu;
 311       break;
 312    case PIPE_FORMAT_Z24S8_UNORM:
 313    case PIPE_FORMAT_S8Z24_UNORM:
 314    case PIPE_FORMAT_Z24X8_UNORM:
 315    case PIPE_FORMAT_X8Z24_UNORM:
 316       spu.fb.zsize = 4;
 317       spu.fb.zscale = (float) 0x00ffffffu;
 318       break;
 319    case PIPE_FORMAT_Z16_UNORM:
 320       spu.fb.zsize = 2;
 321       spu.fb.zscale = (float) 0xffffu;
 322       break;
 323    default:
 324       spu.fb.zsize = 0;
 325       break;
 326    }
 327 }
 328
 329
 330 /**
 331  * Tex texture mask_s/t and scale_s/t fields depend on the texture size and
 332  * sampler wrap modes.
 333  */
 334 static void
 335 update_tex_masks(struct spu_texture *texture,
 336                  const struct pipe_sampler_state *sampler)
 337 {
 338    uint i;
 339
 340    for (i = 0; i < CELL_MAX_TEXTURE_LEVELS; i++) {
 341       int width = texture->level[i].width;
 342       int height = texture->level[i].height;
 343
 344       if (sampler->wrap_s == PIPE_TEX_WRAP_REPEAT)
 345          texture->level[i].mask_s = spu_splats(width - 1);
 346       else
 347          texture->level[i].mask_s = spu_splats(~0);
 348
 349       if (sampler->wrap_t == PIPE_TEX_WRAP_REPEAT)
 350          texture->level[i].mask_t = spu_splats(height - 1);
 351       else
 352          texture->level[i].mask_t = spu_splats(~0);
 353
 354       if (sampler->normalized_coords) {
 355          texture->level[i].scale_s = spu_splats((float) width);
 356          texture->level[i].scale_t = spu_splats((float) height);
 357       }
 358       else {
 359          texture->level[i].scale_s = spu_splats(1.0f);
 360          texture->level[i].scale_t = spu_splats(1.0f);
 361       }
 362    }
 363 }
 364
 365
 366 static void
 367 cmd_state_sampler(const struct cell_command_sampler *sampler)
 368 {
 369    uint unit = sampler->unit;
 370
 371    D_PRINTF(CELL_DEBUG_CMD, "SAMPLER [%u]\n", unit);
 372
 373    spu.sampler[unit] = sampler->state;
 374
 375    switch (spu.sampler[unit].min_img_filter) {
 376    case PIPE_TEX_FILTER_LINEAR:
 377       spu.min_sample_texture_2d[unit] = sample_texture_2d_bilinear;
 378       break;
 379    case PIPE_TEX_FILTER_ANISO:
 380       /* fall-through, for now */
 381    case PIPE_TEX_FILTER_NEAREST:
 382       spu.min_sample_texture_2d[unit] = sample_texture_2d_nearest;
 383       break;
 384    default:
 385       ASSERT(0);
 386    }
 387
 388    switch (spu.sampler[sampler->unit].mag_img_filter) {
 389    case PIPE_TEX_FILTER_LINEAR:
 390       spu.mag_sample_texture_2d[unit] = sample_texture_2d_bilinear;
 391       break;
 392    case PIPE_TEX_FILTER_ANISO:
 393       /* fall-through, for now */
 394    case PIPE_TEX_FILTER_NEAREST:
 395       spu.mag_sample_texture_2d[unit] = sample_texture_2d_nearest;
 396       break;
 397    default:
 398       ASSERT(0);
 399    }
 400
 401    switch (spu.sampler[sampler->unit].min_mip_filter) {
 402    case PIPE_TEX_MIPFILTER_NEAREST:
 403    case PIPE_TEX_MIPFILTER_LINEAR:
 404       spu.sample_texture_2d[unit] = sample_texture_2d_lod;
 405       break;
 406    case PIPE_TEX_MIPFILTER_NONE:
 407       spu.sample_texture_2d[unit] = spu.mag_sample_texture_2d[unit];
 408       break;
 409    default:
 410       ASSERT(0);
 411    }
 412
 413    update_tex_masks(&spu.texture[unit], &spu.sampler[unit]);
 414 }
 415
 416
 417 static void
 418 cmd_state_texture(const struct cell_command_texture *texture)
 419 {
 420    const uint unit = texture->unit;
 421    uint i;
 422
 423    D_PRINTF(CELL_DEBUG_CMD, "TEXTURE [%u]\n", texture->unit);
 424
 425    spu.texture[unit].max_level = 0;
 426    spu.texture[unit].target = texture->target;
 427
 428    for (i = 0; i < CELL_MAX_TEXTURE_LEVELS; i++) {
 429       uint width = texture->width[i];
 430       uint height = texture->height[i];
 431       uint depth = texture->depth[i];
 432
 433       D_PRINTF(CELL_DEBUG_CMD, "  LEVEL %u: at %p  size[0] %u x %u\n", i,
 434              texture->start[i], texture->width[i], texture->height[i]);
 435
 436       spu.texture[unit].level[i].start = texture->start[i];
 437       spu.texture[unit].level[i].width = width;
 438       spu.texture[unit].level[i].height = height;
 439       spu.texture[unit].level[i].depth = depth;
 440
 441       spu.texture[unit].level[i].tiles_per_row =
 442          (width + TILE_SIZE - 1) / TILE_SIZE;
 443
 444       spu.texture[unit].level[i].bytes_per_image =
 445          4 * align(width, TILE_SIZE) * align(height, TILE_SIZE) * depth;
 446
 447       spu.texture[unit].level[i].max_s = spu_splats((int) width - 1);
 448       spu.texture[unit].level[i].max_t = spu_splats((int) height - 1);
 449
 450       if (texture->start[i])
 451          spu.texture[unit].max_level = i;
 452    }
 453
 454    update_tex_masks(&spu.texture[unit], &spu.sampler[unit]);
 455 }
 456
 457
 458 static void
 459 cmd_state_vertex_info(const struct vertex_info *vinfo)
 460 {
 461    D_PRINTF(CELL_DEBUG_CMD, "VERTEX_INFO num_attribs=%u\n", vinfo->num_attribs);
 462    ASSERT(vinfo->num_attribs >= 1);
 463    ASSERT(vinfo->num_attribs <= 8);
 464    memcpy(&spu.vertex_info, vinfo, sizeof(*vinfo));
 465 }
 466
 467
 468 static void
 469 cmd_state_vs_array_info(const struct cell_array_info *vs_info)
 470 {
 471    const unsigned attr = vs_info->attr;
 472
 473    ASSERT(attr < PIPE_MAX_ATTRIBS);
 474    draw.vertex_fetch.src_ptr[attr] = vs_info->base;
 475    draw.vertex_fetch.pitch[attr] = vs_info->pitch;
 476    draw.vertex_fetch.size[attr] = vs_info->size;
 477    draw.vertex_fetch.code_offset[attr] = vs_info->function_offset;
 478    draw.vertex_fetch.dirty = 1;
 479 }
 480
 481
 482 static void
 483 cmd_state_attrib_fetch(const struct cell_attribute_fetch_code *code)
 484 {
 485    mfc_get(attribute_fetch_code_buffer,
 486            (unsigned int) code->base,  /* src */
 487            code->size,
 488            TAG_BATCH_BUFFER,
 489            0, /* tid */
 490            0  /* rid */);
 491    wait_on_mask(1 << TAG_BATCH_BUFFER);
 492
 493    draw.vertex_fetch.code = attribute_fetch_code_buffer;
 494 }
 495
 496
 497 static void
 498 cmd_finish(void)
 499 {
 500    D_PRINTF(CELL_DEBUG_CMD, "FINISH\n");
 501    really_clear_tiles(0);
 502    /* wait for all outstanding DMAs to finish */
 503    mfc_write_tag_mask(~0);
 504    mfc_read_tag_status_all();
 505    /* send mbox message to PPU */
 506    spu_write_out_mbox(CELL_CMD_FINISH);
 507 }
 508
 509
 510 /**
 511  * Execute a batch of commands which was sent to us by the PPU.
 512  * See the cell_emit_state.c code to see where the commands come from.
 513  *
 514  * The opcode param encodes the location of the buffer and its size.
 515  */
 516 static void
 517 cmd_batch(uint opcode)
 518 {
 519    const uint buf = (opcode >> 8) & 0xff;
 520    uint size = (opcode >> 16);
 521    uint64_t buffer[CELL_BUFFER_SIZE / 8] ALIGN16_ATTRIB;
 522    const unsigned usize = size / sizeof(buffer[0]);
 523    uint pos;
 524
 525    D_PRINTF(CELL_DEBUG_CMD, "BATCH buffer %u, len %u, from %p\n",
 526              buf, size, spu.init.buffers[buf]);
 527
 528    ASSERT((opcode & CELL_CMD_OPCODE_MASK) == CELL_CMD_BATCH);
 529
 530    ASSERT_ALIGN16(spu.init.buffers[buf]);
 531
 532    size = ROUNDUP16(size);
 533
 534    ASSERT_ALIGN16(spu.init.buffers[buf]);
 535
 536    mfc_get(buffer,  /* dest */
 537            (unsigned int) spu.init.buffers[buf],  /* src */
 538            size,
 539            TAG_BATCH_BUFFER,
 540            0, /* tid */
 541            0  /* rid */);
 542    wait_on_mask(1 << TAG_BATCH_BUFFER);
 543
 544    /* Tell PPU we're done copying the buffer to local store */
 545    D_PRINTF(CELL_DEBUG_CMD, "release batch buf %u\n", buf);
 546    release_buffer(buf);
 547
 548    /*
 549     * Loop over commands in the batch buffer
 550     */
 551    for (pos = 0; pos < usize; /* no incr */) {
 552       switch (buffer[pos]) {
 553       /*
 554        * rendering commands
 555        */
 556       case CELL_CMD_CLEAR_SURFACE:
 557          {
 558             struct cell_command_clear_surface *clr
 559                = (struct cell_command_clear_surface *) &buffer[pos];
 560             cmd_clear_surface(clr);
 561             pos += sizeof(*clr) / 8;
 562          }
 563          break;
 564       case CELL_CMD_RENDER:
 565          {
 566             struct cell_command_render *render
 567                = (struct cell_command_render *) &buffer[pos];
 568             uint pos_incr;
 569             cmd_render(render, &pos_incr);
 570             pos += pos_incr;
 571          }
 572          break;
 573       /*
 574        * state-update commands
 575        */
 576       case CELL_CMD_STATE_FRAMEBUFFER:
 577          {
 578             struct cell_command_framebuffer *fb
 579                = (struct cell_command_framebuffer *) &buffer[pos];
 580             cmd_state_framebuffer(fb);
 581             pos += sizeof(*fb) / 8;
 582          }
 583          break;
 584       case CELL_CMD_STATE_FRAGMENT_OPS:
 585          {
 586             struct cell_command_fragment_ops *fops
 587                = (struct cell_command_fragment_ops *) &buffer[pos];
 588             cmd_state_fragment_ops(fops);
 589             pos += sizeof(*fops) / 8;
 590          }
 591          break;
 592       case CELL_CMD_STATE_FRAGMENT_PROGRAM:
 593          {
 594             struct cell_command_fragment_program *fp
 595                = (struct cell_command_fragment_program *) &buffer[pos];
 596             cmd_state_fragment_program(fp);
 597             pos += sizeof(*fp) / 8;
 598          }
 599          break;
 600       case CELL_CMD_STATE_FS_CONSTANTS:
 601          pos = cmd_state_fs_constants(buffer, pos);
 602          break;
 603       case CELL_CMD_STATE_RASTERIZER:
 604          {
 605             struct cell_command_rasterizer *rast =
 606                (struct cell_command_rasterizer *) &buffer[pos];
 607             spu.rasterizer = rast->rasterizer;
 608             pos += sizeof(*rast) / 8;
 609          }
 610          break;
 611       case CELL_CMD_STATE_SAMPLER:
 612          {
 613             struct cell_command_sampler *sampler
 614                = (struct cell_command_sampler *) &buffer[pos];
 615             cmd_state_sampler(sampler);
 616             pos += sizeof(*sampler) / 8;
 617          }
 618          break;
 619       case CELL_CMD_STATE_TEXTURE:
 620          {
 621             struct cell_command_texture *texture
 622                = (struct cell_command_texture *) &buffer[pos];
 623             cmd_state_texture(texture);
 624             pos += sizeof(*texture) / 8;
 625          }
 626          break;
 627       case CELL_CMD_STATE_VERTEX_INFO:
 628          cmd_state_vertex_info((struct vertex_info *) &buffer[pos+1]);
 629          pos += (1 + ROUNDUP8(sizeof(struct vertex_info)) / 8);
 630          break;
 631       case CELL_CMD_STATE_VIEWPORT:
 632          (void) memcpy(& draw.viewport, &buffer[pos+1],
 633                        sizeof(struct pipe_viewport_state));
 634          pos += (1 + ROUNDUP8(sizeof(struct pipe_viewport_state)) / 8);
 635          break;
 636       case CELL_CMD_STATE_UNIFORMS:
 637          draw.constants = (const float (*)[4]) (uintptr_t) buffer[pos + 1];
 638          pos += 2;
 639          break;
 640       case CELL_CMD_STATE_VS_ARRAY_INFO:
 641          cmd_state_vs_array_info((struct cell_array_info *) &buffer[pos+1]);
 642          pos += (1 + ROUNDUP8(sizeof(struct cell_array_info)) / 8);
 643          break;
 644       case CELL_CMD_STATE_BIND_VS:
 645 #if 0
 646          spu_bind_vertex_shader(&draw,
 647                                 (struct cell_shader_info *) &buffer[pos+1]);
 648 #endif
 649          pos += (1 + ROUNDUP8(sizeof(struct cell_shader_info)) / 8);
 650          break;
 651       case CELL_CMD_STATE_ATTRIB_FETCH:
 652          cmd_state_attrib_fetch((struct cell_attribute_fetch_code *)
 653                                 &buffer[pos+1]);
 654          pos += (1 + ROUNDUP8(sizeof(struct cell_attribute_fetch_code)) / 8);
 655          break;
 656       /*
 657        * misc commands
 658        */
 659       case CELL_CMD_FINISH:
 660          cmd_finish();
 661          pos += 1;
 662          break;
 663       case CELL_CMD_FENCE:
 664          {
 665             struct cell_command_fence *fence_cmd =
 666                (struct cell_command_fence *) &buffer[pos];
 667             cmd_fence(fence_cmd);
 668             pos += sizeof(*fence_cmd) / 8;
 669          }
 670          break;
 671       case CELL_CMD_RELEASE_VERTS:
 672          {
 673             struct cell_command_release_verts *release
 674                = (struct cell_command_release_verts *) &buffer[pos];
 675             cmd_release_verts(release);
 676             pos += sizeof(*release) / 8;
 677          }
 678          break;
 679       case CELL_CMD_FLUSH_BUFFER_RANGE: {
 680          struct cell_buffer_range *br = (struct cell_buffer_range *)
 681              &buffer[pos+1];
 682
 683          spu_dcache_mark_dirty((unsigned) br->base, br->size);
 684          pos += (1 + ROUNDUP8(sizeof(struct cell_buffer_range)) / 8);
 685          break;
 686       }
 687       default:
 688          printf("SPU %u: bad opcode: 0x%llx\n", spu.init.id, buffer[pos]);
 689          ASSERT(0);
 690          break;
 691       }
 692    }
 693
 694    D_PRINTF(CELL_DEBUG_CMD, "BATCH complete\n");
 695 }
 696
 697
 698 #define PERF 0
 699
 700
 701 /**
 702  * Main loop for SPEs: Get a command, execute it, repeat.
 703  */
 704 void
 705 command_loop(void)
 706 {
 707    int exitFlag = 0;
 708    uint t0, t1;
 709
 710    D_PRINTF(CELL_DEBUG_CMD, "Enter command loop\n");
 711
 712    while (!exitFlag) {
 713       unsigned opcode;
 714
 715       D_PRINTF(CELL_DEBUG_CMD, "Wait for cmd...\n");
 716
 717       if (PERF)
 718          spu_write_decrementer(~0);
 719
 720       /* read/wait from mailbox */
 721       opcode = (unsigned int) spu_read_in_mbox();
 722       D_PRINTF(CELL_DEBUG_CMD, "got cmd 0x%x\n", opcode);
 723
 724       if (PERF)
 725          t0 = spu_read_decrementer();
 726
 727       switch (opcode & CELL_CMD_OPCODE_MASK) {
 728       case CELL_CMD_EXIT:
 729          D_PRINTF(CELL_DEBUG_CMD, "EXIT\n");
 730          exitFlag = 1;
 731          break;
 732       case CELL_CMD_VS_EXECUTE:
 733 #if 0
 734          spu_execute_vertex_shader(&draw, &cmd.vs);
 735 #endif
 736          break;
 737       case CELL_CMD_BATCH:
 738          cmd_batch(opcode);
 739          break;
 740       default:
 741          printf("Bad opcode 0x%x!\n", opcode & CELL_CMD_OPCODE_MASK);
 742       }
 743
 744       if (PERF) {
 745          t1 = spu_read_decrementer();
 746          printf("wait mbox time: %gms   batch time: %gms\n",
 747                 (~0u - t0) * spu.init.inv_timebase,
 748                 (t0 - t1) * spu.init.inv_timebase);
 749       }
 750    }
 751
 752    D_PRINTF(CELL_DEBUG_CMD, "Exit command loop\n");
 753
 754    if (spu.init.debug_flags & CELL_DEBUG_CACHE)
 755       spu_dcache_report();
 756 }