src/gallium/drivers/cell/spu/spu_command.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 /**
  30  * SPU command processing code
  31  */
  32
  33
  34 #include <stdio.h>
  35 #include <libmisc.h>
  36
  37 #include "pipe/p_defines.h"
  38
  39 #include "spu_command.h"
  40 #include "spu_main.h"
  41 #include "spu_render.h"
  42 #include "spu_per_fragment_op.h"
  43 #include "spu_texture.h"
  44 #include "spu_tile.h"
  45 #include "spu_vertex_shader.h"
  46 #include "spu_dcache.h"
  47 #include "cell/common.h"
  48
  49
  50 struct spu_vs_context draw;
  51
  52
  53 /**
  54  * Buffers containing dynamically generated SPU code:
  55  */
  56 static unsigned char attribute_fetch_code_buffer[136 * PIPE_MAX_ATTRIBS]
  57     ALIGN16_ATTRIB;
  58
  59
  60
  61 static INLINE int
  62 align(int value, int alignment)
  63 {
  64    return (value + alignment - 1) & ~(alignment - 1);
  65 }
  66
  67
  68
  69 /**
  70  * Tell the PPU that this SPU has finished copying a buffer to
  71  * local store and that it may be reused by the PPU.
  72  * This is done by writting a 16-byte batch-buffer-status block back into
  73  * main memory (in cell_context->buffer_status[]).
  74  */
  75 static void
  76 release_buffer(uint buffer)
  77 {
  78    /* Evidently, using less than a 16-byte status doesn't work reliably */
  79    static const vector unsigned int status = {CELL_BUFFER_STATUS_FREE,
  80                                               CELL_BUFFER_STATUS_FREE,
  81                                               CELL_BUFFER_STATUS_FREE,
  82                                               CELL_BUFFER_STATUS_FREE};
  83    const uint index = 4 * (spu.init.id * CELL_NUM_BUFFERS + buffer);
  84    uint *dst = spu.init.buffer_status + index;
  85
  86    ASSERT(buffer < CELL_NUM_BUFFERS);
  87
  88    mfc_put((void *) &status,    /* src in local memory */
  89            (unsigned int) dst,  /* dst in main memory */
  90            sizeof(status),      /* size */
  91            TAG_MISC,            /* tag is unimportant */
  92            0, /* tid */
  93            0  /* rid */);
  94 }
  95
  96
  97 /**
  98  * Write CELL_FENCE_SIGNALLED back to the fence status qword in main memory.
  99  * There's a qword of status per SPU.
 100  */
 101 static void
 102 cmd_fence(struct cell_command_fence *fence_cmd)
 103 {
 104    static const vector unsigned int status = {CELL_FENCE_SIGNALLED,
 105                                               CELL_FENCE_SIGNALLED,
 106                                               CELL_FENCE_SIGNALLED,
 107                                               CELL_FENCE_SIGNALLED};
 108    uint *dst = (uint *) fence_cmd->fence;
 109    dst += 4 * spu.init.id;  /* main store/memory address, not local store */
 110    ASSERT_ALIGN16(dst);
 111    mfc_put((void *) &status,    /* src in local memory */
 112            (unsigned int) dst,  /* dst in main memory */
 113            sizeof(status),      /* size */
 114            TAG_FENCE,           /* tag */
 115            0, /* tid */
 116            0  /* rid */);
 117 }
 118
 119
 120 static void
 121 cmd_clear_surface(const struct cell_command_clear_surface *clear)
 122 {
 123    D_PRINTF(CELL_DEBUG_CMD, "CLEAR SURF %u to 0x%08x\n", clear->surface, clear->value);
 124
 125    if (clear->surface == 0) {
 126       spu.fb.color_clear_value = clear->value;
 127       if (spu.init.debug_flags & CELL_DEBUG_CHECKER) {
 128          uint x = (spu.init.id << 4) | (spu.init.id << 12) |
 129             (spu.init.id << 20) | (spu.init.id << 28);
 130          spu.fb.color_clear_value ^= x;
 131       }
 132    }
 133    else {
 134       spu.fb.depth_clear_value = clear->value;
 135    }
 136
 137 #define CLEAR_OPT 1
 138 #if CLEAR_OPT
 139
 140    /* Simply set all tiles' status to CLEAR.
 141     * When we actually begin rendering into a tile, we'll initialize it to
 142     * the clear value.  If any tiles go untouched during the frame,
 143     * really_clear_tiles() will set them to the clear value.
 144     */
 145    if (clear->surface == 0) {
 146       memset(spu.ctile_status, TILE_STATUS_CLEAR, sizeof(spu.ctile_status));
 147    }
 148    else {
 149       memset(spu.ztile_status, TILE_STATUS_CLEAR, sizeof(spu.ztile_status));
 150    }
 151
 152 #else
 153
 154    /*
 155     * This path clears the whole framebuffer to the clear color right now.
 156     */
 157
 158    /*
 159    printf("SPU: %s num=%d w=%d h=%d\n",
 160           __FUNCTION__, num_tiles, spu.fb.width_tiles, spu.fb.height_tiles);
 161    */
 162
 163    /* init a single tile to the clear value */
 164    if (clear->surface == 0) {
 165       clear_c_tile(&spu.ctile);
 166    }
 167    else {
 168       clear_z_tile(&spu.ztile);
 169    }
 170
 171    /* walk over my tiles, writing the 'clear' tile's data */
 172    {
 173       const uint num_tiles = spu.fb.width_tiles * spu.fb.height_tiles;
 174       uint i;
 175       for (i = spu.init.id; i < num_tiles; i += spu.init.num_spus) {
 176          uint tx = i % spu.fb.width_tiles;
 177          uint ty = i / spu.fb.width_tiles;
 178          if (clear->surface == 0)
 179             put_tile(tx, ty, &spu.ctile, TAG_SURFACE_CLEAR, 0);
 180          else
 181             put_tile(tx, ty, &spu.ztile, TAG_SURFACE_CLEAR, 1);
 182       }
 183    }
 184
 185    if (spu.init.debug_flags & CELL_DEBUG_SYNC) {
 186       wait_on_mask(1 << TAG_SURFACE_CLEAR);
 187    }
 188
 189 #endif /* CLEAR_OPT */
 190
 191    D_PRINTF(CELL_DEBUG_CMD, "CLEAR SURF done\n");
 192 }
 193
 194
 195 static void
 196 cmd_release_verts(const struct cell_command_release_verts *release)
 197 {
 198    D_PRINTF(CELL_DEBUG_CMD, "RELEASE VERTS %u\n", release->vertex_buf);
 199    ASSERT(release->vertex_buf != ~0U);
 200    release_buffer(release->vertex_buf);
 201 }
 202
 203
 204 /**
 205  * Process a CELL_CMD_STATE_FRAGMENT_OPS command.
 206  * This involves installing new fragment ops SPU code.
 207  * If this function is never called, we'll use a regular C fallback function
 208  * for fragment processing.
 209  */
 210 static void
 211 cmd_state_fragment_ops(const struct cell_command_fragment_ops *fops)
 212 {
 213    static int warned = 0;
 214
 215    D_PRINTF(CELL_DEBUG_CMD, "CMD_STATE_FRAGMENT_OPS\n");
 216    /* Copy SPU code from batch buffer to spu buffer */
 217    memcpy(spu.fragment_ops_code_front, fops->code_front, SPU_MAX_FRAGMENT_OPS_INSTS * 4);
 218    memcpy(spu.fragment_ops_code_back, fops->code_back, SPU_MAX_FRAGMENT_OPS_INSTS * 4);
 219    /* Copy state info (for fallback case only) */
 220    memcpy(&spu.depth_stencil_alpha, &fops->dsa, sizeof(fops->dsa));
 221    memcpy(&spu.blend, &fops->blend, sizeof(fops->blend));
 222    memcpy(&spu.blend_color, &fops->blend_color, sizeof(fops->blend_color));
 223
 224    /* Parity twist!  For now, always use the fallback code by default,
 225     * only switching to codegen when specifically requested.  This
 226     * allows us to develop freely without risking taking down the
 227     * branch.
 228     *
 229     * Later, the parity of this check will be reversed, so that
 230     * codegen is *always* used, unless we specifically indicate that
 231     * we don't want it.
 232     *
 233     * Eventually, the option will be removed completely, because in
 234     * final code we'll always use codegen and won't even provide the
 235     * raw state records that the fallback code requires.
 236     */
 237    if ((spu.init.debug_flags & CELL_DEBUG_FRAGMENT_OP_FALLBACK) == 0) {
 238       spu.fragment_ops[CELL_FACING_FRONT] = (spu_fragment_ops_func) spu.fragment_ops_code_front;
 239       spu.fragment_ops[CELL_FACING_BACK] = (spu_fragment_ops_func) spu.fragment_ops_code_back;
 240    }
 241    else {
 242       /* otherwise, the default fallback code remains in place */
 243       if (!warned) {
 244          fprintf(stderr, "Cell Warning: using fallback per-fragment code\n");
 245          warned = 1;
 246       }
 247    }
 248
 249    spu.read_depth_stencil = (spu.depth_stencil_alpha.depth.enabled || spu.depth_stencil_alpha.stencil[0].enabled);
 250 }
 251
 252
 253 static void
 254 cmd_state_fragment_program(const struct cell_command_fragment_program *fp)
 255 {
 256    D_PRINTF(CELL_DEBUG_CMD, "CMD_STATE_FRAGMENT_PROGRAM\n");
 257    /* Copy SPU code from batch buffer to spu buffer */
 258    memcpy(spu.fragment_program_code, fp->code,
 259           SPU_MAX_FRAGMENT_PROGRAM_INSTS * 4);
 260 #if 01
 261    /* Point function pointer at new code */
 262    spu.fragment_program = (spu_fragment_program_func)spu.fragment_program_code;
 263 #endif
 264 }
 265
 266
 267 static uint
 268 cmd_state_fs_constants(const uint64_t *buffer, uint pos)
 269 {
 270    const uint num_const = buffer[pos + 1];
 271    const float *constants = (const float *) &buffer[pos + 2];
 272    uint i;
 273
 274    D_PRINTF(CELL_DEBUG_CMD, "CMD_STATE_FS_CONSTANTS (%u)\n", num_const);
 275
 276    /* Expand each float to float[4] for SOA execution */
 277    for (i = 0; i < num_const; i++) {
 278       D_PRINTF(CELL_DEBUG_CMD, "  const[%u] = %f\n", i, constants[i]);
 279       spu.constants[i] = spu_splats(constants[i]);
 280    }
 281
 282    /* return new buffer pos (in 8-byte words) */
 283    return pos + 2 + num_const / 2;
 284 }
 285
 286
 287 static void
 288 cmd_state_framebuffer(const struct cell_command_framebuffer *cmd)
 289 {
 290    D_PRINTF(CELL_DEBUG_CMD, "FRAMEBUFFER: %d x %d at %p, cformat 0x%x  zformat 0x%x\n",
 291              cmd->width,
 292              cmd->height,
 293              cmd->color_start,
 294              cmd->color_format,
 295              cmd->depth_format);
 296
 297    ASSERT_ALIGN16(cmd->color_start);
 298    ASSERT_ALIGN16(cmd->depth_start);
 299
 300    spu.fb.color_start = cmd->color_start;
 301    spu.fb.depth_start = cmd->depth_start;
 302    spu.fb.color_format = cmd->color_format;
 303    spu.fb.depth_format = cmd->depth_format;
 304    spu.fb.width = cmd->width;
 305    spu.fb.height = cmd->height;
 306    spu.fb.width_tiles = (spu.fb.width + TILE_SIZE - 1) / TILE_SIZE;
 307    spu.fb.height_tiles = (spu.fb.height + TILE_SIZE - 1) / TILE_SIZE;
 308
 309    switch (spu.fb.depth_format) {
 310    case PIPE_FORMAT_Z32_UNORM:
 311       spu.fb.zsize = 4;
 312       spu.fb.zscale = (float) 0xffffffffu;
 313       break;
 314    case PIPE_FORMAT_Z24S8_UNORM:
 315    case PIPE_FORMAT_S8Z24_UNORM:
 316    case PIPE_FORMAT_Z24X8_UNORM:
 317    case PIPE_FORMAT_X8Z24_UNORM:
 318       spu.fb.zsize = 4;
 319       spu.fb.zscale = (float) 0x00ffffffu;
 320       break;
 321    case PIPE_FORMAT_Z16_UNORM:
 322       spu.fb.zsize = 2;
 323       spu.fb.zscale = (float) 0xffffu;
 324       break;
 325    default:
 326       spu.fb.zsize = 0;
 327       break;
 328    }
 329 }
 330
 331
 332 /**
 333  * Tex texture mask_s/t and scale_s/t fields depend on the texture size and
 334  * sampler wrap modes.
 335  */
 336 static void
 337 update_tex_masks(struct spu_texture *texture,
 338                  const struct pipe_sampler_state *sampler)
 339 {
 340    uint i;
 341
 342    for (i = 0; i < CELL_MAX_TEXTURE_LEVELS; i++) {
 343       int width = texture->level[i].width;
 344       int height = texture->level[i].height;
 345
 346       if (sampler->wrap_s == PIPE_TEX_WRAP_REPEAT)
 347          texture->level[i].mask_s = spu_splats(width - 1);
 348       else
 349          texture->level[i].mask_s = spu_splats(~0);
 350
 351       if (sampler->wrap_t == PIPE_TEX_WRAP_REPEAT)
 352          texture->level[i].mask_t = spu_splats(height - 1);
 353       else
 354          texture->level[i].mask_t = spu_splats(~0);
 355
 356       if (sampler->normalized_coords) {
 357          texture->level[i].scale_s = spu_splats((float) width);
 358          texture->level[i].scale_t = spu_splats((float) height);
 359       }
 360       else {
 361          texture->level[i].scale_s = spu_splats(1.0f);
 362          texture->level[i].scale_t = spu_splats(1.0f);
 363       }
 364    }
 365 }
 366
 367
 368 static void
 369 cmd_state_sampler(const struct cell_command_sampler *sampler)
 370 {
 371    uint unit = sampler->unit;
 372
 373    D_PRINTF(CELL_DEBUG_CMD, "SAMPLER [%u]\n", unit);
 374
 375    spu.sampler[unit] = sampler->state;
 376
 377    switch (spu.sampler[unit].min_img_filter) {
 378    case PIPE_TEX_FILTER_LINEAR:
 379       spu.min_sample_texture_2d[unit] = sample_texture_2d_bilinear;
 380       break;
 381    case PIPE_TEX_FILTER_ANISO:
 382       /* fall-through, for now */
 383    case PIPE_TEX_FILTER_NEAREST:
 384       spu.min_sample_texture_2d[unit] = sample_texture_2d_nearest;
 385       break;
 386    default:
 387       ASSERT(0);
 388    }
 389
 390    switch (spu.sampler[sampler->unit].mag_img_filter) {
 391    case PIPE_TEX_FILTER_LINEAR:
 392       spu.mag_sample_texture_2d[unit] = sample_texture_2d_bilinear;
 393       break;
 394    case PIPE_TEX_FILTER_ANISO:
 395       /* fall-through, for now */
 396    case PIPE_TEX_FILTER_NEAREST:
 397       spu.mag_sample_texture_2d[unit] = sample_texture_2d_nearest;
 398       break;
 399    default:
 400       ASSERT(0);
 401    }
 402
 403    switch (spu.sampler[sampler->unit].min_mip_filter) {
 404    case PIPE_TEX_MIPFILTER_NEAREST:
 405    case PIPE_TEX_MIPFILTER_LINEAR:
 406       spu.sample_texture_2d[unit] = sample_texture_2d_lod;
 407       break;
 408    case PIPE_TEX_MIPFILTER_NONE:
 409       spu.sample_texture_2d[unit] = spu.mag_sample_texture_2d[unit];
 410       break;
 411    default:
 412       ASSERT(0);
 413    }
 414
 415    update_tex_masks(&spu.texture[unit], &spu.sampler[unit]);
 416 }
 417
 418
 419 static void
 420 cmd_state_texture(const struct cell_command_texture *texture)
 421 {
 422    const uint unit = texture->unit;
 423    uint i;
 424
 425    D_PRINTF(CELL_DEBUG_CMD, "TEXTURE [%u]\n", texture->unit);
 426
 427    spu.texture[unit].max_level = 0;
 428    spu.texture[unit].target = texture->target;
 429
 430    for (i = 0; i < CELL_MAX_TEXTURE_LEVELS; i++) {
 431       uint width = texture->width[i];
 432       uint height = texture->height[i];
 433       uint depth = texture->depth[i];
 434
 435       D_PRINTF(CELL_DEBUG_CMD, "  LEVEL %u: at %p  size[0] %u x %u\n", i,
 436              texture->start[i], texture->width[i], texture->height[i]);
 437
 438       spu.texture[unit].level[i].start = texture->start[i];
 439       spu.texture[unit].level[i].width = width;
 440       spu.texture[unit].level[i].height = height;
 441       spu.texture[unit].level[i].depth = depth;
 442
 443       spu.texture[unit].level[i].tiles_per_row =
 444          (width + TILE_SIZE - 1) / TILE_SIZE;
 445
 446       spu.texture[unit].level[i].bytes_per_image =
 447          4 * align(width, TILE_SIZE) * align(height, TILE_SIZE) * depth;
 448
 449       spu.texture[unit].level[i].max_s = spu_splats((int) width - 1);
 450       spu.texture[unit].level[i].max_t = spu_splats((int) height - 1);
 451
 452       if (texture->start[i])
 453          spu.texture[unit].max_level = i;
 454    }
 455
 456    update_tex_masks(&spu.texture[unit], &spu.sampler[unit]);
 457 }
 458
 459
 460 static void
 461 cmd_state_vertex_info(const struct vertex_info *vinfo)
 462 {
 463    D_PRINTF(CELL_DEBUG_CMD, "VERTEX_INFO num_attribs=%u\n", vinfo->num_attribs);
 464    ASSERT(vinfo->num_attribs >= 1);
 465    ASSERT(vinfo->num_attribs <= 8);
 466    memcpy(&spu.vertex_info, vinfo, sizeof(*vinfo));
 467 }
 468
 469
 470 static void
 471 cmd_state_vs_array_info(const struct cell_array_info *vs_info)
 472 {
 473    const unsigned attr = vs_info->attr;
 474
 475    ASSERT(attr < PIPE_MAX_ATTRIBS);
 476    draw.vertex_fetch.src_ptr[attr] = vs_info->base;
 477    draw.vertex_fetch.pitch[attr] = vs_info->pitch;
 478    draw.vertex_fetch.size[attr] = vs_info->size;
 479    draw.vertex_fetch.code_offset[attr] = vs_info->function_offset;
 480    draw.vertex_fetch.dirty = 1;
 481 }
 482
 483
 484 static void
 485 cmd_state_attrib_fetch(const struct cell_attribute_fetch_code *code)
 486 {
 487    mfc_get(attribute_fetch_code_buffer,
 488            (unsigned int) code->base,  /* src */
 489            code->size,
 490            TAG_BATCH_BUFFER,
 491            0, /* tid */
 492            0  /* rid */);
 493    wait_on_mask(1 << TAG_BATCH_BUFFER);
 494
 495    draw.vertex_fetch.code = attribute_fetch_code_buffer;
 496 }
 497
 498
 499 static void
 500 cmd_finish(void)
 501 {
 502    D_PRINTF(CELL_DEBUG_CMD, "FINISH\n");
 503    really_clear_tiles(0);
 504    /* wait for all outstanding DMAs to finish */
 505    mfc_write_tag_mask(~0);
 506    mfc_read_tag_status_all();
 507    /* send mbox message to PPU */
 508    spu_write_out_mbox(CELL_CMD_FINISH);
 509 }
 510
 511
 512 /**
 513  * Execute a batch of commands which was sent to us by the PPU.
 514  * See the cell_emit_state.c code to see where the commands come from.
 515  *
 516  * The opcode param encodes the location of the buffer and its size.
 517  */
 518 static void
 519 cmd_batch(uint opcode)
 520 {
 521    const uint buf = (opcode >> 8) & 0xff;
 522    uint size = (opcode >> 16);
 523    uint64_t buffer[CELL_BUFFER_SIZE / 8] ALIGN16_ATTRIB;
 524    const unsigned usize = size / sizeof(buffer[0]);
 525    uint pos;
 526
 527    D_PRINTF(CELL_DEBUG_CMD, "BATCH buffer %u, len %u, from %p\n",
 528              buf, size, spu.init.buffers[buf]);
 529
 530    ASSERT((opcode & CELL_CMD_OPCODE_MASK) == CELL_CMD_BATCH);
 531
 532    ASSERT_ALIGN16(spu.init.buffers[buf]);
 533
 534    size = ROUNDUP16(size);
 535
 536    ASSERT_ALIGN16(spu.init.buffers[buf]);
 537
 538    mfc_get(buffer,  /* dest */
 539            (unsigned int) spu.init.buffers[buf],  /* src */
 540            size,
 541            TAG_BATCH_BUFFER,
 542            0, /* tid */
 543            0  /* rid */);
 544    wait_on_mask(1 << TAG_BATCH_BUFFER);
 545
 546    /* Tell PPU we're done copying the buffer to local store */
 547    D_PRINTF(CELL_DEBUG_CMD, "release batch buf %u\n", buf);
 548    release_buffer(buf);
 549
 550    /*
 551     * Loop over commands in the batch buffer
 552     */
 553    for (pos = 0; pos < usize; /* no incr */) {
 554       switch (buffer[pos]) {
 555       /*
 556        * rendering commands
 557        */
 558       case CELL_CMD_CLEAR_SURFACE:
 559          {
 560             struct cell_command_clear_surface *clr
 561                = (struct cell_command_clear_surface *) &buffer[pos];
 562             cmd_clear_surface(clr);
 563             pos += sizeof(*clr) / 8;
 564          }
 565          break;
 566       case CELL_CMD_RENDER:
 567          {
 568             struct cell_command_render *render
 569                = (struct cell_command_render *) &buffer[pos];
 570             uint pos_incr;
 571             cmd_render(render, &pos_incr);
 572             pos += pos_incr;
 573          }
 574          break;
 575       /*
 576        * state-update commands
 577        */
 578       case CELL_CMD_STATE_FRAMEBUFFER:
 579          {
 580             struct cell_command_framebuffer *fb
 581                = (struct cell_command_framebuffer *) &buffer[pos];
 582             cmd_state_framebuffer(fb);
 583             pos += sizeof(*fb) / 8;
 584          }
 585          break;
 586       case CELL_CMD_STATE_FRAGMENT_OPS:
 587          {
 588             struct cell_command_fragment_ops *fops
 589                = (struct cell_command_fragment_ops *) &buffer[pos];
 590             cmd_state_fragment_ops(fops);
 591             pos += sizeof(*fops) / 8;
 592          }
 593          break;
 594       case CELL_CMD_STATE_FRAGMENT_PROGRAM:
 595          {
 596             struct cell_command_fragment_program *fp
 597                = (struct cell_command_fragment_program *) &buffer[pos];
 598             cmd_state_fragment_program(fp);
 599             pos += sizeof(*fp) / 8;
 600          }
 601          break;
 602       case CELL_CMD_STATE_FS_CONSTANTS:
 603          pos = cmd_state_fs_constants(buffer, pos);
 604          break;
 605       case CELL_CMD_STATE_RASTERIZER:
 606          {
 607             struct cell_command_rasterizer *rast =
 608                (struct cell_command_rasterizer *) &buffer[pos];
 609             spu.rasterizer = rast->rasterizer;
 610             pos += sizeof(*rast) / 8;
 611          }
 612          break;
 613       case CELL_CMD_STATE_SAMPLER:
 614          {
 615             struct cell_command_sampler *sampler
 616                = (struct cell_command_sampler *) &buffer[pos];
 617             cmd_state_sampler(sampler);
 618             pos += sizeof(*sampler) / 8;
 619          }
 620          break;
 621       case CELL_CMD_STATE_TEXTURE:
 622          {
 623             struct cell_command_texture *texture
 624                = (struct cell_command_texture *) &buffer[pos];
 625             cmd_state_texture(texture);
 626             pos += sizeof(*texture) / 8;
 627          }
 628          break;
 629       case CELL_CMD_STATE_VERTEX_INFO:
 630          cmd_state_vertex_info((struct vertex_info *) &buffer[pos+1]);
 631          pos += (1 + ROUNDUP8(sizeof(struct vertex_info)) / 8);
 632          break;
 633       case CELL_CMD_STATE_VIEWPORT:
 634          (void) memcpy(& draw.viewport, &buffer[pos+1],
 635                        sizeof(struct pipe_viewport_state));
 636          pos += (1 + ROUNDUP8(sizeof(struct pipe_viewport_state)) / 8);
 637          break;
 638       case CELL_CMD_STATE_UNIFORMS:
 639          draw.constants = (const float (*)[4]) (uintptr_t) buffer[pos + 1];
 640          pos += 2;
 641          break;
 642       case CELL_CMD_STATE_VS_ARRAY_INFO:
 643          cmd_state_vs_array_info((struct cell_array_info *) &buffer[pos+1]);
 644          pos += (1 + ROUNDUP8(sizeof(struct cell_array_info)) / 8);
 645          break;
 646       case CELL_CMD_STATE_BIND_VS:
 647 #if 0
 648          spu_bind_vertex_shader(&draw,
 649                                 (struct cell_shader_info *) &buffer[pos+1]);
 650 #endif
 651          pos += (1 + ROUNDUP8(sizeof(struct cell_shader_info)) / 8);
 652          break;
 653       case CELL_CMD_STATE_ATTRIB_FETCH:
 654          cmd_state_attrib_fetch((struct cell_attribute_fetch_code *)
 655                                 &buffer[pos+1]);
 656          pos += (1 + ROUNDUP8(sizeof(struct cell_attribute_fetch_code)) / 8);
 657          break;
 658       /*
 659        * misc commands
 660        */
 661       case CELL_CMD_FINISH:
 662          cmd_finish();
 663          pos += 1;
 664          break;
 665       case CELL_CMD_FENCE:
 666          {
 667             struct cell_command_fence *fence_cmd =
 668                (struct cell_command_fence *) &buffer[pos];
 669             cmd_fence(fence_cmd);
 670             pos += sizeof(*fence_cmd) / 8;
 671          }
 672          break;
 673       case CELL_CMD_RELEASE_VERTS:
 674          {
 675             struct cell_command_release_verts *release
 676                = (struct cell_command_release_verts *) &buffer[pos];
 677             cmd_release_verts(release);
 678             pos += sizeof(*release) / 8;
 679          }
 680          break;
 681       case CELL_CMD_FLUSH_BUFFER_RANGE: {
 682          struct cell_buffer_range *br = (struct cell_buffer_range *)
 683              &buffer[pos+1];
 684
 685          spu_dcache_mark_dirty((unsigned) br->base, br->size);
 686          pos += (1 + ROUNDUP8(sizeof(struct cell_buffer_range)) / 8);
 687          break;
 688       }
 689       default:
 690          printf("SPU %u: bad opcode: 0x%llx\n", spu.init.id, buffer[pos]);
 691          ASSERT(0);
 692          break;
 693       }
 694    }
 695
 696    D_PRINTF(CELL_DEBUG_CMD, "BATCH complete\n");
 697 }
 698
 699
 700 #define PERF 0
 701
 702
 703 /**
 704  * Main loop for SPEs: Get a command, execute it, repeat.
 705  */
 706 void
 707 command_loop(void)
 708 {
 709    int exitFlag = 0;
 710    uint t0, t1;
 711
 712    D_PRINTF(CELL_DEBUG_CMD, "Enter command loop\n");
 713
 714    while (!exitFlag) {
 715       unsigned opcode;
 716
 717       D_PRINTF(CELL_DEBUG_CMD, "Wait for cmd...\n");
 718
 719       if (PERF)
 720          spu_write_decrementer(~0);
 721
 722       /* read/wait from mailbox */
 723       opcode = (unsigned int) spu_read_in_mbox();
 724       D_PRINTF(CELL_DEBUG_CMD, "got cmd 0x%x\n", opcode);
 725
 726       if (PERF)
 727          t0 = spu_read_decrementer();
 728
 729       switch (opcode & CELL_CMD_OPCODE_MASK) {
 730       case CELL_CMD_EXIT:
 731          D_PRINTF(CELL_DEBUG_CMD, "EXIT\n");
 732          exitFlag = 1;
 733          break;
 734       case CELL_CMD_VS_EXECUTE:
 735 #if 0
 736          spu_execute_vertex_shader(&draw, &cmd.vs);
 737 #endif
 738          break;
 739       case CELL_CMD_BATCH:
 740          cmd_batch(opcode);
 741          break;
 742       default:
 743          printf("Bad opcode 0x%x!\n", opcode & CELL_CMD_OPCODE_MASK);
 744       }
 745
 746       if (PERF) {
 747          t1 = spu_read_decrementer();
 748          printf("wait mbox time: %gms   batch time: %gms\n",
 749                 (~0u - t0) * spu.init.inv_timebase,
 750                 (t0 - t1) * spu.init.inv_timebase);
 751       }
 752    }
 753
 754    D_PRINTF(CELL_DEBUG_CMD, "Exit command loop\n");
 755
 756    if (spu.init.debug_flags & CELL_DEBUG_CACHE)
 757       spu_dcache_report();
 758 }