src/gallium/drivers/cell/spu/spu_dcache.c

   1 /*
   2  * (C) Copyright IBM Corporation 2008
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  19  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "cell/common.h"
  26 #include "spu_main.h"
  27 #include "spu_dcache.h"
  28
  29 #define CACHELINE_LOG2SIZE    7
  30 #define LINE_SIZE             (1U << 7)
  31 #define ALIGN_MASK            (~(LINE_SIZE - 1))
  32
  33 #define CACHE_NAME            data
  34 #define CACHED_TYPE           qword
  35 #define CACHE_TYPE            CACHE_TYPE_RO
  36 #define CACHE_SET_TAGID(set)  (((set) & 0x03) + TAG_DCACHE0)
  37 #define CACHE_LOG2NNWAY       2
  38 #define CACHE_LOG2NSETS       6
  39 /*#define CACHE_STATS           1*/
  40 #include <cache-api.h>
  41
  42 /* Yes folks, this is ugly.
  43  */
  44 #undef CACHE_NWAY
  45 #undef CACHE_NSETS
  46 #define CACHE_NAME            data
  47 #define CACHE_NWAY            4
  48 #define CACHE_NSETS           (1U << 6)
  49
  50
  51 /**
  52  * Fetch between arbitrary number of bytes from an unaligned address
  53  *
  54  * \param dst   Destination data buffer
  55  * \param ea    Main memory effective address of source data
  56  * \param size  Number of bytes to read
  57  *
  58  * \warning
  59  * As is hinted by the type of the \c dst pointer, this function writes
  60  * multiples of 16-bytes.
  61  */
  62 void
  63 spu_dcache_fetch_unaligned(qword *dst, unsigned ea, unsigned size)
  64 {
  65    const int shift = ea & 0x0f;
  66    const unsigned read_size = ROUNDUP16(size + shift);
  67    const unsigned last_read = ROUNDUP16(ea + size);
  68    const qword *const last_write = dst + (ROUNDUP16(size) / 16);
  69    unsigned i;
  70
  71
  72    if (shift == 0) {
  73       /* Data is already aligned.  Fetch directly into the destination buffer.
  74        */
  75       for (i = 0; i < size; i += 16) {
  76          *(dst++) = cache_rd(data, ea + i);
  77       }
  78    } else {
  79       qword hi;
  80
  81
  82       /* Please exercise extreme caution when modifying this code.  This code
  83        * must not read past the end of the page containing the source data,
  84        * and it must not write more than ((size + 15) / 16) qwords to the
  85        * destination buffer.
  86        */
  87       ea &= ~0x0f;
  88       hi = cache_rd(data, ea);
  89       for (i = 16; i < read_size; i += 16) {
  90          qword lo = cache_rd(data, ea + i);
  91
  92          *(dst++) = si_or((qword) spu_slqwbyte(hi, shift),
  93                           (qword) spu_rlmaskqwbyte(lo, shift - 16));
  94          hi = lo;
  95       }
  96
  97       if (dst != last_write) {
  98          *(dst++) = si_or((qword) spu_slqwbyte(hi, shift), si_il(0));
  99       }
 100    }
 101
 102    ASSERT((ea + i) == last_read);
 103    ASSERT(dst == last_write);
 104 }
 105
 106
 107 /**
 108  * Notify the cache that a range of main memory may have been modified
 109  */
 110 void
 111 spu_dcache_mark_dirty(unsigned ea, unsigned size)
 112 {
 113    unsigned i;
 114    const unsigned aligned_start = (ea & ALIGN_MASK);
 115    const unsigned aligned_end = (ea + size + (LINE_SIZE - 1))
 116        & ALIGN_MASK;
 117
 118
 119    for (i = 0; i < (CACHE_NWAY * CACHE_NSETS); i++) {
 120       const unsigned entry = __cache_dir[i];
 121       const unsigned addr = entry & ~0x0f;
 122
 123       __cache_dir[i] = ((addr >= aligned_start) && (addr < aligned_end))
 124           ? (entry & ~CACHELINE_VALID) : entry;
 125    }
 126 }
 127
 128
 129 /**
 130  * Print cache utilization report
 131  */
 132 void
 133 spu_dcache_report(void)
 134 {
 135 #ifdef CACHE_STATS
 136    if (spu.init.id == 0) {
 137       printf("SPU 0: Texture cache report:\n");
 138       cache_pr_stats(data);
 139    }
 140 #endif
 141 }
 142
 143