src/gallium/drivers/cell/spu/spu_main.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef SPU_MAIN_H
  29 #define SPU_MAIN_H
  30
  31
  32 #include <spu_mfcio.h>
  33
  34 #include "cell/common.h"
  35 #include "draw/draw_vertex.h"
  36 #include "pipe/p_state.h"
  37
  38
  39
  40 #define MAX_WIDTH 1024
  41 #define MAX_HEIGHT 1024
  42
  43
  44 typedef union {
  45    ushort us[TILE_SIZE][TILE_SIZE];
  46    uint   ui[TILE_SIZE][TILE_SIZE];
  47    vector unsigned short us8[TILE_SIZE/2][TILE_SIZE/4];
  48    vector unsigned int ui4[TILE_SIZE/2][TILE_SIZE/2];
  49 } tile_t;
  50
  51
  52 #define TILE_STATUS_CLEAR   1
  53 #define TILE_STATUS_DEFINED 2  /**< defined in FB, but not in local store */
  54 #define TILE_STATUS_CLEAN   3  /**< in local store, but not changed */
  55 #define TILE_STATUS_DIRTY   4  /**< modified locally, but not put back yet */
  56 #define TILE_STATUS_GETTING 5  /**< mfc_get() called but not yet arrived */
  57
  58
  59 struct spu_frag_test_results {
  60    qword mask;
  61    qword depth;
  62    qword stencil;
  63 };
  64
  65 typedef struct spu_frag_test_results (*frag_test_func)(qword frag_mask,
  66     qword pixel_depth, qword pixel_stencil, qword frag_depth,
  67     qword frag_alpha, qword facing);
  68
  69
  70 struct spu_blend_results {
  71    qword r;
  72    qword g;
  73    qword b;
  74    qword a;
  75 };
  76
  77 typedef struct spu_blend_results (*blend_func)(
  78     qword frag_r, qword frag_g, qword frag_b, qword frag_a,
  79     qword pixel_r, qword pixel_g, qword pixel_b, qword pixel_a,
  80     qword const_r, qword const_g, qword const_b, qword const_a);
  81
  82 typedef struct spu_blend_results (*logicop_func)(
  83     qword pixel_r, qword pixel_g, qword pixel_b, qword pixel_a,
  84     qword frag_r, qword frag_g, qword frag_b, qword frag_a,
  85     qword frag_mask);
  86
  87
  88 typedef vector float (*sample_texture_func)(uint unit, vector float texcoord);
  89
  90 struct spu_framebuffer {
  91    void *color_start;              /**< addr of color surface in main memory */
  92    void *depth_start;              /**< addr of depth surface in main memory */
  93    enum pipe_format color_format;
  94    enum pipe_format depth_format;
  95    uint width, height;             /**< size in pixels */
  96    uint width_tiles, height_tiles; /**< width and height in tiles */
  97
  98    uint color_clear_value;
  99    uint depth_clear_value;
 100
 101    uint zsize;                     /**< 0, 2 or 4 bytes per Z */
 102 } ALIGN16_ATTRIB;
 103
 104
 105 struct spu_texture
 106 {
 107    void *start;
 108    ushort width, height;
 109    ushort tiles_per_row;
 110    vector float tex_size;
 111    vector unsigned int tex_size_mask; /**< == int(size - 1) */
 112    vector unsigned int tex_size_x_mask; /**< == int(size - 1) */
 113    vector unsigned int tex_size_y_mask; /**< == int(size - 1) */
 114 } ALIGN16_ATTRIB;
 115
 116
 117 /**
 118  * All SPU global/context state will be in singleton object of this type:
 119  */
 120 struct spu_global
 121 {
 122    struct cell_init_info init;
 123
 124    struct spu_framebuffer fb;
 125    boolean read_depth;
 126    boolean read_stencil;
 127    frag_test_func frag_test;  /**< Current depth/stencil test code */
 128
 129    boolean read_fb;   /**< Does current blend mode require framebuffer read? */
 130    blend_func blend;  /**< Current blend code */
 131    qword const_blend_color[4] ALIGN16_ATTRIB;
 132
 133    logicop_func logicop;  /**< Current logicop code **/
 134
 135    struct pipe_sampler_state sampler[PIPE_MAX_SAMPLERS];
 136    struct spu_texture texture[PIPE_MAX_SAMPLERS];
 137
 138    struct vertex_info vertex_info;
 139
 140    /* XXX more state to come */
 141
 142
 143    /** current color and Z tiles */
 144    tile_t ctile ALIGN16_ATTRIB;
 145    tile_t ztile ALIGN16_ATTRIB;
 146
 147    /** Current tiles' status */
 148    ubyte cur_ctile_status, cur_ztile_status;
 149
 150    /** Status of all tiles in framebuffer */
 151    ubyte ctile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
 152    ubyte ztile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
 153
 154
 155    /** for converting RGBA to PIPE_FORMAT_x colors */
 156    vector unsigned char color_shuffle;
 157
 158    sample_texture_func sample_texture[CELL_MAX_SAMPLERS];
 159
 160 } ALIGN16_ATTRIB;
 161
 162
 163 extern struct spu_global spu;
 164 extern boolean Debug;
 165
 166
 167
 168
 169 /* DMA TAGS */
 170
 171 #define TAG_SURFACE_CLEAR     10
 172 #define TAG_VERTEX_BUFFER     11
 173 #define TAG_READ_TILE_COLOR   12
 174 #define TAG_READ_TILE_Z       13
 175 #define TAG_WRITE_TILE_COLOR  14
 176 #define TAG_WRITE_TILE_Z      15
 177 #define TAG_INDEX_BUFFER      16
 178 #define TAG_BATCH_BUFFER      17
 179 #define TAG_MISC              18
 180 #define TAG_DCACHE0           20
 181 #define TAG_DCACHE1           21
 182 #define TAG_DCACHE2           22
 183 #define TAG_DCACHE3           23
 184
 185
 186
 187 static INLINE void
 188 wait_on_mask(unsigned tagMask)
 189 {
 190    mfc_write_tag_mask( tagMask );
 191    /* wait for completion of _any_ DMAs specified by tagMask */
 192    mfc_read_tag_status_any();
 193 }
 194
 195
 196 static INLINE void
 197 wait_on_mask_all(unsigned tagMask)
 198 {
 199    mfc_write_tag_mask( tagMask );
 200    /* wait for completion of _any_ DMAs specified by tagMask */
 201    mfc_read_tag_status_all();
 202 }
 203
 204
 205
 206
 207
 208 static INLINE void
 209 memset16(ushort *d, ushort value, uint count)
 210 {
 211    uint i;
 212    for (i = 0; i < count; i++)
 213       d[i] = value;
 214 }
 215
 216
 217 static INLINE void
 218 memset32(uint *d, uint value, uint count)
 219 {
 220    uint i;
 221    for (i = 0; i < count; i++)
 222       d[i] = value;
 223 }
 224
 225
 226 #endif /* SPU_MAIN_H */