src/gallium/drivers/cell/spu/spu_main.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef SPU_MAIN_H
  29 #define SPU_MAIN_H
  30
  31
  32 #include <spu_mfcio.h>
  33
  34 #include "cell/common.h"
  35 #include "draw/draw_vertex.h"
  36 #include "pipe/p_state.h"
  37
  38
  39
  40 #define MAX_WIDTH 1024
  41 #define MAX_HEIGHT 1024
  42
  43
  44 #define CELL_MAX_CONSTANTS 32  /**< number of float[4] constants */
  45
  46
  47 /**
  48  * A tile is basically a TILE_SIZE x TILE_SIZE block of 4-byte pixels.
  49  * The data may be addressed through several different types.
  50  */
  51 typedef union {
  52    ushort us[TILE_SIZE][TILE_SIZE];
  53    uint   ui[TILE_SIZE][TILE_SIZE];
  54    vector unsigned short us8[TILE_SIZE/2][TILE_SIZE/4];
  55    vector unsigned int ui4[TILE_SIZE/2][TILE_SIZE/2];
  56 } tile_t;
  57
  58
  59 #define TILE_STATUS_CLEAR   1
  60 #define TILE_STATUS_DEFINED 2  /**< defined in FB, but not in local store */
  61 #define TILE_STATUS_CLEAN   3  /**< in local store, but not changed */
  62 #define TILE_STATUS_DIRTY   4  /**< modified locally, but not put back yet */
  63 #define TILE_STATUS_GETTING 5  /**< mfc_get() called but not yet arrived */
  64
  65
  66 /** Function for sampling textures */
  67 typedef vector float (*spu_sample_texture_func)(uint unit,
  68                                                 vector float texcoord);
  69
  70 typedef void (*spu_sample_texture4_func)(vector float s,
  71                                          vector float t,
  72                                          vector float r,
  73                                          vector float q,
  74                                          uint unit,
  75                                          vector float colors[4]);
  76
  77
  78 /** Function for performing per-fragment ops */
  79 typedef void (*spu_fragment_ops_func)(uint x, uint y,
  80                                       tile_t *colorTile,
  81                                       tile_t *depthStencilTile,
  82                                       vector float fragZ,
  83                                       vector float fragRed,
  84                                       vector float fragGreen,
  85                                       vector float fragBlue,
  86                                       vector float fragAlpha,
  87                                       vector unsigned int mask,
  88                                       uint facing);
  89
  90 /** Function for running fragment program */
  91 typedef void (*spu_fragment_program_func)(vector float *inputs,
  92                                           vector float *outputs,
  93                                           vector float *constants);
  94
  95
  96 struct spu_framebuffer
  97 {
  98    void *color_start;              /**< addr of color surface in main memory */
  99    void *depth_start;              /**< addr of depth surface in main memory */
 100    enum pipe_format color_format;
 101    enum pipe_format depth_format;
 102    uint width, height;             /**< size in pixels */
 103    uint width_tiles, height_tiles; /**< width and height in tiles */
 104
 105    uint color_clear_value;
 106    uint depth_clear_value;
 107
 108    uint zsize;                     /**< 0, 2 or 4 bytes per Z */
 109    float zscale;                   /**< 65535.0, 2^24-1 or 2^32-1 */
 110 } ALIGN16_ATTRIB;
 111
 112
 113 struct spu_texture
 114 {
 115    void *start;
 116    ushort width, height;
 117    ushort tiles_per_row;
 118    vector float tex_size; /**< == {width, height, 0, 0} */
 119    vector float width4;   /**< == {width, width, width, width} */
 120    vector float height4;  /**< == {height, height, height, height} */
 121    vector unsigned int tex_size_mask; /**< == {width-1, height-1, 0, 0 } */
 122    vector unsigned int tex_size_x_mask; /**< splat(width-1) */
 123    vector unsigned int tex_size_y_mask; /**< splat(height-1) */
 124 } ALIGN16_ATTRIB;
 125
 126
 127 /**
 128  * All SPU global/context state will be in a singleton object of this type:
 129  */
 130 struct spu_global
 131 {
 132    /** One-time init/constant info */
 133    struct cell_init_info init;
 134
 135    /*
 136     * Current state
 137     */
 138    struct spu_framebuffer fb;
 139    struct pipe_depth_stencil_alpha_state depth_stencil_alpha;
 140    struct pipe_blend_state blend;
 141    struct pipe_sampler_state sampler[PIPE_MAX_SAMPLERS];
 142    struct spu_texture texture[PIPE_MAX_SAMPLERS];
 143    struct vertex_info vertex_info;
 144
 145    /** Current color and Z tiles */
 146    tile_t ctile ALIGN16_ATTRIB;
 147    tile_t ztile ALIGN16_ATTRIB;
 148
 149    /** Read depth/stencil tiles? */
 150    boolean read_depth;
 151    boolean read_stencil;
 152
 153    /** Current tiles' status */
 154    ubyte cur_ctile_status, cur_ztile_status;
 155
 156    /** Status of all tiles in framebuffer */
 157    ubyte ctile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
 158    ubyte ztile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
 159
 160    /** Current fragment ops machine code, at 8-byte boundary */
 161    uint fragment_ops_code[SPU_MAX_FRAGMENT_OPS_INSTS] ALIGN8_ATTRIB;
 162    /** Current fragment ops function */
 163    spu_fragment_ops_func fragment_ops;
 164
 165    /** Current fragment program machine code, at 8-byte boundary */
 166    uint fragment_program_code[SPU_MAX_FRAGMENT_PROGRAM_INSTS] ALIGN8_ATTRIB;
 167    /** Current fragment ops function */
 168    spu_fragment_program_func fragment_program;
 169
 170    /** Current texture sampler function */
 171    spu_sample_texture_func sample_texture[CELL_MAX_SAMPLERS];
 172    spu_sample_texture4_func sample_texture4[CELL_MAX_SAMPLERS];
 173
 174    /** Fragment program constants */
 175    vector float constants[4 * CELL_MAX_CONSTANTS];
 176
 177 } ALIGN16_ATTRIB;
 178
 179
 180 extern struct spu_global spu;
 181 extern boolean Debug;
 182
 183
 184
 185
 186 /* DMA TAGS */
 187
 188 #define TAG_SURFACE_CLEAR     10
 189 #define TAG_VERTEX_BUFFER     11
 190 #define TAG_READ_TILE_COLOR   12
 191 #define TAG_READ_TILE_Z       13
 192 #define TAG_WRITE_TILE_COLOR  14
 193 #define TAG_WRITE_TILE_Z      15
 194 #define TAG_INDEX_BUFFER      16
 195 #define TAG_BATCH_BUFFER      17
 196 #define TAG_MISC              18
 197 #define TAG_DCACHE0           20
 198 #define TAG_DCACHE1           21
 199 #define TAG_DCACHE2           22
 200 #define TAG_DCACHE3           23
 201
 202
 203
 204 static INLINE void
 205 wait_on_mask(unsigned tagMask)
 206 {
 207    mfc_write_tag_mask( tagMask );
 208    /* wait for completion of _any_ DMAs specified by tagMask */
 209    mfc_read_tag_status_any();
 210 }
 211
 212
 213 static INLINE void
 214 wait_on_mask_all(unsigned tagMask)
 215 {
 216    mfc_write_tag_mask( tagMask );
 217    /* wait for completion of _any_ DMAs specified by tagMask */
 218    mfc_read_tag_status_all();
 219 }
 220
 221
 222
 223
 224
 225 static INLINE void
 226 memset16(ushort *d, ushort value, uint count)
 227 {
 228    uint i;
 229    for (i = 0; i < count; i++)
 230       d[i] = value;
 231 }
 232
 233
 234 static INLINE void
 235 memset32(uint *d, uint value, uint count)
 236 {
 237    uint i;
 238    for (i = 0; i < count; i++)
 239       d[i] = value;
 240 }
 241
 242
 243 #endif /* SPU_MAIN_H */