src/gallium/drivers/cell/spu/spu_main.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef SPU_MAIN_H
  29 #define SPU_MAIN_H
  30
  31
  32 #include <spu_mfcio.h>
  33
  34 #include "cell/common.h"
  35 #include "draw/draw_vertex.h"
  36 #include "pipe/p_state.h"
  37
  38
  39
  40 #define MAX_WIDTH 1024
  41 #define MAX_HEIGHT 1024
  42
  43
  44 #define CELL_MAX_CONSTANTS 32  /**< number of float[4] constants */
  45
  46
  47 /**
  48  * A tile is basically a TILE_SIZE x TILE_SIZE block of 4-byte pixels.
  49  * The data may be addressed through several different types.
  50  */
  51 typedef union {
  52    ushort us[TILE_SIZE][TILE_SIZE];
  53    uint   ui[TILE_SIZE][TILE_SIZE];
  54    vector unsigned short us8[TILE_SIZE/2][TILE_SIZE/4];
  55    vector unsigned int ui4[TILE_SIZE/2][TILE_SIZE/2];
  56 } tile_t;
  57
  58
  59 #define TILE_STATUS_CLEAR   1
  60 #define TILE_STATUS_DEFINED 2  /**< defined in FB, but not in local store */
  61 #define TILE_STATUS_CLEAN   3  /**< in local store, but not changed */
  62 #define TILE_STATUS_DIRTY   4  /**< modified locally, but not put back yet */
  63 #define TILE_STATUS_GETTING 5  /**< mfc_get() called but not yet arrived */
  64
  65
  66 /** Function for sampling textures */
  67 typedef void (*spu_sample_texture4_func)(vector float s,
  68                                          vector float t,
  69                                          vector float r,
  70                                          vector float q,
  71                                          uint unit, uint level, uint face,
  72                                          vector float colors[4]);
  73
  74
  75 /** Function for performing per-fragment ops */
  76 typedef void (*spu_fragment_ops_func)(uint x, uint y,
  77                                       tile_t *colorTile,
  78                                       tile_t *depthStencilTile,
  79                                       vector float fragZ,
  80                                       vector float fragRed,
  81                                       vector float fragGreen,
  82                                       vector float fragBlue,
  83                                       vector float fragAlpha,
  84                                       vector unsigned int mask,
  85                                       uint facing);
  86
  87 /** Function for running fragment program */
  88 typedef void (*spu_fragment_program_func)(vector float *inputs,
  89                                           vector float *outputs,
  90                                           vector float *constants);
  91
  92
  93 struct spu_framebuffer
  94 {
  95    void *color_start;              /**< addr of color surface in main memory */
  96    void *depth_start;              /**< addr of depth surface in main memory */
  97    enum pipe_format color_format;
  98    enum pipe_format depth_format;
  99    uint width, height;             /**< size in pixels */
 100    uint width_tiles, height_tiles; /**< width and height in tiles */
 101
 102    uint color_clear_value;
 103    uint depth_clear_value;
 104
 105    uint zsize;                     /**< 0, 2 or 4 bytes per Z */
 106    float zscale;                   /**< 65535.0, 2^24-1 or 2^32-1 */
 107 } ALIGN16_ATTRIB;
 108
 109
 110 /** per-texture level info */
 111 struct spu_texture_level
 112 {
 113    void *start;
 114    ushort width, height;
 115    ushort tiles_per_row;
 116    uint bytes_per_image;
 117    /** texcoord scale factors */
 118    vector float scale_s, scale_t;
 119    /** texcoord masks (if REPEAT then size-1, else ~0) */
 120    vector signed int mask_s, mask_t;
 121    /** texcoord clamp limits */
 122    vector signed int max_s, max_t;
 123 } ALIGN16_ATTRIB;
 124
 125
 126 struct spu_texture
 127 {
 128    struct spu_texture_level level[CELL_MAX_TEXTURE_LEVELS];
 129    uint max_level;
 130    uint target;  /**< PIPE_TEXTURE_x */
 131 } ALIGN16_ATTRIB;
 132
 133
 134 /**
 135  * All SPU global/context state will be in a singleton object of this type:
 136  */
 137 struct spu_global
 138 {
 139    /** One-time init/constant info */
 140    struct cell_init_info init;
 141
 142    /*
 143     * Current state
 144     */
 145    struct spu_framebuffer fb;
 146    struct pipe_depth_stencil_alpha_state depth_stencil_alpha;
 147    struct pipe_blend_state blend;
 148    struct pipe_sampler_state sampler[PIPE_MAX_SAMPLERS];
 149    struct spu_texture texture[PIPE_MAX_SAMPLERS];
 150    struct vertex_info vertex_info;
 151
 152    /** Current color and Z tiles */
 153    tile_t ctile ALIGN16_ATTRIB;
 154    tile_t ztile ALIGN16_ATTRIB;
 155
 156    /** Read depth/stencil tiles? */
 157    boolean read_depth;
 158    boolean read_stencil;
 159
 160    /** Current tiles' status */
 161    ubyte cur_ctile_status, cur_ztile_status;
 162
 163    /** Status of all tiles in framebuffer */
 164    ubyte ctile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
 165    ubyte ztile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
 166
 167    /** Current fragment ops machine code, at 8-byte boundary */
 168    uint fragment_ops_code[SPU_MAX_FRAGMENT_OPS_INSTS] ALIGN8_ATTRIB;
 169    /** Current fragment ops function */
 170    spu_fragment_ops_func fragment_ops;
 171
 172    /** Current fragment program machine code, at 8-byte boundary */
 173    uint fragment_program_code[SPU_MAX_FRAGMENT_PROGRAM_INSTS] ALIGN8_ATTRIB;
 174    /** Current fragment ops function */
 175    spu_fragment_program_func fragment_program;
 176
 177    /** Current texture sampler function */
 178    spu_sample_texture4_func sample_texture4[CELL_MAX_SAMPLERS];
 179    spu_sample_texture4_func min_sample_texture4[CELL_MAX_SAMPLERS];
 180    spu_sample_texture4_func mag_sample_texture4[CELL_MAX_SAMPLERS];
 181
 182    /** Fragment program constants */
 183    vector float constants[4 * CELL_MAX_CONSTANTS];
 184
 185 } ALIGN16_ATTRIB;
 186
 187
 188 extern struct spu_global spu;
 189 extern boolean Debug;
 190
 191
 192
 193
 194 /* DMA TAGS */
 195
 196 #define TAG_SURFACE_CLEAR     10
 197 #define TAG_VERTEX_BUFFER     11
 198 #define TAG_READ_TILE_COLOR   12
 199 #define TAG_READ_TILE_Z       13
 200 #define TAG_WRITE_TILE_COLOR  14
 201 #define TAG_WRITE_TILE_Z      15
 202 #define TAG_INDEX_BUFFER      16
 203 #define TAG_BATCH_BUFFER      17
 204 #define TAG_MISC              18
 205 #define TAG_DCACHE0           20
 206 #define TAG_DCACHE1           21
 207 #define TAG_DCACHE2           22
 208 #define TAG_DCACHE3           23
 209
 210
 211
 212 static INLINE void
 213 wait_on_mask(unsigned tagMask)
 214 {
 215    mfc_write_tag_mask( tagMask );
 216    /* wait for completion of _any_ DMAs specified by tagMask */
 217    mfc_read_tag_status_any();
 218 }
 219
 220
 221 static INLINE void
 222 wait_on_mask_all(unsigned tagMask)
 223 {
 224    mfc_write_tag_mask( tagMask );
 225    /* wait for completion of _any_ DMAs specified by tagMask */
 226    mfc_read_tag_status_all();
 227 }
 228
 229
 230
 231
 232
 233 static INLINE void
 234 memset16(ushort *d, ushort value, uint count)
 235 {
 236    uint i;
 237    for (i = 0; i < count; i++)
 238       d[i] = value;
 239 }
 240
 241
 242 static INLINE void
 243 memset32(uint *d, uint value, uint count)
 244 {
 245    uint i;
 246    for (i = 0; i < count; i++)
 247       d[i] = value;
 248 }
 249
 250
 251 #endif /* SPU_MAIN_H */