Merge branch 'master' into gallium-0.2
[mesa.git] / src / gallium / drivers / cell / spu / spu_main.h
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef SPU_MAIN_H
29 #define SPU_MAIN_H
30
31
32 #include <spu_mfcio.h>
33
34 #include "cell/common.h"
35 #include "draw/draw_vertex.h"
36 #include "pipe/p_state.h"
37
38
39
40 #define MAX_WIDTH 1024
41 #define MAX_HEIGHT 1024
42
43
44 /**
45 * A tile is basically a TILE_SIZE x TILE_SIZE block of 4-byte pixels.
46 * The data may be addressed through several different types.
47 */
48 typedef union {
49 ushort us[TILE_SIZE][TILE_SIZE];
50 uint ui[TILE_SIZE][TILE_SIZE];
51 vector unsigned short us8[TILE_SIZE/2][TILE_SIZE/4];
52 vector unsigned int ui4[TILE_SIZE/2][TILE_SIZE/2];
53 } tile_t;
54
55
56 #define TILE_STATUS_CLEAR 1
57 #define TILE_STATUS_DEFINED 2 /**< defined in FB, but not in local store */
58 #define TILE_STATUS_CLEAN 3 /**< in local store, but not changed */
59 #define TILE_STATUS_DIRTY 4 /**< modified locally, but not put back yet */
60 #define TILE_STATUS_GETTING 5 /**< mfc_get() called but not yet arrived */
61
62
63 /** Function for sampling textures */
64 typedef vector float (*spu_sample_texture_func)(uint unit,
65 vector float texcoord);
66
67 /** Function for performing per-fragment ops */
68 typedef void (*spu_fragment_ops_func)(uint x, uint y,
69 tile_t *colorTile,
70 tile_t *depthStencilTile,
71 vector float fragZ,
72 vector float fragRed,
73 vector float fragGreen,
74 vector float fragBlue,
75 vector float fragAlpha,
76 vector unsigned int mask);
77
78 /** Function for running fragment program */
79 typedef void (*spu_fragment_program_func)(vector float *inputs,
80 vector float *outputs,
81 vector float *constants);
82
83
84 struct spu_framebuffer
85 {
86 void *color_start; /**< addr of color surface in main memory */
87 void *depth_start; /**< addr of depth surface in main memory */
88 enum pipe_format color_format;
89 enum pipe_format depth_format;
90 uint width, height; /**< size in pixels */
91 uint width_tiles, height_tiles; /**< width and height in tiles */
92
93 uint color_clear_value;
94 uint depth_clear_value;
95
96 uint zsize; /**< 0, 2 or 4 bytes per Z */
97 float zscale; /**< 65535.0, 2^24-1 or 2^32-1 */
98 } ALIGN16_ATTRIB;
99
100
101 struct spu_texture
102 {
103 void *start;
104 ushort width, height;
105 ushort tiles_per_row;
106 vector float tex_size;
107 vector unsigned int tex_size_mask; /**< == int(size - 1) */
108 vector unsigned int tex_size_x_mask; /**< == int(size - 1) */
109 vector unsigned int tex_size_y_mask; /**< == int(size - 1) */
110 } ALIGN16_ATTRIB;
111
112
113 /**
114 * All SPU global/context state will be in a singleton object of this type:
115 */
116 struct spu_global
117 {
118 /** One-time init/constant info */
119 struct cell_init_info init;
120
121 /*
122 * Current state
123 */
124 struct spu_framebuffer fb;
125 struct pipe_depth_stencil_alpha_state depth_stencil_alpha;
126 struct pipe_blend_state blend;
127 struct pipe_sampler_state sampler[PIPE_MAX_SAMPLERS];
128 struct spu_texture texture[PIPE_MAX_SAMPLERS];
129 struct vertex_info vertex_info;
130
131 /** Current color and Z tiles */
132 tile_t ctile ALIGN16_ATTRIB;
133 tile_t ztile ALIGN16_ATTRIB;
134
135 /** Read depth/stencil tiles? */
136 boolean read_depth;
137 boolean read_stencil;
138
139 /** Current tiles' status */
140 ubyte cur_ctile_status, cur_ztile_status;
141
142 /** Status of all tiles in framebuffer */
143 ubyte ctile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
144 ubyte ztile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
145
146 /** Current fragment ops machine code, at 32-byte boundary */
147 uint fragment_ops_code[SPU_MAX_FRAGMENT_OPS_INSTS] ALIGN32_ATTRIB;
148 /** Current fragment ops function */
149 spu_fragment_ops_func fragment_ops;
150
151 /** Current fragment program machine code, at 32-byte boundary */
152 uint fragment_program_code[SPU_MAX_FRAGMENT_PROGRAM_INSTS] ALIGN32_ATTRIB;
153 /** Current fragment ops function */
154 spu_fragment_program_func fragment_program;
155
156 /** Current texture sampler function */
157 spu_sample_texture_func sample_texture[CELL_MAX_SAMPLERS];
158
159 /** Fragment program constants (XXX preliminary/used) */
160 #define MAX_CONSTANTS 32
161 vector float constants[MAX_CONSTANTS];
162
163 } ALIGN16_ATTRIB;
164
165
166 extern struct spu_global spu;
167 extern boolean Debug;
168
169
170
171
172 /* DMA TAGS */
173
174 #define TAG_SURFACE_CLEAR 10
175 #define TAG_VERTEX_BUFFER 11
176 #define TAG_READ_TILE_COLOR 12
177 #define TAG_READ_TILE_Z 13
178 #define TAG_WRITE_TILE_COLOR 14
179 #define TAG_WRITE_TILE_Z 15
180 #define TAG_INDEX_BUFFER 16
181 #define TAG_BATCH_BUFFER 17
182 #define TAG_MISC 18
183 #define TAG_DCACHE0 20
184 #define TAG_DCACHE1 21
185 #define TAG_DCACHE2 22
186 #define TAG_DCACHE3 23
187
188
189
190 static INLINE void
191 wait_on_mask(unsigned tagMask)
192 {
193 mfc_write_tag_mask( tagMask );
194 /* wait for completion of _any_ DMAs specified by tagMask */
195 mfc_read_tag_status_any();
196 }
197
198
199 static INLINE void
200 wait_on_mask_all(unsigned tagMask)
201 {
202 mfc_write_tag_mask( tagMask );
203 /* wait for completion of _any_ DMAs specified by tagMask */
204 mfc_read_tag_status_all();
205 }
206
207
208
209
210
211 static INLINE void
212 memset16(ushort *d, ushort value, uint count)
213 {
214 uint i;
215 for (i = 0; i < count; i++)
216 d[i] = value;
217 }
218
219
220 static INLINE void
221 memset32(uint *d, uint value, uint count)
222 {
223 uint i;
224 for (i = 0; i < count; i++)
225 d[i] = value;
226 }
227
228
229 #endif /* SPU_MAIN_H */