Merge ../mesa into vulkan
[mesa.git] / src / gallium / drivers / ddebug / dd_pipe.h
1 /**************************************************************************
2 *
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Copyright 2008 VMware, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef DD_H_
29 #define DD_H_
30
31 #include "pipe/p_context.h"
32 #include "pipe/p_state.h"
33 #include "pipe/p_screen.h"
34 #include "dd_util.h"
35
36 enum dd_mode {
37 DD_DETECT_HANGS,
38 DD_DUMP_ALL_CALLS
39 };
40
41 struct dd_screen
42 {
43 struct pipe_screen base;
44 struct pipe_screen *screen;
45 unsigned timeout_ms;
46 enum dd_mode mode;
47 bool no_flush;
48 };
49
50 struct dd_query
51 {
52 unsigned type;
53 struct pipe_query *query;
54 };
55
56 struct dd_state
57 {
58 void *cso;
59
60 union {
61 struct pipe_blend_state blend;
62 struct pipe_depth_stencil_alpha_state dsa;
63 struct pipe_rasterizer_state rs;
64 struct pipe_sampler_state sampler;
65 struct {
66 struct pipe_vertex_element velems[PIPE_MAX_ATTRIBS];
67 unsigned count;
68 } velems;
69 struct pipe_shader_state shader;
70 } state;
71 };
72
73 struct dd_context
74 {
75 struct pipe_context base;
76 struct pipe_context *pipe;
77
78 struct {
79 struct dd_query *query;
80 bool condition;
81 unsigned mode;
82 } render_cond;
83
84 struct pipe_index_buffer index_buffer;
85 struct pipe_vertex_buffer vertex_buffers[PIPE_MAX_ATTRIBS];
86
87 unsigned num_so_targets;
88 struct pipe_stream_output_target *so_targets[PIPE_MAX_SO_BUFFERS];
89 unsigned so_offsets[PIPE_MAX_SO_BUFFERS];
90
91 struct dd_state *shaders[PIPE_SHADER_TYPES];
92 struct pipe_constant_buffer constant_buffers[PIPE_SHADER_TYPES][PIPE_MAX_CONSTANT_BUFFERS];
93 struct pipe_sampler_view *sampler_views[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
94 struct dd_state *sampler_states[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
95 struct pipe_image_view *shader_images[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_IMAGES];
96 struct pipe_shader_buffer shader_buffers[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
97
98 struct dd_state *velems;
99 struct dd_state *rs;
100 struct dd_state *dsa;
101 struct dd_state *blend;
102
103 struct pipe_blend_color blend_color;
104 struct pipe_stencil_ref stencil_ref;
105 unsigned sample_mask;
106 unsigned min_samples;
107 struct pipe_clip_state clip_state;
108 struct pipe_framebuffer_state framebuffer_state;
109 struct pipe_poly_stipple polygon_stipple;
110 struct pipe_scissor_state scissors[PIPE_MAX_VIEWPORTS];
111 struct pipe_viewport_state viewports[PIPE_MAX_VIEWPORTS];
112 float tess_default_levels[6];
113 };
114
115
116 struct pipe_context *
117 dd_context_create(struct dd_screen *dscreen, struct pipe_context *pipe);
118
119 void
120 dd_init_draw_functions(struct dd_context *dctx);
121
122
123 static inline struct dd_context *
124 dd_context(struct pipe_context *pipe)
125 {
126 return (struct dd_context *)pipe;
127 }
128
129 static inline struct dd_screen *
130 dd_screen(struct pipe_screen *screen)
131 {
132 return (struct dd_screen*)screen;
133 }
134
135
136 #define CTX_INIT(_member) \
137 dctx->base._member = dctx->pipe->_member ? dd_context_##_member : NULL
138
139 #endif /* DD_H_ */