src/gallium/drivers/etnaviv/etnaviv_blend.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  */
  26
  27 #include "etnaviv_blend.h"
  28
  29 #include "etnaviv_context.h"
  30 #include "etnaviv_translate.h"
  31 #include "pipe/p_defines.h"
  32 #include "util/u_memory.h"
  33
  34 void *
  35 etna_blend_state_create(struct pipe_context *pctx,
  36                         const struct pipe_blend_state *so)
  37 {
  38    struct etna_context *ctx = etna_context(pctx);
  39    const struct pipe_rt_blend_state *rt0 = &so->rt[0];
  40    struct etna_blend_state *co = CALLOC_STRUCT(etna_blend_state);
  41    bool alpha_enable, logicop_enable;
  42
  43    if (!co)
  44       return NULL;
  45
  46    co->base = *so;
  47
  48    /* Enable blending if
  49     * - blend enabled in blend state
  50     * - NOT source factor is ONE and destination factor ZERO for both rgb and
  51     *   alpha (which would mean that blending is effectively disabled)
  52     */
  53    alpha_enable = rt0->blend_enable &&
  54                  !(rt0->rgb_src_factor == PIPE_BLENDFACTOR_ONE &&
  55                    rt0->rgb_dst_factor == PIPE_BLENDFACTOR_ZERO &&
  56                    rt0->alpha_src_factor == PIPE_BLENDFACTOR_ONE &&
  57                    rt0->alpha_dst_factor == PIPE_BLENDFACTOR_ZERO);
  58
  59    /* Enable separate alpha if
  60     * - Blending enabled (see above)
  61     * - NOT source factor is equal to destination factor for both rgb abd
  62     *   alpha (which would effectively that mean alpha is not separate)
  63     */
  64    bool separate_alpha = alpha_enable &&
  65                          !(rt0->rgb_src_factor == rt0->alpha_src_factor &&
  66                            rt0->rgb_dst_factor == rt0->alpha_dst_factor);
  67
  68    if (alpha_enable) {
  69       co->PE_ALPHA_CONFIG =
  70          VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR |
  71          COND(separate_alpha, VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA) |
  72          VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(translate_blend_factor(rt0->rgb_src_factor)) |
  73          VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(translate_blend_factor(rt0->alpha_src_factor)) |
  74          VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(translate_blend_factor(rt0->rgb_dst_factor)) |
  75          VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(translate_blend_factor(rt0->alpha_dst_factor)) |
  76          VIVS_PE_ALPHA_CONFIG_EQ_COLOR(translate_blend(rt0->rgb_func)) |
  77          VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(translate_blend(rt0->alpha_func));
  78    } else {
  79       co->PE_ALPHA_CONFIG = 0;
  80    }
  81
  82    logicop_enable = so->logicop_enable &&
  83                     VIV_FEATURE(ctx->screen, chipMinorFeatures2, LOGIC_OP);
  84
  85    co->PE_LOGIC_OP =
  86          VIVS_PE_LOGIC_OP_OP(logicop_enable ? so->logicop_func : LOGIC_OP_COPY) |
  87          0x000E4000 /* ??? */;
  88
  89    co->fo_allowed = !alpha_enable && !logicop_enable;
  90
  91    /* independent_blend_enable not needed: only one rt supported */
  92    /* XXX alpha_to_coverage / alpha_to_one? */
  93    /* Set dither registers based on dither status. These registers set the
  94     * dither pattern,
  95     * for now, set the same values as the blob.
  96     */
  97    if (so->dither) {
  98       co->PE_DITHER[0] = 0x6e4ca280;
  99       co->PE_DITHER[1] = 0x5d7f91b3;
 100    } else {
 101       co->PE_DITHER[0] = 0xffffffff;
 102       co->PE_DITHER[1] = 0xffffffff;
 103    }
 104
 105    return co;
 106 }
 107
 108 bool
 109 etna_update_blend(struct etna_context *ctx)
 110 {
 111    struct pipe_framebuffer_state *pfb = &ctx->framebuffer_s;
 112    struct pipe_blend_state *pblend = ctx->blend;
 113    struct etna_blend_state *blend = etna_blend_state(pblend);
 114    const struct pipe_rt_blend_state *rt0 = &pblend->rt[0];
 115    uint32_t colormask;
 116
 117    if (pfb->cbufs[0] &&
 118        translate_rs_format_rb_swap(pfb->cbufs[0]->texture->format)) {
 119       colormask = rt0->colormask & (PIPE_MASK_A | PIPE_MASK_G);
 120       if (rt0->colormask & PIPE_MASK_R)
 121          colormask |= PIPE_MASK_B;
 122       if (rt0->colormask & PIPE_MASK_B)
 123          colormask |= PIPE_MASK_R;
 124    } else {
 125       colormask = rt0->colormask;
 126    }
 127
 128    /* If the complete render target is written, set full_overwrite:
 129     * - The color mask is 1111
 130     * - No blending is used
 131     */
 132    bool full_overwrite = (rt0->colormask == 0xf) &&
 133                          blend->fo_allowed;
 134    blend->PE_COLOR_FORMAT =
 135             VIVS_PE_COLOR_FORMAT_COMPONENTS(colormask) |
 136             COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE);
 137
 138    return true;
 139 }
 140
 141 void
 142 etna_set_blend_color(struct pipe_context *pctx, const struct pipe_blend_color *bc)
 143 {
 144    struct etna_context *ctx = etna_context(pctx);
 145    struct compiled_blend_color *cs = &ctx->blend_color;
 146
 147    memcpy(cs->color, bc->color, sizeof(float) * 4);
 148
 149    ctx->dirty |= ETNA_DIRTY_BLEND_COLOR;
 150 }
 151
 152 bool
 153 etna_update_blend_color(struct etna_context *ctx)
 154 {
 155    struct pipe_framebuffer_state *pfb = &ctx->framebuffer_s;
 156    struct compiled_blend_color *cs = &ctx->blend_color;
 157
 158    if (pfb->cbufs[0] &&
 159        translate_rs_format_rb_swap(pfb->cbufs[0]->texture->format)) {
 160       cs->PE_ALPHA_BLEND_COLOR =
 161          VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(cs->color[2])) |
 162          VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(cs->color[1])) |
 163          VIVS_PE_ALPHA_BLEND_COLOR_B(etna_cfloat_to_uint8(cs->color[0])) |
 164          VIVS_PE_ALPHA_BLEND_COLOR_A(etna_cfloat_to_uint8(cs->color[3]));
 165    } else {
 166       cs->PE_ALPHA_BLEND_COLOR =
 167          VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(cs->color[0])) |
 168          VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(cs->color[1])) |
 169          VIVS_PE_ALPHA_BLEND_COLOR_B(etna_cfloat_to_uint8(cs->color[2])) |
 170          VIVS_PE_ALPHA_BLEND_COLOR_A(etna_cfloat_to_uint8(cs->color[3]));
 171         }
 172
 173         return true;
 174 }