2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_clear_blit.h"
29 #include "hw/common.xml.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_emit.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_resource.h"
36 #include "etnaviv_surface.h"
37 #include "etnaviv_translate.h"
39 #include "pipe/p_defines.h"
40 #include "pipe/p_state.h"
41 #include "util/u_blitter.h"
42 #include "util/u_inlines.h"
43 #include "util/u_memory.h"
44 #include "util/u_surface.h"
46 /* Save current state for blitter operation */
48 etna_blit_save_state(struct etna_context
*ctx
)
50 util_blitter_save_vertex_buffer_slot(ctx
->blitter
, ctx
->vertex_buffer
.vb
);
51 util_blitter_save_vertex_elements(ctx
->blitter
, ctx
->vertex_elements
);
52 util_blitter_save_vertex_shader(ctx
->blitter
, ctx
->shader
.bind_vs
);
53 util_blitter_save_rasterizer(ctx
->blitter
, ctx
->rasterizer
);
54 util_blitter_save_viewport(ctx
->blitter
, &ctx
->viewport_s
);
55 util_blitter_save_scissor(ctx
->blitter
, &ctx
->scissor_s
);
56 util_blitter_save_fragment_shader(ctx
->blitter
, ctx
->shader
.bind_fs
);
57 util_blitter_save_blend(ctx
->blitter
, ctx
->blend
);
58 util_blitter_save_depth_stencil_alpha(ctx
->blitter
, ctx
->zsa
);
59 util_blitter_save_stencil_ref(ctx
->blitter
, &ctx
->stencil_ref_s
);
60 util_blitter_save_sample_mask(ctx
->blitter
, ctx
->sample_mask
);
61 util_blitter_save_framebuffer(ctx
->blitter
, &ctx
->framebuffer_s
);
62 util_blitter_save_fragment_sampler_states(ctx
->blitter
,
63 ctx
->num_fragment_samplers
, (void **)ctx
->sampler
);
64 util_blitter_save_fragment_sampler_views(ctx
->blitter
,
65 ctx
->num_fragment_sampler_views
, ctx
->sampler_view
);
68 /* Generate clear command for a surface (non-fast clear case) */
70 etna_rs_gen_clear_surface(struct etna_context
*ctx
, struct etna_surface
*surf
,
73 struct etna_resource
*dst
= etna_resource(surf
->base
.texture
);
74 uint32_t format
= translate_rs_format(surf
->base
.format
);
76 if (format
== ETNA_NO_MATCH
) {
77 BUG("etna_rs_gen_clear_surface: Unhandled clear fmt %s", util_format_name(surf
->base
.format
));
78 format
= RS_FORMAT_A8R8G8B8
;
82 /* use tiled clear if width is multiple of 16 */
83 bool tiled_clear
= (surf
->surf
.padded_width
& ETNA_RS_WIDTH_MASK
) == 0 &&
84 (surf
->surf
.padded_height
& ETNA_RS_HEIGHT_MASK
) == 0;
86 etna_compile_rs_state( ctx
, &surf
->clear_command
, &(struct rs_state
) {
87 .source_format
= format
,
88 .dest_format
= format
,
90 .dest_offset
= surf
->surf
.offset
,
91 .dest_stride
= surf
->surf
.stride
,
92 .dest_padded_height
= surf
->surf
.padded_height
,
93 .dest_tiling
= tiled_clear
? dst
->layout
: ETNA_LAYOUT_LINEAR
,
94 .dither
= {0xffffffff, 0xffffffff},
95 .width
= surf
->surf
.padded_width
, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
96 .height
= surf
->surf
.padded_height
,
97 .clear_value
= {clear_value
},
98 .clear_mode
= VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1
,
104 etna_blit_clear_color(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
105 const union pipe_color_union
*color
)
107 struct etna_context
*ctx
= etna_context(pctx
);
108 struct etna_surface
*surf
= etna_surface(dst
);
109 uint32_t new_clear_value
= translate_clear_color(surf
->base
.format
, color
);
111 if (surf
->surf
.ts_size
) { /* TS: use precompiled clear command */
112 ctx
->framebuffer
.TS_COLOR_CLEAR_VALUE
= new_clear_value
;
114 if (!DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE
) &&
115 VIV_FEATURE(ctx
->screen
, chipMinorFeatures1
, AUTO_DISABLE
)) {
116 /* Set number of color tiles to be filled */
117 etna_set_state(ctx
->stream
, VIVS_TS_COLOR_AUTO_DISABLE_COUNT
,
118 surf
->surf
.padded_width
* surf
->surf
.padded_height
/ 16);
119 ctx
->framebuffer
.TS_MEM_CONFIG
|= VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE
;
122 surf
->level
->ts_valid
= true;
123 ctx
->dirty
|= ETNA_DIRTY_TS
;
124 } else if (unlikely(new_clear_value
!= surf
->level
->clear_value
)) { /* Queue normal RS clear for non-TS surfaces */
125 /* If clear color changed, re-generate stored command */
126 etna_rs_gen_clear_surface(ctx
, surf
, new_clear_value
);
129 etna_submit_rs_state(ctx
, &surf
->clear_command
);
130 surf
->level
->clear_value
= new_clear_value
;
131 resource_written(ctx
, surf
->base
.texture
);
132 etna_resource(surf
->base
.texture
)->seqno
++;
136 etna_blit_clear_zs(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
137 unsigned buffers
, double depth
, unsigned stencil
)
139 struct etna_context
*ctx
= etna_context(pctx
);
140 struct etna_surface
*surf
= etna_surface(dst
);
141 uint32_t new_clear_value
= translate_clear_depth_stencil(surf
->base
.format
, depth
, stencil
);
142 uint32_t new_clear_bits
= 0, clear_bits_depth
, clear_bits_stencil
;
144 /* Get the channels to clear */
145 switch (surf
->base
.format
) {
146 case PIPE_FORMAT_Z16_UNORM
:
147 clear_bits_depth
= 0xffff;
148 clear_bits_stencil
= 0;
150 case PIPE_FORMAT_X8Z24_UNORM
:
151 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
152 clear_bits_depth
= 0xeeee;
153 clear_bits_stencil
= 0x1111;
156 clear_bits_depth
= clear_bits_stencil
= 0xffff;
160 if (buffers
& PIPE_CLEAR_DEPTH
)
161 new_clear_bits
|= clear_bits_depth
;
162 if (buffers
& PIPE_CLEAR_STENCIL
)
163 new_clear_bits
|= clear_bits_stencil
;
165 /* FIXME: when tile status is enabled, this becomes more complex as
166 * we may separately clear the depth from the stencil. In this case,
167 * we want to resolve the surface, and avoid using the tile status.
168 * We may be better off recording the pending clear operation,
169 * delaying the actual clear to the first use. This way, we can merge
170 * consecutive clears together. */
171 if (surf
->surf
.ts_size
) { /* TS: use precompiled clear command */
172 /* Set new clear depth value */
173 ctx
->framebuffer
.TS_DEPTH_CLEAR_VALUE
= new_clear_value
;
174 if (!DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE
) &&
175 VIV_FEATURE(ctx
->screen
, chipMinorFeatures1
, AUTO_DISABLE
)) {
176 /* Set number of depth tiles to be filled */
177 etna_set_state(ctx
->stream
, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT
,
178 surf
->surf
.padded_width
* surf
->surf
.padded_height
/ 16);
179 ctx
->framebuffer
.TS_MEM_CONFIG
|= VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE
;
182 surf
->level
->ts_valid
= true;
183 ctx
->dirty
|= ETNA_DIRTY_TS
;
185 if (unlikely(new_clear_value
!= surf
->level
->clear_value
)) { /* Queue normal RS clear for non-TS surfaces */
186 /* If clear depth value changed, re-generate stored command */
187 etna_rs_gen_clear_surface(ctx
, surf
, new_clear_value
);
189 /* Update the channels to be cleared */
190 etna_modify_rs_clearbits(&surf
->clear_command
, new_clear_bits
);
193 etna_submit_rs_state(ctx
, &surf
->clear_command
);
194 surf
->level
->clear_value
= new_clear_value
;
195 resource_written(ctx
, surf
->base
.texture
);
196 etna_resource(surf
->base
.texture
)->seqno
++;
200 etna_clear(struct pipe_context
*pctx
, unsigned buffers
,
201 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
203 struct etna_context
*ctx
= etna_context(pctx
);
205 /* Flush color and depth cache before clearing anything.
206 * This is especially important when coming from another surface, as
207 * otherwise it may clear part of the old surface instead. */
208 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, VIVS_GL_FLUSH_CACHE_COLOR
| VIVS_GL_FLUSH_CACHE_DEPTH
);
209 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
211 /* Preparation: Flush the TS if needed. This must be done after flushing
212 * color and depth, otherwise it can result in crashes */
213 bool need_ts_flush
= false;
214 if ((buffers
& PIPE_CLEAR_COLOR
) && ctx
->framebuffer_s
.nr_cbufs
) {
215 struct etna_surface
*surf
= etna_surface(ctx
->framebuffer_s
.cbufs
[0]);
216 if (surf
->surf
.ts_size
)
217 need_ts_flush
= true;
219 if ((buffers
& PIPE_CLEAR_DEPTHSTENCIL
) && ctx
->framebuffer_s
.zsbuf
!= NULL
) {
220 struct etna_surface
*surf
= etna_surface(ctx
->framebuffer_s
.zsbuf
);
222 if (surf
->surf
.ts_size
)
223 need_ts_flush
= true;
227 etna_set_state(ctx
->stream
, VIVS_TS_FLUSH_CACHE
, VIVS_TS_FLUSH_CACHE_FLUSH
);
229 /* No need to set up the TS here as RS clear operations (in contrast to
230 * resolve and copy) do not require the TS state.
232 if (buffers
& PIPE_CLEAR_COLOR
) {
233 for (int idx
= 0; idx
< ctx
->framebuffer_s
.nr_cbufs
; ++idx
) {
234 etna_blit_clear_color(pctx
, ctx
->framebuffer_s
.cbufs
[idx
],
239 /* Flush the color and depth caches before each RS clear operation
240 * This fixes a hang on GC600. */
241 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
&& buffers
& PIPE_CLEAR_COLOR
)
242 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
,
243 VIVS_GL_FLUSH_CACHE_COLOR
| VIVS_GL_FLUSH_CACHE_DEPTH
);
245 if ((buffers
& PIPE_CLEAR_DEPTHSTENCIL
) && ctx
->framebuffer_s
.zsbuf
!= NULL
)
246 etna_blit_clear_zs(pctx
, ctx
->framebuffer_s
.zsbuf
, buffers
, depth
, stencil
);
248 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
252 etna_clear_render_target(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
253 const union pipe_color_union
*color
, unsigned dstx
,
254 unsigned dsty
, unsigned width
, unsigned height
,
255 bool render_condition_enabled
)
257 struct etna_context
*ctx
= etna_context(pctx
);
259 /* XXX could fall back to RS when target area is full screen / resolveable
261 etna_blit_save_state(ctx
);
262 util_blitter_clear_render_target(ctx
->blitter
, dst
, color
, dstx
, dsty
, width
, height
);
266 etna_clear_depth_stencil(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
267 unsigned clear_flags
, double depth
, unsigned stencil
,
268 unsigned dstx
, unsigned dsty
, unsigned width
,
269 unsigned height
, bool render_condition_enabled
)
271 struct etna_context
*ctx
= etna_context(pctx
);
273 /* XXX could fall back to RS when target area is full screen / resolveable
275 etna_blit_save_state(ctx
);
276 util_blitter_clear_depth_stencil(ctx
->blitter
, dst
, clear_flags
, depth
,
277 stencil
, dstx
, dsty
, width
, height
);
281 etna_resource_copy_region(struct pipe_context
*pctx
, struct pipe_resource
*dst
,
282 unsigned dst_level
, unsigned dstx
, unsigned dsty
,
283 unsigned dstz
, struct pipe_resource
*src
,
284 unsigned src_level
, const struct pipe_box
*src_box
)
286 struct etna_context
*ctx
= etna_context(pctx
);
288 /* The resource must be of the same format. */
289 assert(src
->format
== dst
->format
);
290 /* Resources with nr_samples > 1 are not allowed. */
291 assert(src
->nr_samples
<= 1 && dst
->nr_samples
<= 1);
293 /* XXX we can use the RS as a literal copy engine here
294 * the only complexity is tiling; the size of the boxes needs to be aligned
296 * how to handle the case where a resource is copied from/to a non-aligned
298 * from non-aligned: can fall back to rendering-based copy?
299 * to non-aligned: can fall back to rendering-based copy?
300 * XXX this goes wrong when source surface is supertiled.
302 if (util_blitter_is_copy_supported(ctx
->blitter
, dst
, src
)) {
303 etna_blit_save_state(ctx
);
304 util_blitter_copy_texture(ctx
->blitter
, dst
, dst_level
, dstx
, dsty
, dstz
,
305 src
, src_level
, src_box
);
307 util_resource_copy_region(pctx
, dst
, dst_level
, dstx
, dsty
, dstz
, src
,
313 etna_manual_blit(struct etna_resource
*dst
, struct etna_resource_level
*dst_lev
,
314 unsigned int dst_offset
, struct etna_resource
*src
,
315 struct etna_resource_level
*src_lev
, unsigned int src_offset
,
316 const struct pipe_blit_info
*blit_info
)
318 void *smap
, *srow
, *dmap
, *drow
;
321 assert(src
->layout
== ETNA_LAYOUT_TILED
);
322 assert(dst
->layout
== ETNA_LAYOUT_TILED
);
323 assert(src
->base
.nr_samples
== 0);
324 assert(dst
->base
.nr_samples
== 0);
326 tile_size
= util_format_get_blocksize(blit_info
->src
.format
) * 4 * 4;
328 smap
= etna_bo_map(src
->bo
);
332 dmap
= etna_bo_map(dst
->bo
);
336 srow
= smap
+ src_offset
;
337 drow
= dmap
+ dst_offset
;
339 etna_bo_cpu_prep(src
->bo
, DRM_ETNA_PREP_READ
);
340 etna_bo_cpu_prep(dst
->bo
, DRM_ETNA_PREP_WRITE
);
342 for (int y
= 0; y
< blit_info
->src
.box
.height
; y
+= 4) {
343 memcpy(drow
, srow
, tile_size
* blit_info
->src
.box
.width
);
344 srow
+= src_lev
->stride
* 4;
345 drow
+= dst_lev
->stride
* 4;
348 etna_bo_cpu_fini(dst
->bo
);
349 etna_bo_cpu_fini(src
->bo
);
355 etna_try_rs_blit(struct pipe_context
*pctx
,
356 const struct pipe_blit_info
*blit_info
)
358 struct etna_context
*ctx
= etna_context(pctx
);
359 struct etna_resource
*src
= etna_resource(blit_info
->src
.resource
);
360 struct etna_resource
*dst
= etna_resource(blit_info
->dst
.resource
);
361 struct compiled_rs_state copy_to_screen
;
362 uint32_t ts_mem_config
= 0;
363 int msaa_xscale
= 1, msaa_yscale
= 1;
365 /* Ensure that the level is valid */
366 assert(blit_info
->src
.level
<= src
->base
.last_level
);
367 assert(blit_info
->dst
.level
<= dst
->base
.last_level
);
369 if (!translate_samples_to_xyscale(src
->base
.nr_samples
, &msaa_xscale
, &msaa_yscale
, NULL
))
372 /* The width/height are in pixels; they do not change as a result of
373 * multi-sampling. So, when blitting from a 4x multisampled surface
374 * to a non-multisampled surface, the width and height will be
375 * identical. As we do not support scaling, reject different sizes. */
376 if (blit_info
->dst
.box
.width
!= blit_info
->src
.box
.width
||
377 blit_info
->dst
.box
.height
!= blit_info
->src
.box
.height
) {
378 DBG("scaling requested: source %dx%d destination %dx%d",
379 blit_info
->src
.box
.width
, blit_info
->src
.box
.height
,
380 blit_info
->dst
.box
.width
, blit_info
->dst
.box
.height
);
384 /* No masks - RS can't copy specific channels */
385 unsigned mask
= util_format_get_mask(blit_info
->dst
.format
);
386 if ((blit_info
->mask
& mask
) != mask
) {
387 DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info
->mask
, mask
);
391 unsigned src_format
= etna_compatible_rs_format(blit_info
->src
.format
);
392 unsigned dst_format
= etna_compatible_rs_format(blit_info
->src
.format
);
393 if (translate_rs_format(src_format
) == ETNA_NO_MATCH
||
394 translate_rs_format(dst_format
) == ETNA_NO_MATCH
||
395 blit_info
->scissor_enable
|| blit_info
->src
.box
.x
!= 0 ||
396 blit_info
->src
.box
.y
!= 0 || blit_info
->dst
.box
.x
!= 0 ||
397 blit_info
->dst
.box
.y
!= 0 ||
398 blit_info
->dst
.box
.depth
!= blit_info
->src
.box
.depth
||
399 blit_info
->dst
.box
.depth
!= 1) {
403 /* Ensure that the Z coordinate is sane */
404 if (dst
->base
.target
!= PIPE_TEXTURE_CUBE
)
405 assert(blit_info
->dst
.box
.z
== 0);
406 if (src
->base
.target
!= PIPE_TEXTURE_CUBE
)
407 assert(blit_info
->src
.box
.z
== 0);
409 assert(blit_info
->src
.box
.z
< src
->base
.array_size
);
410 assert(blit_info
->dst
.box
.z
< dst
->base
.array_size
);
412 struct etna_resource_level
*src_lev
= &src
->levels
[blit_info
->src
.level
];
413 struct etna_resource_level
*dst_lev
= &dst
->levels
[blit_info
->dst
.level
];
415 /* we may be given coordinates up to the padded width to avoid
416 * any alignment issues with different tiling formats */
417 assert((blit_info
->src
.box
.x
+ blit_info
->src
.box
.width
) * msaa_xscale
<= src_lev
->padded_width
);
418 assert((blit_info
->src
.box
.y
+ blit_info
->src
.box
.height
) * msaa_yscale
<= src_lev
->padded_height
);
419 assert(blit_info
->dst
.box
.x
+ blit_info
->dst
.box
.width
<= dst_lev
->padded_width
);
420 assert(blit_info
->dst
.box
.y
+ blit_info
->dst
.box
.height
<= dst_lev
->padded_height
);
422 unsigned src_offset
=
423 src_lev
->offset
+ blit_info
->src
.box
.z
* src_lev
->layer_stride
;
424 unsigned dst_offset
=
425 dst_lev
->offset
+ blit_info
->dst
.box
.z
* dst_lev
->layer_stride
;
427 if (src_lev
->padded_width
<= ETNA_RS_WIDTH_MASK
||
428 dst_lev
->padded_width
<= ETNA_RS_WIDTH_MASK
||
429 src_lev
->padded_height
<= ETNA_RS_HEIGHT_MASK
||
430 dst_lev
->padded_height
<= ETNA_RS_HEIGHT_MASK
)
433 /* If the width is not aligned to the RS width, but is within our
434 * padding, adjust the width to suite the RS width restriction.
435 * Note: the RS width/height are converted to source samples here. */
436 unsigned int width
= blit_info
->src
.box
.width
* msaa_xscale
;
437 unsigned int height
= blit_info
->src
.box
.height
* msaa_yscale
;
438 unsigned int w_align
= ETNA_RS_WIDTH_MASK
+ 1;
439 unsigned int h_align
= (ETNA_RS_HEIGHT_MASK
+ 1) * ctx
->specs
.pixel_pipes
;
441 if (width
& (w_align
- 1) && width
>= src_lev
->width
* msaa_xscale
&& width
>= dst_lev
->width
)
442 width
= align(width
, w_align
);
444 if (height
& (h_align
- 1) && height
>= src_lev
->height
* msaa_yscale
&& height
>= dst_lev
->height
)
445 height
= align(height
, h_align
);
447 /* The padded dimensions are in samples */
448 if (width
> src_lev
->padded_width
||
449 width
> dst_lev
->padded_width
* msaa_xscale
||
450 height
> src_lev
->padded_height
||
451 height
> dst_lev
->padded_height
* msaa_yscale
)
454 if (src
->base
.nr_samples
> 1) {
455 uint32_t msaa_format
= translate_msaa_format(src_format
);
456 assert(msaa_format
!= ETNA_NO_MATCH
);
457 ts_mem_config
|= VIVS_TS_MEM_CONFIG_MSAA
| msaa_format
;
460 uint32_t to_flush
= 0;
462 if (src
->base
.bind
& PIPE_BIND_RENDER_TARGET
)
463 to_flush
|= VIVS_GL_FLUSH_CACHE_COLOR
;
464 if (src
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
)
465 to_flush
|= VIVS_GL_FLUSH_CACHE_DEPTH
;
468 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, to_flush
);
469 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
472 /* Set up color TS to source surface before blit, if needed */
473 if (src
->levels
[blit_info
->src
.level
].ts_size
&&
474 src
->levels
[blit_info
->src
.level
].ts_valid
) {
475 struct etna_reloc reloc
;
477 src_lev
->ts_offset
+ blit_info
->src
.box
.z
* src_lev
->ts_layer_stride
;
479 etna_set_state(ctx
->stream
, VIVS_TS_MEM_CONFIG
,
480 VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR
| ts_mem_config
);
482 memset(&reloc
, 0, sizeof(struct etna_reloc
));
483 reloc
.bo
= src
->ts_bo
;
484 reloc
.offset
= ts_offset
;
485 reloc
.flags
= ETNA_RELOC_READ
;
486 etna_set_state_reloc(ctx
->stream
, VIVS_TS_COLOR_STATUS_BASE
, &reloc
);
488 memset(&reloc
, 0, sizeof(struct etna_reloc
));
490 reloc
.offset
= src_offset
;
491 reloc
.flags
= ETNA_RELOC_READ
;
492 etna_set_state_reloc(ctx
->stream
, VIVS_TS_COLOR_SURFACE_BASE
, &reloc
);
494 etna_set_state(ctx
->stream
, VIVS_TS_COLOR_CLEAR_VALUE
,
495 src
->levels
[blit_info
->src
.level
].clear_value
);
497 etna_set_state(ctx
->stream
, VIVS_TS_MEM_CONFIG
, ts_mem_config
);
499 ctx
->dirty
|= ETNA_DIRTY_TS
;
501 /* Kick off RS here */
502 etna_compile_rs_state(ctx
, ©_to_screen
, &(struct rs_state
) {
503 .source_format
= translate_rs_format(src_format
),
504 .source_tiling
= src
->layout
,
506 .source_offset
= src_offset
,
507 .source_stride
= src_lev
->stride
,
508 .source_padded_height
= src_lev
->padded_height
,
509 .dest_format
= translate_rs_format(dst_format
),
510 .dest_tiling
= dst
->layout
,
512 .dest_offset
= dst_offset
,
513 .dest_stride
= dst_lev
->stride
,
514 .dest_padded_height
= dst_lev
->padded_height
,
515 .downsample_x
= msaa_xscale
> 1,
516 .downsample_y
= msaa_yscale
> 1,
517 .swap_rb
= translate_rb_src_dst_swap(src
->base
.format
, dst
->base
.format
),
518 .dither
= {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
519 .clear_mode
= VIVS_RS_CLEAR_CONTROL_MODE_DISABLED
,
524 etna_submit_rs_state(ctx
, ©_to_screen
);
525 resource_written(ctx
, &dst
->base
);
527 dst
->levels
[blit_info
->dst
.level
].ts_valid
= false;
532 if (src
->layout
== ETNA_LAYOUT_TILED
&& dst
->layout
== ETNA_LAYOUT_TILED
) {
533 etna_resource_wait(pctx
, dst
);
534 etna_resource_wait(pctx
, src
);
535 return etna_manual_blit(dst
, dst_lev
, dst_offset
, src
, src_lev
, src_offset
, blit_info
);
542 etna_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
544 /* This is a more extended version of resource_copy_region */
545 /* TODO Some cases can be handled by RS; if not, fall back to rendering or
546 * even CPU copy block of pixels from info->src to info->dst
547 * (resource, level, box, format);
548 * function is used for scaling, flipping in x and y direction (negative
549 * width/height), format conversion, mask and filter and even a scissor rectangle
551 * What can the RS do for us:
552 * convert between tiling formats (layouts)
553 * downsample 2x in x and y
554 * convert between a limited number of pixel formats
556 * For the rest, fall back to util_blitter
557 * XXX this goes wrong when source surface is supertiled. */
558 struct etna_context
*ctx
= etna_context(pctx
);
559 struct pipe_blit_info info
= *blit_info
;
561 if (info
.src
.resource
->nr_samples
> 1 &&
562 info
.dst
.resource
->nr_samples
<= 1 &&
563 !util_format_is_depth_or_stencil(info
.src
.resource
->format
) &&
564 !util_format_is_pure_integer(info
.src
.resource
->format
)) {
565 DBG("color resolve unimplemented");
569 if (etna_try_rs_blit(pctx
, blit_info
))
572 if (util_try_blit_via_copy_region(pctx
, blit_info
))
575 if (info
.mask
& PIPE_MASK_S
) {
576 DBG("cannot blit stencil, skipping");
577 info
.mask
&= ~PIPE_MASK_S
;
580 if (!util_blitter_is_blit_supported(ctx
->blitter
, &info
)) {
581 DBG("blit unsupported %s -> %s",
582 util_format_short_name(info
.src
.resource
->format
),
583 util_format_short_name(info
.dst
.resource
->format
));
587 etna_blit_save_state(ctx
);
588 util_blitter_blit(ctx
->blitter
, &info
);
592 etna_flush_resource(struct pipe_context
*pctx
, struct pipe_resource
*prsc
)
594 struct etna_resource
*rsc
= etna_resource(prsc
);
597 etna_resource_older(etna_resource(rsc
->scanout
->prime
), rsc
)) {
598 etna_copy_resource(pctx
, rsc
->scanout
->prime
, prsc
, 0, 0);
599 etna_resource(rsc
->scanout
->prime
)->seqno
= rsc
->seqno
;
600 } else if (etna_resource_needs_flush(rsc
)) {
601 etna_copy_resource(pctx
, prsc
, prsc
, 0, 0);
602 rsc
->flush_seqno
= rsc
->seqno
;
607 etna_copy_resource(struct pipe_context
*pctx
, struct pipe_resource
*dst
,
608 struct pipe_resource
*src
, int first_level
, int last_level
)
610 struct etna_resource
*src_priv
= etna_resource(src
);
611 struct etna_resource
*dst_priv
= etna_resource(dst
);
613 assert(src
->format
== dst
->format
);
614 assert(src
->array_size
== dst
->array_size
);
615 assert(last_level
<= dst
->last_level
&& last_level
<= src
->last_level
);
617 struct pipe_blit_info blit
= {};
618 blit
.mask
= util_format_get_mask(dst
->format
);
619 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
620 blit
.src
.resource
= src
;
621 blit
.src
.format
= src
->format
;
622 blit
.dst
.resource
= dst
;
623 blit
.dst
.format
= dst
->format
;
624 blit
.dst
.box
.depth
= blit
.src
.box
.depth
= 1;
626 /* Copy each level and each layer */
627 for (int level
= first_level
; level
<= last_level
; level
++) {
628 blit
.src
.level
= blit
.dst
.level
= level
;
629 blit
.src
.box
.width
= blit
.dst
.box
.width
=
630 MIN2(src_priv
->levels
[level
].width
, dst_priv
->levels
[level
].width
);
631 blit
.src
.box
.height
= blit
.dst
.box
.height
=
632 MIN2(src_priv
->levels
[level
].height
, dst_priv
->levels
[level
].height
);
634 for (int layer
= 0; layer
< dst
->array_size
; layer
++) {
635 blit
.src
.box
.z
= blit
.dst
.box
.z
= layer
;
636 pctx
->blit(pctx
, &blit
);
642 etna_clear_blit_init(struct pipe_context
*pctx
)
644 pctx
->clear
= etna_clear
;
645 pctx
->clear_render_target
= etna_clear_render_target
;
646 pctx
->clear_depth_stencil
= etna_clear_depth_stencil
;
647 pctx
->resource_copy_region
= etna_resource_copy_region
;
648 pctx
->blit
= etna_blit
;
649 pctx
->flush_resource
= etna_flush_resource
;