2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 /* TGSI->Vivante shader ISA conversion */
29 /* What does the compiler return (see etna_shader_object)?
31 * 2) input-to-temporary mapping (fixed for ps)
32 * *) in case of ps, semantic -> varying id mapping
33 * *) for each varying: number of components used (r, rg, rgb, rgba)
34 * 3) temporary-to-output mapping (in case of vs, fixed for ps)
35 * 4) for each input/output: possible semantic (position, color, glpointcoord, ...)
36 * 5) immediates base offset, immediates data
37 * 6) used texture units (and possibly the TGSI_TEXTURE_* type); not needed to
38 * configure the hw, but useful for error checking
39 * 7) enough information to add the z=(z+w)/2.0 necessary for older chips
40 * (output reg id is enough)
42 * Empty shaders are not allowed, should always at least generate a NOP. Also
43 * if there is a label at the end of the shader, an extra NOP should be
44 * generated as jump target.
47 * * Use an instruction scheduler
48 * * Indirect access to uniforms / temporaries using amode
51 #include "etnaviv_compiler.h"
53 #include "etnaviv_asm.h"
54 #include "etnaviv_context.h"
55 #include "etnaviv_debug.h"
56 #include "etnaviv_disasm.h"
57 #include "etnaviv_uniforms.h"
58 #include "etnaviv_util.h"
60 #include "pipe/p_shader_tokens.h"
61 #include "tgsi/tgsi_info.h"
62 #include "tgsi/tgsi_iterate.h"
63 #include "tgsi/tgsi_lowering.h"
64 #include "tgsi/tgsi_strings.h"
65 #include "tgsi/tgsi_util.h"
66 #include "util/u_math.h"
67 #include "util/u_memory.h"
72 #include <sys/types.h>
74 #define ETNA_MAX_INNER_TEMPS 2
76 static const float sincos_const
[2][4] = {
81 1. / (2. * M_PI
), 0.75, 0.5, 0.0,
85 /* Native register description structure */
86 struct etna_native_reg
{
88 unsigned is_tex
: 1; /* is texture unit, overrides rgroup */
93 /* Register description */
94 struct etna_reg_desc
{
95 enum tgsi_file_type file
; /* IN, OUT, TEMP, ... */
96 int idx
; /* index into file */
97 bool active
; /* used in program */
98 int first_use
; /* instruction id of first use (scope begin) */
99 int last_use
; /* instruction id of last use (scope end, inclusive) */
101 struct etna_native_reg native
; /* native register to map to */
102 unsigned usage_mask
: 4; /* usage, per channel */
103 bool has_semantic
; /* register has associated TGSI semantic */
104 struct tgsi_declaration_semantic semantic
; /* TGSI semantic */
105 struct tgsi_declaration_interp interp
; /* Interpolation type */
108 /* Label information structure */
109 struct etna_compile_label
{
110 int inst_idx
; /* Instruction id that label points to */
113 enum etna_compile_frame_type
{
114 ETNA_COMPILE_FRAME_IF
, /* IF/ELSE/ENDIF */
115 ETNA_COMPILE_FRAME_LOOP
,
118 /* nesting scope frame (LOOP, IF, ...) during compilation
120 struct etna_compile_frame
{
121 enum etna_compile_frame_type type
;
124 int lbl_loop_bgn_idx
;
125 int lbl_loop_end_idx
;
128 struct etna_compile_file
{
129 /* Number of registers in each TGSI file (max register+1) */
131 /* Register descriptions, per register index */
132 struct etna_reg_desc
*reg
;
135 #define array_insert(arr, val) \
137 if (arr##_count == arr##_sz) { \
138 arr##_sz = MAX2(2 * arr##_sz, 16); \
139 arr = realloc(arr, arr##_sz * sizeof(arr[0])); \
141 arr[arr##_count++] = val; \
145 /* scratch area for compiling shader, freed after compilation finishes */
146 struct etna_compile
{
147 const struct tgsi_token
*tokens
;
150 struct tgsi_shader_info info
;
152 /* Register descriptions, per TGSI file, per register index */
153 struct etna_compile_file file
[TGSI_FILE_COUNT
];
155 /* Keep track of TGSI register declarations */
156 struct etna_reg_desc decl
[ETNA_MAX_DECL
];
159 /* Bitmap of dead instructions which are removed in a separate pass */
160 bool dead_inst
[ETNA_MAX_TOKENS
];
163 enum etna_immediate_contents imm_contents
[ETNA_MAX_IMM
];
164 uint32_t imm_data
[ETNA_MAX_IMM
];
165 uint32_t imm_base
; /* base of immediates (in 32 bit units) */
166 uint32_t imm_size
; /* size of immediates (in 32 bit units) */
168 /* Next free native register, for register allocation */
169 uint32_t next_free_native
;
171 /* Temporary register for use within translated TGSI instruction,
172 * only allocated when needed.
174 int inner_temps
; /* number of inner temps used; only up to one available at
176 struct etna_native_reg inner_temp
[ETNA_MAX_INNER_TEMPS
];
178 /* Fields for handling nested conditionals */
179 struct etna_compile_frame frame_stack
[ETNA_MAX_DEPTH
];
181 int lbl_usage
[ETNA_MAX_INSTRUCTIONS
];
183 unsigned labels_count
, labels_sz
;
184 struct etna_compile_label
*labels
;
188 /* Code generation */
189 int inst_ptr
; /* current instruction pointer */
190 uint32_t code
[ETNA_MAX_INSTRUCTIONS
* ETNA_INST_SIZE
];
194 /* Number of varyings (PS only) */
197 /* GPU hardware specs */
198 const struct etna_specs
*specs
;
200 const struct etna_shader_key
*key
;
203 static struct etna_reg_desc
*
204 etna_get_dst_reg(struct etna_compile
*c
, struct tgsi_dst_register dst
)
206 return &c
->file
[dst
.File
].reg
[dst
.Index
];
209 static struct etna_reg_desc
*
210 etna_get_src_reg(struct etna_compile
*c
, struct tgsi_src_register src
)
212 return &c
->file
[src
.File
].reg
[src
.Index
];
215 static struct etna_native_reg
216 etna_native_temp(unsigned reg
)
218 return (struct etna_native_reg
) {
220 .rgroup
= INST_RGROUP_TEMP
,
225 /** Register allocation **/
226 enum reg_sort_order
{
233 /* Augmented register description for sorting */
235 struct etna_reg_desc
*ptr
;
240 sort_rec_compar(const struct sort_rec
*a
, const struct sort_rec
*b
)
251 /* create an index on a register set based on certain criteria. */
253 sort_registers(struct sort_rec
*sorted
, struct etna_compile_file
*file
,
254 enum reg_sort_order so
)
256 struct etna_reg_desc
*regs
= file
->reg
;
259 /* pre-populate keys from active registers */
260 for (int idx
= 0; idx
< file
->reg_size
; ++idx
) {
261 /* only interested in active registers now; will only assign inactive ones
262 * if no space in active ones */
263 if (regs
[idx
].active
) {
264 sorted
[ptr
].ptr
= ®s
[idx
];
268 sorted
[ptr
].key
= regs
[idx
].first_use
;
271 sorted
[ptr
].key
= regs
[idx
].last_use
;
274 sorted
[ptr
].key
= -regs
[idx
].first_use
;
277 sorted
[ptr
].key
= -regs
[idx
].last_use
;
284 /* sort index by key */
285 qsort(sorted
, ptr
, sizeof(struct sort_rec
),
286 (int (*)(const void *, const void *))sort_rec_compar
);
291 /* Allocate a new, unused, native temp register */
292 static struct etna_native_reg
293 alloc_new_native_reg(struct etna_compile
*c
)
295 assert(c
->next_free_native
< ETNA_MAX_TEMPS
);
296 return etna_native_temp(c
->next_free_native
++);
299 /* assign TEMPs to native registers */
301 assign_temporaries_to_native(struct etna_compile
*c
,
302 struct etna_compile_file
*file
)
304 struct etna_reg_desc
*temps
= file
->reg
;
306 for (int idx
= 0; idx
< file
->reg_size
; ++idx
)
307 temps
[idx
].native
= alloc_new_native_reg(c
);
310 /* assign inputs and outputs to temporaries
311 * Gallium assumes that the hardware has separate registers for taking input and
312 * output, however Vivante GPUs use temporaries both for passing in inputs and
313 * passing back outputs.
314 * Try to re-use temporary registers where possible. */
316 assign_inouts_to_temporaries(struct etna_compile
*c
, uint file
)
318 bool mode_inputs
= (file
== TGSI_FILE_INPUT
);
319 int inout_ptr
= 0, num_inouts
;
320 int temp_ptr
= 0, num_temps
;
321 struct sort_rec inout_order
[ETNA_MAX_TEMPS
];
322 struct sort_rec temps_order
[ETNA_MAX_TEMPS
];
323 num_inouts
= sort_registers(inout_order
, &c
->file
[file
],
324 mode_inputs
? LAST_USE_ASC
: FIRST_USE_ASC
);
325 num_temps
= sort_registers(temps_order
, &c
->file
[TGSI_FILE_TEMPORARY
],
326 mode_inputs
? FIRST_USE_ASC
: LAST_USE_ASC
);
328 while (inout_ptr
< num_inouts
&& temp_ptr
< num_temps
) {
329 struct etna_reg_desc
*inout
= inout_order
[inout_ptr
].ptr
;
330 struct etna_reg_desc
*temp
= temps_order
[temp_ptr
].ptr
;
332 if (!inout
->active
|| inout
->native
.valid
) { /* Skip if already a native register assigned */
337 /* last usage of this input is before or in same instruction of first use
339 if (mode_inputs
? (inout
->last_use
<= temp
->first_use
)
340 : (inout
->first_use
>= temp
->last_use
)) {
341 /* assign it and advance to next input */
342 inout
->native
= temp
->native
;
349 /* if we couldn't reuse current ones, allocate new temporaries */
350 for (inout_ptr
= 0; inout_ptr
< num_inouts
; ++inout_ptr
) {
351 struct etna_reg_desc
*inout
= inout_order
[inout_ptr
].ptr
;
353 if (inout
->active
&& !inout
->native
.valid
)
354 inout
->native
= alloc_new_native_reg(c
);
358 /* Allocate an immediate with a certain value and return the index. If
359 * there is already an immediate with that value, return that.
361 static struct etna_inst_src
362 alloc_imm(struct etna_compile
*c
, enum etna_immediate_contents contents
,
367 /* Could use a hash table to speed this up */
368 for (idx
= 0; idx
< c
->imm_size
; ++idx
) {
369 if (c
->imm_contents
[idx
] == contents
&& c
->imm_data
[idx
] == value
)
373 /* look if there is an unused slot */
374 if (idx
== c
->imm_size
) {
375 for (idx
= 0; idx
< c
->imm_size
; ++idx
) {
376 if (c
->imm_contents
[idx
] == ETNA_IMMEDIATE_UNUSED
)
381 /* allocate new immediate */
382 if (idx
== c
->imm_size
) {
383 assert(c
->imm_size
< ETNA_MAX_IMM
);
385 c
->imm_data
[idx
] = value
;
386 c
->imm_contents
[idx
] = contents
;
389 /* swizzle so that component with value is returned in all components */
391 struct etna_inst_src imm_src
= {
393 .rgroup
= INST_RGROUP_UNIFORM_0
,
395 .swiz
= INST_SWIZ_BROADCAST(idx
& 3)
401 static struct etna_inst_src
402 alloc_imm_u32(struct etna_compile
*c
, uint32_t value
)
404 return alloc_imm(c
, ETNA_IMMEDIATE_CONSTANT
, value
);
407 static struct etna_inst_src
408 alloc_imm_vec4u(struct etna_compile
*c
, enum etna_immediate_contents contents
,
409 const uint32_t *values
)
411 struct etna_inst_src imm_src
= { };
414 for (idx
= 0; idx
+ 3 < c
->imm_size
; idx
+= 4) {
415 /* What if we can use a uniform with a different swizzle? */
416 for (i
= 0; i
< 4; i
++)
417 if (c
->imm_contents
[idx
+ i
] != contents
|| c
->imm_data
[idx
+ i
] != values
[i
])
423 if (idx
+ 3 >= c
->imm_size
) {
424 idx
= align(c
->imm_size
, 4);
425 assert(idx
+ 4 <= ETNA_MAX_IMM
);
427 for (i
= 0; i
< 4; i
++) {
428 c
->imm_data
[idx
+ i
] = values
[i
];
429 c
->imm_contents
[idx
+ i
] = contents
;
432 c
->imm_size
= idx
+ 4;
435 assert((c
->imm_base
& 3) == 0);
438 imm_src
.rgroup
= INST_RGROUP_UNIFORM_0
;
439 imm_src
.reg
= idx
/ 4;
440 imm_src
.swiz
= INST_SWIZ_IDENTITY
;
446 get_imm_u32(struct etna_compile
*c
, const struct etna_inst_src
*imm
,
449 assert(imm
->use
== 1 && imm
->rgroup
== INST_RGROUP_UNIFORM_0
);
450 unsigned int idx
= imm
->reg
* 4 + ((imm
->swiz
>> (swiz_idx
* 2)) & 3);
452 return c
->imm_data
[idx
];
455 /* Allocate immediate with a certain float value. If there is already an
456 * immediate with that value, return that.
458 static struct etna_inst_src
459 alloc_imm_f32(struct etna_compile
*c
, float value
)
461 return alloc_imm_u32(c
, fui(value
));
464 static struct etna_inst_src
465 etna_imm_vec4f(struct etna_compile
*c
, const float *vec4
)
469 for (int i
= 0; i
< 4; i
++)
470 val
[i
] = fui(vec4
[i
]);
472 return alloc_imm_vec4u(c
, ETNA_IMMEDIATE_CONSTANT
, val
);
475 /* Pass -- check register file declarations and immediates */
477 etna_compile_parse_declarations(struct etna_compile
*c
)
479 struct tgsi_parse_context ctx
= { };
480 unsigned status
= TGSI_PARSE_OK
;
481 status
= tgsi_parse_init(&ctx
, c
->tokens
);
482 assert(status
== TGSI_PARSE_OK
);
484 while (!tgsi_parse_end_of_tokens(&ctx
)) {
485 tgsi_parse_token(&ctx
);
487 switch (ctx
.FullToken
.Token
.Type
) {
488 case TGSI_TOKEN_TYPE_IMMEDIATE
: {
489 /* immediates are handled differently from other files; they are
490 * not declared explicitly, and always add four components */
491 const struct tgsi_full_immediate
*imm
= &ctx
.FullToken
.FullImmediate
;
492 assert(c
->imm_size
<= (ETNA_MAX_IMM
- 4));
494 for (int i
= 0; i
< 4; ++i
) {
495 unsigned idx
= c
->imm_size
++;
497 c
->imm_data
[idx
] = imm
->u
[i
].Uint
;
498 c
->imm_contents
[idx
] = ETNA_IMMEDIATE_CONSTANT
;
505 tgsi_parse_free(&ctx
);
508 /* Allocate register declarations for the registers in all register files */
510 etna_allocate_decls(struct etna_compile
*c
)
514 for (int x
= 0; x
< TGSI_FILE_COUNT
; ++x
) {
515 c
->file
[x
].reg
= &c
->decl
[idx
];
516 c
->file
[x
].reg_size
= c
->info
.file_max
[x
] + 1;
518 for (int sub
= 0; sub
< c
->file
[x
].reg_size
; ++sub
) {
519 c
->decl
[idx
].file
= x
;
520 c
->decl
[idx
].idx
= sub
;
525 c
->total_decls
= idx
;
528 /* Pass -- check and record usage of temporaries, inputs, outputs */
530 etna_compile_pass_check_usage(struct etna_compile
*c
)
532 struct tgsi_parse_context ctx
= { };
533 unsigned status
= TGSI_PARSE_OK
;
534 status
= tgsi_parse_init(&ctx
, c
->tokens
);
535 assert(status
== TGSI_PARSE_OK
);
537 for (int idx
= 0; idx
< c
->total_decls
; ++idx
) {
538 c
->decl
[idx
].active
= false;
539 c
->decl
[idx
].first_use
= c
->decl
[idx
].last_use
= -1;
543 while (!tgsi_parse_end_of_tokens(&ctx
)) {
544 tgsi_parse_token(&ctx
);
545 /* find out max register #s used
546 * For every register mark first and last instruction index where it's
547 * used this allows finding ranges where the temporary can be borrowed
548 * as input and/or output register
550 * XXX in the case of loops this needs special care, or even be completely
552 * the last usage of a register inside a loop means it can still be used
554 * iteration (execution is no longer * chronological). The register can
556 * declared "free" after the loop finishes.
558 * Same for inputs: the first usage of a register inside a loop doesn't
559 * mean that the register
560 * won't have been overwritten in previous iteration. The register can
561 * only be declared free before the loop
563 * The proper way would be to do full dominator / post-dominator analysis
564 * (especially with more complicated
565 * control flow such as direct branch instructions) but not for now...
567 switch (ctx
.FullToken
.Token
.Type
) {
568 case TGSI_TOKEN_TYPE_DECLARATION
: {
569 /* Declaration: fill in file details */
570 const struct tgsi_full_declaration
*decl
= &ctx
.FullToken
.FullDeclaration
;
571 struct etna_compile_file
*file
= &c
->file
[decl
->Declaration
.File
];
573 for (int idx
= decl
->Range
.First
; idx
<= decl
->Range
.Last
; ++idx
) {
574 file
->reg
[idx
].usage_mask
= 0; // we'll compute this ourselves
575 file
->reg
[idx
].has_semantic
= decl
->Declaration
.Semantic
;
576 file
->reg
[idx
].semantic
= decl
->Semantic
;
577 file
->reg
[idx
].interp
= decl
->Interp
;
580 case TGSI_TOKEN_TYPE_INSTRUCTION
: {
581 /* Instruction: iterate over operands of instruction */
582 const struct tgsi_full_instruction
*inst
= &ctx
.FullToken
.FullInstruction
;
584 /* iterate over destination registers */
585 for (int idx
= 0; idx
< inst
->Instruction
.NumDstRegs
; ++idx
) {
586 struct etna_reg_desc
*reg_desc
= &c
->file
[inst
->Dst
[idx
].Register
.File
].reg
[inst
->Dst
[idx
].Register
.Index
];
588 if (reg_desc
->first_use
== -1)
589 reg_desc
->first_use
= inst_idx
;
591 reg_desc
->last_use
= inst_idx
;
592 reg_desc
->active
= true;
595 /* iterate over source registers */
596 for (int idx
= 0; idx
< inst
->Instruction
.NumSrcRegs
; ++idx
) {
597 struct etna_reg_desc
*reg_desc
= &c
->file
[inst
->Src
[idx
].Register
.File
].reg
[inst
->Src
[idx
].Register
.Index
];
599 if (reg_desc
->first_use
== -1)
600 reg_desc
->first_use
= inst_idx
;
602 reg_desc
->last_use
= inst_idx
;
603 reg_desc
->active
= true;
604 /* accumulate usage mask for register, this is used to determine how
605 * many slots for varyings
606 * should be allocated */
607 reg_desc
->usage_mask
|= tgsi_util_get_inst_usage_mask(inst
, idx
);
616 tgsi_parse_free(&ctx
);
619 /* assign inputs that need to be assigned to specific registers */
621 assign_special_inputs(struct etna_compile
*c
)
623 if (c
->info
.processor
== PIPE_SHADER_FRAGMENT
) {
624 /* never assign t0 as it is the position output, start assigning at t1 */
625 c
->next_free_native
= 1;
627 /* hardwire TGSI_SEMANTIC_POSITION (input and output) to t0 */
628 for (int idx
= 0; idx
< c
->total_decls
; ++idx
) {
629 struct etna_reg_desc
*reg
= &c
->decl
[idx
];
631 if (reg
->active
&& reg
->semantic
.Name
== TGSI_SEMANTIC_POSITION
)
632 reg
->native
= etna_native_temp(0);
637 /* Check that a move instruction does not swizzle any of the components
641 etna_mov_check_no_swizzle(const struct tgsi_dst_register dst
,
642 const struct tgsi_src_register src
)
644 return (!(dst
.WriteMask
& TGSI_WRITEMASK_X
) || src
.SwizzleX
== TGSI_SWIZZLE_X
) &&
645 (!(dst
.WriteMask
& TGSI_WRITEMASK_Y
) || src
.SwizzleY
== TGSI_SWIZZLE_Y
) &&
646 (!(dst
.WriteMask
& TGSI_WRITEMASK_Z
) || src
.SwizzleZ
== TGSI_SWIZZLE_Z
) &&
647 (!(dst
.WriteMask
& TGSI_WRITEMASK_W
) || src
.SwizzleW
== TGSI_SWIZZLE_W
);
650 /* Pass -- optimize outputs
651 * Mesa tends to generate code like this at the end if their shaders
652 * MOV OUT[1], TEMP[2]
653 * MOV OUT[0], TEMP[0]
654 * MOV OUT[2], TEMP[1]
656 * a) there is only a single assignment to an output register and
657 * b) the temporary is not used after that
658 * Also recognize direct assignment of IN to OUT (passthrough)
661 etna_compile_pass_optimize_outputs(struct etna_compile
*c
)
663 struct tgsi_parse_context ctx
= { };
665 unsigned status
= TGSI_PARSE_OK
;
666 status
= tgsi_parse_init(&ctx
, c
->tokens
);
667 assert(status
== TGSI_PARSE_OK
);
669 while (!tgsi_parse_end_of_tokens(&ctx
)) {
670 tgsi_parse_token(&ctx
);
672 switch (ctx
.FullToken
.Token
.Type
) {
673 case TGSI_TOKEN_TYPE_INSTRUCTION
: {
674 const struct tgsi_full_instruction
*inst
= &ctx
.FullToken
.FullInstruction
;
676 /* iterate over operands */
677 switch (inst
->Instruction
.Opcode
) {
678 case TGSI_OPCODE_MOV
: {
679 /* We are only interested in eliminating MOVs which write to
680 * the shader outputs. Test for this early. */
681 if (inst
->Dst
[0].Register
.File
!= TGSI_FILE_OUTPUT
)
683 /* Elimination of a MOV must have no visible effect on the
684 * resulting shader: this means the MOV must not swizzle or
685 * saturate, and its source must not have the negate or
686 * absolute modifiers. */
687 if (!etna_mov_check_no_swizzle(inst
->Dst
[0].Register
, inst
->Src
[0].Register
) ||
688 inst
->Instruction
.Saturate
|| inst
->Src
[0].Register
.Negate
||
689 inst
->Src
[0].Register
.Absolute
)
692 uint out_idx
= inst
->Dst
[0].Register
.Index
;
693 uint in_idx
= inst
->Src
[0].Register
.Index
;
694 /* assignment of temporary to output --
695 * and the output doesn't yet have a native register assigned
696 * and the last use of the temporary is this instruction
697 * and the MOV does not do a swizzle
699 if (inst
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
&&
700 !c
->file
[TGSI_FILE_OUTPUT
].reg
[out_idx
].native
.valid
&&
701 c
->file
[TGSI_FILE_TEMPORARY
].reg
[in_idx
].last_use
== inst_idx
) {
702 c
->file
[TGSI_FILE_OUTPUT
].reg
[out_idx
].native
=
703 c
->file
[TGSI_FILE_TEMPORARY
].reg
[in_idx
].native
;
704 /* prevent temp from being re-used for the rest of the shader */
705 c
->file
[TGSI_FILE_TEMPORARY
].reg
[in_idx
].last_use
= ETNA_MAX_TOKENS
;
706 /* mark this MOV instruction as a no-op */
707 c
->dead_inst
[inst_idx
] = true;
709 /* direct assignment of input to output --
710 * and the input or output doesn't yet have a native register
712 * and the output is only used in this instruction,
713 * allocate a new register, and associate both input and output to
715 * and the MOV does not do a swizzle
717 if (inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
&&
718 !c
->file
[TGSI_FILE_INPUT
].reg
[in_idx
].native
.valid
&&
719 !c
->file
[TGSI_FILE_OUTPUT
].reg
[out_idx
].native
.valid
&&
720 c
->file
[TGSI_FILE_OUTPUT
].reg
[out_idx
].last_use
== inst_idx
&&
721 c
->file
[TGSI_FILE_OUTPUT
].reg
[out_idx
].first_use
== inst_idx
) {
722 c
->file
[TGSI_FILE_OUTPUT
].reg
[out_idx
].native
=
723 c
->file
[TGSI_FILE_INPUT
].reg
[in_idx
].native
=
724 alloc_new_native_reg(c
);
725 /* mark this MOV instruction as a no-op */
726 c
->dead_inst
[inst_idx
] = true;
736 tgsi_parse_free(&ctx
);
739 /* Get a temporary to be used within one TGSI instruction.
740 * The first time that this function is called the temporary will be allocated.
741 * Each call to this function will return the same temporary.
743 static struct etna_native_reg
744 etna_compile_get_inner_temp(struct etna_compile
*c
)
746 int inner_temp
= c
->inner_temps
;
748 if (inner_temp
< ETNA_MAX_INNER_TEMPS
) {
749 if (!c
->inner_temp
[inner_temp
].valid
)
750 c
->inner_temp
[inner_temp
] = alloc_new_native_reg(c
);
752 /* alloc_new_native_reg() handles lack of registers */
755 BUG("Too many inner temporaries (%i) requested in one instruction",
759 return c
->inner_temp
[inner_temp
];
762 static struct etna_inst_dst
763 etna_native_to_dst(struct etna_native_reg native
, unsigned comps
)
765 /* Can only assign to temporaries */
766 assert(native
.valid
&& !native
.is_tex
&& native
.rgroup
== INST_RGROUP_TEMP
);
768 struct etna_inst_dst rv
= {
777 static struct etna_inst_src
778 etna_native_to_src(struct etna_native_reg native
, uint32_t swizzle
)
780 assert(native
.valid
&& !native
.is_tex
);
782 struct etna_inst_src rv
= {
785 .rgroup
= native
.rgroup
,
787 .amode
= INST_AMODE_DIRECT
,
793 static inline struct etna_inst_src
794 negate(struct etna_inst_src src
)
801 static inline struct etna_inst_src
802 absolute(struct etna_inst_src src
)
809 static inline struct etna_inst_src
810 swizzle(struct etna_inst_src src
, unsigned swizzle
)
812 src
.swiz
= inst_swiz_compose(src
.swiz
, swizzle
);
817 /* Emit instruction and append it to program */
819 emit_inst(struct etna_compile
*c
, struct etna_inst
*inst
)
821 assert(c
->inst_ptr
<= ETNA_MAX_INSTRUCTIONS
);
823 /* Check for uniform conflicts (each instruction can only access one
825 * if detected, use an intermediate temporary */
826 unsigned uni_rgroup
= -1;
827 unsigned uni_reg
= -1;
829 for (int src
= 0; src
< ETNA_NUM_SRC
; ++src
) {
830 if (etna_rgroup_is_uniform(inst
->src
[src
].rgroup
)) {
831 if (uni_reg
== -1) { /* first unique uniform used */
832 uni_rgroup
= inst
->src
[src
].rgroup
;
833 uni_reg
= inst
->src
[src
].reg
;
834 } else { /* second or later; check that it is a re-use */
835 if (uni_rgroup
!= inst
->src
[src
].rgroup
||
836 uni_reg
!= inst
->src
[src
].reg
) {
837 DBG_F(ETNA_DBG_COMPILER_MSGS
, "perf warning: instruction that "
838 "accesses different uniforms, "
839 "need to generate extra MOV");
840 struct etna_native_reg inner_temp
= etna_compile_get_inner_temp(c
);
842 /* Generate move instruction to temporary */
843 etna_assemble(&c
->code
[c
->inst_ptr
* 4], &(struct etna_inst
) {
844 .opcode
= INST_OPCODE_MOV
,
845 .dst
= etna_native_to_dst(inner_temp
, INST_COMPS_X
| INST_COMPS_Y
|
846 INST_COMPS_Z
| INST_COMPS_W
),
847 .src
[2] = inst
->src
[src
]
852 /* Modify instruction to use temp register instead of uniform */
853 inst
->src
[src
].use
= 1;
854 inst
->src
[src
].rgroup
= INST_RGROUP_TEMP
;
855 inst
->src
[src
].reg
= inner_temp
.id
;
856 inst
->src
[src
].swiz
= INST_SWIZ_IDENTITY
; /* swizzling happens on MOV */
857 inst
->src
[src
].neg
= 0; /* negation happens on MOV */
858 inst
->src
[src
].abs
= 0; /* abs happens on MOV */
859 inst
->src
[src
].amode
= 0; /* amode effects happen on MOV */
865 /* Finally assemble the actual instruction */
866 etna_assemble(&c
->code
[c
->inst_ptr
* 4], inst
);
871 etna_amode(struct tgsi_ind_register indirect
)
873 assert(indirect
.File
== TGSI_FILE_ADDRESS
);
874 assert(indirect
.Index
== 0);
876 switch (indirect
.Swizzle
) {
878 return INST_AMODE_ADD_A_X
;
880 return INST_AMODE_ADD_A_Y
;
882 return INST_AMODE_ADD_A_Z
;
884 return INST_AMODE_ADD_A_W
;
886 assert(!"Invalid swizzle");
889 unreachable("bad swizzle");
892 /* convert destination operand */
893 static struct etna_inst_dst
894 convert_dst(struct etna_compile
*c
, const struct tgsi_full_dst_register
*in
)
896 struct etna_inst_dst rv
= {
898 .comps
= in
->Register
.WriteMask
,
901 if (in
->Register
.File
== TGSI_FILE_ADDRESS
) {
902 assert(in
->Register
.Index
== 0);
903 rv
.reg
= in
->Register
.Index
;
906 rv
= etna_native_to_dst(etna_get_dst_reg(c
, in
->Register
)->native
,
907 in
->Register
.WriteMask
);
910 if (in
->Register
.Indirect
)
911 rv
.amode
= etna_amode(in
->Indirect
);
916 /* convert texture operand */
917 static struct etna_inst_tex
918 convert_tex(struct etna_compile
*c
, const struct tgsi_full_src_register
*in
,
919 const struct tgsi_instruction_texture
*tex
)
921 struct etna_native_reg native_reg
= etna_get_src_reg(c
, in
->Register
)->native
;
922 struct etna_inst_tex rv
= {
923 // XXX .amode (to allow for an array of samplers?)
924 .swiz
= INST_SWIZ_IDENTITY
927 assert(native_reg
.is_tex
&& native_reg
.valid
);
928 rv
.id
= native_reg
.id
;
933 /* convert source operand */
934 static struct etna_inst_src
935 etna_create_src(const struct tgsi_full_src_register
*tgsi
,
936 const struct etna_native_reg
*native
)
938 const struct tgsi_src_register
*reg
= &tgsi
->Register
;
939 struct etna_inst_src rv
= {
941 .swiz
= INST_SWIZ(reg
->SwizzleX
, reg
->SwizzleY
, reg
->SwizzleZ
, reg
->SwizzleW
),
943 .abs
= reg
->Absolute
,
944 .rgroup
= native
->rgroup
,
946 .amode
= INST_AMODE_DIRECT
,
949 assert(native
->valid
&& !native
->is_tex
);
952 rv
.amode
= etna_amode(tgsi
->Indirect
);
957 static struct etna_inst_src
958 etna_mov_src_to_temp(struct etna_compile
*c
, struct etna_inst_src src
,
959 struct etna_native_reg temp
)
961 struct etna_inst mov
= { };
963 mov
.opcode
= INST_OPCODE_MOV
;
965 mov
.dst
= etna_native_to_dst(temp
, INST_COMPS_X
| INST_COMPS_Y
|
966 INST_COMPS_Z
| INST_COMPS_W
);
970 src
.swiz
= INST_SWIZ_IDENTITY
;
971 src
.neg
= src
.abs
= 0;
972 src
.rgroup
= temp
.rgroup
;
978 static struct etna_inst_src
979 etna_mov_src(struct etna_compile
*c
, struct etna_inst_src src
)
981 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
);
983 return etna_mov_src_to_temp(c
, src
, temp
);
987 etna_src_uniforms_conflict(struct etna_inst_src a
, struct etna_inst_src b
)
989 return etna_rgroup_is_uniform(a
.rgroup
) &&
990 etna_rgroup_is_uniform(b
.rgroup
) &&
991 (a
.rgroup
!= b
.rgroup
|| a
.reg
!= b
.reg
);
994 /* create a new label */
996 alloc_new_label(struct etna_compile
*c
)
998 struct etna_compile_label label
= {
999 .inst_idx
= -1, /* start by point to no specific instruction */
1002 array_insert(c
->labels
, label
);
1004 return c
->labels_count
- 1;
1007 /* place label at current instruction pointer */
1009 label_place(struct etna_compile
*c
, struct etna_compile_label
*label
)
1011 label
->inst_idx
= c
->inst_ptr
;
1014 /* mark label use at current instruction.
1015 * target of the label will be filled in in the marked instruction's src2.imm
1017 * as the value becomes known.
1020 label_mark_use(struct etna_compile
*c
, int lbl_idx
)
1022 assert(c
->inst_ptr
< ETNA_MAX_INSTRUCTIONS
);
1023 c
->lbl_usage
[c
->inst_ptr
] = lbl_idx
;
1026 /* walk the frame stack and return first frame with matching type */
1027 static struct etna_compile_frame
*
1028 find_frame(struct etna_compile
*c
, enum etna_compile_frame_type type
)
1030 for (int sp
= c
->frame_sp
; sp
>= 0; sp
--)
1031 if (c
->frame_stack
[sp
].type
== type
)
1032 return &c
->frame_stack
[sp
];
1038 struct instr_translater
{
1039 void (*fxn
)(const struct instr_translater
*t
, struct etna_compile
*c
,
1040 const struct tgsi_full_instruction
*inst
,
1041 struct etna_inst_src
*src
);
1045 /* tgsi src -> etna src swizzle */
1052 trans_instr(const struct instr_translater
*t
, struct etna_compile
*c
,
1053 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1055 const struct tgsi_opcode_info
*info
= tgsi_get_opcode_info(inst
->Instruction
.Opcode
);
1056 struct etna_inst instr
= { };
1058 instr
.opcode
= t
->opc
;
1059 instr
.cond
= t
->cond
;
1060 instr
.sat
= inst
->Instruction
.Saturate
;
1062 assert(info
->num_dst
<= 1);
1064 instr
.dst
= convert_dst(c
, &inst
->Dst
[0]);
1066 assert(info
->num_src
<= ETNA_NUM_SRC
);
1068 for (unsigned i
= 0; i
< info
->num_src
; i
++) {
1069 int swizzle
= t
->src
[i
];
1071 assert(swizzle
!= -1);
1072 instr
.src
[swizzle
] = src
[i
];
1075 emit_inst(c
, &instr
);
1079 trans_min_max(const struct instr_translater
*t
, struct etna_compile
*c
,
1080 const struct tgsi_full_instruction
*inst
,
1081 struct etna_inst_src
*src
)
1083 emit_inst(c
, &(struct etna_inst
) {
1084 .opcode
= INST_OPCODE_SELECT
,
1086 .sat
= inst
->Instruction
.Saturate
,
1087 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1095 trans_if(const struct instr_translater
*t
, struct etna_compile
*c
,
1096 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1098 struct etna_compile_frame
*f
= &c
->frame_stack
[c
->frame_sp
++];
1099 struct etna_inst_src imm_0
= alloc_imm_f32(c
, 0.0f
);
1101 /* push IF to stack */
1102 f
->type
= ETNA_COMPILE_FRAME_IF
;
1103 /* create "else" label */
1104 f
->lbl_else_idx
= alloc_new_label(c
);
1105 f
->lbl_endif_idx
= -1;
1107 /* We need to avoid the emit_inst() below becoming two instructions */
1108 if (etna_src_uniforms_conflict(src
[0], imm_0
))
1109 src
[0] = etna_mov_src(c
, src
[0]);
1111 /* mark position in instruction stream of label reference so that it can be
1112 * filled in in next pass */
1113 label_mark_use(c
, f
->lbl_else_idx
);
1115 /* create conditional branch to label if src0 EQ 0 */
1116 emit_inst(c
, &(struct etna_inst
){
1117 .opcode
= INST_OPCODE_BRANCH
,
1118 .cond
= INST_CONDITION_EQ
,
1121 /* imm is filled in later */
1126 trans_else(const struct instr_translater
*t
, struct etna_compile
*c
,
1127 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1129 assert(c
->frame_sp
> 0);
1130 struct etna_compile_frame
*f
= &c
->frame_stack
[c
->frame_sp
- 1];
1131 assert(f
->type
== ETNA_COMPILE_FRAME_IF
);
1133 /* create "endif" label, and branch to endif label */
1134 f
->lbl_endif_idx
= alloc_new_label(c
);
1135 label_mark_use(c
, f
->lbl_endif_idx
);
1136 emit_inst(c
, &(struct etna_inst
) {
1137 .opcode
= INST_OPCODE_BRANCH
,
1138 .cond
= INST_CONDITION_TRUE
,
1139 /* imm is filled in later */
1142 /* mark "else" label at this position in instruction stream */
1143 label_place(c
, &c
->labels
[f
->lbl_else_idx
]);
1147 trans_endif(const struct instr_translater
*t
, struct etna_compile
*c
,
1148 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1150 assert(c
->frame_sp
> 0);
1151 struct etna_compile_frame
*f
= &c
->frame_stack
[--c
->frame_sp
];
1152 assert(f
->type
== ETNA_COMPILE_FRAME_IF
);
1154 /* assign "endif" or "else" (if no ELSE) label to current position in
1155 * instruction stream, pop IF */
1156 if (f
->lbl_endif_idx
!= -1)
1157 label_place(c
, &c
->labels
[f
->lbl_endif_idx
]);
1159 label_place(c
, &c
->labels
[f
->lbl_else_idx
]);
1163 trans_loop_bgn(const struct instr_translater
*t
, struct etna_compile
*c
,
1164 const struct tgsi_full_instruction
*inst
,
1165 struct etna_inst_src
*src
)
1167 struct etna_compile_frame
*f
= &c
->frame_stack
[c
->frame_sp
++];
1169 /* push LOOP to stack */
1170 f
->type
= ETNA_COMPILE_FRAME_LOOP
;
1171 f
->lbl_loop_bgn_idx
= alloc_new_label(c
);
1172 f
->lbl_loop_end_idx
= alloc_new_label(c
);
1174 label_place(c
, &c
->labels
[f
->lbl_loop_bgn_idx
]);
1180 trans_loop_end(const struct instr_translater
*t
, struct etna_compile
*c
,
1181 const struct tgsi_full_instruction
*inst
,
1182 struct etna_inst_src
*src
)
1184 assert(c
->frame_sp
> 0);
1185 struct etna_compile_frame
*f
= &c
->frame_stack
[--c
->frame_sp
];
1186 assert(f
->type
== ETNA_COMPILE_FRAME_LOOP
);
1188 /* mark position in instruction stream of label reference so that it can be
1189 * filled in in next pass */
1190 label_mark_use(c
, f
->lbl_loop_bgn_idx
);
1192 /* create branch to loop_bgn label */
1193 emit_inst(c
, &(struct etna_inst
) {
1194 .opcode
= INST_OPCODE_BRANCH
,
1195 .cond
= INST_CONDITION_TRUE
,
1197 /* imm is filled in later */
1200 label_place(c
, &c
->labels
[f
->lbl_loop_end_idx
]);
1204 trans_brk(const struct instr_translater
*t
, struct etna_compile
*c
,
1205 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1207 assert(c
->frame_sp
> 0);
1208 struct etna_compile_frame
*f
= find_frame(c
, ETNA_COMPILE_FRAME_LOOP
);
1210 /* mark position in instruction stream of label reference so that it can be
1211 * filled in in next pass */
1212 label_mark_use(c
, f
->lbl_loop_end_idx
);
1214 /* create branch to loop_end label */
1215 emit_inst(c
, &(struct etna_inst
) {
1216 .opcode
= INST_OPCODE_BRANCH
,
1217 .cond
= INST_CONDITION_TRUE
,
1219 /* imm is filled in later */
1224 trans_cont(const struct instr_translater
*t
, struct etna_compile
*c
,
1225 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1227 assert(c
->frame_sp
> 0);
1228 struct etna_compile_frame
*f
= find_frame(c
, ETNA_COMPILE_FRAME_LOOP
);
1230 /* mark position in instruction stream of label reference so that it can be
1231 * filled in in next pass */
1232 label_mark_use(c
, f
->lbl_loop_bgn_idx
);
1234 /* create branch to loop_end label */
1235 emit_inst(c
, &(struct etna_inst
) {
1236 .opcode
= INST_OPCODE_BRANCH
,
1237 .cond
= INST_CONDITION_TRUE
,
1239 /* imm is filled in later */
1244 trans_deriv(const struct instr_translater
*t
, struct etna_compile
*c
,
1245 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1247 emit_inst(c
, &(struct etna_inst
) {
1249 .sat
= inst
->Instruction
.Saturate
,
1250 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1257 trans_arl(const struct instr_translater
*t
, struct etna_compile
*c
,
1258 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1260 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
);
1261 struct etna_inst arl
= { };
1262 struct etna_inst_dst dst
;
1264 dst
= etna_native_to_dst(temp
, INST_COMPS_X
| INST_COMPS_Y
| INST_COMPS_Z
|
1267 if (c
->specs
->has_sign_floor_ceil
) {
1268 struct etna_inst floor
= { };
1270 floor
.opcode
= INST_OPCODE_FLOOR
;
1271 floor
.src
[2] = src
[0];
1274 emit_inst(c
, &floor
);
1276 struct etna_inst floor
[2] = { };
1278 floor
[0].opcode
= INST_OPCODE_FRC
;
1279 floor
[0].sat
= inst
->Instruction
.Saturate
;
1281 floor
[0].src
[2] = src
[0];
1283 floor
[1].opcode
= INST_OPCODE_ADD
;
1284 floor
[1].sat
= inst
->Instruction
.Saturate
;
1286 floor
[1].src
[0] = src
[0];
1287 floor
[1].src
[2].use
= 1;
1288 floor
[1].src
[2].swiz
= INST_SWIZ_IDENTITY
;
1289 floor
[1].src
[2].neg
= 1;
1290 floor
[1].src
[2].rgroup
= temp
.rgroup
;
1291 floor
[1].src
[2].reg
= temp
.id
;
1293 emit_inst(c
, &floor
[0]);
1294 emit_inst(c
, &floor
[1]);
1297 arl
.opcode
= INST_OPCODE_MOVAR
;
1298 arl
.sat
= inst
->Instruction
.Saturate
;
1299 arl
.dst
= convert_dst(c
, &inst
->Dst
[0]);
1300 arl
.src
[2] = etna_native_to_src(temp
, INST_SWIZ_IDENTITY
);
1306 trans_lrp(const struct instr_translater
*t
, struct etna_compile
*c
,
1307 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1309 /* dst = src0 * src1 + (1 - src0) * src2
1310 * => src0 * src1 - (src0 - 1) * src2
1311 * => src0 * src1 - (src0 * src2 - src2)
1312 * MAD tTEMP.xyzw, tSRC0.xyzw, tSRC2.xyzw, -tSRC2.xyzw
1313 * MAD tDST.xyzw, tSRC0.xyzw, tSRC1.xyzw, -tTEMP.xyzw
1315 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
);
1316 if (etna_src_uniforms_conflict(src
[0], src
[1]) ||
1317 etna_src_uniforms_conflict(src
[0], src
[2])) {
1318 src
[0] = etna_mov_src(c
, src
[0]);
1321 struct etna_inst mad
[2] = { };
1322 mad
[0].opcode
= INST_OPCODE_MAD
;
1324 mad
[0].dst
= etna_native_to_dst(temp
, INST_COMPS_X
| INST_COMPS_Y
|
1325 INST_COMPS_Z
| INST_COMPS_W
);
1326 mad
[0].src
[0] = src
[0];
1327 mad
[0].src
[1] = src
[2];
1328 mad
[0].src
[2] = negate(src
[2]);
1329 mad
[1].opcode
= INST_OPCODE_MAD
;
1330 mad
[1].sat
= inst
->Instruction
.Saturate
;
1331 mad
[1].dst
= convert_dst(c
, &inst
->Dst
[0]), mad
[1].src
[0] = src
[0];
1332 mad
[1].src
[1] = src
[1];
1333 mad
[1].src
[2] = negate(etna_native_to_src(temp
, INST_SWIZ_IDENTITY
));
1335 emit_inst(c
, &mad
[0]);
1336 emit_inst(c
, &mad
[1]);
1340 trans_lit(const struct instr_translater
*t
, struct etna_compile
*c
,
1341 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1343 /* SELECT.LT tmp._y__, 0, src.yyyy, 0
1344 * - can be eliminated if src.y is a uniform and >= 0
1345 * SELECT.GT tmp.___w, 128, src.wwww, 128
1346 * SELECT.LT tmp.___w, -128, tmp.wwww, -128
1347 * - can be eliminated if src.w is a uniform and fits clamp
1348 * LOG tmp.x, void, void, tmp.yyyy
1349 * MUL tmp.x, tmp.xxxx, tmp.wwww, void
1350 * LITP dst, undef, src.xxxx, tmp.xxxx
1352 struct etna_native_reg inner_temp
= etna_compile_get_inner_temp(c
);
1353 struct etna_inst_src src_y
= { };
1355 if (!etna_rgroup_is_uniform(src
[0].rgroup
)) {
1356 src_y
= etna_native_to_src(inner_temp
, SWIZZLE(Y
, Y
, Y
, Y
));
1358 struct etna_inst ins
= { };
1359 ins
.opcode
= INST_OPCODE_SELECT
;
1360 ins
.cond
= INST_CONDITION_LT
;
1361 ins
.dst
= etna_native_to_dst(inner_temp
, INST_COMPS_Y
);
1362 ins
.src
[0] = ins
.src
[2] = alloc_imm_f32(c
, 0.0);
1363 ins
.src
[1] = swizzle(src
[0], SWIZZLE(Y
, Y
, Y
, Y
));
1365 } else if (uif(get_imm_u32(c
, &src
[0], 1)) < 0)
1366 src_y
= alloc_imm_f32(c
, 0.0);
1368 src_y
= swizzle(src
[0], SWIZZLE(Y
, Y
, Y
, Y
));
1370 struct etna_inst_src src_w
= { };
1372 if (!etna_rgroup_is_uniform(src
[0].rgroup
)) {
1373 src_w
= etna_native_to_src(inner_temp
, SWIZZLE(W
, W
, W
, W
));
1375 struct etna_inst ins
= { };
1376 ins
.opcode
= INST_OPCODE_SELECT
;
1377 ins
.cond
= INST_CONDITION_GT
;
1378 ins
.dst
= etna_native_to_dst(inner_temp
, INST_COMPS_W
);
1379 ins
.src
[0] = ins
.src
[2] = alloc_imm_f32(c
, 128.);
1380 ins
.src
[1] = swizzle(src
[0], SWIZZLE(W
, W
, W
, W
));
1382 ins
.cond
= INST_CONDITION_LT
;
1383 ins
.src
[0].neg
= !ins
.src
[0].neg
;
1384 ins
.src
[2].neg
= !ins
.src
[2].neg
;
1387 } else if (uif(get_imm_u32(c
, &src
[0], 3)) < -128.)
1388 src_w
= alloc_imm_f32(c
, -128.);
1389 else if (uif(get_imm_u32(c
, &src
[0], 3)) > 128.)
1390 src_w
= alloc_imm_f32(c
, 128.);
1392 src_w
= swizzle(src
[0], SWIZZLE(W
, W
, W
, W
));
1394 if (c
->specs
->has_new_transcendentals
) { /* Alternative LOG sequence */
1395 emit_inst(c
, &(struct etna_inst
) {
1396 .opcode
= INST_OPCODE_LOG
,
1397 .dst
= etna_native_to_dst(inner_temp
, INST_COMPS_X
| INST_COMPS_Y
),
1399 .tex
= { .amode
=1 }, /* Unknown bit needs to be set */
1401 emit_inst(c
, &(struct etna_inst
) {
1402 .opcode
= INST_OPCODE_MUL
,
1403 .dst
= etna_native_to_dst(inner_temp
, INST_COMPS_X
),
1404 .src
[0] = etna_native_to_src(inner_temp
, SWIZZLE(X
, X
, X
, X
)),
1405 .src
[1] = etna_native_to_src(inner_temp
, SWIZZLE(Y
, Y
, Y
, Y
)),
1408 struct etna_inst ins
[3] = { };
1409 ins
[0].opcode
= INST_OPCODE_LOG
;
1410 ins
[0].dst
= etna_native_to_dst(inner_temp
, INST_COMPS_X
);
1411 ins
[0].src
[2] = src_y
;
1413 emit_inst(c
, &ins
[0]);
1415 emit_inst(c
, &(struct etna_inst
) {
1416 .opcode
= INST_OPCODE_MUL
,
1418 .dst
= etna_native_to_dst(inner_temp
, INST_COMPS_X
),
1419 .src
[0] = etna_native_to_src(inner_temp
, SWIZZLE(X
, X
, X
, X
)),
1422 emit_inst(c
, &(struct etna_inst
) {
1423 .opcode
= INST_OPCODE_LITP
,
1425 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1426 .src
[0] = swizzle(src
[0], SWIZZLE(X
, X
, X
, X
)),
1427 .src
[1] = swizzle(src
[0], SWIZZLE(X
, X
, X
, X
)),
1428 .src
[2] = etna_native_to_src(inner_temp
, SWIZZLE(X
, X
, X
, X
)),
1433 trans_ssg(const struct instr_translater
*t
, struct etna_compile
*c
,
1434 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1436 if (c
->specs
->has_sign_floor_ceil
) {
1437 emit_inst(c
, &(struct etna_inst
){
1438 .opcode
= INST_OPCODE_SIGN
,
1439 .sat
= inst
->Instruction
.Saturate
,
1440 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1444 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
);
1445 struct etna_inst ins
[2] = { };
1447 ins
[0].opcode
= INST_OPCODE_SET
;
1448 ins
[0].cond
= INST_CONDITION_NZ
;
1449 ins
[0].dst
= etna_native_to_dst(temp
, INST_COMPS_X
| INST_COMPS_Y
|
1450 INST_COMPS_Z
| INST_COMPS_W
);
1451 ins
[0].src
[0] = src
[0];
1453 ins
[1].opcode
= INST_OPCODE_SELECT
;
1454 ins
[1].cond
= INST_CONDITION_LZ
;
1455 ins
[1].sat
= inst
->Instruction
.Saturate
;
1456 ins
[1].dst
= convert_dst(c
, &inst
->Dst
[0]);
1457 ins
[1].src
[0] = src
[0];
1458 ins
[1].src
[2] = etna_native_to_src(temp
, INST_SWIZ_IDENTITY
);
1459 ins
[1].src
[1] = negate(ins
[1].src
[2]);
1461 emit_inst(c
, &ins
[0]);
1462 emit_inst(c
, &ins
[1]);
1467 trans_trig(const struct instr_translater
*t
, struct etna_compile
*c
,
1468 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1470 if (c
->specs
->has_new_transcendentals
) { /* Alternative SIN/COS */
1471 /* On newer chips alternative SIN/COS instructions are implemented,
1473 * - Need their input scaled by 1/pi instead of 2/pi
1474 * - Output an x and y component, which need to be multiplied to
1477 /* TGSI lowering should deal with SCS */
1478 assert(inst
->Instruction
.Opcode
!= TGSI_OPCODE_SCS
);
1480 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
); /* only using .xyz */
1481 emit_inst(c
, &(struct etna_inst
) {
1482 .opcode
= INST_OPCODE_MUL
,
1484 .dst
= etna_native_to_dst(temp
, INST_COMPS_Z
),
1485 .src
[0] = src
[0], /* any swizzling happens here */
1486 .src
[1] = alloc_imm_f32(c
, 1.0f
/ M_PI
),
1488 emit_inst(c
, &(struct etna_inst
) {
1489 .opcode
= inst
->Instruction
.Opcode
== TGSI_OPCODE_COS
1493 .dst
= etna_native_to_dst(temp
, INST_COMPS_X
| INST_COMPS_Y
),
1494 .src
[2] = etna_native_to_src(temp
, SWIZZLE(Z
, Z
, Z
, Z
)),
1495 .tex
= { .amode
=1 }, /* Unknown bit needs to be set */
1497 emit_inst(c
, &(struct etna_inst
) {
1498 .opcode
= INST_OPCODE_MUL
,
1499 .sat
= inst
->Instruction
.Saturate
,
1500 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1501 .src
[0] = etna_native_to_src(temp
, SWIZZLE(X
, X
, X
, X
)),
1502 .src
[1] = etna_native_to_src(temp
, SWIZZLE(Y
, Y
, Y
, Y
)),
1505 } else if (c
->specs
->has_sin_cos_sqrt
) {
1506 /* TGSI lowering should deal with SCS */
1507 assert(inst
->Instruction
.Opcode
!= TGSI_OPCODE_SCS
);
1509 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
);
1510 /* add divide by PI/2, using a temp register. GC2000
1511 * fails with src==dst for the trig instruction. */
1512 emit_inst(c
, &(struct etna_inst
) {
1513 .opcode
= INST_OPCODE_MUL
,
1515 .dst
= etna_native_to_dst(temp
, INST_COMPS_X
| INST_COMPS_Y
|
1516 INST_COMPS_Z
| INST_COMPS_W
),
1517 .src
[0] = src
[0], /* any swizzling happens here */
1518 .src
[1] = alloc_imm_f32(c
, 2.0f
/ M_PI
),
1520 emit_inst(c
, &(struct etna_inst
) {
1521 .opcode
= inst
->Instruction
.Opcode
== TGSI_OPCODE_COS
1524 .sat
= inst
->Instruction
.Saturate
,
1525 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1526 .src
[2] = etna_native_to_src(temp
, INST_SWIZ_IDENTITY
),
1529 /* Implement Nick's fast sine/cosine. Taken from:
1530 * http://forum.devmaster.net/t/fast-and-accurate-sine-cosine/9648
1531 * A=(1/2*PI 0 1/2*PI 0) B=(0.75 0 0.5 0) C=(-4 4 X X)
1532 * MAD t.x_zw, src.xxxx, A, B
1533 * FRC t.x_z_, void, void, t.xwzw
1534 * MAD t.x_z_, t.xwzw, 2, -1
1535 * MUL t._y__, t.wzww, |t.wzww|, void (for sin/scs)
1536 * DP3 t.x_z_, t.zyww, C, void (for sin)
1537 * DP3 t.__z_, t.zyww, C, void (for scs)
1538 * MUL t._y__, t.wxww, |t.wxww|, void (for cos/scs)
1539 * DP3 t.x_z_, t.xyww, C, void (for cos)
1540 * DP3 t.x___, t.xyww, C, void (for scs)
1541 * MAD t._y_w, t,xxzz, |t.xxzz|, -t.xxzz
1542 * MAD dst, t.ywyw, .2225, t.xzxz
1544 * TODO: we don't set dst.zw correctly for SCS.
1546 struct etna_inst
*p
, ins
[9] = { };
1547 struct etna_native_reg t0
= etna_compile_get_inner_temp(c
);
1548 struct etna_inst_src t0s
= etna_native_to_src(t0
, INST_SWIZ_IDENTITY
);
1549 struct etna_inst_src sincos
[3], in
= src
[0];
1550 sincos
[0] = etna_imm_vec4f(c
, sincos_const
[0]);
1551 sincos
[1] = etna_imm_vec4f(c
, sincos_const
[1]);
1553 /* A uniform source will cause the inner temp limit to
1554 * be exceeded. Explicitly deal with that scenario.
1556 if (etna_rgroup_is_uniform(src
[0].rgroup
)) {
1557 struct etna_inst ins
= { };
1558 ins
.opcode
= INST_OPCODE_MOV
;
1559 ins
.dst
= etna_native_to_dst(t0
, INST_COMPS_X
);
1565 ins
[0].opcode
= INST_OPCODE_MAD
;
1566 ins
[0].dst
= etna_native_to_dst(t0
, INST_COMPS_X
| INST_COMPS_Z
| INST_COMPS_W
);
1567 ins
[0].src
[0] = swizzle(in
, SWIZZLE(X
, X
, X
, X
));
1568 ins
[0].src
[1] = swizzle(sincos
[1], SWIZZLE(X
, W
, X
, W
)); /* 1/2*PI */
1569 ins
[0].src
[2] = swizzle(sincos
[1], SWIZZLE(Y
, W
, Z
, W
)); /* 0.75, 0, 0.5, 0 */
1571 ins
[1].opcode
= INST_OPCODE_FRC
;
1572 ins
[1].dst
= etna_native_to_dst(t0
, INST_COMPS_X
| INST_COMPS_Z
);
1573 ins
[1].src
[2] = swizzle(t0s
, SWIZZLE(X
, W
, Z
, W
));
1575 ins
[2].opcode
= INST_OPCODE_MAD
;
1576 ins
[2].dst
= etna_native_to_dst(t0
, INST_COMPS_X
| INST_COMPS_Z
);
1577 ins
[2].src
[0] = swizzle(t0s
, SWIZZLE(X
, W
, Z
, W
));
1578 ins
[2].src
[1] = swizzle(sincos
[0], SWIZZLE(X
, X
, X
, X
)); /* 2 */
1579 ins
[2].src
[2] = swizzle(sincos
[0], SWIZZLE(Y
, Y
, Y
, Y
)); /* -1 */
1581 unsigned mul_swiz
, dp3_swiz
;
1582 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SIN
) {
1583 mul_swiz
= SWIZZLE(W
, Z
, W
, W
);
1584 dp3_swiz
= SWIZZLE(Z
, Y
, W
, W
);
1586 mul_swiz
= SWIZZLE(W
, X
, W
, W
);
1587 dp3_swiz
= SWIZZLE(X
, Y
, W
, W
);
1590 ins
[3].opcode
= INST_OPCODE_MUL
;
1591 ins
[3].dst
= etna_native_to_dst(t0
, INST_COMPS_Y
);
1592 ins
[3].src
[0] = swizzle(t0s
, mul_swiz
);
1593 ins
[3].src
[1] = absolute(ins
[3].src
[0]);
1595 ins
[4].opcode
= INST_OPCODE_DP3
;
1596 ins
[4].dst
= etna_native_to_dst(t0
, INST_COMPS_X
| INST_COMPS_Z
);
1597 ins
[4].src
[0] = swizzle(t0s
, dp3_swiz
);
1598 ins
[4].src
[1] = swizzle(sincos
[0], SWIZZLE(Z
, W
, W
, W
));
1600 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SCS
) {
1603 ins
[4].dst
.comps
= INST_COMPS_X
;
1604 ins
[6].dst
.comps
= INST_COMPS_Z
;
1605 ins
[5].src
[0] = swizzle(t0s
, SWIZZLE(W
, Z
, W
, W
));
1606 ins
[6].src
[0] = swizzle(t0s
, SWIZZLE(Z
, Y
, W
, W
));
1607 ins
[5].src
[1] = absolute(ins
[5].src
[0]);
1613 p
->opcode
= INST_OPCODE_MAD
;
1614 p
->dst
= etna_native_to_dst(t0
, INST_COMPS_Y
| INST_COMPS_W
);
1615 p
->src
[0] = swizzle(t0s
, SWIZZLE(X
, X
, Z
, Z
));
1616 p
->src
[1] = absolute(p
->src
[0]);
1617 p
->src
[2] = negate(p
->src
[0]);
1620 p
->opcode
= INST_OPCODE_MAD
;
1621 p
->sat
= inst
->Instruction
.Saturate
;
1622 p
->dst
= convert_dst(c
, &inst
->Dst
[0]),
1623 p
->src
[0] = swizzle(t0s
, SWIZZLE(Y
, W
, Y
, W
));
1624 p
->src
[1] = alloc_imm_f32(c
, 0.2225);
1625 p
->src
[2] = swizzle(t0s
, SWIZZLE(X
, Z
, X
, Z
));
1627 for (int i
= 0; &ins
[i
] <= p
; i
++)
1628 emit_inst(c
, &ins
[i
]);
1633 trans_lg2(const struct instr_translater
*t
, struct etna_compile
*c
,
1634 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1636 if (c
->specs
->has_new_transcendentals
) {
1637 /* On newer chips alternative LOG instruction is implemented,
1638 * which outputs an x and y component, which need to be multiplied to
1641 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
); /* only using .xy */
1642 emit_inst(c
, &(struct etna_inst
) {
1643 .opcode
= INST_OPCODE_LOG
,
1645 .dst
= etna_native_to_dst(temp
, INST_COMPS_X
| INST_COMPS_Y
),
1647 .tex
= { .amode
=1 }, /* Unknown bit needs to be set */
1649 emit_inst(c
, &(struct etna_inst
) {
1650 .opcode
= INST_OPCODE_MUL
,
1651 .sat
= inst
->Instruction
.Saturate
,
1652 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1653 .src
[0] = etna_native_to_src(temp
, SWIZZLE(X
, X
, X
, X
)),
1654 .src
[1] = etna_native_to_src(temp
, SWIZZLE(Y
, Y
, Y
, Y
)),
1657 emit_inst(c
, &(struct etna_inst
) {
1658 .opcode
= INST_OPCODE_LOG
,
1659 .sat
= inst
->Instruction
.Saturate
,
1660 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1667 trans_sampler(const struct instr_translater
*t
, struct etna_compile
*c
,
1668 const struct tgsi_full_instruction
*inst
,
1669 struct etna_inst_src
*src
)
1671 /* There is no native support for GL texture rectangle coordinates, so
1672 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0, 1]). */
1673 if (inst
->Texture
.Texture
== TGSI_TEXTURE_RECT
) {
1674 uint32_t unit
= inst
->Src
[1].Register
.Index
;
1675 struct etna_inst ins
[2] = { };
1676 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
);
1678 ins
[0].opcode
= INST_OPCODE_MUL
;
1679 ins
[0].dst
= etna_native_to_dst(temp
, INST_COMPS_X
);
1680 ins
[0].src
[0] = src
[0];
1681 ins
[0].src
[1] = alloc_imm(c
, ETNA_IMMEDIATE_TEXRECT_SCALE_X
, unit
);
1683 ins
[1].opcode
= INST_OPCODE_MUL
;
1684 ins
[1].dst
= etna_native_to_dst(temp
, INST_COMPS_Y
);
1685 ins
[1].src
[0] = src
[0];
1686 ins
[1].src
[1] = alloc_imm(c
, ETNA_IMMEDIATE_TEXRECT_SCALE_Y
, unit
);
1688 emit_inst(c
, &ins
[0]);
1689 emit_inst(c
, &ins
[1]);
1691 src
[0] = etna_native_to_src(temp
, INST_SWIZ_IDENTITY
); /* temp.xyzw */
1694 switch (inst
->Instruction
.Opcode
) {
1695 case TGSI_OPCODE_TEX
:
1696 emit_inst(c
, &(struct etna_inst
) {
1697 .opcode
= INST_OPCODE_TEXLD
,
1699 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1700 .tex
= convert_tex(c
, &inst
->Src
[1], &inst
->Texture
),
1705 case TGSI_OPCODE_TXB
:
1706 emit_inst(c
, &(struct etna_inst
) {
1707 .opcode
= INST_OPCODE_TEXLDB
,
1709 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1710 .tex
= convert_tex(c
, &inst
->Src
[1], &inst
->Texture
),
1715 case TGSI_OPCODE_TXL
:
1716 emit_inst(c
, &(struct etna_inst
) {
1717 .opcode
= INST_OPCODE_TEXLDL
,
1719 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1720 .tex
= convert_tex(c
, &inst
->Src
[1], &inst
->Texture
),
1725 case TGSI_OPCODE_TXP
: { /* divide src.xyz by src.w */
1726 struct etna_native_reg temp
= etna_compile_get_inner_temp(c
);
1728 emit_inst(c
, &(struct etna_inst
) {
1729 .opcode
= INST_OPCODE_RCP
,
1731 .dst
= etna_native_to_dst(temp
, INST_COMPS_W
), /* tmp.w */
1732 .src
[2] = swizzle(src
[0], SWIZZLE(W
, W
, W
, W
)),
1734 emit_inst(c
, &(struct etna_inst
) {
1735 .opcode
= INST_OPCODE_MUL
,
1737 .dst
= etna_native_to_dst(temp
, INST_COMPS_X
| INST_COMPS_Y
|
1738 INST_COMPS_Z
), /* tmp.xyz */
1739 .src
[0] = etna_native_to_src(temp
, SWIZZLE(W
, W
, W
, W
)),
1740 .src
[1] = src
[0], /* src.xyzw */
1742 emit_inst(c
, &(struct etna_inst
) {
1743 .opcode
= INST_OPCODE_TEXLD
,
1745 .dst
= convert_dst(c
, &inst
->Dst
[0]),
1746 .tex
= convert_tex(c
, &inst
->Src
[1], &inst
->Texture
),
1747 .src
[0] = etna_native_to_src(temp
, INST_SWIZ_IDENTITY
), /* tmp.xyzw */
1752 BUG("Unhandled instruction %s",
1753 tgsi_get_opcode_name(inst
->Instruction
.Opcode
));
1760 trans_dummy(const struct instr_translater
*t
, struct etna_compile
*c
,
1761 const struct tgsi_full_instruction
*inst
, struct etna_inst_src
*src
)
1766 static const struct instr_translater translaters
[TGSI_OPCODE_LAST
] = {
1767 #define INSTR(n, f, ...) \
1768 [TGSI_OPCODE_##n] = {.fxn = (f), .tgsi_opc = TGSI_OPCODE_##n, ##__VA_ARGS__}
1770 INSTR(MOV
, trans_instr
, .opc
= INST_OPCODE_MOV
, .src
= {2, -1, -1}),
1771 INSTR(RCP
, trans_instr
, .opc
= INST_OPCODE_RCP
, .src
= {2, -1, -1}),
1772 INSTR(RSQ
, trans_instr
, .opc
= INST_OPCODE_RSQ
, .src
= {2, -1, -1}),
1773 INSTR(MUL
, trans_instr
, .opc
= INST_OPCODE_MUL
, .src
= {0, 1, -1}),
1774 INSTR(ADD
, trans_instr
, .opc
= INST_OPCODE_ADD
, .src
= {0, 2, -1}),
1775 INSTR(DP3
, trans_instr
, .opc
= INST_OPCODE_DP3
, .src
= {0, 1, -1}),
1776 INSTR(DP4
, trans_instr
, .opc
= INST_OPCODE_DP4
, .src
= {0, 1, -1}),
1777 INSTR(DST
, trans_instr
, .opc
= INST_OPCODE_DST
, .src
= {0, 1, -1}),
1778 INSTR(MAD
, trans_instr
, .opc
= INST_OPCODE_MAD
, .src
= {0, 1, 2}),
1779 INSTR(EX2
, trans_instr
, .opc
= INST_OPCODE_EXP
, .src
= {2, -1, -1}),
1780 INSTR(LG2
, trans_lg2
),
1781 INSTR(SQRT
, trans_instr
, .opc
= INST_OPCODE_SQRT
, .src
= {2, -1, -1}),
1782 INSTR(FRC
, trans_instr
, .opc
= INST_OPCODE_FRC
, .src
= {2, -1, -1}),
1783 INSTR(CEIL
, trans_instr
, .opc
= INST_OPCODE_CEIL
, .src
= {2, -1, -1}),
1784 INSTR(FLR
, trans_instr
, .opc
= INST_OPCODE_FLOOR
, .src
= {2, -1, -1}),
1785 INSTR(CMP
, trans_instr
, .opc
= INST_OPCODE_SELECT
, .src
= {0, 1, 2}, .cond
= INST_CONDITION_LZ
),
1787 INSTR(KILL
, trans_instr
, .opc
= INST_OPCODE_TEXKILL
),
1788 INSTR(KILL_IF
, trans_instr
, .opc
= INST_OPCODE_TEXKILL
, .src
= {0, -1, -1}, .cond
= INST_CONDITION_LZ
),
1790 INSTR(DDX
, trans_deriv
, .opc
= INST_OPCODE_DSX
),
1791 INSTR(DDY
, trans_deriv
, .opc
= INST_OPCODE_DSY
),
1793 INSTR(IF
, trans_if
),
1794 INSTR(ELSE
, trans_else
),
1795 INSTR(ENDIF
, trans_endif
),
1797 INSTR(BGNLOOP
, trans_loop_bgn
),
1798 INSTR(ENDLOOP
, trans_loop_end
),
1799 INSTR(BRK
, trans_brk
),
1800 INSTR(CONT
, trans_cont
),
1802 INSTR(MIN
, trans_min_max
, .opc
= INST_OPCODE_SELECT
, .cond
= INST_CONDITION_GT
),
1803 INSTR(MAX
, trans_min_max
, .opc
= INST_OPCODE_SELECT
, .cond
= INST_CONDITION_LT
),
1805 INSTR(ARL
, trans_arl
),
1806 INSTR(LRP
, trans_lrp
),
1807 INSTR(LIT
, trans_lit
),
1808 INSTR(SSG
, trans_ssg
),
1810 INSTR(SIN
, trans_trig
),
1811 INSTR(COS
, trans_trig
),
1812 INSTR(SCS
, trans_trig
),
1814 INSTR(SLT
, trans_instr
, .opc
= INST_OPCODE_SET
, .src
= {0, 1, -1}, .cond
= INST_CONDITION_LT
),
1815 INSTR(SGE
, trans_instr
, .opc
= INST_OPCODE_SET
, .src
= {0, 1, -1}, .cond
= INST_CONDITION_GE
),
1816 INSTR(SEQ
, trans_instr
, .opc
= INST_OPCODE_SET
, .src
= {0, 1, -1}, .cond
= INST_CONDITION_EQ
),
1817 INSTR(SGT
, trans_instr
, .opc
= INST_OPCODE_SET
, .src
= {0, 1, -1}, .cond
= INST_CONDITION_GT
),
1818 INSTR(SLE
, trans_instr
, .opc
= INST_OPCODE_SET
, .src
= {0, 1, -1}, .cond
= INST_CONDITION_LE
),
1819 INSTR(SNE
, trans_instr
, .opc
= INST_OPCODE_SET
, .src
= {0, 1, -1}, .cond
= INST_CONDITION_NE
),
1821 INSTR(TEX
, trans_sampler
),
1822 INSTR(TXB
, trans_sampler
),
1823 INSTR(TXL
, trans_sampler
),
1824 INSTR(TXP
, trans_sampler
),
1826 INSTR(NOP
, trans_dummy
),
1827 INSTR(END
, trans_dummy
),
1830 /* Pass -- compile instructions */
1832 etna_compile_pass_generate_code(struct etna_compile
*c
)
1834 struct tgsi_parse_context ctx
= { };
1835 unsigned status
= tgsi_parse_init(&ctx
, c
->tokens
);
1836 assert(status
== TGSI_PARSE_OK
);
1839 while (!tgsi_parse_end_of_tokens(&ctx
)) {
1840 const struct tgsi_full_instruction
*inst
= 0;
1842 /* No inner temps used yet for this instruction, clear counter */
1845 tgsi_parse_token(&ctx
);
1847 switch (ctx
.FullToken
.Token
.Type
) {
1848 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1849 /* iterate over operands */
1850 inst
= &ctx
.FullToken
.FullInstruction
;
1851 if (c
->dead_inst
[inst_idx
]) { /* skip dead instructions */
1856 /* Lookup the TGSI information and generate the source arguments */
1857 struct etna_inst_src src
[ETNA_NUM_SRC
];
1858 memset(src
, 0, sizeof(src
));
1860 const struct tgsi_opcode_info
*tgsi
= tgsi_get_opcode_info(inst
->Instruction
.Opcode
);
1862 for (int i
= 0; i
< tgsi
->num_src
&& i
< ETNA_NUM_SRC
; i
++) {
1863 const struct tgsi_full_src_register
*reg
= &inst
->Src
[i
];
1864 const struct etna_native_reg
*n
= &etna_get_src_reg(c
, reg
->Register
)->native
;
1866 if (!n
->valid
|| n
->is_tex
)
1869 src
[i
] = etna_create_src(reg
, n
);
1872 const unsigned opc
= inst
->Instruction
.Opcode
;
1873 const struct instr_translater
*t
= &translaters
[opc
];
1876 t
->fxn(t
, c
, inst
, src
);
1880 BUG("Unhandled instruction %s", tgsi_get_opcode_name(opc
));
1886 tgsi_parse_free(&ctx
);
1889 /* Look up register by semantic */
1890 static struct etna_reg_desc
*
1891 find_decl_by_semantic(struct etna_compile
*c
, uint file
, uint name
, uint index
)
1893 for (int idx
= 0; idx
< c
->file
[file
].reg_size
; ++idx
) {
1894 struct etna_reg_desc
*reg
= &c
->file
[file
].reg
[idx
];
1896 if (reg
->semantic
.Name
== name
&& reg
->semantic
.Index
== index
)
1900 return NULL
; /* not found */
1903 /** Add ADD and MUL instruction to bring Z/W to 0..1 if -1..1 if needed:
1904 * - this is a vertex shader
1905 * - and this is an older GPU
1908 etna_compile_add_z_div_if_needed(struct etna_compile
*c
)
1910 if (c
->info
.processor
== PIPE_SHADER_VERTEX
&& c
->specs
->vs_need_z_div
) {
1911 /* find position out */
1912 struct etna_reg_desc
*pos_reg
=
1913 find_decl_by_semantic(c
, TGSI_FILE_OUTPUT
, TGSI_SEMANTIC_POSITION
, 0);
1915 if (pos_reg
!= NULL
) {
1917 * ADD tX.__z_, tX.zzzz, void, tX.wwww
1918 * MUL tX.__z_, tX.zzzz, 0.5, void
1920 emit_inst(c
, &(struct etna_inst
) {
1921 .opcode
= INST_OPCODE_ADD
,
1922 .dst
= etna_native_to_dst(pos_reg
->native
, INST_COMPS_Z
),
1923 .src
[0] = etna_native_to_src(pos_reg
->native
, SWIZZLE(Z
, Z
, Z
, Z
)),
1924 .src
[2] = etna_native_to_src(pos_reg
->native
, SWIZZLE(W
, W
, W
, W
)),
1926 emit_inst(c
, &(struct etna_inst
) {
1927 .opcode
= INST_OPCODE_MUL
,
1928 .dst
= etna_native_to_dst(pos_reg
->native
, INST_COMPS_Z
),
1929 .src
[0] = etna_native_to_src(pos_reg
->native
, SWIZZLE(Z
, Z
, Z
, Z
)),
1930 .src
[1] = alloc_imm_f32(c
, 0.5f
),
1937 etna_compile_frag_rb_swap(struct etna_compile
*c
)
1939 if (c
->info
.processor
== PIPE_SHADER_FRAGMENT
&& c
->key
->frag_rb_swap
) {
1940 /* find color out */
1941 struct etna_reg_desc
*color_reg
=
1942 find_decl_by_semantic(c
, TGSI_FILE_OUTPUT
, TGSI_SEMANTIC_COLOR
, 0);
1944 emit_inst(c
, &(struct etna_inst
) {
1945 .opcode
= INST_OPCODE_MOV
,
1946 .dst
= etna_native_to_dst(color_reg
->native
, INST_COMPS_X
| INST_COMPS_Y
| INST_COMPS_Z
| INST_COMPS_W
),
1947 .src
[2] = etna_native_to_src(color_reg
->native
, SWIZZLE(Z
, Y
, X
, W
)),
1952 /** add a NOP to the shader if
1953 * a) the shader is empty
1955 * b) there is a label at the end of the shader
1958 etna_compile_add_nop_if_needed(struct etna_compile
*c
)
1960 bool label_at_last_inst
= false;
1962 for (int idx
= 0; idx
< c
->labels_count
; ++idx
) {
1963 if (c
->labels
[idx
].inst_idx
== c
->inst_ptr
)
1964 label_at_last_inst
= true;
1968 if (c
->inst_ptr
== 0 || label_at_last_inst
)
1969 emit_inst(c
, &(struct etna_inst
){.opcode
= INST_OPCODE_NOP
});
1973 assign_uniforms(struct etna_compile_file
*file
, unsigned base
)
1975 for (int idx
= 0; idx
< file
->reg_size
; ++idx
) {
1976 file
->reg
[idx
].native
.valid
= 1;
1977 file
->reg
[idx
].native
.rgroup
= INST_RGROUP_UNIFORM_0
;
1978 file
->reg
[idx
].native
.id
= base
+ idx
;
1982 /* Allocate CONST and IMM to native ETNA_RGROUP_UNIFORM(x).
1983 * CONST must be consecutive as const buffers are supposed to be consecutive,
1984 * and before IMM, as this is
1985 * more convenient because is possible for the compilation process itself to
1987 * immediates for constants such as pi, one, zero.
1990 assign_constants_and_immediates(struct etna_compile
*c
)
1992 assign_uniforms(&c
->file
[TGSI_FILE_CONSTANT
], 0);
1993 /* immediates start after the constants */
1994 c
->imm_base
= c
->file
[TGSI_FILE_CONSTANT
].reg_size
* 4;
1995 assign_uniforms(&c
->file
[TGSI_FILE_IMMEDIATE
], c
->imm_base
/ 4);
1996 DBG_F(ETNA_DBG_COMPILER_MSGS
, "imm base: %i size: %i", c
->imm_base
,
2000 /* Assign declared samplers to native texture units */
2002 assign_texture_units(struct etna_compile
*c
)
2006 if (c
->info
.processor
== PIPE_SHADER_VERTEX
)
2007 tex_base
= c
->specs
->vertex_sampler_offset
;
2009 for (int idx
= 0; idx
< c
->file
[TGSI_FILE_SAMPLER
].reg_size
; ++idx
) {
2010 c
->file
[TGSI_FILE_SAMPLER
].reg
[idx
].native
.valid
= 1;
2011 c
->file
[TGSI_FILE_SAMPLER
].reg
[idx
].native
.is_tex
= 1; // overrides rgroup
2012 c
->file
[TGSI_FILE_SAMPLER
].reg
[idx
].native
.id
= tex_base
+ idx
;
2016 /* Additional pass to fill in branch targets. This pass should be last
2017 * as no instruction reordering or removing/addition can be done anymore
2018 * once the branch targets are computed.
2021 etna_compile_fill_in_labels(struct etna_compile
*c
)
2023 for (int idx
= 0; idx
< c
->inst_ptr
; ++idx
) {
2024 if (c
->lbl_usage
[idx
] != -1)
2025 etna_assemble_set_imm(&c
->code
[idx
* 4],
2026 c
->labels
[c
->lbl_usage
[idx
]].inst_idx
);
2030 /* compare two etna_native_reg structures, return true if equal */
2032 cmp_etna_native_reg(const struct etna_native_reg to
,
2033 const struct etna_native_reg from
)
2035 return to
.valid
== from
.valid
&& to
.is_tex
== from
.is_tex
&&
2036 to
.rgroup
== from
.rgroup
&& to
.id
== from
.id
;
2039 /* go through all declarations and swap native registers *to* and *from* */
2041 swap_native_registers(struct etna_compile
*c
, const struct etna_native_reg to
,
2042 const struct etna_native_reg from
)
2044 if (cmp_etna_native_reg(from
, to
))
2045 return; /* Nothing to do */
2047 for (int idx
= 0; idx
< c
->total_decls
; ++idx
) {
2048 if (cmp_etna_native_reg(c
->decl
[idx
].native
, from
)) {
2049 c
->decl
[idx
].native
= to
;
2050 } else if (cmp_etna_native_reg(c
->decl
[idx
].native
, to
)) {
2051 c
->decl
[idx
].native
= from
;
2056 /* For PS we need to permute so that inputs are always in temporary 0..N-1.
2057 * Semantic POS is always t0. If that semantic is not used, avoid t0.
2060 permute_ps_inputs(struct etna_compile
*c
)
2063 * gl_FragCoord VARYING_SLOT_POS TGSI_SEMANTIC_POSITION
2064 * gl_PointCoord VARYING_SLOT_PNTC TGSI_SEMANTIC_PCOORD
2066 uint native_idx
= 1;
2068 for (int idx
= 0; idx
< c
->file
[TGSI_FILE_INPUT
].reg_size
; ++idx
) {
2069 struct etna_reg_desc
*reg
= &c
->file
[TGSI_FILE_INPUT
].reg
[idx
];
2071 assert(reg
->has_semantic
);
2073 if (!reg
->active
|| reg
->semantic
.Name
== TGSI_SEMANTIC_POSITION
)
2076 input_id
= native_idx
++;
2077 swap_native_registers(c
, etna_native_temp(input_id
),
2078 c
->file
[TGSI_FILE_INPUT
].reg
[idx
].native
);
2081 c
->num_varyings
= native_idx
- 1;
2083 if (native_idx
> c
->next_free_native
)
2084 c
->next_free_native
= native_idx
;
2087 /* fill in ps inputs into shader object */
2089 fill_in_ps_inputs(struct etna_shader_variant
*sobj
, struct etna_compile
*c
)
2091 struct etna_shader_io_file
*sf
= &sobj
->infile
;
2095 for (int idx
= 0; idx
< c
->file
[TGSI_FILE_INPUT
].reg_size
; ++idx
) {
2096 struct etna_reg_desc
*reg
= &c
->file
[TGSI_FILE_INPUT
].reg
[idx
];
2098 if (reg
->native
.id
> 0) {
2099 assert(sf
->num_reg
< ETNA_NUM_INPUTS
);
2100 sf
->reg
[sf
->num_reg
].reg
= reg
->native
.id
;
2101 sf
->reg
[sf
->num_reg
].semantic
= reg
->semantic
;
2102 /* convert usage mask to number of components (*=wildcard)
2103 * .r (0..1) -> 1 component
2104 * .*g (2..3) -> 2 component
2105 * .**b (4..7) -> 3 components
2106 * .***a (8..15) -> 4 components
2108 sf
->reg
[sf
->num_reg
].num_components
= util_last_bit(reg
->usage_mask
);
2113 assert(sf
->num_reg
== c
->num_varyings
);
2114 sobj
->input_count_unk8
= 31; /* XXX what is this */
2117 /* fill in output mapping for ps into shader object */
2119 fill_in_ps_outputs(struct etna_shader_variant
*sobj
, struct etna_compile
*c
)
2121 sobj
->outfile
.num_reg
= 0;
2123 for (int idx
= 0; idx
< c
->file
[TGSI_FILE_OUTPUT
].reg_size
; ++idx
) {
2124 struct etna_reg_desc
*reg
= &c
->file
[TGSI_FILE_OUTPUT
].reg
[idx
];
2126 switch (reg
->semantic
.Name
) {
2127 case TGSI_SEMANTIC_COLOR
: /* FRAG_RESULT_COLOR */
2128 sobj
->ps_color_out_reg
= reg
->native
.id
;
2130 case TGSI_SEMANTIC_POSITION
: /* FRAG_RESULT_DEPTH */
2131 sobj
->ps_depth_out_reg
= reg
->native
.id
; /* =always native reg 0, only z component should be assigned */
2134 assert(0); /* only outputs supported are COLOR and POSITION at the moment */
2139 /* fill in inputs for vs into shader object */
2141 fill_in_vs_inputs(struct etna_shader_variant
*sobj
, struct etna_compile
*c
)
2143 struct etna_shader_io_file
*sf
= &sobj
->infile
;
2146 for (int idx
= 0; idx
< c
->file
[TGSI_FILE_INPUT
].reg_size
; ++idx
) {
2147 struct etna_reg_desc
*reg
= &c
->file
[TGSI_FILE_INPUT
].reg
[idx
];
2148 assert(sf
->num_reg
< ETNA_NUM_INPUTS
);
2149 /* XXX exclude inputs with special semantics such as gl_frontFacing */
2150 sf
->reg
[sf
->num_reg
].reg
= reg
->native
.id
;
2151 sf
->reg
[sf
->num_reg
].semantic
= reg
->semantic
;
2152 sf
->reg
[sf
->num_reg
].num_components
= util_last_bit(reg
->usage_mask
);
2156 sobj
->input_count_unk8
= (sf
->num_reg
+ 19) / 16; /* XXX what is this */
2159 /* build two-level output index [Semantic][Index] for fast linking */
2161 build_output_index(struct etna_shader_variant
*sobj
)
2166 for (int name
= 0; name
< TGSI_SEMANTIC_COUNT
; ++name
)
2167 total
+= sobj
->output_count_per_semantic
[name
];
2169 sobj
->output_per_semantic_list
= CALLOC(total
, sizeof(struct etna_shader_inout
*));
2171 for (int name
= 0; name
< TGSI_SEMANTIC_COUNT
; ++name
) {
2172 sobj
->output_per_semantic
[name
] = &sobj
->output_per_semantic_list
[offset
];
2173 offset
+= sobj
->output_count_per_semantic
[name
];
2176 for (int idx
= 0; idx
< sobj
->outfile
.num_reg
; ++idx
) {
2177 sobj
->output_per_semantic
[sobj
->outfile
.reg
[idx
].semantic
.Name
]
2178 [sobj
->outfile
.reg
[idx
].semantic
.Index
] =
2179 &sobj
->outfile
.reg
[idx
];
2183 /* fill in outputs for vs into shader object */
2185 fill_in_vs_outputs(struct etna_shader_variant
*sobj
, struct etna_compile
*c
)
2187 struct etna_shader_io_file
*sf
= &sobj
->outfile
;
2190 for (int idx
= 0; idx
< c
->file
[TGSI_FILE_OUTPUT
].reg_size
; ++idx
) {
2191 struct etna_reg_desc
*reg
= &c
->file
[TGSI_FILE_OUTPUT
].reg
[idx
];
2192 assert(sf
->num_reg
< ETNA_NUM_INPUTS
);
2194 switch (reg
->semantic
.Name
) {
2195 case TGSI_SEMANTIC_POSITION
:
2196 sobj
->vs_pos_out_reg
= reg
->native
.id
;
2198 case TGSI_SEMANTIC_PSIZE
:
2199 sobj
->vs_pointsize_out_reg
= reg
->native
.id
;
2202 sf
->reg
[sf
->num_reg
].reg
= reg
->native
.id
;
2203 sf
->reg
[sf
->num_reg
].semantic
= reg
->semantic
;
2204 sf
->reg
[sf
->num_reg
].num_components
= 4; // XXX reg->num_components;
2206 sobj
->output_count_per_semantic
[reg
->semantic
.Name
] =
2207 MAX2(reg
->semantic
.Index
+ 1,
2208 sobj
->output_count_per_semantic
[reg
->semantic
.Name
]);
2212 /* build two-level index for linking */
2213 build_output_index(sobj
);
2215 /* fill in "mystery meat" load balancing value. This value determines how
2216 * work is scheduled between VS and PS
2217 * in the unified shader architecture. More precisely, it is determined from
2218 * the number of VS outputs, as well as chip-specific
2219 * vertex output buffer size, vertex cache size, and the number of shader
2222 * XXX this is a conservative estimate, the "optimal" value is only known for
2223 * sure at link time because some
2224 * outputs may be unused and thus unmapped. Then again, in the general use
2225 * case with GLSL the vertex and fragment
2226 * shaders are linked already before submitting to Gallium, thus all outputs
2229 int half_out
= (c
->file
[TGSI_FILE_OUTPUT
].reg_size
+ 1) / 2;
2232 uint32_t b
= ((20480 / (c
->specs
->vertex_output_buffer_size
-
2233 2 * half_out
* c
->specs
->vertex_cache_size
)) +
2236 uint32_t a
= (b
+ 256 / (c
->specs
->shader_core_count
* half_out
)) / 2;
2237 sobj
->vs_load_balancing
= VIVS_VS_LOAD_BALANCING_A(MIN2(a
, 255)) |
2238 VIVS_VS_LOAD_BALANCING_B(MIN2(b
, 255)) |
2239 VIVS_VS_LOAD_BALANCING_C(0x3f) |
2240 VIVS_VS_LOAD_BALANCING_D(0x0f);
2244 etna_compile_check_limits(struct etna_compile
*c
)
2246 int max_uniforms
= (c
->info
.processor
== PIPE_SHADER_VERTEX
)
2247 ? c
->specs
->max_vs_uniforms
2248 : c
->specs
->max_ps_uniforms
;
2249 /* round up number of uniforms, including immediates, in units of four */
2250 int num_uniforms
= c
->imm_base
/ 4 + (c
->imm_size
+ 3) / 4;
2252 if (!c
->specs
->has_icache
&& c
->inst_ptr
> c
->specs
->max_instructions
) {
2253 DBG("Number of instructions (%d) exceeds maximum %d", c
->inst_ptr
,
2254 c
->specs
->max_instructions
);
2258 if (c
->next_free_native
> c
->specs
->max_registers
) {
2259 DBG("Number of registers (%d) exceeds maximum %d", c
->next_free_native
,
2260 c
->specs
->max_registers
);
2264 if (num_uniforms
> max_uniforms
) {
2265 DBG("Number of uniforms (%d) exceeds maximum %d", num_uniforms
,
2270 if (c
->num_varyings
> c
->specs
->max_varyings
) {
2271 DBG("Number of varyings (%d) exceeds maximum %d", c
->num_varyings
,
2272 c
->specs
->max_varyings
);
2276 if (c
->imm_base
> c
->specs
->num_constants
) {
2277 DBG("Number of constants (%d) exceeds maximum %d", c
->imm_base
,
2278 c
->specs
->num_constants
);
2285 copy_uniform_state_to_shader(struct etna_compile
*c
, struct etna_shader_variant
*sobj
)
2287 uint32_t count
= c
->imm_size
;
2288 struct etna_shader_uniform_info
*uinfo
= &sobj
->uniforms
;
2290 uinfo
->const_count
= c
->imm_base
;
2291 uinfo
->imm_count
= count
;
2292 uinfo
->imm_data
= mem_dup(c
->imm_data
, count
* sizeof(*c
->imm_data
));
2293 uinfo
->imm_contents
= mem_dup(c
->imm_contents
, count
* sizeof(*c
->imm_contents
));
2295 etna_set_shader_uniforms_dirty_flags(sobj
);
2299 etna_compile_shader(struct etna_shader_variant
*v
)
2301 /* Create scratch space that may be too large to fit on stack
2304 struct etna_compile
*c
;
2309 const struct etna_specs
*specs
= v
->shader
->specs
;
2311 struct tgsi_lowering_config lconfig
= {
2312 .lower_SCS
= specs
->has_sin_cos_sqrt
,
2313 .lower_FLR
= !specs
->has_sign_floor_ceil
,
2314 .lower_CEIL
= !specs
->has_sign_floor_ceil
,
2319 .lower_TRUNC
= true,
2323 c
= CALLOC_STRUCT(etna_compile
);
2327 memset(&c
->lbl_usage
, -1, sizeof(c
->lbl_usage
));
2329 const struct tgsi_token
*tokens
= v
->shader
->tokens
;
2333 c
->tokens
= tgsi_transform_lowering(&lconfig
, tokens
, &c
->info
);
2334 c
->free_tokens
= !!c
->tokens
;
2340 /* Build a map from gallium register to native registers for files
2341 * CONST, SAMP, IMM, OUT, IN, TEMP.
2342 * SAMP will map as-is for fragment shaders, there will be a +8 offset for
2345 /* Pass one -- check register file declarations and immediates */
2346 etna_compile_parse_declarations(c
);
2348 etna_allocate_decls(c
);
2350 /* Pass two -- check usage of temporaries, inputs, outputs */
2351 etna_compile_pass_check_usage(c
);
2353 assign_special_inputs(c
);
2355 /* Assign native temp register to TEMPs */
2356 assign_temporaries_to_native(c
, &c
->file
[TGSI_FILE_TEMPORARY
]);
2358 /* optimize outputs */
2359 etna_compile_pass_optimize_outputs(c
);
2361 /* XXX assign special inputs: gl_FrontFacing (VARYING_SLOT_FACE)
2362 * this is part of RGROUP_INTERNAL
2365 /* assign inputs: last usage of input should be <= first usage of temp */
2366 /* potential optimization case:
2367 * if single MOV TEMP[y], IN[x] before which temp y is not used, and
2369 * is not read, temp[y] can be used as input register as-is
2371 /* sort temporaries by first use
2372 * sort inputs by last usage
2373 * iterate over inputs, temporaries
2374 * if last usage of input <= first usage of temp:
2375 * assign input to temp
2376 * advance input, temporary pointer
2378 * advance temporary pointer
2380 * potential problem: instruction with multiple inputs of which one is the
2381 * temp and the other is the input;
2382 * however, as the temp is not used before this, how would this make
2383 * sense? uninitialized temporaries have an undefined
2384 * value, so this would be ok
2386 assign_inouts_to_temporaries(c
, TGSI_FILE_INPUT
);
2388 /* assign outputs: first usage of output should be >= last usage of temp */
2389 /* potential optimization case:
2390 * if single MOV OUT[x], TEMP[y] (with full write mask, or at least
2391 * writing all components that are used in
2392 * the shader) after which temp y is no longer used temp[y] can be
2393 * used as output register as-is
2395 * potential problem: instruction with multiple outputs of which one is the
2396 * temp and the other is the output;
2397 * however, as the temp is not used after this, how would this make
2398 * sense? could just discard the output value
2400 /* sort temporaries by last use
2401 * sort outputs by first usage
2402 * iterate over outputs, temporaries
2403 * if first usage of output >= last usage of temp:
2404 * assign output to temp
2405 * advance output, temporary pointer
2407 * advance temporary pointer
2409 assign_inouts_to_temporaries(c
, TGSI_FILE_OUTPUT
);
2411 assign_constants_and_immediates(c
);
2412 assign_texture_units(c
);
2414 /* list declarations */
2415 for (int x
= 0; x
< c
->total_decls
; ++x
) {
2416 DBG_F(ETNA_DBG_COMPILER_MSGS
, "%i: %s,%d active=%i first_use=%i "
2417 "last_use=%i native=%i usage_mask=%x "
2419 x
, tgsi_file_name(c
->decl
[x
].file
), c
->decl
[x
].idx
,
2420 c
->decl
[x
].active
, c
->decl
[x
].first_use
, c
->decl
[x
].last_use
,
2421 c
->decl
[x
].native
.valid
? c
->decl
[x
].native
.id
: -1,
2422 c
->decl
[x
].usage_mask
, c
->decl
[x
].has_semantic
);
2423 if (c
->decl
[x
].has_semantic
)
2424 DBG_F(ETNA_DBG_COMPILER_MSGS
, " semantic_name=%s semantic_idx=%i",
2425 tgsi_semantic_names
[c
->decl
[x
].semantic
.Name
],
2426 c
->decl
[x
].semantic
.Index
);
2428 /* XXX for PS we need to permute so that inputs are always in temporary
2430 * There is no "switchboard" for varyings (AFAIK!). The output color,
2431 * however, can be routed
2432 * from an arbitrary temporary.
2434 if (c
->info
.processor
== PIPE_SHADER_FRAGMENT
)
2435 permute_ps_inputs(c
);
2438 /* list declarations */
2439 for (int x
= 0; x
< c
->total_decls
; ++x
) {
2440 DBG_F(ETNA_DBG_COMPILER_MSGS
, "%i: %s,%d active=%i first_use=%i "
2441 "last_use=%i native=%i usage_mask=%x "
2443 x
, tgsi_file_name(c
->decl
[x
].file
), c
->decl
[x
].idx
,
2444 c
->decl
[x
].active
, c
->decl
[x
].first_use
, c
->decl
[x
].last_use
,
2445 c
->decl
[x
].native
.valid
? c
->decl
[x
].native
.id
: -1,
2446 c
->decl
[x
].usage_mask
, c
->decl
[x
].has_semantic
);
2447 if (c
->decl
[x
].has_semantic
)
2448 DBG_F(ETNA_DBG_COMPILER_MSGS
, " semantic_name=%s semantic_idx=%i",
2449 tgsi_semantic_names
[c
->decl
[x
].semantic
.Name
],
2450 c
->decl
[x
].semantic
.Index
);
2453 /* pass 3: generate instructions */
2454 etna_compile_pass_generate_code(c
);
2455 etna_compile_add_z_div_if_needed(c
);
2456 etna_compile_frag_rb_swap(c
);
2457 etna_compile_add_nop_if_needed(c
);
2459 ret
= etna_compile_check_limits(c
);
2463 etna_compile_fill_in_labels(c
);
2465 /* fill in output structure */
2466 v
->processor
= c
->info
.processor
;
2467 v
->code_size
= c
->inst_ptr
* 4;
2468 v
->code
= mem_dup(c
->code
, c
->inst_ptr
* 16);
2469 v
->num_loops
= c
->num_loops
;
2470 v
->num_temps
= c
->next_free_native
;
2471 v
->vs_pos_out_reg
= -1;
2472 v
->vs_pointsize_out_reg
= -1;
2473 v
->ps_color_out_reg
= -1;
2474 v
->ps_depth_out_reg
= -1;
2475 v
->needs_icache
= c
->inst_ptr
> c
->specs
->max_instructions
;
2476 copy_uniform_state_to_shader(c
, v
);
2478 if (c
->info
.processor
== PIPE_SHADER_VERTEX
) {
2479 fill_in_vs_inputs(v
, c
);
2480 fill_in_vs_outputs(v
, c
);
2481 } else if (c
->info
.processor
== PIPE_SHADER_FRAGMENT
) {
2482 fill_in_ps_inputs(v
, c
);
2483 fill_in_ps_outputs(v
, c
);
2488 FREE((void *)c
->tokens
);
2496 extern const char *tgsi_swizzle_names
[];
2498 etna_dump_shader(const struct etna_shader_variant
*shader
)
2500 if (shader
->processor
== PIPE_SHADER_VERTEX
)
2506 etna_disasm(shader
->code
, shader
->code_size
, PRINT_RAW
);
2508 printf("num loops: %i\n", shader
->num_loops
);
2509 printf("num temps: %i\n", shader
->num_temps
);
2510 printf("num const: %i\n", shader
->uniforms
.const_count
);
2511 printf("immediates:\n");
2512 for (int idx
= 0; idx
< shader
->uniforms
.imm_count
; ++idx
) {
2513 printf(" [%i].%s = %f (0x%08x)\n",
2514 (idx
+ shader
->uniforms
.const_count
) / 4,
2515 tgsi_swizzle_names
[idx
% 4],
2516 *((float *)&shader
->uniforms
.imm_data
[idx
]),
2517 shader
->uniforms
.imm_data
[idx
]);
2519 printf("inputs:\n");
2520 for (int idx
= 0; idx
< shader
->infile
.num_reg
; ++idx
) {
2521 printf(" [%i] name=%s index=%i comps=%i\n", shader
->infile
.reg
[idx
].reg
,
2522 tgsi_semantic_names
[shader
->infile
.reg
[idx
].semantic
.Name
],
2523 shader
->infile
.reg
[idx
].semantic
.Index
,
2524 shader
->infile
.reg
[idx
].num_components
);
2526 printf("outputs:\n");
2527 for (int idx
= 0; idx
< shader
->outfile
.num_reg
; ++idx
) {
2528 printf(" [%i] name=%s index=%i comps=%i\n", shader
->outfile
.reg
[idx
].reg
,
2529 tgsi_semantic_names
[shader
->outfile
.reg
[idx
].semantic
.Name
],
2530 shader
->outfile
.reg
[idx
].semantic
.Index
,
2531 shader
->outfile
.reg
[idx
].num_components
);
2533 printf("special:\n");
2534 if (shader
->processor
== PIPE_SHADER_VERTEX
) {
2535 printf(" vs_pos_out_reg=%i\n", shader
->vs_pos_out_reg
);
2536 printf(" vs_pointsize_out_reg=%i\n", shader
->vs_pointsize_out_reg
);
2537 printf(" vs_load_balancing=0x%08x\n", shader
->vs_load_balancing
);
2539 printf(" ps_color_out_reg=%i\n", shader
->ps_color_out_reg
);
2540 printf(" ps_depth_out_reg=%i\n", shader
->ps_depth_out_reg
);
2542 printf(" input_count_unk8=0x%08x\n", shader
->input_count_unk8
);
2546 etna_destroy_shader(struct etna_shader_variant
*shader
)
2551 FREE(shader
->uniforms
.imm_data
);
2552 FREE(shader
->uniforms
.imm_contents
);
2553 FREE(shader
->output_per_semantic_list
);
2557 static const struct etna_shader_inout
*
2558 etna_shader_vs_lookup(const struct etna_shader_variant
*sobj
,
2559 const struct etna_shader_inout
*in
)
2561 if (in
->semantic
.Index
< sobj
->output_count_per_semantic
[in
->semantic
.Name
])
2562 return sobj
->output_per_semantic
[in
->semantic
.Name
][in
->semantic
.Index
];
2568 etna_link_shader(struct etna_shader_link_info
*info
,
2569 const struct etna_shader_variant
*vs
, const struct etna_shader_variant
*fs
)
2571 /* For each fragment input we need to find the associated vertex shader
2572 * output, which can be found by matching on semantic name and index. A
2573 * binary search could be used because the vs outputs are sorted by their
2574 * semantic index and grouped by semantic type by fill_in_vs_outputs.
2576 assert(fs
->infile
.num_reg
< ETNA_NUM_INPUTS
);
2578 for (int idx
= 0; idx
< fs
->infile
.num_reg
; ++idx
) {
2579 const struct etna_shader_inout
*fsio
= &fs
->infile
.reg
[idx
];
2580 const struct etna_shader_inout
*vsio
= etna_shader_vs_lookup(vs
, fsio
);
2581 struct etna_varying
*varying
;
2583 assert(fsio
->reg
> 0 && fsio
->reg
<= ARRAY_SIZE(info
->varyings
));
2585 if (fsio
->reg
> info
->num_varyings
)
2586 info
->num_varyings
= fsio
->reg
;
2588 varying
= &info
->varyings
[fsio
->reg
- 1];
2589 varying
->num_components
= fsio
->num_components
;
2591 if (fsio
->semantic
.Name
== TGSI_SEMANTIC_COLOR
) /* colors affected by flat shading */
2592 varying
->pa_attributes
= 0x200;
2593 else /* texture coord or other bypasses flat shading */
2594 varying
->pa_attributes
= 0x2f1;
2596 if (fsio
->semantic
.Name
== TGSI_SEMANTIC_PCOORD
) {
2597 varying
->use
[0] = VARYING_COMPONENT_USE_POINTCOORD_X
;
2598 varying
->use
[1] = VARYING_COMPONENT_USE_POINTCOORD_Y
;
2599 varying
->use
[2] = VARYING_COMPONENT_USE_USED
;
2600 varying
->use
[3] = VARYING_COMPONENT_USE_USED
;
2601 varying
->reg
= 0; /* replaced by point coord -- doesn't matter */
2606 return true; /* not found -- link error */
2608 varying
->use
[0] = VARYING_COMPONENT_USE_USED
;
2609 varying
->use
[1] = VARYING_COMPONENT_USE_USED
;
2610 varying
->use
[2] = VARYING_COMPONENT_USE_USED
;
2611 varying
->use
[3] = VARYING_COMPONENT_USE_USED
;
2612 varying
->reg
= vsio
->reg
;
2615 assert(info
->num_varyings
== fs
->infile
.num_reg
);