etnaviv: implement UBOs
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_context.c
1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
26 */
27
28 #include "etnaviv_context.h"
29
30 #include "etnaviv_blend.h"
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_debug.h"
34 #include "etnaviv_emit.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_query.h"
37 #include "etnaviv_query_hw.h"
38 #include "etnaviv_rasterizer.h"
39 #include "etnaviv_resource.h"
40 #include "etnaviv_screen.h"
41 #include "etnaviv_shader.h"
42 #include "etnaviv_state.h"
43 #include "etnaviv_surface.h"
44 #include "etnaviv_texture.h"
45 #include "etnaviv_transfer.h"
46 #include "etnaviv_translate.h"
47 #include "etnaviv_zsa.h"
48
49 #include "pipe/p_context.h"
50 #include "pipe/p_state.h"
51 #include "util/hash_table.h"
52 #include "util/u_blitter.h"
53 #include "util/u_helpers.h"
54 #include "util/u_memory.h"
55 #include "util/u_prim.h"
56 #include "util/u_upload_mgr.h"
57
58 #include "hw/common.xml.h"
59
60 static void
61 etna_context_destroy(struct pipe_context *pctx)
62 {
63 struct etna_context *ctx = etna_context(pctx);
64
65 mtx_lock(&ctx->lock);
66 if (ctx->used_resources_read) {
67
68 /*
69 * There should be no resources tracked in the context when it's being
70 * destroyed. Be sure there are none to avoid memory leaks on buggy
71 * programs.
72 */
73 set_foreach(ctx->used_resources_read, entry) {
74 struct etna_resource *rsc = (struct etna_resource *)entry->key;
75
76 _mesa_set_remove_key(rsc->pending_ctx, ctx);
77 }
78 _mesa_set_destroy(ctx->used_resources_read, NULL);
79
80 }
81 if (ctx->used_resources_write) {
82
83 /*
84 * There should be no resources tracked in the context when it's being
85 * destroyed. Be sure there are none to avoid memory leaks on buggy
86 * programs.
87 */
88 set_foreach(ctx->used_resources_write, entry) {
89 struct etna_resource *rsc = (struct etna_resource *)entry->key;
90
91 _mesa_set_remove_key(rsc->pending_ctx, ctx);
92 }
93 _mesa_set_destroy(ctx->used_resources_write, NULL);
94
95 }
96 mtx_unlock(&ctx->lock);
97
98 if (ctx->dummy_rt)
99 etna_bo_del(ctx->dummy_rt);
100
101 util_copy_framebuffer_state(&ctx->framebuffer_s, NULL);
102
103 if (ctx->primconvert)
104 util_primconvert_destroy(ctx->primconvert);
105
106 if (ctx->blitter)
107 util_blitter_destroy(ctx->blitter);
108
109 if (pctx->stream_uploader)
110 u_upload_destroy(pctx->stream_uploader);
111
112 if (ctx->stream)
113 etna_cmd_stream_del(ctx->stream);
114
115 slab_destroy_child(&ctx->transfer_pool);
116
117 if (ctx->in_fence_fd != -1)
118 close(ctx->in_fence_fd);
119
120 mtx_destroy(&ctx->lock);
121
122 FREE(pctx);
123 }
124
125 /* Update render state where needed based on draw operation */
126 static void
127 etna_update_state_for_draw(struct etna_context *ctx, const struct pipe_draw_info *info)
128 {
129 /* Handle primitive restart:
130 * - If not an indexed draw, we don't care about the state of the primitive restart bit.
131 * - Otherwise, set the bit in INDEX_STREAM_CONTROL in the index buffer state
132 * accordingly
133 * - If the value of the INDEX_STREAM_CONTROL register changed due to this, or
134 * primitive restart is enabled and the restart index changed, mark the index
135 * buffer state as dirty
136 */
137
138 if (info->index_size) {
139 uint32_t new_control = ctx->index_buffer.FE_INDEX_STREAM_CONTROL;
140
141 if (info->primitive_restart)
142 new_control |= VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART;
143 else
144 new_control &= ~VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART;
145
146 if (ctx->index_buffer.FE_INDEX_STREAM_CONTROL != new_control ||
147 (info->primitive_restart && ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX != info->restart_index)) {
148 ctx->index_buffer.FE_INDEX_STREAM_CONTROL = new_control;
149 ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX = info->restart_index;
150 ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER;
151 }
152 }
153 }
154
155 static bool
156 etna_get_vs(struct etna_context *ctx, struct etna_shader_key key)
157 {
158 const struct etna_shader_variant *old = ctx->shader.vs;
159
160 ctx->shader.vs = etna_shader_variant(ctx->shader.bind_vs, key, &ctx->debug);
161
162 if (!ctx->shader.vs)
163 return false;
164
165 if (old != ctx->shader.vs)
166 ctx->dirty |= ETNA_DIRTY_SHADER;
167
168 return true;
169 }
170
171 static bool
172 etna_get_fs(struct etna_context *ctx, struct etna_shader_key key)
173 {
174 const struct etna_shader_variant *old = ctx->shader.fs;
175
176 ctx->shader.fs = etna_shader_variant(ctx->shader.bind_fs, key, &ctx->debug);
177
178 if (!ctx->shader.fs)
179 return false;
180
181 if (old != ctx->shader.fs)
182 ctx->dirty |= ETNA_DIRTY_SHADER;
183
184 return true;
185 }
186
187 static void
188 etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
189 {
190 struct etna_context *ctx = etna_context(pctx);
191 struct pipe_framebuffer_state *pfb = &ctx->framebuffer_s;
192 uint32_t draw_mode;
193 unsigned i;
194
195 if (!info->count_from_stream_output && !info->indirect &&
196 !info->primitive_restart &&
197 !u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
198 return;
199
200 if (ctx->vertex_elements == NULL || ctx->vertex_elements->num_elements == 0)
201 return; /* Nothing to do */
202
203 if (!(ctx->prim_hwsupport & (1 << info->mode))) {
204 struct primconvert_context *primconvert = ctx->primconvert;
205 util_primconvert_save_rasterizer_state(primconvert, ctx->rasterizer);
206 util_primconvert_draw_vbo(primconvert, info);
207 return;
208 }
209
210 int prims = u_decomposed_prims_for_vertices(info->mode, info->count);
211 if (unlikely(prims <= 0)) {
212 DBG("Invalid draw primitive mode=%i or no primitives to be drawn", info->mode);
213 return;
214 }
215
216 draw_mode = translate_draw_mode(info->mode);
217 if (draw_mode == ETNA_NO_MATCH) {
218 BUG("Unsupported draw mode");
219 return;
220 }
221
222 /* Upload a user index buffer. */
223 unsigned index_offset = 0;
224 struct pipe_resource *indexbuf = NULL;
225
226 if (info->index_size) {
227 indexbuf = info->has_user_indices ? NULL : info->index.resource;
228 if (info->has_user_indices &&
229 !util_upload_index_buffer(pctx, info, &indexbuf, &index_offset, 4)) {
230 BUG("Index buffer upload failed.");
231 return;
232 }
233 /* Add start to index offset, when rendering indexed */
234 index_offset += info->start * info->index_size;
235
236 ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo = etna_resource(indexbuf)->bo;
237 ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.offset = index_offset;
238 ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
239 ctx->index_buffer.FE_INDEX_STREAM_CONTROL = translate_index_size(info->index_size);
240
241 if (!ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo) {
242 BUG("Unsupported or no index buffer");
243 return;
244 }
245 } else {
246 ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo = 0;
247 ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.offset = 0;
248 ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.flags = 0;
249 ctx->index_buffer.FE_INDEX_STREAM_CONTROL = 0;
250 }
251 ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER;
252
253 struct etna_shader_key key = {
254 .front_ccw = ctx->rasterizer->front_ccw,
255 };
256
257 if (pfb->cbufs[0])
258 key.frag_rb_swap = !!translate_pe_format_rb_swap(pfb->cbufs[0]->format);
259
260 if (!etna_get_vs(ctx, key) || !etna_get_fs(ctx, key)) {
261 BUG("compiled shaders are not okay");
262 return;
263 }
264
265 /* Update any derived state */
266 if (!etna_state_update(ctx))
267 return;
268
269 mtx_lock(&ctx->lock);
270
271 /*
272 * Figure out the buffers/features we need:
273 */
274 if (etna_depth_enabled(ctx))
275 resource_written(ctx, pfb->zsbuf->texture);
276
277 if (etna_stencil_enabled(ctx))
278 resource_written(ctx, pfb->zsbuf->texture);
279
280 for (i = 0; i < pfb->nr_cbufs; i++) {
281 struct pipe_resource *surf;
282
283 if (!pfb->cbufs[i])
284 continue;
285
286 surf = pfb->cbufs[i]->texture;
287 resource_written(ctx, surf);
288 }
289
290 /* Mark constant buffers as being read */
291 for (unsigned i = 0; i < ETNA_MAX_CONST_BUF; i++) {
292 resource_read(ctx, ctx->constant_buffer[PIPE_SHADER_VERTEX][i].buffer);
293 resource_read(ctx, ctx->constant_buffer[PIPE_SHADER_FRAGMENT][i].buffer);
294 }
295
296 /* Mark VBOs as being read */
297 foreach_bit(i, ctx->vertex_buffer.enabled_mask) {
298 assert(!ctx->vertex_buffer.vb[i].is_user_buffer);
299 resource_read(ctx, ctx->vertex_buffer.vb[i].buffer.resource);
300 }
301
302 /* Mark index buffer as being read */
303 resource_read(ctx, indexbuf);
304
305 /* Mark textures as being read */
306 for (i = 0; i < PIPE_MAX_SAMPLERS; i++) {
307 if (ctx->sampler_view[i]) {
308 resource_read(ctx, ctx->sampler_view[i]->texture);
309
310 /* if texture was modified since the last update,
311 * we need to clear the texture cache and possibly
312 * resolve/update ts
313 */
314 etna_update_sampler_source(ctx->sampler_view[i], i);
315 }
316 }
317
318 list_for_each_entry(struct etna_hw_query, hq, &ctx->active_hw_queries, node)
319 resource_written(ctx, hq->prsc);
320
321 ctx->stats.prims_emitted += u_reduced_prims_for_vertices(info->mode, info->count);
322 ctx->stats.draw_calls++;
323
324 /* Update state for this draw operation */
325 etna_update_state_for_draw(ctx, info);
326
327 /* First, sync state, then emit DRAW_PRIMITIVES or DRAW_INDEXED_PRIMITIVES */
328 etna_emit_state(ctx);
329
330 if (ctx->specs.halti >= 2) {
331 /* On HALTI2+ (GC3000 and higher) only use instanced drawing commands, as the blob does */
332 etna_draw_instanced(ctx->stream, info->index_size, draw_mode, info->instance_count,
333 info->count, info->index_size ? info->index_bias : info->start);
334 } else {
335 if (info->index_size)
336 etna_draw_indexed_primitives(ctx->stream, draw_mode, 0, prims, info->index_bias);
337 else
338 etna_draw_primitives(ctx->stream, draw_mode, info->start, prims);
339 }
340
341 if (DBG_ENABLED(ETNA_DBG_DRAW_STALL)) {
342 /* Stall the FE after every draw operation. This allows better
343 * debug of GPU hang conditions, as the FE will indicate which
344 * draw op has caused the hang. */
345 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
346 }
347 mtx_unlock(&ctx->lock);
348
349 if (DBG_ENABLED(ETNA_DBG_FLUSH_ALL))
350 pctx->flush(pctx, NULL, 0);
351
352 if (ctx->framebuffer_s.cbufs[0])
353 etna_resource(ctx->framebuffer_s.cbufs[0]->texture)->seqno++;
354 if (ctx->framebuffer_s.zsbuf)
355 etna_resource(ctx->framebuffer_s.zsbuf->texture)->seqno++;
356 if (info->index_size && indexbuf != info->index.resource)
357 pipe_resource_reference(&indexbuf, NULL);
358 }
359
360 static void
361 etna_reset_gpu_state(struct etna_context *ctx)
362 {
363 struct etna_cmd_stream *stream = ctx->stream;
364
365 etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENGL);
366 etna_set_state(stream, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x00000001);
367 /* blob sets this to 0x40000031 on GC7000, seems to make no difference,
368 * but keep it in mind if depth behaves strangely. */
369 etna_set_state(stream, VIVS_RA_EARLY_DEPTH, 0x00000031);
370 etna_set_state(stream, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
371 etna_set_state(stream, VIVS_PA_FLAGS, 0x00000000); /* blob sets ZCONVERT_BYPASS on GC3000+, this messes up z for us */
372 etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A80, 0x38a01404);
373 etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A84, fui(8192.0));
374 etna_set_state(stream, VIVS_PA_ZFARCLIPPING, 0x00000000);
375 etna_set_state(stream, VIVS_RA_HDEPTH_CONTROL, 0x00007000);
376 etna_set_state(stream, VIVS_PE_STENCIL_CONFIG_EXT2, 0x00000000);
377 etna_set_state(stream, VIVS_PS_CONTROL_EXT, 0x00000000);
378
379 /* There is no HALTI0 specific state */
380 if (ctx->specs.halti >= 1) { /* Only on HALTI1+ */
381 etna_set_state(stream, VIVS_VS_HALTI1_UNK00884, 0x00000808);
382 }
383 if (ctx->specs.halti >= 2) { /* Only on HALTI2+ */
384 etna_set_state(stream, VIVS_RA_UNK00E0C, 0x00000000);
385 }
386 if (ctx->specs.halti >= 3) { /* Only on HALTI3+ */
387 etna_set_state(stream, VIVS_PS_HALTI3_UNK0103C, 0x76543210);
388 }
389 if (ctx->specs.halti >= 4) { /* Only on HALTI4+ */
390 etna_set_state(stream, VIVS_PS_MSAA_CONFIG, 0x6fffffff & 0xf70fffff & 0xfff6ffff &
391 0xffff6fff & 0xfffff6ff & 0xffffff7f);
392 etna_set_state(stream, VIVS_PE_HALTI4_UNK014C0, 0x00000000);
393 }
394 if (ctx->specs.halti >= 5) { /* Only on HALTI5+ */
395 etna_set_state(stream, VIVS_NTE_DESCRIPTOR_UNK14C40, 0x00000001);
396 etna_set_state(stream, VIVS_FE_HALTI5_UNK007D8, 0x00000002);
397 etna_set_state(stream, VIVS_FE_HALTI5_ID_CONFIG, 0x00000000);
398 etna_set_state(stream, VIVS_PS_SAMPLER_BASE, 0x00000000);
399 etna_set_state(stream, VIVS_VS_SAMPLER_BASE, 0x00000020);
400 etna_set_state(stream, VIVS_SH_CONFIG, VIVS_SH_CONFIG_RTNE_ROUNDING);
401 } else { /* Only on pre-HALTI5 */
402 etna_set_state(stream, VIVS_GL_UNK03834, 0x00000000);
403 etna_set_state(stream, VIVS_GL_UNK03838, 0x00000000);
404 etna_set_state(stream, VIVS_GL_UNK03854, 0x00000000);
405 }
406
407 if (!ctx->specs.use_blt) {
408 /* Enable SINGLE_BUFFER for resolve, if supported */
409 etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, COND(ctx->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE));
410 }
411
412 if (ctx->specs.halti >= 5) {
413 /* TXDESC cache flush - do this once at the beginning, as texture
414 * descriptors are only written by the CPU once, then patched by the kernel
415 * before command stream submission. It does not need flushing if the
416 * referenced image data changes.
417 */
418 etna_set_state(stream, VIVS_NTE_DESCRIPTOR_FLUSH, 0);
419 etna_set_state(stream, VIVS_GL_FLUSH_CACHE,
420 VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 |
421 VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13);
422
423 /* Icache invalidate (should do this on shader change?) */
424 etna_set_state(stream, VIVS_VS_ICACHE_INVALIDATE,
425 VIVS_VS_ICACHE_INVALIDATE_UNK0 | VIVS_VS_ICACHE_INVALIDATE_UNK1 |
426 VIVS_VS_ICACHE_INVALIDATE_UNK2 | VIVS_VS_ICACHE_INVALIDATE_UNK3 |
427 VIVS_VS_ICACHE_INVALIDATE_UNK4);
428 }
429
430 ctx->dirty = ~0L;
431 ctx->dirty_sampler_views = ~0L;
432 }
433
434 static void
435 etna_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
436 enum pipe_flush_flags flags)
437 {
438 struct etna_context *ctx = etna_context(pctx);
439 int out_fence_fd = -1;
440
441 mtx_lock(&ctx->lock);
442
443 list_for_each_entry(struct etna_hw_query, hq, &ctx->active_hw_queries, node)
444 etna_hw_query_suspend(hq, ctx);
445
446 etna_cmd_stream_flush(ctx->stream, ctx->in_fence_fd,
447 (flags & PIPE_FLUSH_FENCE_FD) ? &out_fence_fd : NULL);
448
449 list_for_each_entry(struct etna_hw_query, hq, &ctx->active_hw_queries, node)
450 etna_hw_query_resume(hq, ctx);
451
452 if (fence)
453 *fence = etna_fence_create(pctx, out_fence_fd);
454
455 /*
456 * Go through all _resources_ pending in this _context_ and mark them as
457 * not pending in this _context_ anymore, since they were just flushed.
458 */
459 set_foreach(ctx->used_resources_read, entry) {
460 struct etna_resource *rsc = (struct etna_resource *)entry->key;
461 struct pipe_resource *referenced = &rsc->base;
462
463 _mesa_set_remove_key(rsc->pending_ctx, ctx);
464
465 /* if resource has no pending ctx's reset its status */
466 if (_mesa_set_next_entry(rsc->pending_ctx, NULL) == NULL)
467 rsc->status &= ~ETNA_PENDING_READ;
468
469 pipe_resource_reference(&referenced, NULL);
470 }
471 _mesa_set_clear(ctx->used_resources_read, NULL);
472
473 set_foreach(ctx->used_resources_write, entry) {
474 struct etna_resource *rsc = (struct etna_resource *)entry->key;
475 struct pipe_resource *referenced = &rsc->base;
476
477 _mesa_set_remove_key(rsc->pending_ctx, ctx);
478
479 /* if resource has no pending ctx's reset its status */
480 if (_mesa_set_next_entry(rsc->pending_ctx, NULL) == NULL)
481 rsc->status &= ~ETNA_PENDING_WRITE;
482
483 pipe_resource_reference(&referenced, NULL);
484 }
485 _mesa_set_clear(ctx->used_resources_write, NULL);
486
487 etna_reset_gpu_state(ctx);
488 mtx_unlock(&ctx->lock);
489 }
490
491 static void
492 etna_context_force_flush(struct etna_cmd_stream *stream, void *priv)
493 {
494 struct pipe_context *pctx = priv;
495
496 pctx->flush(pctx, NULL, 0);
497
498 }
499
500 static void
501 etna_set_debug_callback(struct pipe_context *pctx,
502 const struct pipe_debug_callback *cb)
503 {
504 struct etna_context *ctx = etna_context(pctx);
505
506 if (cb)
507 ctx->debug = *cb;
508 else
509 memset(&ctx->debug, 0, sizeof(ctx->debug));
510 }
511
512 struct pipe_context *
513 etna_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
514 {
515 struct etna_context *ctx = CALLOC_STRUCT(etna_context);
516 struct etna_screen *screen;
517 struct pipe_context *pctx;
518
519 if (ctx == NULL)
520 return NULL;
521
522 pctx = &ctx->base;
523 pctx->priv = ctx;
524 pctx->screen = pscreen;
525 pctx->stream_uploader = u_upload_create_default(pctx);
526 if (!pctx->stream_uploader)
527 goto fail;
528 pctx->const_uploader = pctx->stream_uploader;
529
530 screen = etna_screen(pscreen);
531 ctx->stream = etna_cmd_stream_new(screen->pipe, 0x2000,
532 &etna_context_force_flush, pctx);
533 if (ctx->stream == NULL)
534 goto fail;
535
536 ctx->used_resources_read = _mesa_set_create(NULL, _mesa_hash_pointer,
537 _mesa_key_pointer_equal);
538 if (!ctx->used_resources_read)
539 goto fail;
540
541 ctx->used_resources_write = _mesa_set_create(NULL, _mesa_hash_pointer,
542 _mesa_key_pointer_equal);
543 if (!ctx->used_resources_write)
544 goto fail;
545
546 mtx_init(&ctx->lock, mtx_recursive);
547
548 /* context ctxate setup */
549 ctx->specs = screen->specs;
550 ctx->screen = screen;
551 /* need some sane default in case state tracker doesn't set some state: */
552 ctx->sample_mask = 0xffff;
553
554 /* Set sensible defaults for state */
555 etna_reset_gpu_state(ctx);
556
557 ctx->in_fence_fd = -1;
558
559 pctx->destroy = etna_context_destroy;
560 pctx->draw_vbo = etna_draw_vbo;
561 pctx->flush = etna_flush;
562 pctx->set_debug_callback = etna_set_debug_callback;
563 pctx->create_fence_fd = etna_create_fence_fd;
564 pctx->fence_server_sync = etna_fence_server_sync;
565
566 /* creation of compile states */
567 pctx->create_blend_state = etna_blend_state_create;
568 pctx->create_rasterizer_state = etna_rasterizer_state_create;
569 pctx->create_depth_stencil_alpha_state = etna_zsa_state_create;
570
571 etna_clear_blit_init(pctx);
572 etna_query_context_init(pctx);
573 etna_state_init(pctx);
574 etna_surface_init(pctx);
575 etna_shader_init(pctx);
576 etna_texture_init(pctx);
577 etna_transfer_init(pctx);
578
579 ctx->blitter = util_blitter_create(pctx);
580 if (!ctx->blitter)
581 goto fail;
582
583 /* Generate the bitmask of supported draw primitives. */
584 ctx->prim_hwsupport = 1 << PIPE_PRIM_POINTS |
585 1 << PIPE_PRIM_LINES |
586 1 << PIPE_PRIM_LINE_STRIP |
587 1 << PIPE_PRIM_TRIANGLES |
588 1 << PIPE_PRIM_TRIANGLE_FAN;
589
590 /* TODO: The bug relates only to indexed draws, but here we signal
591 * that there is no support for triangle strips at all. This should
592 * be refined.
593 */
594 if (VIV_FEATURE(ctx->screen, chipMinorFeatures2, BUG_FIXES8))
595 ctx->prim_hwsupport |= 1 << PIPE_PRIM_TRIANGLE_STRIP;
596
597 if (VIV_FEATURE(ctx->screen, chipMinorFeatures2, LINE_LOOP))
598 ctx->prim_hwsupport |= 1 << PIPE_PRIM_LINE_LOOP;
599
600 ctx->primconvert = util_primconvert_create(pctx, ctx->prim_hwsupport);
601 if (!ctx->primconvert)
602 goto fail;
603
604 slab_create_child(&ctx->transfer_pool, &screen->transfer_pool);
605 list_inithead(&ctx->active_hw_queries);
606
607 /* create dummy RT buffer, used when rendering with no color buffer */
608 ctx->dummy_rt = etna_bo_new(ctx->screen->dev, 64 * 64 * 4,
609 DRM_ETNA_GEM_CACHE_WC);
610 if (!ctx->dummy_rt)
611 goto fail;
612
613 ctx->dummy_rt_reloc.bo = ctx->dummy_rt;
614 ctx->dummy_rt_reloc.offset = 0;
615 ctx->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
616
617 if (screen->specs.halti >= 5) {
618 /* Create an empty dummy texture descriptor */
619 ctx->dummy_desc_bo = etna_bo_new(ctx->screen->dev, 0x100, DRM_ETNA_GEM_CACHE_WC);
620 if (!ctx->dummy_desc_bo)
621 goto fail;
622 uint32_t *buf = etna_bo_map(ctx->dummy_desc_bo);
623 etna_bo_cpu_prep(ctx->dummy_desc_bo, DRM_ETNA_PREP_WRITE);
624 memset(buf, 0, 0x100);
625 etna_bo_cpu_fini(ctx->dummy_desc_bo);
626 ctx->DUMMY_DESC_ADDR.bo = ctx->dummy_desc_bo;
627 ctx->DUMMY_DESC_ADDR.offset = 0;
628 ctx->DUMMY_DESC_ADDR.flags = ETNA_RELOC_READ;
629 }
630
631 return pctx;
632
633 fail:
634 pctx->destroy(pctx);
635
636 return NULL;
637 }