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[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_emit.c
1 /*
2 * Copyright (c) 2014-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_emit.h"
28
29 #include "etnaviv_blend.h"
30 #include "etnaviv_compiler.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_rasterizer.h"
33 #include "etnaviv_resource.h"
34 #include "etnaviv_rs.h"
35 #include "etnaviv_screen.h"
36 #include "etnaviv_shader.h"
37 #include "etnaviv_texture.h"
38 #include "etnaviv_translate.h"
39 #include "etnaviv_uniforms.h"
40 #include "etnaviv_util.h"
41 #include "etnaviv_zsa.h"
42 #include "hw/common.xml.h"
43 #include "hw/state.xml.h"
44 #include "hw/state_blt.xml.h"
45 #include "util/u_math.h"
46
47 /* Queue a STALL command (queues 2 words) */
48 static inline void
49 CMD_STALL(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
50 {
51 etna_cmd_stream_emit(stream, VIV_FE_STALL_HEADER_OP_STALL);
52 etna_cmd_stream_emit(stream, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
53 }
54
55 void
56 etna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
57 {
58 bool blt = (from == SYNC_RECIPIENT_BLT) || (to == SYNC_RECIPIENT_BLT);
59 etna_cmd_stream_reserve(stream, blt ? 8 : 4);
60
61 if (blt) {
62 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
63 etna_cmd_stream_emit(stream, 1);
64 }
65
66 /* TODO: set bit 28/29 of token after BLT COPY_BUFFER */
67 etna_emit_load_state(stream, VIVS_GL_SEMAPHORE_TOKEN >> 2, 1, 0);
68 etna_cmd_stream_emit(stream, VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | VIVS_GL_SEMAPHORE_TOKEN_TO(to));
69
70 if (from == SYNC_RECIPIENT_FE) {
71 /* if the frontend is to be stalled, queue a STALL frontend command */
72 CMD_STALL(stream, from, to);
73 } else {
74 /* otherwise, load the STALL token state */
75 etna_emit_load_state(stream, VIVS_GL_STALL_TOKEN >> 2, 1, 0);
76 etna_cmd_stream_emit(stream, VIVS_GL_STALL_TOKEN_FROM(from) | VIVS_GL_STALL_TOKEN_TO(to));
77 }
78
79 if (blt) {
80 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
81 etna_cmd_stream_emit(stream, 0);
82 }
83 }
84
85 #define EMIT_STATE(state_name, src_value) \
86 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
87
88 #define EMIT_STATE_FIXP(state_name, src_value) \
89 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
90
91 #define EMIT_STATE_RELOC(state_name, src_value) \
92 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
93
94 #define ETNA_3D_CONTEXT_SIZE (400) /* keep this number above "Total state updates (fixed)" from gen_weave_state tool */
95
96 static unsigned
97 required_stream_size(struct etna_context *ctx)
98 {
99 unsigned size = ETNA_3D_CONTEXT_SIZE;
100
101 /* stall + flush */
102 size += 2 + 4;
103
104 /* vertex elements */
105 size += ctx->vertex_elements->num_elements + 1;
106
107 /* uniforms - worst case (2 words per uniform load) */
108 size += ctx->shader.vs->uniforms.imm_count * 2;
109 size += ctx->shader.fs->uniforms.imm_count * 2;
110
111 /* shader */
112 size += ctx->shader_state.vs_inst_mem_size + 1;
113 size += ctx->shader_state.ps_inst_mem_size + 1;
114
115 /* DRAW_INDEXED_PRIMITIVES command */
116 size += 6;
117
118 /* reserve for alignment etc. */
119 size += 64;
120
121 return size;
122 }
123
124 /* Emit state that only exists on HALTI5+ */
125 static void
126 emit_halti5_only_state(struct etna_context *ctx, int vs_output_count)
127 {
128 struct etna_cmd_stream *stream = ctx->stream;
129 uint32_t dirty = ctx->dirty;
130 struct etna_coalesce coalesce;
131
132 etna_coalesce_start(stream, &coalesce);
133 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
134 /* Magic states (load balancing, inter-unit sync, buffers) */
135 /*007C4*/ EMIT_STATE(FE_HALTI5_ID_CONFIG, ctx->shader_state.FE_HALTI5_ID_CONFIG);
136 /*00870*/ EMIT_STATE(VS_HALTI5_OUTPUT_COUNT, vs_output_count | ((vs_output_count * 0x10) << 8));
137 /*008A0*/ EMIT_STATE(VS_HALTI5_UNK008A0, 0x0001000e | ((0x110/vs_output_count) << 20));
138 for (int x = 0; x < 4; ++x) {
139 /*008E0*/ EMIT_STATE(VS_HALTI5_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
140 }
141 }
142 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
143 for (int x = 0; x < 4; ++x) {
144 /*008C0*/ EMIT_STATE(VS_HALTI5_INPUT(x), ctx->shader_state.VS_INPUT[x]);
145 }
146 }
147 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
148 /*00A90*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
149 /*00A94*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(1), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
150 /*00AA8*/ EMIT_STATE(PA_VS_OUTPUT_COUNT, vs_output_count);
151 /*01080*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
152 /*01084*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(1), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
153 /*03888*/ EMIT_STATE(GL_HALTI5_SH_SPECIALS, ctx->shader_state.GL_HALTI5_SH_SPECIALS);
154 }
155 etna_coalesce_end(stream, &coalesce);
156 }
157
158 /* Emit state that no longer exists on HALTI5 */
159 static void
160 emit_pre_halti5_state(struct etna_context *ctx)
161 {
162 struct etna_cmd_stream *stream = ctx->stream;
163 uint32_t dirty = ctx->dirty;
164 struct etna_coalesce coalesce;
165
166 etna_coalesce_start(stream, &coalesce);
167 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
168 /*00800*/ EMIT_STATE(VS_END_PC, ctx->shader_state.VS_END_PC);
169 }
170 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
171 for (int x = 0; x < 4; ++x) {
172 /*00810*/ EMIT_STATE(VS_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
173 }
174 }
175 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
176 for (int x = 0; x < 4; ++x) {
177 /*00820*/ EMIT_STATE(VS_INPUT(x), ctx->shader_state.VS_INPUT[x]);
178 }
179 }
180 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
181 /*00838*/ EMIT_STATE(VS_START_PC, ctx->shader_state.VS_START_PC);
182 }
183 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
184 for (int x = 0; x < 10; ++x) {
185 /*00A40*/ EMIT_STATE(PA_SHADER_ATTRIBUTES(x), ctx->shader_state.PA_SHADER_ATTRIBUTES[x]);
186 }
187 }
188 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
189 /*00E04*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E04, ctx->framebuffer.RA_MULTISAMPLE_UNK00E04);
190 for (int x = 0; x < 4; ++x) {
191 /*00E10*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E10(x), ctx->framebuffer.RA_MULTISAMPLE_UNK00E10[x]);
192 }
193 for (int x = 0; x < 16; ++x) {
194 /*00E40*/ EMIT_STATE(RA_CENTROID_TABLE(x), ctx->framebuffer.RA_CENTROID_TABLE[x]);
195 }
196 }
197 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
198 /*01000*/ EMIT_STATE(PS_END_PC, ctx->shader_state.PS_END_PC);
199 }
200 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
201 /*01018*/ EMIT_STATE(PS_START_PC, ctx->shader_state.PS_START_PC);
202 }
203 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
204 /*03820*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS, ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
205 for (int x = 0; x < 2; ++x) {
206 /*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), ctx->shader_state.GL_VARYING_COMPONENT_USE[x]);
207 }
208 /*03834*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS2, ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
209 }
210 etna_coalesce_end(stream, &coalesce);
211 }
212
213 /* Weave state before draw operation. This function merges all the compiled
214 * state blocks under the context into one device register state. Parts of
215 * this state that are changed since last call (dirty) will be uploaded as
216 * state changes in the command buffer. */
217 void
218 etna_emit_state(struct etna_context *ctx)
219 {
220 struct etna_cmd_stream *stream = ctx->stream;
221 unsigned ccw = ctx->rasterizer->front_ccw;
222
223
224 /* Pre-reserve the command buffer space which we are likely to need.
225 * This must cover all the state emitted below, and the following
226 * draw command. */
227 etna_cmd_stream_reserve(stream, required_stream_size(ctx));
228
229 uint32_t dirty = ctx->dirty;
230
231 /* Pre-processing: see what caches we need to flush before making state changes. */
232 uint32_t to_flush = 0;
233 if (unlikely(dirty & (ETNA_DIRTY_BLEND)))
234 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR;
235 if (unlikely(dirty & (ETNA_DIRTY_TEXTURE_CACHES)))
236 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE;
237 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) /* Framebuffer config changed? */
238 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH;
239 if (DBG_ENABLED(ETNA_DBG_CFLUSH_ALL))
240 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE | VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH;
241
242 if (to_flush) {
243 etna_set_state(stream, VIVS_GL_FLUSH_CACHE, to_flush);
244 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
245 }
246
247 /* Flush TS cache before changing TS configuration. */
248 if (unlikely(dirty & ETNA_DIRTY_TS)) {
249 etna_set_state(stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
250 }
251
252 /* Update vertex elements. This is different from any of the other states, in that
253 * a) the number of vertex elements written matters: so write only active ones
254 * b) the vertex element states must all be written: do not skip entries that stay the same */
255 if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) {
256 if (ctx->specs.halti >= 5) {
257 /*17800*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0),
258 ctx->vertex_elements->num_elements,
259 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG0);
260 /*17A00*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_SCALE(0),
261 ctx->vertex_elements->num_elements,
262 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
263 /*17A80*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG1(0),
264 ctx->vertex_elements->num_elements,
265 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG1);
266 } else {
267 /* Special case: vertex elements must always be sent in full if changed */
268 /*00600*/ etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
269 ctx->vertex_elements->num_elements,
270 ctx->vertex_elements->FE_VERTEX_ELEMENT_CONFIG);
271 if (ctx->specs.halti >= 2) {
272 /*00780*/ etna_set_state_multi(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0),
273 ctx->vertex_elements->num_elements,
274 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
275 }
276 }
277 }
278 unsigned vs_output_count = etna_rasterizer_state(ctx->rasterizer)->point_size_per_vertex
279 ? ctx->shader_state.VS_OUTPUT_COUNT_PSIZE
280 : ctx->shader_state.VS_OUTPUT_COUNT;
281
282 /* The following code is originally generated by gen_merge_state.py, to
283 * emit state in increasing order of address (this makes it possible to merge
284 * consecutive register updates into one SET_STATE command)
285 *
286 * There have been some manual changes, where the weaving operation is not
287 * simply bitwise or:
288 * - scissor fixp
289 * - num vertex elements
290 * - scissor handling
291 * - num samplers
292 * - texture lod
293 * - ETNA_DIRTY_TS
294 * - removed ETNA_DIRTY_BASE_SETUP statements -- these are guaranteed to not
295 * change anyway
296 * - PS / framebuffer interaction for MSAA
297 * - move update of GL_MULTI_SAMPLE_CONFIG first
298 * - add unlikely()/likely()
299 */
300 struct etna_coalesce coalesce;
301
302 etna_coalesce_start(stream, &coalesce);
303
304 /* begin only EMIT_STATE -- make sure no new etna_reserve calls are done here
305 * directly
306 * or indirectly */
307 /* multi sample config is set first, and outside of the normal sorting
308 * order, as changing the multisample state clobbers PS.INPUT_COUNT (and
309 * possibly PS.TEMP_REGISTER_CONTROL).
310 */
311 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_SAMPLE_MASK))) {
312 uint32_t val = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(ctx->sample_mask);
313 val |= ctx->framebuffer.GL_MULTI_SAMPLE_CONFIG;
314
315 /*03818*/ EMIT_STATE(GL_MULTI_SAMPLE_CONFIG, val);
316 }
317 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) {
318 /*00644*/ EMIT_STATE_RELOC(FE_INDEX_STREAM_BASE_ADDR, &ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR);
319 /*00648*/ EMIT_STATE(FE_INDEX_STREAM_CONTROL, ctx->index_buffer.FE_INDEX_STREAM_CONTROL);
320 }
321 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) {
322 /*00674*/ EMIT_STATE(FE_PRIMITIVE_RESTART_INDEX, ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX);
323 }
324 if (likely(dirty & (ETNA_DIRTY_VERTEX_BUFFERS))) {
325 if (ctx->specs.halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */
326 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
327 /*14600*/ EMIT_STATE_RELOC(NFE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
328 }
329 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
330 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) {
331 /*14640*/ EMIT_STATE(NFE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_CONTROL);
332 }
333 }
334 } else if(ctx->specs.stream_count > 1) { /* hw w/ multiple vertex streams */
335 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
336 /*00680*/ EMIT_STATE_RELOC(FE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
337 }
338 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
339 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) {
340 /*006A0*/ EMIT_STATE(FE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_CONTROL);
341 }
342 }
343 } else { /* hw w/ single vertex stream */
344 /*0064C*/ EMIT_STATE_RELOC(FE_VERTEX_STREAM_BASE_ADDR, &ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_BASE_ADDR);
345 /*00650*/ EMIT_STATE(FE_VERTEX_STREAM_CONTROL, ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_CONTROL);
346 }
347 }
348 /* gallium has instance divisor as part of elements state */
349 if ((dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) && ctx->specs.halti >= 2) {
350 for (int x = 0; x < ctx->vertex_elements->num_buffers; ++x) {
351 /*14680*/ EMIT_STATE(NFE_VERTEX_STREAMS_VERTEX_DIVISOR(x), ctx->vertex_elements->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[x]);
352 }
353 }
354
355 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_RASTERIZER))) {
356
357 /*00804*/ EMIT_STATE(VS_OUTPUT_COUNT, vs_output_count);
358 }
359 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
360 /*00808*/ EMIT_STATE(VS_INPUT_COUNT, ctx->shader_state.VS_INPUT_COUNT);
361 /*0080C*/ EMIT_STATE(VS_TEMP_REGISTER_CONTROL, ctx->shader_state.VS_TEMP_REGISTER_CONTROL);
362 }
363 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
364 /*00830*/ EMIT_STATE(VS_LOAD_BALANCING, ctx->shader_state.VS_LOAD_BALANCING);
365 }
366 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) {
367 /*00A00*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_X, ctx->viewport.PA_VIEWPORT_SCALE_X);
368 /*00A04*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_Y, ctx->viewport.PA_VIEWPORT_SCALE_Y);
369 /*00A08*/ EMIT_STATE(PA_VIEWPORT_SCALE_Z, ctx->viewport.PA_VIEWPORT_SCALE_Z);
370 /*00A0C*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_X, ctx->viewport.PA_VIEWPORT_OFFSET_X);
371 /*00A10*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_Y, ctx->viewport.PA_VIEWPORT_OFFSET_Y);
372 /*00A14*/ EMIT_STATE(PA_VIEWPORT_OFFSET_Z, ctx->viewport.PA_VIEWPORT_OFFSET_Z);
373 }
374 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
375 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
376
377 /*00A18*/ EMIT_STATE(PA_LINE_WIDTH, rasterizer->PA_LINE_WIDTH);
378 /*00A1C*/ EMIT_STATE(PA_POINT_SIZE, rasterizer->PA_POINT_SIZE);
379 /*00A28*/ EMIT_STATE(PA_SYSTEM_MODE, rasterizer->PA_SYSTEM_MODE);
380 }
381 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
382 /*00A30*/ EMIT_STATE(PA_ATTRIBUTE_ELEMENT_COUNT, ctx->shader_state.PA_ATTRIBUTE_ELEMENT_COUNT);
383 }
384 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_SHADER))) {
385 uint32_t val = etna_rasterizer_state(ctx->rasterizer)->PA_CONFIG;
386 /*00A34*/ EMIT_STATE(PA_CONFIG, val & ctx->shader_state.PA_CONFIG);
387 }
388 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
389 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
390 /*00A38*/ EMIT_STATE(PA_WIDE_LINE_WIDTH0, rasterizer->PA_LINE_WIDTH);
391 /*00A3C*/ EMIT_STATE(PA_WIDE_LINE_WIDTH1, rasterizer->PA_LINE_WIDTH);
392 }
393 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
394 ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) {
395 /* this is a bit of a mess: rasterizer.scissor determines whether to use
396 * only the framebuffer scissor, or specific scissor state, and the
397 * viewport clips too so the logic spans four CSOs */
398 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
399
400 uint32_t scissor_left =
401 MAX2(ctx->framebuffer.SE_SCISSOR_LEFT, ctx->viewport.SE_SCISSOR_LEFT);
402 uint32_t scissor_top =
403 MAX2(ctx->framebuffer.SE_SCISSOR_TOP, ctx->viewport.SE_SCISSOR_TOP);
404 uint32_t scissor_right =
405 MIN2(ctx->framebuffer.SE_SCISSOR_RIGHT, ctx->viewport.SE_SCISSOR_RIGHT);
406 uint32_t scissor_bottom =
407 MIN2(ctx->framebuffer.SE_SCISSOR_BOTTOM, ctx->viewport.SE_SCISSOR_BOTTOM);
408
409 if (rasterizer->scissor) {
410 scissor_left = MAX2(ctx->scissor.SE_SCISSOR_LEFT, scissor_left);
411 scissor_top = MAX2(ctx->scissor.SE_SCISSOR_TOP, scissor_top);
412 scissor_right = MIN2(ctx->scissor.SE_SCISSOR_RIGHT, scissor_right);
413 scissor_bottom = MIN2(ctx->scissor.SE_SCISSOR_BOTTOM, scissor_bottom);
414 }
415
416 /*00C00*/ EMIT_STATE_FIXP(SE_SCISSOR_LEFT, scissor_left);
417 /*00C04*/ EMIT_STATE_FIXP(SE_SCISSOR_TOP, scissor_top);
418 /*00C08*/ EMIT_STATE_FIXP(SE_SCISSOR_RIGHT, scissor_right);
419 /*00C0C*/ EMIT_STATE_FIXP(SE_SCISSOR_BOTTOM, scissor_bottom);
420 }
421 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
422 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
423
424 /*00C10*/ EMIT_STATE(SE_DEPTH_SCALE, rasterizer->SE_DEPTH_SCALE);
425 /*00C14*/ EMIT_STATE(SE_DEPTH_BIAS, rasterizer->SE_DEPTH_BIAS);
426 /*00C18*/ EMIT_STATE(SE_CONFIG, rasterizer->SE_CONFIG);
427 }
428 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
429 ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) {
430 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
431
432 uint32_t clip_right =
433 MIN2(ctx->framebuffer.SE_CLIP_RIGHT, ctx->viewport.SE_CLIP_RIGHT);
434 uint32_t clip_bottom =
435 MIN2(ctx->framebuffer.SE_CLIP_BOTTOM, ctx->viewport.SE_CLIP_BOTTOM);
436
437 if (rasterizer->scissor) {
438 clip_right = MIN2(ctx->scissor.SE_CLIP_RIGHT, clip_right);
439 clip_bottom = MIN2(ctx->scissor.SE_CLIP_BOTTOM, clip_bottom);
440 }
441
442 /*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, clip_right);
443 /*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, clip_bottom);
444 }
445 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
446 /*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL);
447 }
448 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
449 /*01004*/ EMIT_STATE(PS_OUTPUT_REG, ctx->shader_state.PS_OUTPUT_REG);
450 /*01008*/ EMIT_STATE(PS_INPUT_COUNT,
451 ctx->framebuffer.msaa_mode
452 ? ctx->shader_state.PS_INPUT_COUNT_MSAA
453 : ctx->shader_state.PS_INPUT_COUNT);
454 /*0100C*/ EMIT_STATE(PS_TEMP_REGISTER_CONTROL,
455 ctx->framebuffer.msaa_mode
456 ? ctx->shader_state.PS_TEMP_REGISTER_CONTROL_MSAA
457 : ctx->shader_state.PS_TEMP_REGISTER_CONTROL);
458 /*01010*/ EMIT_STATE(PS_CONTROL, ctx->framebuffer.PS_CONTROL);
459 /*01030*/ EMIT_STATE(PS_CONTROL_EXT, ctx->framebuffer.PS_CONTROL_EXT);
460 }
461 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_SHADER))) {
462 /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, (etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG |
463 ctx->framebuffer.PE_DEPTH_CONFIG) &
464 ctx->shader_state.PE_DEPTH_CONFIG);
465 }
466 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) {
467 /*01404*/ EMIT_STATE(PE_DEPTH_NEAR, ctx->viewport.PE_DEPTH_NEAR);
468 /*01408*/ EMIT_STATE(PE_DEPTH_FAR, ctx->viewport.PE_DEPTH_FAR);
469 }
470 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
471 /*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE);
472
473 if (ctx->specs.pixel_pipes == 1) {
474 /*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR);
475 }
476
477 /*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE);
478 }
479
480 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) {
481 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP[ccw];
482 /*01418*/ EMIT_STATE(PE_STENCIL_OP, val);
483 }
484 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER))) {
485 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG[ccw];
486 /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG[ccw]);
487 }
488 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
489 uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP;
490 /*01420*/ EMIT_STATE(PE_ALPHA_OP, val);
491 }
492 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR))) {
493 /*01424*/ EMIT_STATE(PE_ALPHA_BLEND_COLOR, ctx->blend_color.PE_ALPHA_BLEND_COLOR);
494 }
495 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
496 uint32_t val = etna_blend_state(ctx->blend)->PE_ALPHA_CONFIG;
497 /*01428*/ EMIT_STATE(PE_ALPHA_CONFIG, val);
498 }
499 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
500 uint32_t val;
501 /* Use the components and overwrite bits in framebuffer.PE_COLOR_FORMAT
502 * as a mask to enable the bits from blend PE_COLOR_FORMAT */
503 val = ~(VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
504 VIVS_PE_COLOR_FORMAT_OVERWRITE);
505 val |= etna_blend_state(ctx->blend)->PE_COLOR_FORMAT;
506 val &= ctx->framebuffer.PE_COLOR_FORMAT;
507 /*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val);
508 }
509 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
510 if (ctx->specs.pixel_pipes == 1) {
511 /*01430*/ EMIT_STATE_RELOC(PE_COLOR_ADDR, &ctx->framebuffer.PE_COLOR_ADDR);
512 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
513 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
514 } else if (ctx->specs.pixel_pipes == 2) {
515 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
516 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
517 /*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]);
518 /*01464*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(1), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[1]);
519 /*01480*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(0), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[0]);
520 /*01484*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(1), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[1]);
521 } else {
522 abort();
523 }
524 }
525 if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_ZSA))) {
526 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT;
527 /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, val | ctx->stencil_ref.PE_STENCIL_CONFIG_EXT[ccw]);
528 }
529 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
530 struct etna_blend_state *blend = etna_blend_state(ctx->blend);
531 /*014A4*/ EMIT_STATE(PE_LOGIC_OP, blend->PE_LOGIC_OP | ctx->framebuffer.PE_LOGIC_OP);
532 }
533 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
534 struct etna_blend_state *blend = etna_blend_state(ctx->blend);
535 for (int x = 0; x < 2; ++x) {
536 /*014A8*/ EMIT_STATE(PE_DITHER(x), blend->PE_DITHER[x]);
537 }
538 }
539 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR))) {
540 /*014B0*/ EMIT_STATE(PE_ALPHA_COLOR_EXT0, ctx->blend_color.PE_ALPHA_COLOR_EXT0);
541 /*014B4*/ EMIT_STATE(PE_ALPHA_COLOR_EXT1, ctx->blend_color.PE_ALPHA_COLOR_EXT1);
542 }
543 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) {
544 /*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]);
545 }
546 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && ctx->specs.halti >= 3)
547 /*014BC*/ EMIT_STATE(PE_MEM_CONFIG, ctx->framebuffer.PE_MEM_CONFIG);
548 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) {
549 /*01654*/ EMIT_STATE(TS_MEM_CONFIG, ctx->framebuffer.TS_MEM_CONFIG);
550 /*01658*/ EMIT_STATE_RELOC(TS_COLOR_STATUS_BASE, &ctx->framebuffer.TS_COLOR_STATUS_BASE);
551 /*0165C*/ EMIT_STATE_RELOC(TS_COLOR_SURFACE_BASE, &ctx->framebuffer.TS_COLOR_SURFACE_BASE);
552 /*01660*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE, ctx->framebuffer.TS_COLOR_CLEAR_VALUE);
553 /*01664*/ EMIT_STATE_RELOC(TS_DEPTH_STATUS_BASE, &ctx->framebuffer.TS_DEPTH_STATUS_BASE);
554 /*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, &ctx->framebuffer.TS_DEPTH_SURFACE_BASE);
555 /*0166C*/ EMIT_STATE(TS_DEPTH_CLEAR_VALUE, ctx->framebuffer.TS_DEPTH_CLEAR_VALUE);
556 /*016BC*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE_EXT, ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT);
557 }
558 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
559 /*0381C*/ EMIT_STATE(GL_VARYING_TOTAL_COMPONENTS, ctx->shader_state.GL_VARYING_TOTAL_COMPONENTS);
560 }
561 etna_coalesce_end(stream, &coalesce);
562 /* end only EMIT_STATE */
563
564 /* Emit strongly architecture-specific state */
565 if (ctx->specs.halti >= 5)
566 emit_halti5_only_state(ctx, vs_output_count);
567 else
568 emit_pre_halti5_state(ctx);
569
570 ctx->emit_texture_state(ctx);
571
572 /* Insert a FE/PE stall as changing the shader instructions (and maybe
573 * the uniforms) can corrupt the previous in-progress draw operation.
574 * Observed with amoeba on GC2000 during the right-to-left rendering
575 * of PI, and can cause GPU hangs immediately after.
576 * I summise that this is because the "new" locations at 0xc000 are not
577 * properly protected against updates as other states seem to be. Hence,
578 * we detect the "new" vertex shader instruction offset to apply this. */
579 if (ctx->dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF) && ctx->specs.vs_offset > 0x4000)
580 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
581
582 /* We need to update the uniform cache only if one of the following bits are
583 * set in ctx->dirty:
584 * - ETNA_DIRTY_SHADER
585 * - ETNA_DIRTY_CONSTBUF
586 * - uniforms_dirty_bits
587 *
588 * In case of ETNA_DIRTY_SHADER we need load all uniforms from the cache. In
589 * all
590 * other cases we can load on the changed uniforms.
591 */
592 static const uint32_t uniform_dirty_bits =
593 ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF;
594
595 /**** Large dynamically-sized state ****/
596 bool do_uniform_flush = ctx->specs.halti < 5;
597 if (dirty & (ETNA_DIRTY_SHADER)) {
598 /* Special case: a new shader was loaded; simply re-load all uniforms and
599 * shader code at once */
600 /* This sequence is special, do not change ordering unless necessary. According to comment
601 snippets in the Vivante kernel driver a process called "steering" goes on while programming
602 shader state. This (as I understand it) means certain unified states are "steered"
603 toward a specific shader unit (VS/PS/...) based on either explicit flags in register
604 00860, or what other state is written before "auto-steering". So this means some
605 state can legitimately be programmed multiple times.
606 */
607
608 if (ctx->specs.halti >= 5) { /* ICACHE (HALTI5) */
609 assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo);
610 /* Set icache (VS) */
611 etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0);
612 etna_set_state(stream, VIVS_VS_NEWRANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4);
613 assert(ctx->shader_state.VS_INST_ADDR.bo);
614 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
615 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
616 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
617 etna_set_state(stream, VIVS_VS_ICACHE_COUNT, ctx->shader_state.vs_inst_mem_size / 4 - 1);
618
619 /* Set icache (PS) */
620 etna_set_state(stream, VIVS_PS_NEWRANGE_LOW, 0);
621 etna_set_state(stream, VIVS_PS_NEWRANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4);
622 assert(ctx->shader_state.PS_INST_ADDR.bo);
623 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
624 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
625 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
626 etna_set_state(stream, VIVS_PS_ICACHE_COUNT, ctx->shader_state.ps_inst_mem_size / 4 - 1);
627
628 } else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) {
629 /* ICACHE (pre-HALTI5) */
630 assert(ctx->specs.has_icache && ctx->specs.has_shader_range_registers);
631 /* Set icache (VS) */
632 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
633 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
634 VIVS_VS_ICACHE_CONTROL_ENABLE |
635 VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
636 assert(ctx->shader_state.VS_INST_ADDR.bo);
637 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
638
639 /* Set icache (PS) */
640 etna_set_state(stream, VIVS_PS_RANGE, (ctx->shader_state.ps_inst_mem_size / 4 - 1) << 16);
641 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
642 VIVS_VS_ICACHE_CONTROL_ENABLE |
643 VIVS_VS_ICACHE_CONTROL_FLUSH_PS);
644 assert(ctx->shader_state.PS_INST_ADDR.bo);
645 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
646 } else {
647 /* Upload shader directly, first flushing and disabling icache if
648 * supported on this hw */
649 if (ctx->specs.has_icache) {
650 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
651 VIVS_VS_ICACHE_CONTROL_FLUSH_PS |
652 VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
653 }
654 if (ctx->specs.has_shader_range_registers) {
655 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
656 etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) |
657 0x100);
658 }
659 etna_set_state_multi(stream, ctx->specs.vs_offset,
660 ctx->shader_state.vs_inst_mem_size,
661 ctx->shader_state.VS_INST_MEM);
662 etna_set_state_multi(stream, ctx->specs.ps_offset,
663 ctx->shader_state.ps_inst_mem_size,
664 ctx->shader_state.PS_INST_MEM);
665 }
666
667 if (ctx->specs.has_unified_uniforms) {
668 etna_set_state(stream, VIVS_VS_UNIFORM_BASE, 0);
669 etna_set_state(stream, VIVS_PS_UNIFORM_BASE, ctx->specs.max_vs_uniforms);
670 }
671
672 if (do_uniform_flush)
673 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
674
675 etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
676
677 if (do_uniform_flush)
678 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
679
680 etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
681
682 if (ctx->specs.halti >= 5) {
683 /* HALTI5 needs to be prompted to pre-fetch shaders */
684 etna_set_state(stream, VIVS_VS_ICACHE_PREFETCH, 0x00000000);
685 etna_set_state(stream, VIVS_PS_ICACHE_PREFETCH, 0x00000000);
686 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
687 }
688 } else {
689 /* ideally this cache would only be flushed if there are VS uniform changes */
690 if (do_uniform_flush)
691 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
692
693 if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
694 etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
695
696 /* ideally this cache would only be flushed if there are PS uniform changes */
697 if (do_uniform_flush)
698 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
699
700 if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
701 etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
702 }
703 /**** End of state update ****/
704 #undef EMIT_STATE
705 #undef EMIT_STATE_FIXP
706 #undef EMIT_STATE_RELOC
707 ctx->dirty = 0;
708 ctx->dirty_sampler_views = 0;
709 }