f43c954f1fdb684899f6f6076e385d2e44548c89
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_emit.c
1 /*
2 * Copyright (c) 2014-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_emit.h"
28
29 #include "etnaviv_blend.h"
30 #include "etnaviv_compiler.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_rasterizer.h"
33 #include "etnaviv_resource.h"
34 #include "etnaviv_rs.h"
35 #include "etnaviv_screen.h"
36 #include "etnaviv_shader.h"
37 #include "etnaviv_texture.h"
38 #include "etnaviv_translate.h"
39 #include "etnaviv_uniforms.h"
40 #include "etnaviv_util.h"
41 #include "etnaviv_zsa.h"
42 #include "hw/common.xml.h"
43 #include "hw/state.xml.h"
44 #include "hw/state_blt.xml.h"
45 #include "util/u_math.h"
46
47 /* Queue a STALL command (queues 2 words) */
48 static inline void
49 CMD_STALL(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
50 {
51 etna_cmd_stream_emit(stream, VIV_FE_STALL_HEADER_OP_STALL);
52 etna_cmd_stream_emit(stream, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
53 }
54
55 void
56 etna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
57 {
58 bool blt = (from == SYNC_RECIPIENT_BLT) || (to == SYNC_RECIPIENT_BLT);
59 etna_cmd_stream_reserve(stream, blt ? 8 : 4);
60
61 if (blt) {
62 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
63 etna_cmd_stream_emit(stream, 1);
64 }
65
66 /* TODO: set bit 28/29 of token after BLT COPY_BUFFER */
67 etna_emit_load_state(stream, VIVS_GL_SEMAPHORE_TOKEN >> 2, 1, 0);
68 etna_cmd_stream_emit(stream, VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | VIVS_GL_SEMAPHORE_TOKEN_TO(to));
69
70 if (from == SYNC_RECIPIENT_FE) {
71 /* if the frontend is to be stalled, queue a STALL frontend command */
72 CMD_STALL(stream, from, to);
73 } else {
74 /* otherwise, load the STALL token state */
75 etna_emit_load_state(stream, VIVS_GL_STALL_TOKEN >> 2, 1, 0);
76 etna_cmd_stream_emit(stream, VIVS_GL_STALL_TOKEN_FROM(from) | VIVS_GL_STALL_TOKEN_TO(to));
77 }
78
79 if (blt) {
80 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
81 etna_cmd_stream_emit(stream, 0);
82 }
83 }
84
85 #define EMIT_STATE(state_name, src_value) \
86 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
87
88 #define EMIT_STATE_FIXP(state_name, src_value) \
89 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
90
91 #define EMIT_STATE_RELOC(state_name, src_value) \
92 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
93
94 #define ETNA_3D_CONTEXT_SIZE (400) /* keep this number above "Total state updates (fixed)" from gen_weave_state tool */
95
96 static unsigned
97 required_stream_size(struct etna_context *ctx)
98 {
99 unsigned size = ETNA_3D_CONTEXT_SIZE;
100
101 /* stall + flush */
102 size += 2 + 4;
103
104 /* vertex elements */
105 size += ctx->vertex_elements->num_elements + 1;
106
107 /* uniforms - worst case (2 words per uniform load) */
108 size += ctx->shader.vs->uniforms.const_count * 2;
109 size += ctx->shader.fs->uniforms.const_count * 2;
110
111 /* shader */
112 size += ctx->shader_state.vs_inst_mem_size + 1;
113 size += ctx->shader_state.ps_inst_mem_size + 1;
114
115 /* DRAW_INDEXED_PRIMITIVES command */
116 size += 6;
117
118 /* reserve for alignment etc. */
119 size += 64;
120
121 return size;
122 }
123
124 /* Emit state that only exists on HALTI5+ */
125 static void
126 emit_halti5_only_state(struct etna_context *ctx, int vs_output_count)
127 {
128 struct etna_cmd_stream *stream = ctx->stream;
129 uint32_t dirty = ctx->dirty;
130 struct etna_coalesce coalesce;
131
132 etna_coalesce_start(stream, &coalesce);
133 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
134 /* Magic states (load balancing, inter-unit sync, buffers) */
135 /*00870*/ EMIT_STATE(VS_HALTI5_OUTPUT_COUNT, vs_output_count | ((vs_output_count * 0x10) << 8));
136 /*008A0*/ EMIT_STATE(VS_HALTI5_UNK008A0, 0x0001000e | ((0x110/vs_output_count) << 20));
137 for (int x = 0; x < 4; ++x) {
138 /*008E0*/ EMIT_STATE(VS_HALTI5_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
139 }
140 }
141 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
142 for (int x = 0; x < 4; ++x) {
143 /*008C0*/ EMIT_STATE(VS_HALTI5_INPUT(x), ctx->shader_state.VS_INPUT[x]);
144 }
145 }
146 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
147 /*00A90*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS);
148 /*00AA8*/ EMIT_STATE(PA_VS_OUTPUT_COUNT, vs_output_count);
149 /*01080*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS);
150 /*03888*/ EMIT_STATE(GL_HALTI5_SH_SPECIALS, ctx->shader_state.GL_HALTI5_SH_SPECIALS);
151 }
152 etna_coalesce_end(stream, &coalesce);
153 }
154
155 /* Emit state that no longer exists on HALTI5 */
156 static void
157 emit_pre_halti5_state(struct etna_context *ctx)
158 {
159 struct etna_cmd_stream *stream = ctx->stream;
160 uint32_t dirty = ctx->dirty;
161 struct etna_coalesce coalesce;
162
163 etna_coalesce_start(stream, &coalesce);
164 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
165 /*00800*/ EMIT_STATE(VS_END_PC, ctx->shader_state.VS_END_PC);
166 }
167 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
168 for (int x = 0; x < 4; ++x) {
169 /*00810*/ EMIT_STATE(VS_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
170 }
171 }
172 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
173 for (int x = 0; x < 4; ++x) {
174 /*00820*/ EMIT_STATE(VS_INPUT(x), ctx->shader_state.VS_INPUT[x]);
175 }
176 }
177 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
178 /*00838*/ EMIT_STATE(VS_START_PC, ctx->shader_state.VS_START_PC);
179 }
180 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
181 for (int x = 0; x < 10; ++x) {
182 /*00A40*/ EMIT_STATE(PA_SHADER_ATTRIBUTES(x), ctx->shader_state.PA_SHADER_ATTRIBUTES[x]);
183 }
184 }
185 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
186 /*00E04*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E04, ctx->framebuffer.RA_MULTISAMPLE_UNK00E04);
187 for (int x = 0; x < 4; ++x) {
188 /*00E10*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E10(x), ctx->framebuffer.RA_MULTISAMPLE_UNK00E10[x]);
189 }
190 for (int x = 0; x < 16; ++x) {
191 /*00E40*/ EMIT_STATE(RA_CENTROID_TABLE(x), ctx->framebuffer.RA_CENTROID_TABLE[x]);
192 }
193 }
194 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
195 /*01000*/ EMIT_STATE(PS_END_PC, ctx->shader_state.PS_END_PC);
196 }
197 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
198 /*01018*/ EMIT_STATE(PS_START_PC, ctx->shader_state.PS_START_PC);
199 }
200 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
201 /*03820*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS, ctx->shader_state.GL_VARYING_NUM_COMPONENTS);
202 for (int x = 0; x < 2; ++x) {
203 /*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), ctx->shader_state.GL_VARYING_COMPONENT_USE[x]);
204 }
205 }
206 etna_coalesce_end(stream, &coalesce);
207 }
208
209 /* Weave state before draw operation. This function merges all the compiled
210 * state blocks under the context into one device register state. Parts of
211 * this state that are changed since last call (dirty) will be uploaded as
212 * state changes in the command buffer. */
213 void
214 etna_emit_state(struct etna_context *ctx)
215 {
216 struct etna_cmd_stream *stream = ctx->stream;
217 uint32_t active_samplers = active_samplers_bits(ctx);
218
219 /* Pre-reserve the command buffer space which we are likely to need.
220 * This must cover all the state emitted below, and the following
221 * draw command. */
222 etna_cmd_stream_reserve(stream, required_stream_size(ctx));
223
224 uint32_t dirty = ctx->dirty;
225
226 /* Pre-processing: see what caches we need to flush before making state changes. */
227 uint32_t to_flush = 0;
228 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
229 /* Need flush COLOR when changing PE.COLOR_FORMAT.OVERWRITE. */
230 #if 0
231 /* TODO*/
232 if ((ctx->gpu3d.PE_COLOR_FORMAT & VIVS_PE_COLOR_FORMAT_OVERWRITE) !=
233 (etna_blend_state(ctx->blend)->PE_COLOR_FORMAT & VIVS_PE_COLOR_FORMAT_OVERWRITE))
234 #endif
235 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR;
236 }
237 if (unlikely(dirty & (ETNA_DIRTY_TEXTURE_CACHES)))
238 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE;
239 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) /* Framebuffer config changed? */
240 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH;
241 if (DBG_ENABLED(ETNA_DBG_CFLUSH_ALL))
242 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE | VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH;
243
244 if (to_flush) {
245 etna_set_state(stream, VIVS_GL_FLUSH_CACHE, to_flush);
246 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
247 }
248
249 /* Flush TS cache before changing TS configuration. */
250 if (unlikely(dirty & ETNA_DIRTY_TS)) {
251 etna_set_state(stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
252 }
253
254 /* If MULTI_SAMPLE_CONFIG.MSAA_SAMPLES changed, clobber affected shader
255 * state to make sure it is always rewritten. */
256 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
257 if ((ctx->gpu3d.GL_MULTI_SAMPLE_CONFIG & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK) !=
258 (ctx->framebuffer.GL_MULTI_SAMPLE_CONFIG & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK)) {
259 /* XXX what does the GPU set these states to on MSAA samples change?
260 * Does it do the right thing?
261 * (increase/decrease as necessary) or something else? Just set some
262 * invalid value until we know for
263 * sure. */
264 ctx->gpu3d.PS_INPUT_COUNT = 0xffffffff;
265 ctx->gpu3d.PS_TEMP_REGISTER_CONTROL = 0xffffffff;
266 }
267 }
268
269 /* Update vertex elements. This is different from any of the other states, in that
270 * a) the number of vertex elements written matters: so write only active ones
271 * b) the vertex element states must all be written: do not skip entries that stay the same */
272 if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) {
273 if (ctx->specs.halti >= 5) {
274 /*17800*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0),
275 ctx->vertex_elements->num_elements,
276 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG0);
277 /*17A00*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_SCALE(0),
278 ctx->vertex_elements->num_elements,
279 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
280 /*17A80*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG1(0),
281 ctx->vertex_elements->num_elements,
282 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG1);
283 } else {
284 /* Special case: vertex elements must always be sent in full if changed */
285 /*00600*/ etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
286 ctx->vertex_elements->num_elements,
287 ctx->vertex_elements->FE_VERTEX_ELEMENT_CONFIG);
288 if (ctx->specs.halti >= 2) {
289 /*00780*/ etna_set_state_multi(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0),
290 ctx->vertex_elements->num_elements,
291 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
292 }
293 }
294 }
295 unsigned vs_output_count = etna_rasterizer_state(ctx->rasterizer)->point_size_per_vertex
296 ? ctx->shader_state.VS_OUTPUT_COUNT_PSIZE
297 : ctx->shader_state.VS_OUTPUT_COUNT;
298
299 /* The following code is originally generated by gen_merge_state.py, to
300 * emit state in increasing order of address (this makes it possible to merge
301 * consecutive register updates into one SET_STATE command)
302 *
303 * There have been some manual changes, where the weaving operation is not
304 * simply bitwise or:
305 * - scissor fixp
306 * - num vertex elements
307 * - scissor handling
308 * - num samplers
309 * - texture lod
310 * - ETNA_DIRTY_TS
311 * - removed ETNA_DIRTY_BASE_SETUP statements -- these are guaranteed to not
312 * change anyway
313 * - PS / framebuffer interaction for MSAA
314 * - move update of GL_MULTI_SAMPLE_CONFIG first
315 * - add unlikely()/likely()
316 */
317 struct etna_coalesce coalesce;
318
319 etna_coalesce_start(stream, &coalesce);
320
321 /* begin only EMIT_STATE -- make sure no new etna_reserve calls are done here
322 * directly
323 * or indirectly */
324 /* multi sample config is set first, and outside of the normal sorting
325 * order, as changing the multisample state clobbers PS.INPUT_COUNT (and
326 * possibly PS.TEMP_REGISTER_CONTROL).
327 */
328 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_SAMPLE_MASK))) {
329 uint32_t val = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(ctx->sample_mask);
330 val |= ctx->framebuffer.GL_MULTI_SAMPLE_CONFIG;
331
332 /*03818*/ EMIT_STATE(GL_MULTI_SAMPLE_CONFIG, val);
333 }
334 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) {
335 /*00644*/ EMIT_STATE_RELOC(FE_INDEX_STREAM_BASE_ADDR, &ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR);
336 /*00648*/ EMIT_STATE(FE_INDEX_STREAM_CONTROL, ctx->index_buffer.FE_INDEX_STREAM_CONTROL);
337 }
338 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) {
339 /*00674*/ EMIT_STATE(FE_PRIMITIVE_RESTART_INDEX, ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX);
340 }
341 if (likely(dirty & (ETNA_DIRTY_VERTEX_BUFFERS))) {
342 if (ctx->specs.halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */
343 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
344 /*14600*/ EMIT_STATE_RELOC(NFE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
345 }
346 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
347 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) {
348 /*14640*/ EMIT_STATE(NFE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_CONTROL);
349 }
350 }
351 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
352 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) {
353 /*14680*/ EMIT_STATE(NFE_VERTEX_STREAMS_UNK14680(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_UNK14680);
354 }
355 }
356 } else if(ctx->specs.stream_count >= 1) { /* hw w/ multiple vertex streams */
357 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
358 /*00680*/ EMIT_STATE_RELOC(FE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
359 }
360 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
361 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) {
362 /*006A0*/ EMIT_STATE(FE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_CONTROL);
363 }
364 }
365 } else { /* hw w/ single vertex stream */
366 /*0064C*/ EMIT_STATE_RELOC(FE_VERTEX_STREAM_BASE_ADDR, &ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_BASE_ADDR);
367 /*00650*/ EMIT_STATE(FE_VERTEX_STREAM_CONTROL, ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_CONTROL);
368 }
369 }
370 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_RASTERIZER))) {
371
372 /*00804*/ EMIT_STATE(VS_OUTPUT_COUNT, vs_output_count);
373 }
374 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
375 /*00808*/ EMIT_STATE(VS_INPUT_COUNT, ctx->shader_state.VS_INPUT_COUNT);
376 /*0080C*/ EMIT_STATE(VS_TEMP_REGISTER_CONTROL, ctx->shader_state.VS_TEMP_REGISTER_CONTROL);
377 }
378 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
379 /*00830*/ EMIT_STATE(VS_LOAD_BALANCING, ctx->shader_state.VS_LOAD_BALANCING);
380 }
381 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) {
382 /*00A00*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_X, ctx->viewport.PA_VIEWPORT_SCALE_X);
383 /*00A04*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_Y, ctx->viewport.PA_VIEWPORT_SCALE_Y);
384 /*00A08*/ EMIT_STATE(PA_VIEWPORT_SCALE_Z, ctx->viewport.PA_VIEWPORT_SCALE_Z);
385 /*00A0C*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_X, ctx->viewport.PA_VIEWPORT_OFFSET_X);
386 /*00A10*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_Y, ctx->viewport.PA_VIEWPORT_OFFSET_Y);
387 /*00A14*/ EMIT_STATE(PA_VIEWPORT_OFFSET_Z, ctx->viewport.PA_VIEWPORT_OFFSET_Z);
388 }
389 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
390 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
391
392 /*00A18*/ EMIT_STATE(PA_LINE_WIDTH, rasterizer->PA_LINE_WIDTH);
393 /*00A1C*/ EMIT_STATE(PA_POINT_SIZE, rasterizer->PA_POINT_SIZE);
394 /*00A28*/ EMIT_STATE(PA_SYSTEM_MODE, rasterizer->PA_SYSTEM_MODE);
395 }
396 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
397 /*00A30*/ EMIT_STATE(PA_ATTRIBUTE_ELEMENT_COUNT, ctx->shader_state.PA_ATTRIBUTE_ELEMENT_COUNT);
398 }
399 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_SHADER))) {
400 uint32_t val = etna_rasterizer_state(ctx->rasterizer)->PA_CONFIG;
401 /*00A34*/ EMIT_STATE(PA_CONFIG, val & ctx->shader_state.PA_CONFIG);
402 }
403 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
404 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
405 /*00A38*/ EMIT_STATE(PA_WIDE_LINE_WIDTH0, rasterizer->PA_LINE_WIDTH);
406 /*00A3C*/ EMIT_STATE(PA_WIDE_LINE_WIDTH1, rasterizer->PA_LINE_WIDTH);
407 }
408 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
409 ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) {
410 /* this is a bit of a mess: rasterizer.scissor determines whether to use
411 * only the framebuffer scissor, or specific scissor state, and the
412 * viewport clips too so the logic spans four CSOs */
413 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
414
415 uint32_t scissor_left =
416 MAX2(ctx->framebuffer.SE_SCISSOR_LEFT, ctx->viewport.SE_SCISSOR_LEFT);
417 uint32_t scissor_top =
418 MAX2(ctx->framebuffer.SE_SCISSOR_TOP, ctx->viewport.SE_SCISSOR_TOP);
419 uint32_t scissor_right =
420 MIN2(ctx->framebuffer.SE_SCISSOR_RIGHT, ctx->viewport.SE_SCISSOR_RIGHT);
421 uint32_t scissor_bottom =
422 MIN2(ctx->framebuffer.SE_SCISSOR_BOTTOM, ctx->viewport.SE_SCISSOR_BOTTOM);
423
424 if (rasterizer->scissor) {
425 scissor_left = MAX2(ctx->scissor.SE_SCISSOR_LEFT, scissor_left);
426 scissor_top = MAX2(ctx->scissor.SE_SCISSOR_TOP, scissor_top);
427 scissor_right = MIN2(ctx->scissor.SE_SCISSOR_RIGHT, scissor_right);
428 scissor_bottom = MIN2(ctx->scissor.SE_SCISSOR_BOTTOM, scissor_bottom);
429 }
430
431 /*00C00*/ EMIT_STATE_FIXP(SE_SCISSOR_LEFT, scissor_left);
432 /*00C04*/ EMIT_STATE_FIXP(SE_SCISSOR_TOP, scissor_top);
433 /*00C08*/ EMIT_STATE_FIXP(SE_SCISSOR_RIGHT, scissor_right);
434 /*00C0C*/ EMIT_STATE_FIXP(SE_SCISSOR_BOTTOM, scissor_bottom);
435 }
436 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
437 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
438
439 /*00C10*/ EMIT_STATE(SE_DEPTH_SCALE, rasterizer->SE_DEPTH_SCALE);
440 /*00C14*/ EMIT_STATE(SE_DEPTH_BIAS, rasterizer->SE_DEPTH_BIAS);
441 /*00C18*/ EMIT_STATE(SE_CONFIG, rasterizer->SE_CONFIG);
442 }
443 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
444 ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) {
445 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
446
447 uint32_t clip_right =
448 MIN2(ctx->framebuffer.SE_CLIP_RIGHT, ctx->viewport.SE_CLIP_RIGHT);
449 uint32_t clip_bottom =
450 MIN2(ctx->framebuffer.SE_CLIP_BOTTOM, ctx->viewport.SE_CLIP_BOTTOM);
451
452 if (rasterizer->scissor) {
453 clip_right = MIN2(ctx->scissor.SE_CLIP_RIGHT, clip_right);
454 clip_bottom = MIN2(ctx->scissor.SE_CLIP_BOTTOM, clip_bottom);
455 }
456
457 /*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, clip_right);
458 /*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, clip_bottom);
459 }
460 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
461 /*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL);
462 }
463 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
464 /*01004*/ EMIT_STATE(PS_OUTPUT_REG, ctx->shader_state.PS_OUTPUT_REG);
465 /*01008*/ EMIT_STATE(PS_INPUT_COUNT,
466 ctx->framebuffer.msaa_mode
467 ? ctx->shader_state.PS_INPUT_COUNT_MSAA
468 : ctx->shader_state.PS_INPUT_COUNT);
469 /*0100C*/ EMIT_STATE(PS_TEMP_REGISTER_CONTROL,
470 ctx->framebuffer.msaa_mode
471 ? ctx->shader_state.PS_TEMP_REGISTER_CONTROL_MSAA
472 : ctx->shader_state.PS_TEMP_REGISTER_CONTROL);
473 /*01010*/ EMIT_STATE(PS_CONTROL, ctx->shader_state.PS_CONTROL);
474 }
475 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_FRAMEBUFFER))) {
476 uint32_t val = etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG;
477 /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, val | ctx->framebuffer.PE_DEPTH_CONFIG);
478 }
479 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) {
480 /*01404*/ EMIT_STATE(PE_DEPTH_NEAR, ctx->viewport.PE_DEPTH_NEAR);
481 /*01408*/ EMIT_STATE(PE_DEPTH_FAR, ctx->viewport.PE_DEPTH_FAR);
482 }
483 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
484 /*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE);
485
486 if (ctx->specs.pixel_pipes == 1) {
487 /*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR);
488 }
489
490 /*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE);
491 }
492 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
493 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP;
494 /*01418*/ EMIT_STATE(PE_STENCIL_OP, val);
495 }
496 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF))) {
497 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG;
498 /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG);
499 }
500 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
501 uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP;
502 /*01420*/ EMIT_STATE(PE_ALPHA_OP, val);
503 }
504 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR))) {
505 /*01424*/ EMIT_STATE(PE_ALPHA_BLEND_COLOR, ctx->blend_color.PE_ALPHA_BLEND_COLOR);
506 }
507 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
508 uint32_t val = etna_blend_state(ctx->blend)->PE_ALPHA_CONFIG;
509 /*01428*/ EMIT_STATE(PE_ALPHA_CONFIG, val);
510 }
511 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
512 uint32_t val;
513 /* Use the components and overwrite bits in framebuffer.PE_COLOR_FORMAT
514 * as a mask to enable the bits from blend PE_COLOR_FORMAT */
515 val = ~(VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
516 VIVS_PE_COLOR_FORMAT_OVERWRITE);
517 val |= etna_blend_state(ctx->blend)->PE_COLOR_FORMAT;
518 val &= ctx->framebuffer.PE_COLOR_FORMAT;
519 /*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val);
520 }
521 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
522 if (ctx->specs.pixel_pipes == 1) {
523 /*01430*/ EMIT_STATE_RELOC(PE_COLOR_ADDR, &ctx->framebuffer.PE_COLOR_ADDR);
524 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
525 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
526 } else if (ctx->specs.pixel_pipes == 2) {
527 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
528 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
529 /*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]);
530 /*01464*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(1), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[1]);
531 /*01480*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(0), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[0]);
532 /*01484*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(1), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[1]);
533 } else {
534 abort();
535 }
536 }
537 if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF))) {
538 /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, ctx->stencil_ref.PE_STENCIL_CONFIG_EXT);
539 }
540 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
541 struct etna_blend_state *blend = etna_blend_state(ctx->blend);
542 /*014A4*/ EMIT_STATE(PE_LOGIC_OP, blend->PE_LOGIC_OP | ctx->framebuffer.PE_LOGIC_OP);
543 }
544 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
545 struct etna_blend_state *blend = etna_blend_state(ctx->blend);
546 for (int x = 0; x < 2; ++x) {
547 /*014A8*/ EMIT_STATE(PE_DITHER(x), blend->PE_DITHER[x]);
548 }
549 }
550 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) {
551 /*01654*/ EMIT_STATE(TS_MEM_CONFIG, ctx->framebuffer.TS_MEM_CONFIG);
552 /*01658*/ EMIT_STATE_RELOC(TS_COLOR_STATUS_BASE, &ctx->framebuffer.TS_COLOR_STATUS_BASE);
553 /*0165C*/ EMIT_STATE_RELOC(TS_COLOR_SURFACE_BASE, &ctx->framebuffer.TS_COLOR_SURFACE_BASE);
554 /*01660*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE, ctx->framebuffer.TS_COLOR_CLEAR_VALUE);
555 /*01664*/ EMIT_STATE_RELOC(TS_DEPTH_STATUS_BASE, &ctx->framebuffer.TS_DEPTH_STATUS_BASE);
556 /*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, &ctx->framebuffer.TS_DEPTH_SURFACE_BASE);
557 /*0166C*/ EMIT_STATE(TS_DEPTH_CLEAR_VALUE, ctx->framebuffer.TS_DEPTH_CLEAR_VALUE);
558 }
559 if (unlikely(dirty & ETNA_DIRTY_SAMPLER_VIEWS)) {
560 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
561 if ((1 << x) & active_samplers) {
562 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
563 /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x), sv->TS_SAMPLER_CONFIG);
564 }
565 }
566 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
567 if ((1 << x) & active_samplers) {
568 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
569 /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x), &sv->TS_SAMPLER_STATUS_BASE);
570 }
571 }
572 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
573 if ((1 << x) & active_samplers) {
574 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
575 /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x), sv->TS_SAMPLER_CLEAR_VALUE);
576 }
577 }
578 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
579 if ((1 << x) & active_samplers) {
580 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
581 /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x), sv->TS_SAMPLER_CLEAR_VALUE2);
582 }
583 }
584 }
585 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
586 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
587 uint32_t val = 0; /* 0 == sampler inactive */
588
589 /* set active samplers to their configuration value (determined by both
590 * the sampler state and sampler view) */
591 if ((1 << x) & active_samplers) {
592 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
593 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
594
595 val = (ss->TE_SAMPLER_CONFIG0 & sv->TE_SAMPLER_CONFIG0_MASK) |
596 sv->TE_SAMPLER_CONFIG0;
597 }
598
599 /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
600 }
601 }
602 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
603 struct etna_sampler_view *sv;
604
605 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
606 if ((1 << x) & active_samplers) {
607 sv = etna_sampler_view(ctx->sampler_view[x]);
608 /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->TE_SAMPLER_SIZE);
609 }
610 }
611 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
612 if ((1 << x) & active_samplers) {
613 sv = etna_sampler_view(ctx->sampler_view[x]);
614 /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), sv->TE_SAMPLER_LOG_SIZE);
615 }
616 }
617 }
618 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
619 struct etna_sampler_state *ss;
620 struct etna_sampler_view *sv;
621
622 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
623 if ((1 << x) & active_samplers) {
624 ss = etna_sampler_state(ctx->sampler[x]);
625 sv = etna_sampler_view(ctx->sampler_view[x]);
626
627 /* min and max lod is determined both by the sampler and the view */
628 /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x),
629 ss->TE_SAMPLER_LOD_CONFIG |
630 VIVS_TE_SAMPLER_LOD_CONFIG_MAX(MIN2(ss->max_lod, sv->max_lod)) |
631 VIVS_TE_SAMPLER_LOD_CONFIG_MIN(MAX2(ss->min_lod, sv->min_lod)));
632 }
633 }
634 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
635 if ((1 << x) & active_samplers) {
636 ss = etna_sampler_state(ctx->sampler[x]);
637 sv = etna_sampler_view(ctx->sampler_view[x]);
638
639 /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x), ss->TE_SAMPLER_CONFIG1 |
640 sv->TE_SAMPLER_CONFIG1);
641 }
642 }
643 }
644 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
645 for (int y = 0; y < VIVS_TE_SAMPLER_LOD_ADDR__LEN; ++y) {
646 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
647 if ((1 << x) & active_samplers) {
648 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
649 /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x, y),&sv->TE_SAMPLER_LOD_ADDR[y]);
650 }
651 }
652 }
653 }
654
655 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
656 /*0381C*/ EMIT_STATE(GL_VARYING_TOTAL_COMPONENTS, ctx->shader_state.GL_VARYING_TOTAL_COMPONENTS);
657 }
658 if (unlikely(ctx->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
659 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
660 if ((1 << x) & active_samplers) {
661 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
662 /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->TE_SAMPLER_ASTC0);
663 }
664 }
665 }
666 etna_coalesce_end(stream, &coalesce);
667 /* end only EMIT_STATE */
668
669 /* Emit strongly architecture-specific state */
670 if (ctx->specs.halti >= 5)
671 emit_halti5_only_state(ctx, vs_output_count);
672 else
673 emit_pre_halti5_state(ctx);
674
675 /* Insert a FE/PE stall as changing the shader instructions (and maybe
676 * the uniforms) can corrupt the previous in-progress draw operation.
677 * Observed with amoeba on GC2000 during the right-to-left rendering
678 * of PI, and can cause GPU hangs immediately after.
679 * I summise that this is because the "new" locations at 0xc000 are not
680 * properly protected against updates as other states seem to be. Hence,
681 * we detect the "new" vertex shader instruction offset to apply this. */
682 if (ctx->dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF) && ctx->specs.vs_offset > 0x4000)
683 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
684
685 /* We need to update the uniform cache only if one of the following bits are
686 * set in ctx->dirty:
687 * - ETNA_DIRTY_SHADER
688 * - ETNA_DIRTY_CONSTBUF
689 * - uniforms_dirty_bits
690 *
691 * In case of ETNA_DIRTY_SHADER we need load all uniforms from the cache. In
692 * all
693 * other cases we can load on the changed uniforms.
694 */
695 static const uint32_t uniform_dirty_bits =
696 ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF;
697
698 if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
699 etna_uniforms_write(
700 ctx, ctx->shader.vs, &ctx->constant_buffer[PIPE_SHADER_VERTEX],
701 ctx->shader_state.VS_UNIFORMS, &ctx->shader_state.vs_uniforms_size);
702
703 if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
704 etna_uniforms_write(
705 ctx, ctx->shader.fs, &ctx->constant_buffer[PIPE_SHADER_FRAGMENT],
706 ctx->shader_state.PS_UNIFORMS, &ctx->shader_state.ps_uniforms_size);
707
708 /**** Large dynamically-sized state ****/
709 bool do_uniform_flush = ctx->specs.halti < 5;
710 if (dirty & (ETNA_DIRTY_SHADER)) {
711 /* Special case: a new shader was loaded; simply re-load all uniforms and
712 * shader code at once */
713 /* This sequence is special, do not change ordering unless necessary. According to comment
714 snippets in the Vivante kernel driver a process called "steering" goes on while programming
715 shader state. This (as I understand it) means certain unified states are "steered"
716 toward a specific shader unit (VS/PS/...) based on either explicit flags in register
717 00860, or what other state is written before "auto-steering". So this means some
718 state can legitimately be programmed multiple times.
719 */
720
721 if (ctx->specs.halti >= 5) { /* ICACHE (HALTI5) */
722 assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo);
723 /* Set icache (VS) */
724 etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0);
725 etna_set_state(stream, VIVS_VS_NEWRANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4);
726 assert(ctx->shader_state.VS_INST_ADDR.bo);
727 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
728 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
729 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
730 etna_set_state(stream, VIVS_VS_ICACHE_COUNT, ctx->shader_state.vs_inst_mem_size / 4 - 1);
731
732 /* Set icache (PS) */
733 etna_set_state(stream, VIVS_PS_NEWRANGE_LOW, 0);
734 etna_set_state(stream, VIVS_PS_NEWRANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4);
735 assert(ctx->shader_state.PS_INST_ADDR.bo);
736 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
737 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
738 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
739 etna_set_state(stream, VIVS_PS_ICACHE_COUNT, ctx->shader_state.ps_inst_mem_size / 4 - 1);
740
741 } else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) {
742 /* ICACHE (pre-HALTI5) */
743 assert(ctx->specs.has_icache && ctx->specs.has_shader_range_registers);
744 /* Set icache (VS) */
745 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
746 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
747 VIVS_VS_ICACHE_CONTROL_ENABLE |
748 VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
749 assert(ctx->shader_state.VS_INST_ADDR.bo);
750 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
751
752 /* Set icache (PS) */
753 etna_set_state(stream, VIVS_PS_RANGE, (ctx->shader_state.ps_inst_mem_size / 4 - 1) << 16);
754 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
755 VIVS_VS_ICACHE_CONTROL_ENABLE |
756 VIVS_VS_ICACHE_CONTROL_FLUSH_PS);
757 assert(ctx->shader_state.PS_INST_ADDR.bo);
758 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
759 } else {
760 /* Upload shader directly, first flushing and disabling icache if
761 * supported on this hw */
762 if (ctx->specs.has_icache) {
763 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
764 VIVS_VS_ICACHE_CONTROL_FLUSH_PS |
765 VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
766 }
767 if (ctx->specs.has_shader_range_registers) {
768 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
769 etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) |
770 0x100);
771 }
772 etna_set_state_multi(stream, ctx->specs.vs_offset,
773 ctx->shader_state.vs_inst_mem_size,
774 ctx->shader_state.VS_INST_MEM);
775 etna_set_state_multi(stream, ctx->specs.ps_offset,
776 ctx->shader_state.ps_inst_mem_size,
777 ctx->shader_state.PS_INST_MEM);
778 }
779
780 if (ctx->specs.has_unified_uniforms) {
781 etna_set_state(stream, VIVS_VS_UNIFORM_BASE, 0);
782 etna_set_state(stream, VIVS_PS_UNIFORM_BASE, ctx->specs.max_vs_uniforms);
783 }
784
785 if (do_uniform_flush)
786 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
787 etna_set_state_multi(stream, ctx->specs.vs_uniforms_offset,
788 ctx->shader_state.vs_uniforms_size,
789 ctx->shader_state.VS_UNIFORMS);
790 if (do_uniform_flush)
791 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
792 etna_set_state_multi(stream, ctx->specs.ps_uniforms_offset,
793 ctx->shader_state.ps_uniforms_size,
794 ctx->shader_state.PS_UNIFORMS);
795
796 /* Copy uniforms to gpu3d, so that incremental updates to uniforms are
797 * possible as long as the
798 * same shader remains bound */
799 ctx->gpu3d.vs_uniforms_size = ctx->shader_state.vs_uniforms_size;
800 ctx->gpu3d.ps_uniforms_size = ctx->shader_state.ps_uniforms_size;
801 memcpy(ctx->gpu3d.VS_UNIFORMS, ctx->shader_state.VS_UNIFORMS,
802 ctx->shader_state.vs_uniforms_size * 4);
803 memcpy(ctx->gpu3d.PS_UNIFORMS, ctx->shader_state.PS_UNIFORMS,
804 ctx->shader_state.ps_uniforms_size * 4);
805
806 if (ctx->specs.halti >= 5) {
807 /* HALTI5 needs to be prompted to pre-fetch shaders */
808 etna_set_state(stream, VIVS_VS_ICACHE_PREFETCH, 0x00000000);
809 etna_set_state(stream, VIVS_PS_ICACHE_PREFETCH, 0x00000000);
810 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
811 }
812 } else {
813 /* ideally this cache would only be flushed if there are VS uniform changes */
814 if (do_uniform_flush)
815 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
816 etna_coalesce_start(stream, &coalesce);
817 for (int x = 0; x < ctx->shader.vs->uniforms.const_count; ++x) {
818 if (ctx->gpu3d.VS_UNIFORMS[x] != ctx->shader_state.VS_UNIFORMS[x]) {
819 etna_coalsence_emit(stream, &coalesce, ctx->specs.vs_uniforms_offset + x*4, ctx->shader_state.VS_UNIFORMS[x]);
820 ctx->gpu3d.VS_UNIFORMS[x] = ctx->shader_state.VS_UNIFORMS[x];
821 }
822 }
823 etna_coalesce_end(stream, &coalesce);
824
825 /* ideally this cache would only be flushed if there are PS uniform changes */
826 if (do_uniform_flush)
827 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
828 etna_coalesce_start(stream, &coalesce);
829 for (int x = 0; x < ctx->shader.fs->uniforms.const_count; ++x) {
830 if (ctx->gpu3d.PS_UNIFORMS[x] != ctx->shader_state.PS_UNIFORMS[x]) {
831 etna_coalsence_emit(stream, &coalesce, ctx->specs.ps_uniforms_offset + x*4, ctx->shader_state.PS_UNIFORMS[x]);
832 ctx->gpu3d.PS_UNIFORMS[x] = ctx->shader_state.PS_UNIFORMS[x];
833 }
834 }
835 etna_coalesce_end(stream, &coalesce);
836 }
837 /**** End of state update ****/
838 #undef EMIT_STATE
839 #undef EMIT_STATE_FIXP
840 #undef EMIT_STATE_RELOC
841 ctx->dirty = 0;
842 ctx->dirty_sampler_views = 0;
843 }